Environmentally adaptable lidar analog front end circuit

Abstract

The application discloses a laser radar simulation front-end circuit with strong environmental adaptability, and solves the problem that a correlation detection method in the prior art is difficult to filter out change noise. The circuit comprises a synchronous clock active quenching reset circuit outputting a SPAD pulse signal; a time window configuration circuit generating a window signal with adjustable pulse width; an analog domain intensity integration circuit outputting an analog integration voltage varying with the number of SPAD pulses within the effective period of the window signal; a sample-and-hold and inter-frame reset circuit sampling as a reference voltage and resetting the integration circuit after the window ends; and a correlation detection logic circuit comparing the analog integration voltage with the reference voltage within the effective period of the window signal and outputting a trigger signal when the analog integration voltage exceeds the reference voltage. The application integrates light intensity in real time and adaptively updates a threshold value, triggers only effective target echoes in a complex light environment, reduces resource consumption and power consumption, and improves system environmental adaptability and ranging reliability.

Description

Technical Field

[0001] This invention relates to the field of mixed-signal integrated circuit technology, and in particular to a highly environmentally adaptable analog front-end circuit for lidar. Background Technology

[0002] Three-dimensional imaging area array lidar has significant application value and broad application prospects in military and civilian fields such as spacecraft docking, environmental scanning, and unmanned driving. Single-photon devices can be integrated with data processing circuits on a single chip, which is an important guarantee for high integration, miniaturization, and high reliability. Monolithic integration has advantages such as high integration, good consistency of photoelectric sensors, and large spatial resolution, making it possible to adapt to complex working scenarios.

[0003] Complex outdoor environments mean real-time and high-intensity noise interference, making TDCs (Time-to-Digital Converters) susceptible to triggering by noise signals, resulting in ineffective time-to-digital quantization. In current time-space correlation detection schemes, the noise filtering threshold is relatively fixed. While this can filter out environmental noise to some extent, it cannot filter out changing noise under outdoor detection conditions. When ambient light noise increases, raising the threshold can filter out noise signals, but it will also filter out the target signal, especially when the target signal strength is weak. Summary of the Invention

[0004] This invention provides a highly environmentally adaptable lidar analog front-end circuit, which solves the problem that existing correlation detection methods are difficult to filter out changing noise. It realizes real-time integration of ambient light intensity and generation of adaptive reference voltage, thereby triggering only time quantization of the echo of the effective target in complex and changing outdoor environments. This significantly reduces the system's resource consumption and power consumption, and improves the environmental adaptability and ranging reliability of the lidar.

[0005] This invention provides a highly environmentally adaptable lidar analog front-end circuit, which includes: a synchronous clock active quenching and reset circuit, a time window configuration circuit, an analog domain intensity integration circuit, a sample-and-hold and inter-frame reset circuit, and a correlation detection logic circuit.

[0006] The synchronous clock active quenching and reset circuit is used to periodically quench and reset the SPAD (Single-Photon Avalanche Diode) device under the control of an external synchronous clock signal, and output the SPAD pulse signal corresponding to the photon event.

[0007] The time window configuration circuit is used to receive the SPAD pulse signal and generate a window pulse signal W with adjustable pulse width.

[0008] The analog domain intensity integration circuit is used to perform analog domain charge integration on the SPAD pulse signal during the effective level of the window pulse signal W, and output a real-time analog integrated voltage Vint that changes continuously with the accumulation of pulses.

[0009] The sample-and-hold and inter-frame reset circuit is used to sample and hold the analog integral voltage Vint before the window pulse signal W ends, output a reference voltage as a comparison threshold, and generate a reset pulse signal after the window pulse signal W ends to clear and reset the analog domain intensity integral circuit.

[0010] The correlation detection logic circuit is used to compare the real-time analog integral voltage Vint with the reference voltage during the effective level of the window pulse signal W, and output the TDC quantization pulse Flip signal when the instantaneous value of the real-time analog integral voltage Vint exceeds the reference voltage.

[0011] One or more technical solutions provided in this invention have at least the following technical effects or advantages:

[0012] This invention employs a synchronous clock active quenching and reset circuit to periodically and actively quench and reset the SPAD device under the control of an external synchronous clock signal. This rapid and synchronous quenching and reset mechanism effectively suppresses afterpulse effects, improves detection reliability, and outputs a SPAD pulse signal corresponding to a photon event. A time window configuration circuit receives the SPAD pulse signal and generates a pulse-width-adjustable window pulse signal W. By flexibly configuring the window width, it achieves precise gating of the target echo signal in the time domain, effectively suppressing random noise interference. An analog domain intensity integration circuit performs analog domain charge integration on the SPAD pulse signal during the effective level of the window pulse signal W, outputting a real-time analog integrated voltage Vint that continuously changes with pulse accumulation. This voltage reflects changes in ambient light intensity in real time, providing accurate input for adaptive threshold generation, and achieving high linearity through analog integration. The system includes a high-intensity and low-power signal conversion; a sample-and-hold and inter-frame reset circuit, used to sample and hold the analog integral voltage Vint before the end of the window pulse signal W, and output it as a reference voltage for the comparison threshold, enabling the threshold to be updated adaptively with ambient light intensity; and after the end of the window pulse signal W, a reset pulse signal is generated to clear and reset the analog domain intensity integral circuit, ensuring that the detection start state is consistent for each frame and avoiding the influence of signal accumulation and residue; and a correlation detection logic circuit, used to compare the real-time analog integral voltage Vint with the reference voltage during the effective level of the window pulse signal W. When the instantaneous value of the real-time analog integral voltage Vint exceeds the reference voltage, a TDC quantization pulse Flip signal is output. Through a dynamic threshold comparison mechanism, only valid echoes with intensity exceeding ambient noise are triggered, significantly reducing the number of invalid time quantizations and improving system resource utilization efficiency and environmental adaptability. Attached Figure Description

[0013] Figure 1 A schematic diagram of a lidar analog front-end circuit with strong environmental adaptability provided in an embodiment of the present invention;

[0014] Figure 2 This is a schematic diagram of the active quenching and reset circuit structure for a synchronous clock provided in an embodiment of the present invention;

[0015] Figure 3 Timing diagram of the synchronous clock active quenching and reset circuit provided in the embodiment of the present invention;

[0016] Figure 4 The principle and timing diagram of the correlation detection logic circuit provided in the embodiments of the present invention;

[0017] Figure 5 This is a schematic diagram of the analog domain intensity integration circuit, sample-and-hold circuit, and inter-frame reset circuit provided in an embodiment of the present invention.

[0018] Figure 6 This is a schematic diagram of the structure and timing of the inter-frame reset circuit provided in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0020] This invention provides a highly environmentally adaptable analog front-end circuit for lidar, see [link / reference]. Figure 1 The circuit includes: a synchronous clock active quenching and reset circuit, a time window configuration circuit, an analog domain intensity integration circuit, a sample-and-hold and inter-frame reset circuit, and a correlation detection logic circuit.

[0021] The synchronous clock active quenching and reset circuit is used to periodically quench and reset the SPAD device under the control of an external synchronous clock signal, and output the SPAD pulse signal corresponding to the photon event.

[0022] For details, see Figure 2 The synchronous clock active quenching and reset circuit includes: SPAD device, NMOS transistor M1, NMOS transistor M2, NMOS transistor M3, PMOS transistor M4, inverter N1, inverter N2, inverter N3, Schmitt trigger, NAND gate A1, NAND gate A2, NOR gate O1 and NOR gate O2.

[0023] The cathode of the SPAD device is connected to the bias voltage; the anode of the SPAD device is connected to the input of inverter N1, the input of Schmitt trigger, the gate of NMOS transistor M1, the drain of NMOS transistor M1, and the drain of NMOS transistor M3; the source of NMOS transistor M1 is connected to the drain of NMOS transistor M2.

[0024] The source of NMOS transistor M2 is connected to the source of NMOS transistor M3 and grounded; the gate of NMOS transistor M2 is connected to the gate of PMOS transistor M4 and the output of inverter N1; the gate of NMOS transistor M3 is connected to the output of NAND gate A1; the source of PMOS transistor M4 is connected to the power supply voltage VDD, and the drain of PMOS transistor M4 is connected to the gate and drain of NMOS transistor M1; the input of inverter N2 is connected to the output of NOR gate O1; the input of inverter N3 is connected to the output of inverter N2, and the output of inverter N3 outputs a SPAD pulse signal; the input of Schmitt trigger is connected to S... The PAD device is connected to the anode. The output of the Schmitt trigger is connected to the first input of NOR gate O1, the first input of NOR gate O2, and the first input of NAND gate A2, respectively. The first input of NAND gate A1 is connected to the reference clock CLK, and the second input of NAND gate A1 is connected to the output of NOR gate O2. The first input of NAND gate A2 is connected to the output of the Schmitt trigger, and the second input of NAND gate A2 is grounded. The output of NAND gate A2 is connected to the second input of NOR gate O1 and the second input of NOR gate O2, respectively. The output of NOR gate O1 is connected to the input of inverter N2.

[0025] In the synchronous clock active quenching and reset circuit, see Figure 3 Under the control of an external synchronous clock signal, the SPAD device is periodically actively quenched and reset, and outputs SPAD pulse signals corresponding to photon events, including:

[0026] (1) In the initial state, the anode voltage of the SPAD device is reset to a low level, and the output of the Schmitt trigger is at a high level;

[0027] (2) Avalanche and quenching stage: When an avalanche occurs in the SPAD device, the anode voltage of the SPAD device rises rapidly. When the anode voltage exceeds the threshold voltage of the Schmitt trigger, the output of the Schmitt trigger flips to a low level. The low level of the output of the Schmitt trigger is controlled by the logic gate circuit to turn on the PMOS transistor M4, connecting the power supply voltage VDD to the anode of the SPAD device, so that the anode voltage of the SPAD device is quickly pulled up to VDD to quench the avalanche current.

[0028] (3) During the reset phase, under the synchronous control of the reference clock CLK, the NMOS transistor M3 is turned on, pulling the anode voltage of the SPAD device down to ground potential, thus completing the reset.

[0029] (4) After reset, the circuit returns to the initial stage.

[0030] For example, a synchronous clock active quenching and reset circuit periodically quenches the SPAD device, such as... Figure 2As shown, in the initial state, the anode voltage of the SPAD drops to ground, the output of the Schmitt trigger is high, and the SPAD pulse signal output is low. Once the incident photon triggers an avalanche, the avalanche current rapidly rises to its peak value.

[0031] Because the avalanche current flows rapidly through the high-resistance path formed by the anode of the SPAD device at the input of inverter N1, NMOS transistor M1, and NMOS transistor M2, the anode voltage increases rapidly and the avalanche is detected immediately.

[0032] When inverter N1 flips, its output changes from high to low. This low level quickly turns off NMOS transistor M2, blocking the avalanche current path and initiating current depletion. Simultaneously, the low level turns on PMOS transistor M4, rapidly raising the anode voltage to the supply voltage VDD through the positive feedback loop, creating a positive feedback acceleration process. As a result, the avalanche current decreases rapidly and is quenched within a short time. It's important to note that the Schmitt trigger only begins to flip when the anode voltage exceeds the high threshold of the Schmitt trigger, i.e., after the avalanche current is completely quenched, and the circuit enters the charging phase. The positive feedback loop refers to the closed signal path formed by SPAD anode → inverter N1 → PMOS transistors M4 / M2 → SPAD anode.

[0033] Furthermore, after a brief delay, when the reference clock CLK and the internal logic signal used to control the reset, namely the output of NAND gate A1, are both high, NMOS transistor M3 turns on, pulling the anode voltage down to ground, charging the circuit to its initial state, ready for the next photon detection. The output of NOR gate O1, after being shaped by two inverters N2 and N3, finally outputs a SPAD pulse signal with steep edges.

[0034] A time window configuration circuit is used to receive SPAD pulse signals and generate a window pulse signal W with adjustable pulse width.

[0035] For details, see Figure 5 The time window configuration circuit includes: D flip-flop DFF1, delay unit DLY1, and AND gate AN1.

[0036] The input terminal D of D flip-flop DFF1 is connected to the bias voltage VDD; the CLK terminal of D flip-flop DFF1 is connected to the SPAD pulse signal; the reset terminal R of D flip-flop DFF1 is connected to the output terminal of AND gate AN1; the non-inverting output terminal Q of D flip-flop DFF1 outputs the window pulse signal W; the inverting output terminal of D flip-flop DFF1... The signal input terminal of the delay unit DLY1 is connected to the voltage control terminal of the delay unit DLY1 and the bias voltage VC is connected to the voltage control terminal of the delay unit DLY1; the output terminal of the delay unit DLY1 is connected to the first input terminal of the AND gate AN1; and the second input terminal of the AND gate AN1 is connected to the digital reset signal RST.

[0037] For details, see Figure 4 It receives SPAD pulse signals and generates a window pulse signal W with adjustable pulse width, including:

[0038] (1) During the triggering phase, when the rising edge of the SPAD pulse signal reaches the CLK terminal of the D flip-flop DFF1, the D flip-flop DFF1 is triggered, and the window pulse signal W output by the non-inverting output terminal Q of the D flip-flop DFF1 jumps to the effective level.

[0039] (2) During the window sustaining phase, while the window pulse signal W is at an active level, the inverted output of the D flip-flop DFF1... The signal is at a low level. After being delayed by the delay unit DLY1, the low-level signal reaches the first input terminal of the AND gate AN1. The delay time of the delay unit DLY1 is controlled by the bias voltage VC.

[0040] (3) During the window end and reset phase, when the delay signal output by the delay unit DLY1 becomes high, if the digital reset signal RST is valid at this time, the output of the AND gate AN1 becomes valid, the reset terminal R of the D flip-flop DFF1 is set, and the window pulse signal W jumps back to invalid level, completing one window cycle.

[0041] For example, Figure 4 The timing scheme for configuring the time window circuitry includes the analog domain echo integration module and the adaptive threshold generation module. The relevant requirements in the time and spatial domains are implemented at the circuit level to create a configurable window pulse. The width W of the window pulse signal W is controlled by the bias voltage VC; increasing the bias voltage VC results in a narrower detection window.

[0042] Within the time window, each SPAD pulse signal triggers a charge integration process, converting a single SPAD pulse into a fixed voltage increment ΔV. The more SPAD pulse signals within the time window, the higher the final simulated integrated voltage Vint, indicating a higher ambient light intensity.

[0043] Before each detection, the reference voltage used by the correlation detection logic circuit is reset to a fixed potential, slightly lower than a fixed voltage increment ΔV. A TDC quantized pulse flip signal is generated within the first window as long as a SPAD pulse signal is present. However, as the ambient intensity accumulates, the analog integral voltage Vint is sampled at the end of each window and used as the new reference voltage for subsequent time windows. Therefore, only genuine target echoes can generate new TDC quantized pulse flip signals. With appropriate window width configuration, randomly distributed noise signals in the time domain are filtered out. If other TDC quantized pulse flip signals exist, the first TDC quantized pulse flip signal is filtered out. If there is only one TDC quantized pulse flip signal, it means the ambient light intensity is very low (single photon level) and the target echo is weak; in this case, the unique TDC quantized pulse flip signal is not filtered out, and target distance information is obtained through off-chip histogram accumulation.

[0044] Specifically, the structure of the analog domain intensity integration circuit and the sample-and-hold and inter-frame reset circuit is as follows: Figure 5 As shown, the time window configuration circuit consists of a trigger network and a delay unit, which is implemented based on a current-limited voltage control module. To achieve compact intensity integration, a common-source cascode switching current source is used to convert the number of pulses to the analog integral voltage Vint. During the active period of the window signal W, the first sampling control signal S1 and the second sampling control signal S2 sample the analog integral voltage Vint and store the current integral value in capacitor Cc. Subsequently, if the new analog integral voltage Vint is greater than the reference voltage value stored in capacitor Cc, the TDC quantization pulse Flip signal flips.

[0045] The analog domain intensity integration circuit is used to perform analog domain charge integration on the SPAD pulse signal during the effective level of the window pulse signal W, and outputs a real-time analog integrated voltage Vint that changes continuously with the accumulation of pulses.

[0046] For details, see Figure 5 The analog domain strength integration circuit includes: inverter N4, PMOS transistor M5, PMOS transistor M6, NMOS transistor M7, NMOS transistor M8, NMOS transistor M9 and integrating capacitor C.

[0047] The input of inverter N4 is connected to the non-inverting output Q of D flip-flop DFF1 in the time window configuration circuit; the output of inverter N4 is connected to the gate of NMOS transistor M9; the source of NMOS transistor M9 is connected to the lower plate of integrating capacitor C and grounded; the gate of PMOS transistor M5 is connected to bias voltage VP1; the source of PMOS transistor M5 is connected to power supply voltage VDD; the drain of PMOS transistor M5 is connected to the source of transistor M6; the gate of PMOS transistor M6 is connected to bias voltage VP2; the drain of PMOS transistor M6 is connected to the drains of NMOS transistors M7 and M8; the gate of NMOS transistor M7 is connected to the output of inverter N3 in the synchronous clock active quenching reset circuit; the source of NMOS transistor M7 is connected to the drain of NMOS transistor M9 and the upper plate of integrating capacitor C; the source of NMOS transistor M8 is grounded; the gate of NMOS transistor M8 is connected to the SPAD pulse inverting signal.

[0048] Specifically, during the effective level of the window pulse signal W, the SPAD pulse signal is integrated in the analog domain, and the output is a real-time analog integrated voltage Vint that varies continuously with pulse accumulation, including:

[0049] (1) During the period when the window pulse signal W is at an effective level, the NMOS transistor M9 is turned off, and the discharge path of the integrating capacitor C is blocked.

[0050] (2) When the SPAD pulse signal is at an effective level, the NMOS transistor M7 is turned on, and the current source formed by the PMOS transistors M5 and M6 charges the integrating capacitor C, causing the analog integrating voltage Vint to rise by a fixed voltage step.

[0051] (3) When the SPAD pulse signal is invalid, NMOS transistor M7 is turned off and NMOS transistor M8 is turned on, which pulls down the drain potential of PMOS transistor M6 and stops charging the integrating capacitor C.

[0052] (4) During the effective level duration of the window pulse signal W, the rise of the analog integral voltage Vint is proportional to the number of pulses of the SPAD pulse signal.

[0053] The sample-and-hold and inter-frame reset circuit is used to sample and hold the analog integral voltage Vint before the end of the window pulse signal W, output the reference voltage as the comparison threshold, and generate a reset pulse signal after the end of the window pulse signal W to clear and reset the analog domain intensity integral circuit.

[0054] For details, see Figure 5 and Figure 6The sample-and-hold and inter-frame reset circuit includes: NMOS transistor M10, NMOS transistor M11, capacitor Cc, inverter N5, D flip-flop DFF2, delay unit DLY2, inverter N6, AND gate AN2 and AND gate AN3.

[0055] The drain of NMOS transistor M10 is connected to the analog integrating voltage Vint; the gate of NMOS transistor M10 is connected to the first sampling control signal S1; the source of NMOS transistor M10 is connected to the upper plate of capacitor Cc; the lower plate of capacitor Cc is connected to the drain of NMOS transistor M11 and the input of inverter N5; the gate of NMOS transistor M11 is connected to the second sampling control signal S2; the source of NMOS transistor M11 is connected to the output of inverter N5; the output of inverter N5 outputs the reference voltage Vref; the input D of D flip-flop DFF2 is connected to the power supply voltage VDD; the CLK terminal of D flip-flop DFF2 is connected to the window pulse signal W; D flip-flop DFF... The non-inverting output Q of the D flip-flop is connected to the input of the delay unit DLY2; the reset terminal R of the D flip-flop DFF2 is connected to the output of the inverter N6; the output of the delay unit DLY2 is connected to the first input of the AND gate AN2 and the input of the inverter N6; the second input of the AND gate AN2 is connected to the window pulse signal W; the output of the AND gate AN2 is connected to the first input of the AND gate AN3; the second input of the AND gate AN3 is connected to the output of the inverter N5, and the output of the AND gate AN3 is connected to the second sampling control signal S2; wherein, the first sampling control signal S1 is the sampling pulse that appears before the effective level of the window pulse signal W ends; the second sampling control signal S2 is the reset sampling pulse output by the AND gate AN3.

[0056] Specifically, before the window pulse signal W ends, the analog integral voltage Vint is sampled and held, and the output is used as a reference voltage for the comparison threshold. After the window pulse signal W ends, a reset pulse signal is generated to clear and reset the analog domain intensity integral circuit, including:

[0057] (1) During the sampling and holding phase, before the effective level of the window pulse signal W ends, the first sampling control signal S1 becomes effective, which turns on the NMOS transistor M10, samples the current analog integral voltage Vint onto the capacitor Cc, and outputs the reference voltage Vref through the inverter N5.

[0058] (2) During the inter-frame reset and threshold update stage, near the falling edge of the window pulse signal W, the delay unit DLY2 outputs a delay pulse; when the delay pulse and the window pulse signal W are both valid, the AND gate AN2 outputs a valid pulse; if the input of the inverter N5 is low and the output is high at this time, the AND gate AN3 outputs a valid second sampling control signal S2, which turns on the NMOS transistor M11, discharges and resets the capacitor Cc, and resets the reference voltage Vref to the initial low level.

[0059] (3) During the reset phase of the integrator circuit: When the window pulse signal W becomes invalid, the reverse signal of the window pulse signal W controls the NMOS transistor M9 in the analog domain strength integrator circuit to turn on, discharge the integrator capacitor C, and reset the analog integrator voltage Vint to the initial voltage.

[0060] The correlation detection logic circuit is used to compare the real-time analog integrated voltage Vint with the reference voltage during the effective level of the window pulse signal W. When the instantaneous value of the real-time analog integrated voltage Vint exceeds the reference voltage, the TDC quantization pulse Flip signal is output.

[0061] For example, Figure 6 The inter-frame reset circuit in the model combines a D flip-flop DFF2 and a delay unit DLY2 to generate a delayed signal for the window signal W. The delay is less than the pulse width of the window signal W. This delayed signal is then ANDed with the window signal W to generate a narrow pulse signal before the falling edge of the window signal W. Within this narrow pulse signal, a second sampling control signal S2 is generated based on the state of the TDC quantization pulse Flip signal, updating the voltage stored on capacitor Cc. This ultimately achieves real-time updating of the reference voltage when the TDC quantization pulse Flip signal is triggered. Compared to current time-space correlation detection schemes, the architecture of this analog domain has a compact structure, meaning lower on-chip resource overhead. The proposed inter-frame reset circuit innovatively achieves an adaptive reference voltage configuration related to ambient intensity, which triggers only a very small number of time quantization processes during ranging. This has a significant advantage when ambient light intensity changes drastically, i.e., in the light intensity range of 0.1 lux to 100 klux, reducing invalid time quantization processes, achieving lower on-chip resource and power consumption, and reducing the bandwidth requirements of the data transmission interface, thereby avoiding a decrease in the sensor frame rate.

[0062] This invention discloses a highly environmentally adaptable analog front-end circuit for lidar, comprising: a synchronous clock active quenching and reset circuit, a time window configuration circuit, an analog domain intensity integration circuit, and a sample-and-hold and inter-frame reset circuit. The invention utilizes the synchronous clock active quenching and reset circuit to periodically quench the SPAD device, outputting a SPAD pulse signal. Based on the SPAD pulse signal, the time window configuration circuit generates a pulse-width-adjustable window signal W. The analog domain intensity integration circuit converts the input SPAD pulse signal into an analog integrated voltage Vint. Based on the sample-and-hold and inter-frame reset circuit, the analog integrated voltage Vint is sampled and used as a reference voltage for the correlation detection logic circuit. During the valid period of the window signal W, by comparing the analog integrated voltage Vint with the reference voltage, the correlation detection logic circuit outputs a TDC quantization pulse Flip signal. Based on this environmentally adaptable time-space correlation detection scheme, the acquisition of environmental intensity information and adaptive configuration of the correlation detection reference voltage are achieved with low resource overhead, improving the environmental adaptability of the lidar system during complex and changing outdoor detection. Therefore, this invention is applicable to applications such as SPAD-based lidar sensor chips.

[0063] The various embodiments described in this specification are presented in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. All or part of this invention can be used in numerous general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, mobile communication terminals, multiprocessor systems, microprocessor-based systems, programmable electronic devices, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices, etc.

[0064] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the present invention.

Claims

1. A lidar analog front-end circuit with strong environmental adaptability, characterized in that, include: Synchronous clock active quenching and reset circuit, time window configuration circuit, analog domain strength integration circuit, sample and hold and inter-frame reset circuit, and correlation detection logic circuit; The synchronous clock active quenching and reset circuit is used to periodically quench and reset the SPAD device under the control of an external synchronous clock signal, and output the SPAD pulse signal corresponding to the photon event. The time window configuration circuit is used to receive the SPAD pulse signal and generate a window pulse signal W with adjustable pulse width. The analog domain intensity integration circuit is used to perform analog domain charge integration on the SPAD pulse signal during the effective level of the window pulse signal W, and output a real-time analog integrated voltage Vint that changes continuously with the accumulation of pulses. The sample-and-hold and inter-frame reset circuit is used to sample and hold the analog integral voltage Vint before the window pulse signal W ends, output a reference voltage as a comparison threshold, and generate a reset pulse signal after the window pulse signal W ends to clear and reset the analog domain intensity integral circuit. The correlation detection logic circuit is used to compare the real-time analog integral voltage Vint with the reference voltage during the effective level of the window pulse signal W, and output the TDC quantization pulse Flip signal when the instantaneous value of the real-time analog integral voltage Vint exceeds the reference voltage.

2. The environmentally adaptable lidar analog front-end circuit according to claim 1, characterized in that, The synchronous clock active quenching reset circuit includes: SPAD device, NMOS transistor M1, NMOS transistor M2, NMOS transistor M3, PMOS transistor M4, inverter N1, inverter N2, inverter N3, Schmitt trigger, NAND gate A1, NAND gate A2, NOR gate O1 and NOR gate O2. The cathode of the SPAD device is connected to the bias voltage; the anode of the SPAD device is connected to the input terminal of the inverter N1, the input terminal of the Schmitt trigger, the gate of the NMOS transistor M1, the drain of the NMOS transistor M1, and the drain of the NMOS transistor M3. The source of the NMOS transistor M1 is connected to the drain of the NMOS transistor M2; The source of NMOS transistor M2 is connected to the source of NMOS transistor M3 and grounded; the gate of NMOS transistor M2 and the gate of PMOS transistor M4 are connected to the output terminal of inverter N1. The gate of the NMOS transistor M3 is connected to the output terminal of the NAND gate A1; The source of the PMOS transistor M4 is connected to the power supply voltage VDD, and the drain of the PMOS transistor M4 is connected to the gate and drain of the NMOS transistor M1. The input terminal of the inverter N2 is connected to the output terminal of the NOR gate O1; The input terminal of inverter N3 is connected to the output terminal of inverter N2, and the output terminal of inverter N3 outputs a SPAD pulse signal. The input terminal of the Schmitt trigger is connected to the anode of the SPAD device, and the output terminal of the Schmitt trigger is connected to the first input terminal of the NOR gate O1, the first input terminal of the NOR gate O2, and the first input terminal of the NAND gate A2, respectively. The first input terminal of the NAND gate A1 is connected to the reference clock CLK, and the second input terminal of the NAND gate A1 is connected to the output terminal of the NOR gate O2. The first input terminal of the NAND gate A2 is connected to the output terminal of the Schmitt trigger, the second input terminal of the NAND gate A2 is grounded, and the output terminal of the NAND gate A2 is connected to the second input terminal of the NOR gate O1 and the second input terminal of the NOR gate O2 respectively. The output of the NOR gate O1 is connected to the input of the inverter N2.

3. The environmentally adaptable lidar analog front-end circuit according to claim 2, characterized in that, The process of periodically quenching and resetting the SPAD device under the control of an external synchronous clock signal, and outputting a SPAD pulse signal corresponding to a photon event, includes: In the initial state, the anode voltage of the SPAD device is reset to a low level, and the output of the Schmitt trigger is at a high level. During the avalanche and quenching phase, when an avalanche occurs in the SPAD device, the anode voltage of the SPAD device rises rapidly. When the anode voltage exceeds the threshold voltage of the Schmitt trigger, the output of the Schmitt trigger flips to a low level. The low level of the output of the Schmitt trigger is controlled by a logic gate circuit to turn on the PMOS transistor M4, connecting the power supply voltage VDD to the anode of the SPAD device, thereby rapidly pulling the anode voltage of the SPAD device up to VDD to quench the avalanche current. During the reset phase, under the synchronous control of the reference clock CLK, the NMOS transistor M3 is turned on, pulling the anode voltage of the SPAD device down to ground potential, thus completing the reset. After reset, the circuit returns to its initial state.

4. The environmentally adaptable lidar analog front-end circuit according to claim 1, characterized in that, The time window configuration circuit includes: a D flip-flop DFF1, a delay unit DLY1, and an AND gate AN1; The input terminal D of the D flip-flop DFF1 is connected to the bias voltage VDD; the CLK terminal of the D flip-flop DFF1 is connected to the SPAD pulse signal; the reset terminal R of the D flip-flop DFF1 is connected to the output terminal of the AND gate AN1; the non-inverting output terminal Q of the D flip-flop DFF1 outputs the window pulse signal W; the inverting output terminal of the D flip-flop DFF1... Connect to the signal input terminal of the delay unit DLY1; The voltage control terminal of the delay unit DLY1 is connected to the bias voltage VC; the output terminal of the delay unit DLY1 is connected to the first input terminal of the AND gate AN1. The second input terminal of the AND gate AN1 is connected to the digital reset signal RST.

5. The environmentally adaptable lidar analog front-end circuit according to claim 4, characterized in that, The step of receiving the SPAD pulse signal and generating a pulse width adjustable window pulse signal W includes: During the triggering phase, when the rising edge of the SPAD pulse signal reaches the CLK terminal of the D flip-flop DFF1, the D flip-flop DFF1 is triggered, and the window pulse signal W output by the non-inverting output terminal Q of the D flip-flop DFF1 jumps to an active level. During the window sustaining phase, while the window pulse signal W is at an active level, the inverted output of the D flip-flop DFF1... The signal is at a low level. After being delayed by the delay unit DLY1, the low-level signal reaches the first input terminal of the AND gate AN1. The delay time of the delay unit DLY1 is controlled by the bias voltage VC. During the window end and reset phase, when the delay signal output by the delay unit DLY1 becomes high, if the digital reset signal RST is active at this time, the output of the AND gate AN1 becomes active, the reset terminal R of the D flip-flop DFF1 is set, and the window pulse signal W jumps back to inactive, completing one window cycle.

6. The environmentally adaptable lidar analog front-end circuit according to claim 1, characterized in that, The analog domain strength integration circuit includes: an inverter N4, a PMOS transistor M5, a PMOS transistor M6, an NMOS transistor M7, an NMOS transistor M8, an NMOS transistor M9, and an integrating capacitor C; The input terminal of the inverter N4 is connected to the non-inverting output terminal Q of the D flip-flop DFF1 of the time window configuration circuit; the output terminal of the inverter N4 is connected to the gate of the NMOS transistor M9. The source of the NMOS transistor M9 is connected to the lower plate of the integrating capacitor C and grounded; The gate of the PMOS transistor M5 is connected to the bias voltage VP1; the source of the PMOS transistor M5 is connected to the power supply voltage VDD; and the drain of the PMOS transistor M5 is connected to the source of the transistor M6. The gate of the PMOS transistor M6 is connected to the bias voltage VP2; the drain of the PMOS transistor M6 is connected to the drain of the NMOS transistor M7 and the drain of the NMOS transistor M8. The gate of the NMOS transistor M7 is connected to the output terminal of the inverter N3 of the synchronous clock active quenching reset circuit; the source of the NMOS transistor M7 is connected to the drain of the NMOS transistor M9 and the upper plate of the integrating capacitor C. The source of the NMOS transistor M8 is grounded; the gate of the NMOS transistor M8 is connected to the SPAD pulse inverted signal.

7. The environmentally adaptable lidar analog front-end circuit according to claim 6, characterized in that, The step of performing analog domain charge integration on the SPAD pulse signal during the effective level of the window pulse signal W, and outputting a real-time analog integrated voltage Vint that continuously varies with pulse accumulation, includes: During the period when the window pulse signal W is at an active level, the NMOS transistor M9 is turned off, and the discharge path of the integrating capacitor C is blocked. When the SPAD pulse signal is at an active level, the NMOS transistor M7 is turned on, and the current source formed by the PMOS transistors M5 and M6 charges the integrating capacitor C, causing the analog integrating voltage Vint to rise by a fixed voltage step. When the SPAD pulse signal is at an invalid level, the NMOS transistor M7 is turned off and the NMOS transistor M8 is turned on, pulling the drain potential of the PMOS transistor M6 low and stopping the charging of the integrating capacitor C. During the effective level duration of the window pulse signal W, the rise in the analog integral voltage Vint is proportional to the number of pulses in the SPAD pulse signal.

8. The environmentally adaptable lidar analog front-end circuit according to claim 1, characterized in that, The sample-and-hold and inter-frame reset circuit includes: NMOS transistor M10, NMOS transistor M11, capacitor Cc, inverter N5, D flip-flop DFF2, delay unit DLY2, inverter N6, AND gate AN2 and AND gate AN3. The drain of the NMOS transistor M10 is connected to the analog integration voltage Vint; the gate of the NMOS transistor M10 is connected to the first sampling control signal S1; and the source of the NMOS transistor M10 is connected to the upper plate of the capacitor Cc. The lower plate of the capacitor Cc is connected to the drain of the NMOS transistor M11 and the input terminal of the inverter N5. The gate of the NMOS transistor M11 is connected to the second sampling control signal S2; the source of the NMOS transistor M11 is connected to the output terminal of the inverter N5. The inverter N5 outputs the reference voltage Vref. The input terminal D of the D flip-flop DFF2 is connected to the power supply voltage VDD; the CLK terminal of the D flip-flop DFF2 is connected to the window pulse signal W; the non-inverting output terminal Q of the D flip-flop DFF2 is connected to the input terminal of the delay unit DLY2; and the reset terminal R of the D flip-flop DFF2 is connected to the output terminal of the inverter N6. The output of the delay unit DLY2 is connected to the first input of the AND gate AN2 and the input of the inverter N6. The second input terminal of AND gate AN2 is connected to the window pulse signal W; the output terminal of AND gate AN2 is connected to the first input terminal of AND gate AN3. The second input terminal of the AND gate AN3 is connected to the output terminal of the inverter N5, and the second sampling control signal S2 is connected to the output terminal of the AND gate AN3. Wherein, the first sampling control signal S1 is a sampling pulse that appears before the end of the effective level of the window pulse signal W; the second sampling control signal S2 is the reset sampling pulse output by the AND gate AN3.

9. The environmentally adaptable lidar analog front-end circuit according to claim 8, characterized in that, Before the window pulse signal W ends, the analog integral voltage Vint is sampled and held, and output as a reference voltage for the comparison threshold. After the window pulse signal W ends, a reset pulse signal is generated to clear and reset the analog domain intensity integration circuit, including: During the sample-and-hold phase, before the effective level of the window pulse signal W ends, the first sampling control signal S1 becomes effective, turning on the NMOS transistor M10, sampling the current analog integral voltage Vint onto the capacitor Cc, and outputting the reference voltage Vref through the inverter N5; During the inter-frame reset and threshold update phase, near the falling edge of the window pulse signal W, the delay unit DLY2 outputs a delay pulse; When the delayed pulse and the window pulse signal W are both valid, the AND gate AN2 outputs a valid pulse; If the input of the inverter N5 is low and the output is high at this time, the AND gate AN3 outputs the valid second sampling control signal S2, which turns on the NMOS transistor M11, discharges and resets the capacitor Cc, and resets the reference voltage Vref to the initial low level. During the integrator circuit reset phase: when the window pulse signal W becomes invalid, the inverse signal of the window pulse signal W controls the NMOS transistor M9 in the analog domain intensity integrator circuit to turn on, discharging the integrator capacitor C in the analog domain intensity integrator circuit, thereby resetting the analog integrator voltage Vint to its initial voltage.

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