Digital-analog verification method and system based on real-time waveform dynamic analysis, and electronic device

Abstract

The application discloses a digital-analog verification method and system based on real-time waveform dynamic analysis and electronic equipment, and the method comprises the following steps: collecting mixed signal waveform data streams output by a tested chip in real time; calculating key performance indicators from the waveform data streams in real time, and evaluating the current performance state of the tested chip according to the key performance indicators; dynamically generating an excitation adjustment strategy based on the current performance state and a target performance state; and switching and injecting the generated new test excitation to the tested chip under the premise that the current tested chip verification is not interrupted. The application can reduce the verification iteration number and improve the verification efficiency. Through a real-time feedback system, whether the performance meets the expectation can be checked in time, real-time analysis can be performed, problems can be quickly located, the positioning efficiency is improved, and thus the verification period is shortened.

Description

Technical Field

[0001] This application relates to the field of digital-analog chip technology, and in particular to a digital-analog verification method, system and electronic device based on real-time waveform dynamic analysis. Background Technology

[0002] The complexity of mixed-signal chips is reflected in multiple core aspects such as design, manufacturing process, system integration, and verification. Furthermore, with the advancement of advanced processes and the expansion of application scenarios, this complexity increases exponentially, resulting in a significantly higher first-time fabrication failure rate compared to purely digital or purely analog chips. As a core component, analog-to-digital verification is crucial.

[0003] Numerical model verification currently faces several challenges, resulting in long verification cycles and significant manpower investment. These challenges mainly include simulation accuracy, verification efficiency, and coverage.

[0004] In mixed-signal chips, the analog portion requires transistor-level simulation to ensure accuracy, while the digital portion relies on high-level abstract simulation to improve speed. During full-chip-level simulation, the coordination of these different levels of abstraction leads to a surge in computation, potentially extending the verification cycle to several weeks. Reducing analog simulation accuracy to increase speed could introduce potential problems during tape-out. Failure scenarios in mixed-signal chips often stem from cross-domain interactions, such as interface timing mismatches and reset signal glitches. As the complexity of mixed-signal chips increases, insufficient coverage of extreme scenarios becomes increasingly likely.

[0005] In existing technologies, the general process of digital model verification is as follows: Figure 1 As shown:

[0006] 1. Analog circuit designers abstract the complex underlying analog circuits into behavioral-level code logic;

[0007] 2. After each analog circuit has behavioral-level code logic, the analog circuit designer integrates all the analog circuits and extracts them into an analog model;

[0008] 3. Digital circuit designers provide digital register transfer level code;

[0009] 4. Verification personnel integrate the analog model and digital register transfer level code on the verification platform and set up the verification environment;

[0010] 5. Verification personnel configure relevant registers and provide stimuli in the verification environment;

[0011] 6. After the simulation is completed, the verification personnel should check the output comparison and record the simulation data;

[0012] 7. Analyze the simulation data to see if the performance meets expectations. If it does not meet expectations, it is necessary to locate the problem. Possible problems include: analog circuit design errors, analog behavioral description errors, digital circuit design errors, register configuration errors, verification environment stimulus errors, algorithm design errors, etc.

[0013] Eliminate the above errors until the performance meets expectations; the digital model verification is then complete.

[0014] The above-mentioned numerical model verification technology has the following disadvantages:

[0015] I. Large-scale mixed-signal verification is slow in both compilation and simulation processes. Traditional verification methods cannot determine whether the performance is correct during simulation; the simulation results can only be checked through algorithm code or scripts after the simulation is completed to see if they meet expectations.

[0016] Second, when the simulation results do not meet expectations, it is necessary to correct the corresponding errors based on the possible problems. However, errors may be multifaceted, and it is impossible to correct all errors at once. Therefore, the entire verification process requires multiple iterations, which in turn lengthens the numerical model verification cycle.

[0017] Third, traditional verification methods can only observe the timing of individual signal waveforms. To pinpoint the exact location of the error, engineers need to perform manual calculations, resulting in low efficiency. Summary of the Invention

[0018] In view of this, embodiments of this application provide a digital model verification method and system based on real-time waveform dynamic analysis to solve the problems of numerous verification iterations, long verification cycles, and low positioning efficiency in the prior art.

[0019] Firstly, a digital-analog chip verification method based on real-time waveform dynamic analysis is provided, which is applied to a mixed-signal verification platform. The method includes the following steps:

[0020] The system acquires a mixed signal waveform data stream output by the chip under test in real time, wherein the mixed signal includes analog signals and digital signals;

[0021] Key performance indicators are calculated in real time from the waveform data stream, and the current performance status of the chip under test is evaluated based on the key performance indicators.

[0022] Based on the current performance state and the target performance state, an incentive adjustment strategy is dynamically generated.

[0023] According to the incentive adjustment strategy, the newly generated test incentives are switched and injected into the chip under test without interrupting the current chip under test verification.

[0024] In some implementations, the parameters of the key performance indicators include, but are not limited to, at least one or more: signal amplitude, frequency, and signal-to-noise ratio.

[0025] In some implementations, the dynamic generation of incentive adjustment strategies based on the current performance state and the target performance state specifically includes:

[0026] The current performance state is compared with the target performance state to calculate the performance deviation;

[0027] Based on the direction and degree of deviation, an incentive adjustment strategy is obtained, which includes the direction and magnitude of incentive adjustment.

[0028] In some implementations, the incentive adjustment strategy includes a preset feedback strategy, including negative feedback and / or positive feedback;

[0029] The negative feedback is as follows: when there is a negative deviation between the current performance state and the target performance state, an incentive adjustment strategy is generated to reduce the deviation.

[0030] The positive feedback is as follows: when there is a positive deviation between the current performance state and the target performance state, an incentive adjustment strategy is generated to amplify the deviation or accelerate the change in system state.

[0031] In some implementations, switching and injecting the generated new test stimulus into the chip under test specifically includes: adjusting the parameter adjustment amount of the stimulus signal in real time by updating the configuration register of the stimulus generator or calling new stimulus waveform data. The parameter adjustment amount of the stimulus signal is used to reduce or amplify the deviation and is calculated by a negative feedback control algorithm or a positive feedback control algorithm.

[0032] Secondly, embodiments of the present invention provide a digital-analog chip verification system based on real-time waveform dynamic analysis, comprising: a waveform monitoring module for real-time acquisition of mixed signal waveform data streams output by the chip under test, wherein the mixed signal includes analog signals and digital signals;

[0033] A performance analysis module, connected to the waveform monitoring module, is used to calculate key performance indicators in real time from the waveform data stream and evaluate the current performance status of the chip under test based on the key performance indicators.

[0034] The strategy decision module, connected to the performance analysis module, is used to dynamically generate incentive adjustment strategies based on the comparison results between the current performance state and the preset target performance state.

[0035] The stimulus injection module, connected to the strategy decision module, is used to adjust the strategy according to the stimulus, generate new test stimuli and switch to inject them into the chip under test without interrupting the current simulation.

[0036] The waveform monitoring module, performance analysis module, strategy decision module, and stimulus injection module constitute a closed-loop feedback verification architecture.

[0037] In some implementations, the parameters of the key performance indicators include, but are not limited to, at least one or more: signal amplitude, frequency, and signal-to-noise ratio.

[0038] In some implementations, the strategy decision module has a built-in preset feedback strategy, which includes negative feedback and / or positive feedback; wherein, the negative feedback is used to generate an incentive adjustment strategy to reduce the deviation when there is a negative deviation between the current performance state and the target performance state.

[0039] The positive feedback is used to generate an incentive adjustment strategy to amplify the deviation or accelerate the change of system state when there is a positive deviation between the current performance state and the target performance state.

[0040] In some implementations, the stimulus injection module includes a stimulus generator and a dynamic configuration interface;

[0041] The excitation generator is used to generate test excitation signals;

[0042] The dynamic configuration interface is used to adjust the parameter adjustment amount of the excitation signal in real time by updating the configuration register of the excitation generator or calling new excitation waveform data according to the excitation adjustment strategy.

[0043] Thirdly, embodiments of the present invention also provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method as described above.

[0044] The embodiments of the present invention described above can reduce the number of verification iterations and improve verification efficiency. Through a real-time feedback system, performance can be checked promptly to ensure it meets expectations. When simulation results do not meet expectations, the stimulus can be adjusted directly on the verification platform without repeating previous steps. All relevant signals are analyzed in real time to quickly locate the problem, improving localization efficiency and shortening the verification cycle. This contrasts with existing technologies that require waiting until the simulation is complete before checking the simulation results using algorithm code or scripts. Attached Figure Description

[0045] The accompanying drawings used in the description of the embodiments of this disclosure are briefly introduced below:

[0046] Figure 1 A schematic diagram of a general digital model verification method in the prior art is shown;

[0047] Figure 2The diagram shows a flowchart of a digital-to-analog chip verification method based on real-time waveform dynamic analysis provided in some embodiments of this application;

[0048] Figure 3a The diagram illustrates the interaction between digital and analog signals in a mixed-signal verification process within a digital-analog chip verification method based on real-time waveform dynamic analysis provided in some embodiments of this application.

[0049] Figure 3b This illustration shows a schematic diagram of histogram statistics of the output data of an FFE (feedforward equalizer) provided in some embodiments of this application;

[0050] Figure 4 This illustration shows another histogram statistical diagram of the output data of an FFE (feedforward equalizer) provided in some embodiments of this application;

[0051] Figure 5 This illustration shows another histogram statistical diagram of the output data of an FFE (feedforward equalizer) provided in some embodiments of this application;

[0052] Figure 6 The present application illustrates an analog signal eye diagram showing the initial stage of acquiring signals from an analog channel in real time from a waveform data real-time acquisition device, as provided in some embodiments of this application.

[0053] Figure 7 The present application provides simulated signal eye diagrams in analog channels after real-time excitation adjustment, as shown in some embodiments of this application.

[0054] Figure 8 The diagram shows a schematic of a digital-to-analog chip verification system based on real-time waveform dynamic analysis in some embodiments of this application;

[0055] Figure 9 This paper illustrates a schematic diagram of another analog-digital chip verification system based on real-time waveform dynamic analysis in some embodiments of this application;

[0056] Figure 10 A schematic diagram of the structure of an electronic device provided in some embodiments of this application is shown. Detailed Implementation

[0057] To more clearly illustrate the technical solutions in the embodiments of this disclosure, examples of implementation methods of this disclosure will be described below with reference to the accompanying drawings. The accompanying drawings described below are merely some embodiments of this disclosure. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without creative effort. Adjustments and improvements made without departing from the concept of this disclosure are all within the protection scope of this disclosure.

[0058] To keep the drawings simple, each figure only schematically shows the parts relevant to the embodiment, and they do not represent the actual structure of the product. In addition, for the sake of clarity and ease of understanding, some figures only schematically show parts of components with the same structure or function, and there may actually be more or fewer components with the same structure or function.

[0059] like Figure 2 As shown, this embodiment of the invention provides a digital-analog chip verification method based on real-time waveform dynamic analysis, applied to a mixed-signal verification platform. The method includes the following steps:

[0060] S1. Real-time acquisition of the mixed signal waveform data stream output by the chip under test, wherein the mixed signal includes analog signals and digital signals;

[0061] S2. Calculate key performance indicators from the waveform data stream in real time, and evaluate the current performance status of the chip under test based on the key performance indicators;

[0062] S3. Based on the current performance state and the target performance state, dynamically generate an incentive adjustment strategy;

[0063] S4. According to the incentive adjustment strategy, without interrupting the current chip under test verification, switch the generated new test incentive and inject it into the chip under test.

[0064] In this embodiment, the method is applied to a mixed-signal verification platform, and the specific steps are as follows:

[0065] The system acquires a mixed-signal waveform data stream output by the chip under test (DUT). The mixed signal includes analog and digital signals. Driven by an initial excitation signal, the DUT outputs a mixed waveform containing analog signals and digital modulation components. This waveform is continuously acquired at a sampling rate of 1 GS / s using a high-speed ADC in the platform and uploaded in real time to form a continuous waveform data stream.

[0066] Key performance indicators are calculated in real time from the waveform data stream, and the current performance status of the chip under test is evaluated based on the key performance indicators.

[0067] For example, digital-to-analog (DAC) verification is based on simulation verification using EDA tools. EDA tools provide interfaces, and Python scripts are written using these interfaces to collect data and then perform real-time analysis. The overall EDA simulation time is typically a maximum of 1ms, which can be modified to use a sliding window every 1µs of reception. This is because EDA simulation itself is very slow; it calculates a set of key performance indicators, including signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), and total harmonic distortion (THD). After calculation, the indicator values ​​are sent to a state evaluation unit and compared with preset performance thresholds. For example, if the current SNR is more than 3dB lower than the target value, the current DAC performance state is determined to be "high distortion".

[0068] Based on the current performance state and the target performance state, an incentive adjustment strategy is dynamically generated.

[0069] For example, if the signal is determined to be "too high distortion", the generation strategy is to reduce the amplitude of the input excitation signal and switch to frequency sweep mode.

[0070] If SFDR does not meet the target, the generation strategy is to increase the digital pre-emphasis coefficient in the stimulus and fine-tune the clock phase.

[0071] According to the excitation adjustment strategy, without interrupting the current verification of the chip under test, the newly generated test excitation is switched and injected into the chip under test. After receiving the new strategy, the excitation generation module immediately synthesizes a new excitation waveform (such as the adjusted amplitude and sweep frequency sequence) in the background, and completes the seamless switching of the excitation within the waveform frame interval (< 1μs) through a high-speed switching circuit, ensuring that the DAC verification process continues without the need for reset or interruption of the test. After switching, the next round of waveform acquisition and analysis immediately begins, forming a "acquisition-analysis-adjustment" closed loop.

[0072] This method can quickly locate problems and make timely adjustments in a single test, automatically completing dynamic optimization and multi-state verification of the DAC chip. It can solve the problems of multiple verification iterations, long verification cycles, and low location efficiency in existing technologies.

[0073] In some embodiments of the present invention, the method includes:

[0074] The system acquires a mixed signal waveform data stream output by the chip under test in real time, wherein the mixed signal includes analog signals and digital signals;

[0075] Key performance indicators are calculated in real time from the waveform data stream, and the current performance status of the chip under test is evaluated based on the key performance indicators.

[0076] The current performance state is compared with the target performance state to calculate the performance deviation;

[0077] Based on the direction and degree of deviation, an incentive adjustment strategy is obtained, which includes the direction and magnitude of incentive adjustment. The incentive adjustment strategy includes a preset feedback strategy, including negative feedback and / or positive feedback.

[0078] The negative feedback is as follows: when there is a negative deviation between the current performance state and the target performance state, an incentive adjustment strategy is generated to reduce the deviation.

[0079] The positive feedback is as follows: when there is a positive deviation between the current performance state and the target performance state, an incentive adjustment strategy is generated to amplify the deviation or accelerate the change of system state.

[0080] According to the incentive adjustment strategy, the newly generated test incentives are switched and injected into the chip under test without interrupting the current chip under test verification.

[0081] The specific implementation steps of the method described in the above embodiments are as follows:

[0082] The platform acquires the mixed-signal waveform data stream output by the chip under test (taking an RF transceiver chip as an example) in real time, and verifies that the RF transceiver chip under test is driven to operate in transmit mode. Its RF output is converted into an intermediate frequency signal by a down-conversion module after passing through a controllable attenuation network. Subsequently, it is simulated and verified using EDA tools. The advantage of EDA over FPGA is that simulation can directly view all internal data signals. Using the interface provided by EDA tools, these signals are acquired and post-processed to obtain performance indicators and form a real-time mixed-signal waveform data stream (including I / Q modulation signals, noise, and spurious components).

[0083] The performance analysis platform processes the waveform data stream in frames (10μs per frame). For each frame, multiple key performance indicators (KPIs) are calculated in parallel, including output power and carrier frequency accuracy.

[0084] The calculated EVM (current value -28 dB) and ACLR (current value -48 dBc) are used as core indicators and compared with preset performance state thresholds to determine that the chip is currently in a "critical performance state".

[0085] Compare the current performance metrics with the target performance status (e.g., EVM target is -32 dB, ACLR target is -50 dBc) and calculate the quantization deviation: ΔEVM = +4 dB (positive deviation, performance is better than the target), ΔACLR = -2 dBc (negative deviation, performance is worse than the target).

[0086] Based on a pre-defined feedback strategy library, the system generates a composite incentive adjustment strategy:

[0087] To address the negative bias in ACLR (performance not meeting standards), a negative feedback strategy is triggered: an adjustment strategy is generated to "reduce the bias." Specifically, the nonlinear correction coefficient of the digital predistortion (DPD) model in the excitation signal is increased by 15% to improve linearity and enhance ACLR performance.

[0088] For the positive deviation of the EVM (performance better than expected), a positive feedback strategy is triggered: an adjustment strategy is generated to "amplify the deviation or accelerate state changes". Specifically, in the next testing phase, the modulation order of the baseband signal is increased from 64-QAM to 256-QAM, and the symbol rate is increased by 5%.

[0089] According to the excitation adjustment strategy, a new test excitation is seamlessly switched and injected without interruption. Based on the above excitation adjustment strategy, a new test vector (including a DPD module with updated coefficients and a higher-order modulation signal) is seamlessly synthesized in the background. Through the excitation switching switch, the seamless switching between the old and new excitation signals is completed within the guard interval of two adjacent frames of waveform data. The switching process is transparent to the chip under test; its power supply, clock, and status are not interrupted, and the verification process continues. Subsequently, the system immediately acquires and analyzes the output waveform under the new excitation, forming a closed-loop adaptive verification loop.

[0090] The following is in conjunction with the appendix Figure 3a and 3b Taking mixed-signal verification as an example, the positive and negative feedback of this invention will be described as follows:

[0091] like Figure 3a As shown, taking the SERDES chip as an example, the block diagram of the interaction between digital and analog signals in mixed-signal verification is as follows:

[0092] The digital transmitter sends a digital signal, the analog DAC converts the digital signal back to an analog signal, the analog signal attenuates as it passes through the channel model, and the digital ADC converts the analog signal back to a digital signal. Because the signal attenuates as it passes through the channel model, the digital receiver needs to compensate for this attenuation by adjusting the FFE coefficients, which is called sliding window statistics.

[0093] The digital receiver FFE can store the data in real time and then perform actions such as... Figure 3b The image.

[0094] The performance metrics are the amplitude and signal-to-noise ratio mentioned earlier, which can be obtained from the FFE at the digital receiver. The FFE coefficient adjustment strategy is roughly a negative feedback process, and the configuration can be sent down through the bus interface.

[0095] The overall metric in digital-analog verification is to connect the digital and analog data together and ensure that the final eye diagram or signal-to-noise ratio meets expectations. If there is a problem with the intermediate analog signal, the final eye diagram or signal-to-noise ratio will be lower than expected.

[0096] Figure 3b On the left is the ADC data acquired by the real-time waveform data acquisition device and displayed on the performance analysis platform. Figure 3b The right side shows the results of histogram statistics and analysis of the output data of the FFE (feedforward equalizer).

[0097] Specifically, in the data receiving direction, the ADC data from the analog circuit needs to be compensated by the FFE (feedforward equalizer) at the digital receiver.

[0098] In the initial verification phase, the verification team used the analysis platform to adjust the incentives in real time to achieve rapid data convergence.

[0099] The following explains the basic steps for adjusting feedback incentives:

[0100] 1. Set the initial FFE coefficients and send them to the digital configuration. Figure 3b The ADC data on the left is selected by sliding a window to perform histogram statistics, resulting in... Figure 3b The statistical results on the right show that the data is mixed together, and when the signal-to-noise ratio register is read back, the signal-to-noise ratio is very low, indicating that the FFE coefficients are not achieving a balancing effect. It can be observed that the FFE output data value ranges from -100 to +100, while the ideal range for the FFE output data value is -64 to +64. Therefore, the main tap coefficient value needs to be reduced.

[0101] 2. Try reducing the main tap coefficient value. Observe that the FFE output data value ranges from -80 to +80, and you can see... Figure 4 The histogram on the right shows the trend of four data bars.

[0102] 3. Further configuring the main tap coefficient value to a smaller value, we observed that the FFE output data value range was now between -64 and +64. Figure 5 The histogram on the right shows four bars. At the same time, the signal-to-noise ratio register is read back. At this time, the signal-to-noise ratio is very high, which is consistent with the normal signal transmission characteristics.

[0103] Among them, the signal-to-noise ratio data can be directly extracted from the waveform data in the digital code.

[0104] Regarding the data transmission direction, let's take the adjustment of the digital transmitter coefficient of the mixed-signal chip as an example:

[0105] In the initial stage of the simulation, a basic coefficient configuration is predefined, and signals from the analog channel are acquired in real time from a waveform data acquisition device. The eye diagram of the analog signal in the initial stage is as follows: Figure 6 By adjusting the digital transmitter coefficients in real time through a performance analysis platform, the eye diagram opening effect is ultimately achieved, such as... Figure 7 As shown.

[0106] The adjustment of digital transmitter coefficients is generally provided by a positive feedback algorithm link. The basic idea is to calculate the attenuation characteristics based on the acquired signal's spectral response, and finally convert this attenuation characteristic into the transmitter coefficients. Therefore, a dynamic excitation adjustment platform can also embed a mature digital-to-analog algorithm link.

[0107] The embodiments of the present invention described above can reduce the number of verification iterations and improve verification efficiency. Through a real-time feedback system, performance can be checked promptly to ensure it meets expectations. When simulation results do not meet expectations, the stimulus can be adjusted directly on the verification platform without repeating previous steps. All relevant signals are analyzed in real time to quickly locate the problem, improving localization efficiency and shortening the verification cycle. This contrasts with existing technologies that require waiting until the simulation is complete before checking the simulation results using algorithm code or scripts.

[0108] In one implementation, such as Figure 8 As shown, this embodiment of the invention also provides a digital-analog chip verification system based on real-time waveform dynamic analysis, comprising:

[0109] The waveform monitoring module 100 is used to acquire the mixed signal waveform data stream output by the chip under test in real time.

[0110] The performance analysis module 200, connected to the waveform monitoring module 100, is used to calculate key performance indicators in real time from the waveform data stream and evaluate the current performance status of the chip under test based on the key performance indicators.

[0111] The strategy decision module 300, connected to the performance analysis module 200, is used to dynamically generate incentive adjustment strategies based on the comparison results between the current performance state and the preset target performance state.

[0112] The stimulus injection module 400 is connected to the strategy decision module 300 and is used to adjust the strategy according to the stimulus, generate new test stimuli and switch to inject them into the chip under test without interrupting the current simulation.

[0113] The waveform monitoring module 100, performance analysis module 200, strategy decision module 300, and stimulus injection module 400 constitute a closed-loop feedback verification architecture.

[0114] The parameters of the key performance indicators include, but are not limited to, at least one or more: signal amplitude, frequency, and signal-to-noise ratio.

[0115] Specifically, this embodiment is a system embodiment corresponding to the above method embodiment. For specific effects, please refer to the above method embodiment, which will not be repeated here.

[0116] Based on the foregoing embodiments, the strategy decision module 300 has a built-in preset feedback strategy, which includes negative feedback and / or positive feedback; wherein, the negative feedback is used to generate an incentive adjustment strategy to reduce the deviation when there is a negative deviation between the current performance state and the target performance state.

[0117] The positive feedback is used to generate an incentive adjustment strategy to amplify the deviation or accelerate the change of system state when there is a positive deviation between the current performance state and the target performance state.

[0118] The stimulus injection module 400 includes a stimulus generator and a dynamic configuration interface;

[0119] The excitation generator is used to generate test excitation signals;

[0120] The dynamic configuration interface is used to adjust the parameter adjustment amount of the excitation signal in real time by updating the configuration register of the excitation generator or calling new excitation waveform data according to the excitation adjustment strategy.

[0121] The block diagram of the above-mentioned digital model verification system based on real-time waveform dynamic analysis is as follows: Figure 9 As shown, after preparing the simulation model and digital register transfer level code, the following components are integrated into the verification platform:

[0122] The waveform data real-time acquisition device, namely the waveform monitoring module 100, can acquire circuit signals in real time according to the interface reserved by the EDA tool; the performance analysis module 200 comprehensively analyzes all signal waveforms and extracts key performance indicators. The key performance indicators generally refer to signal amplitude or signal-to-noise ratio, or other core indicators selected according to the function or design characteristics of different chips.

[0123] The strategy decision module 300 is used to send a dynamic adjustment command to the stimulus generator according to the key performance indicators. The stimulus generator is used to adjust the register configuration and data stimulus according to the key performance indicators, generate stimulus data and send it to the digital-to-analog chip under test.

[0124] Optionally, the stimulus injection module 400 includes:

[0125] The manual interaction interface allows verification personnel to manually adjust the incentives based on the key performance indicators and send the adjusted indicators to the incentive generator via the dynamic adjustment command.

[0126] In fact, the ways to adjust incentives include:

[0127] The human-interaction platform is adjusted to automatically generate dynamic adjustment commands for the stimulus generator in real time for situations requiring rapid response or known closed-loop feedback logic.

[0128] In other words, in a specific implementation environment, verification personnel manually adjust the incentives based on known performance indicators through a human interaction platform. For example, based on a negative feedback mechanism, if the amplitude is too large, the coefficient is adjusted to be smaller; if the amplitude is too small, the coefficient is adjusted to be larger.

[0129] Alternatively, through automated adjustment, for applications requiring fast response times or with known closed-loop feedback logic, this automated adjustment platform can be selected to automatically adjust to the optimal stimulus in real time, such as adjusting the signal-to-noise ratio to the expected level, for example, reaching 28dB or higher.

[0130] The above division of units is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, these units can be implemented by a processor calling software; for example, a signal processing device includes a processor connected to a memory containing instructions. The processor calls the instructions stored in the memory to implement any of the above methods or to realize the functions of each unit. The processor can be, for example, a general-purpose processor, such as a central processing unit (CPU), and the memory can be internal or external to the device. Alternatively, these units can be implemented as hardware circuits. The functions of some or all units can be implemented through the design of the hardware circuit, which can be understood as one or more processors. For example, in some embodiments, the hardware circuit is an application-specific integrated circuit (ASIC), which implements the functions of some or all units by designing the logical relationships between the components within the circuit. In another implementation, the hardware circuit can be implemented using a programmable logic device (PLD), which can include a large number of logic gates. The logical relationships between the logic gates are configured through a configuration file, thereby realizing the functions of some or all units. All units of the above devices can be implemented entirely through processor calling programs, or entirely through hardware circuits, or partially through processor calling programs with the remaining parts implemented through hardware circuits.

[0131] Based on the same technical concept, this application also provides an electronic device, such as... Figure 10As shown in the figure, an embodiment of this application provides a computing device 1000, which includes a processor or calculator (not shown) 1001 and a memory 1002. The processor or calculator 1001 and the memory 1002 can be interconnected via a communication bus 1003. The communication bus 1003 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus 1003 can be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, the memory 1002 is used to store a computer program, which includes program instructions. The processor 1001 is configured to call the program instructions, and the program includes steps for executing some or all of the steps in the aforementioned methods.

[0132] The processor 1001 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of the above-mentioned program.

[0133] The memory 1002 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or it may be an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto. The memory may exist independently and be connected to the processor via a bus. The memory may also be integrated with the processor.

[0134] The computing device 1000 may further include a communication module 1004 and a display 1005. The communication module 1004 can communicate with the optical tracking device. The communication module 1004 can be a wireless communication module (e.g., a WiFi module, a Bluetooth module, etc.) or a wired communication module.

[0135] In addition, the computing device 1000 may also include general components such as communication interfaces (e.g., USB interfaces, microphone interfaces, etc.) and antennas, which will not be described in detail here.

[0136] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0137] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0138] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another apparatus, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical or other forms.

[0139] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0140] Furthermore, the functional units in the various embodiments of the application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software program module.

[0141] If the integrated unit is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0142] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage device, which may include: a flash drive, a read-only memory, a random access memory, a magnetic disk, or an optical disk, etc.

[0143] The embodiments of this application have been described in detail above. Specific examples have been used in the embodiments of this invention to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

[0144] It should be noted that the above embodiments can be freely combined as needed. The above are merely preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for verifying analog-digital chips based on real-time waveform dynamic analysis, characterized in that, Applied to a mixed-signal verification platform, the method includes the following steps: The system acquires the mixed signal waveform data stream output by the chip under test in real time. The mixed signal includes analog and digital signals. The digital signal is sent by the digital transmitter of the chip under test. The digital-to-analog converter (DAC) converts the digital signal into an analog signal. The analog signal is attenuated by the channel model. The analog-to-digital converter (ADC) converts the analog signal into a digital signal. The waveform data stream is acquired from the digital receiver FFE and key performance indicators are calculated in real time. The current performance status of the chip under test is evaluated based on the key performance indicators. Based on the current performance state and the target performance state, an incentive adjustment strategy is dynamically generated, specifically including: comparing the current performance state with the target performance state to calculate the performance deviation; and obtaining an incentive adjustment strategy including the direction and magnitude of incentive adjustment according to the direction and degree of the deviation. The incentive adjustment strategy includes preset feedback strategies, including negative feedback and positive feedback. The negative feedback generates an incentive adjustment strategy to reduce the deviation when there is a negative deviation between the evaluated current performance state and the target performance state, while the positive feedback generates an incentive adjustment strategy to amplify the deviation or accelerate system state changes when there is a positive deviation between the evaluated current performance state and the target performance state. According to the excitation adjustment strategy, without interrupting the current chip under test verification, the newly generated test excitation is switched and injected into the chip under test. Specifically, switching and injecting the newly generated test excitation into the chip under test includes: adjusting the parameter adjustment amount of the excitation signal in real time by updating the configuration register of the excitation generator or calling new excitation waveform data. The parameter adjustment amount of the excitation signal is used to reduce or amplify the deviation and is calculated by a negative feedback control algorithm or a positive feedback control algorithm.

2. The digital-analog chip verification method based on real-time waveform dynamic analysis according to claim 1, characterized in that, The parameters of the key performance indicators include, but are not limited to, at least one or more: signal amplitude, frequency, and signal-to-noise ratio.

3. A digital-analog chip verification system based on real-time waveform dynamic analysis, characterized in that, include: The waveform monitoring module is used to acquire the mixed signal waveform data stream output by the chip under test in real time. The mixed signal includes analog signals and digital signals. The digital signal is sent by the digital transmitter of the chip under test. The digital-to-analog converter (DAC) converts the digital signal into an analog signal. The analog signal is attenuated after passing through the channel model. The analog-to-digital converter (ADC) converts the analog signal into a digital signal. The performance analysis module, connected to the waveform monitoring module, is used to acquire the waveform data stream from the digital receiver FFE and calculate key performance indicators in real time, and evaluate the current performance status of the chip under test based on the key performance indicators. The strategy decision module, connected to the performance analysis module, is used to dynamically generate an incentive adjustment strategy based on the comparison result between the current performance state and the preset target performance state. Specifically, it includes: comparing the current performance state with the target performance state to calculate the performance deviation; and obtaining an incentive adjustment strategy including the direction and magnitude of incentive adjustment according to the direction and degree of the deviation. The strategy decision module has a built-in preset feedback strategy, which includes negative feedback and positive feedback. The negative feedback is used to generate an incentive adjustment strategy to reduce the deviation when there is a negative deviation between the current performance state and the target performance state. The positive feedback is used to generate an incentive adjustment strategy to amplify the deviation or accelerate the change of system state when there is a positive deviation between the current performance state and the target performance state. An excitation injection module, connected to the strategy decision module, is used to generate new test stimuli and switch to inject them into the chip under test according to the excitation adjustment strategy without interrupting the current simulation. The excitation injection module includes an excitation generator and a dynamic configuration interface. The excitation generator is used to generate test excitation signals. The dynamic configuration interface is used to adjust the parameter adjustment amount of the excitation signal in real time according to the excitation adjustment strategy by updating the configuration register of the excitation generator or calling new excitation waveform data. The parameter adjustment amount of the excitation signal is used to reduce or amplify the deviation and is calculated by a negative feedback control algorithm or a positive feedback control algorithm. The waveform monitoring module, performance analysis module, strategy decision module, and stimulus injection module constitute a closed-loop feedback verification architecture.

4. The digital-analog chip verification system based on real-time waveform dynamic analysis according to claim 3, characterized in that, The parameters of the key performance indicators include, but are not limited to, at least one or more: signal amplitude, frequency, and signal-to-noise ratio.

5. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method as described in claim 1 or 2.

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