Power supply driving circuit of display panel

Abstract

The invention relates to a power supply driving circuit of a display panel. The power supply driving circuit comprises a time sequence control circuit unit, a first power supply management circuit unit, a second power supply management circuit unit and a line unit, the time sequence control circuit unit is electrically connected with the first power supply management circuit unit and the second power supply management circuit unit so as to receive the time sequence control signal. The line unit is electrically connected with the first power management circuit unit and the second power management circuit unit, and is electrically connected to the plurality of line unit output ports after being connected in parallel with a first output port of the first power management circuit unit and a second output port of the second power management circuit unit. Therefore, the current flow is increased, enough thrust is provided for the rear end, the cost caused by excessive design is avoided, and the power management circuit unit can be applied to various panel unit products through a power management circuit unit of a single specification.

Description

Technical Field

[0001] This invention relates to a power drive circuit, and more particularly to a power drive circuit for a display panel. Background Technology

[0002] A power driver circuit is a type of power management integrated circuit (PMIC). The function of this PMIC is to control the power and flow of the power supply to meet the needs of various downstream electronic devices. A typical PMIC provides power conversion, power management, and current control and protection mechanisms within its architecture. Power conversion transforms the input voltage into a stable voltage required by various downstream devices. Power management dynamically adjusts power based on device operating conditions to save power. Current control and protection mechanisms provide precise current control and incorporate current protection, temperature control, and short-circuit protection mechanisms to ensure system safety.

[0003] like Figure 9 As shown, the power drive circuit architecture of a display panel typically includes a timing control circuit unit 50, a power management circuit unit 60, and a panel unit 70. The timing control circuit unit 50 is a timing controller IC (TCON). The power management circuit unit 60 is a power management integrated circuit. The panel unit 70 has a display driver circuit 71 and a display panel 72. The timing control circuit unit 50 is electrically connected to the power management circuit unit 60 and outputs a timing control signal to the power management circuit unit 60. The power management circuit unit 60 is electrically connected to the panel driver circuit 71 and outputs a power management signal to the panel driver circuit 71. The panel driver circuit 71 is electrically connected to the display panel 72 and outputs a drive signal to the display panel 72, allowing the display panel 72 to display an image according to the drive signal.

[0004] Generally, the function of the power management circuit unit 60 is to provide a stable voltage to the backend panel unit 70. However, when applied to panel units 70 of different products or sizes, the voltage or current of the power drive signal output by the power management circuit unit 60 will be affected by the differences in the capacitive reactance and impedance of the panel unit 70. For example, when the power management circuit unit 60 is applied to a high-load panel unit 70 with high capacitive reactance or high impedance, the complexity of the internal architecture of the power management circuit unit 60 also increases. Therefore, when developing products with panel units 70 for different applications, different power management circuit units 60 need to be designed according to specifications, resulting in over-design of the power management circuit unit 60, which also increases the overall cost. Summary of the Invention

[0005] In view of the fact that existing products for developing panel units for different applications require the design of different power management circuit units according to specifications, resulting in an increase in overall cost, the present invention provides a power driving circuit for display panels, so that a single power management circuit unit can be applied to a variety of panel unit products.

[0006] One embodiment of the power drive circuit for the display panel includes a timing control circuit unit, a first power management circuit unit, a second power management circuit unit, and a line unit. The first power management circuit unit has a first input port and several first output ports. The first input port is electrically connected to the timing control circuit unit to receive a timing control signal. The second power management circuit unit has a second input port and several second output ports. The second input port is electrically connected to the timing control circuit unit to receive the timing control signal. The line unit has several first line unit input ports, several second line unit input ports, and several line unit output ports. The several first line unit input ports are respectively electrically connected to the several first output ports, and the several second line unit input ports are respectively electrically connected to the several second output ports to receive several power management signals output by the first power management circuit unit and the second power management circuit unit. The line unit is electrically connected to the line unit output ports via the plurality of first line unit input ports and the plurality of second line unit input ports, which are then connected in parallel to the plurality of first output ports of the first power management circuit unit and the plurality of second output ports of the second power management circuit unit. The plurality of line unit output ports are powered to a panel unit and output a parallel drive signal to the panel unit.

[0007] Another embodiment of the power drive circuit of the display panel includes a timing control circuit unit, a first power management circuit unit, a second power management circuit unit, and a line unit. The first power management circuit unit has a first input port and several first output ports. The first input port is electrically connected to the timing control circuit unit to receive a timing control signal. The line unit has several first line unit input ports and several line unit output ports. The several first line unit input ports are respectively electrically connected to the several first output ports to receive several power management signals output by the first power management circuit unit and the second power management circuit unit. The several first output ports of the first power management circuit unit include at least a first output terminal, a second output terminal, a third output terminal, and a fourth output terminal. The several line unit output ports of the line unit include at least a first line unit output terminal and a second line unit output terminal. The line unit is electrically connected to the output terminal of the first line unit after being connected in parallel to the first output terminal and the second output terminal of the first power management circuit unit through the plurality of first line unit input ports. The line unit is also electrically connected to the output terminal of the second line unit after being connected in parallel to the third output terminal and the fourth output terminal of the first power management circuit unit through the plurality of first line unit input ports. The output ports of the plurality of line units are powered and connected to a panel unit, and output a parallel drive signal to the panel unit.

[0008] Because this circuit unit can adjust the connection relationship of the input ports of the first circuit unit and the input ports of the second circuit unit in parallel, when the load of the panel unit at the back end is too large, causing the current originally provided by the first power management circuit unit and the second power management circuit unit to be insufficient, the circuit unit can increase the current flow by connecting the first output ports and the second output ports of the first power management circuit unit and the second power management circuit unit in parallel, so as to provide sufficient thrust to the display panel at the back end without redesigning a new power management circuit unit to drive the panel unit with an excessive load. This avoids the cost caused by over-design and allows a single power management circuit unit to be applied to a variety of panel unit products. Attached Figure Description

[0009] Figure 1 This is a block diagram of the power drive circuit of the display panel of the present invention.

[0010] Figure 2 This is a block diagram of a first embodiment of the power drive circuit for the display panel of the present invention.

[0011] Figure 3 This is a block diagram of a second embodiment of the power drive circuit for the display panel of the present invention.

[0012] Figure 4 This is a block diagram of a third embodiment of the power drive circuit for the display panel of the present invention.

[0013] Figure 5 This is a block diagram of the fourth embodiment of the power drive circuit for the display panel of the present invention.

[0014] Figure 6 This is a block diagram of the fifth embodiment of the power drive circuit for the display panel of the present invention.

[0015] Figure 7 This is a block diagram of the sixth embodiment of the power drive circuit for the display panel of the present invention.

[0016] Figure 8 This is a block diagram of the seventh embodiment of the power drive circuit for the display panel of the present invention.

[0017] Figure 9 This is a block diagram of the power drive circuit architecture of an existing display panel. Detailed Implementation

[0018] Please see Figure 1 As shown, the power driving circuit of the display panel of the present invention includes a timing control circuit unit 10, a first power management circuit unit 21, a second power management circuit unit 22, and a line unit 30.

[0019] The first power management circuit unit 21 has a first input port 210 and several first output ports 211. The first input port 210 is electrically connected to the timing control circuit unit 10 to receive a timing control signal. The second power management circuit unit 22 has a second input port 220 and several second output ports 221. The second input port 220 is electrically connected to the timing control circuit unit 10 to receive a timing control signal. The line unit 30 has several first line unit input ports 310, several second line unit input ports 320, and several line unit output ports 330. The several first line unit input ports 310 are respectively electrically connected to the several first output ports 211, and the several second line unit input ports 320 are respectively electrically connected to the several second output ports 221 to receive several power management signals output by the first power management circuit unit 21 and the second power management circuit unit 22.

[0020] The line unit 30 is connected in parallel to the first output ports 211 of the first power management circuit unit 21 and the second output ports 221 of the second power management circuit unit 22 via the plurality of first line unit input ports 310 and the plurality of second line unit input ports 320, and then electrically connected to the plurality of line unit output ports 330. The plurality of line unit output ports 330 are powered to a panel unit 40 and output a parallel drive signal to the panel unit 40.

[0021] The line unit 30 can connect the plurality of first line unit input ports 310 and the plurality of second line unit input ports 320 in parallel, and output the parallel power management signal through the plurality of line unit output ports 330 in a parallel manner. In this way, when the back-end panel unit 40 is a large panel with a large load, and the current originally provided by the first power management circuit unit 21 or the second power management circuit unit 22 is insufficient to meet the demand, the line unit 30 can connect the plurality of first output ports 211 and the plurality of second output ports 221 of the first power management circuit unit 21 and the second power management circuit unit 22 in parallel, thereby increasing the output current flow and providing sufficient thrust to the back-end panel unit 40 without redesigning a new power management circuit unit to drive the panel unit 40 with an excessive load. This avoids the cost caused by over-design and allows a single specification of power management circuit unit to be applied to a variety of panel unit 40 products.

[0022] Please see Figure 2 As shown, in a first embodiment, the plurality of first output ports 211 of the first power management circuit unit 21 include at least a first main output terminal 2111 and a second main output terminal 2112. The plurality of second output ports 221 of the second power management circuit unit 22 include at least a first slave output terminal 2211 and a second slave output terminal 2212. The plurality of first line unit input ports 310 of the line unit 30 include at least a first line unit main input terminal 311 and a second line unit main input terminal 312, and the plurality of second line unit input ports 320 include at least a first line unit slave input terminal 321 and a second line unit slave input terminal 322. The plurality of line unit output ports 330 of the line unit 30 include at least a first line unit output terminal 331 and a second line unit output terminal 332.

[0023] The first main output terminal 2111 of the first power management circuit unit 21 is electrically connected to the first main input terminal 311 of the line unit 30, and the second main output terminal 2112 of the first power management circuit unit 21 is electrically connected to the second main input terminal 312 of the line unit 30. The first slave output terminal 2211 of the second power management circuit unit 22 is electrically connected to the first slave input terminal 321 of the line unit 30, and the second slave output terminal 2212 of the second power management circuit unit 22 is electrically connected to the second slave input terminal 322 of the line unit 30.

[0024] The line unit 30 is connected in parallel with the first main output terminal 2111 and the first slave output terminal 2211, and is then electrically connected to the first line unit output terminal 331. The line unit 30 is also connected in parallel with the second main output terminal 2112 and the second slave output terminal 2212, and is then electrically connected to the second line unit output terminal 332.

[0025] In this embodiment, the line unit 30 is a line unit with directly parallel outputs. The first power management circuit unit 21 serves as a master power management circuit unit, and the second power management circuit unit 22 serves as a slave power management circuit unit. When the power drive circuit of the display panel has three or more power management circuit units, one of them is selected as the master power management circuit unit, and the remaining power management circuit units serve as slave power management circuit units.

[0026] In the embodiment of the directly parallel output line unit 30, a device address is defined for the main power management circuit unit, such as the first power management circuit unit 21. Only when the main power management circuit unit receives an instruction matching this address and completes the instruction will it reply with an acknowledgment (ACK), such as the first acknowledgment signal. The remaining slave power management circuit units are silent devices, such as the second power management circuit unit 22, which only accepts writes and does not allow reads. Because of the unreadable nature of the slave power management circuit units, their protection mechanism operates in a linked manner. For example, when a power management circuit unit triggers its protection mechanism, the remaining power management circuit units will be shut down sequentially. The outputs of the main power management circuit unit and the slave power management circuit units are connected in parallel to the back-end panel unit 40. Due to the increased current flow under parallel connection, the requirements of the high-load back-end panel unit 40 can be met.

[0027] Furthermore, in this embodiment, the first power management circuit unit 21 further includes a first interrupt signal output terminal 212, and the first interrupt signal output terminal 212 is electrically connected to the timing control circuit unit 10 to output a first interrupt signal to the timing control circuit unit 10. For example, the first interrupt signal output terminal 212 is an INTB output terminal, used to output an INTB signal.

[0028] Please see Figure 3 As shown, in a second embodiment, the plurality of first output ports 211 of the first power management circuit unit 21 include at least a first main output terminal 2111, a second main output terminal 2112, a third main output terminal 2113, and a fourth main output terminal 2114. The plurality of second output ports 221 of the second power management circuit unit 22 include at least a first slave output terminal 2211, a second slave output terminal 2212, a third slave output terminal 2213, and a fourth slave output terminal 2214. The plurality of first line unit input ports 310 of the line unit 30 includes at least one first line unit main input terminal 311, one second line unit main input terminal 312, one third line unit main input terminal 313, and one fourth line unit main input terminal 314, and the plurality of second line unit input ports 320 includes at least one first line unit slave input terminal 321, one second line unit slave input terminal 322, one third line unit slave input terminal 323, and one fourth line unit slave input terminal 324. The plurality of line unit output ports 330 of the line unit 30 includes at least one first line unit output terminal 331, one second line unit output terminal 332, one third line unit output terminal 333, and one fourth line unit output terminal 334.

[0029] The first main output terminal 2111 of the first power management circuit unit 21 is electrically connected to the first main input terminal 311 of the line unit 30, the second main output terminal 2112 of the first power management circuit unit 21 is electrically connected to the second main input terminal 312 of the line unit 30, the third main output terminal 2113 of the first power management circuit unit 21 is electrically connected to the third main input terminal 313 of the line unit 30, and the fourth main output terminal 2114 of the first power management circuit unit 21 is electrically connected to the fourth main input terminal 314 of the line unit 30. The first slave output terminal 2211 of the second power management circuit unit 22 is electrically connected to the first line unit slave input terminal 321 of the line unit 30, the second slave output terminal 2212 of the second power management circuit unit 22 is electrically connected to the second line unit slave input terminal 322 of the line unit 30, the third slave output terminal 2213 of the second power management circuit unit 22 is electrically connected to the third line unit slave input terminal 323 of the line unit 30, and the fourth slave output terminal 2214 of the second power management circuit unit 22 is electrically connected to the fourth line unit slave input terminal 324 of the line unit 30.

[0030] The line unit 30 is connected in parallel with the first main output terminal 2111 and the first slave output terminal 2211, and is electrically connected to the first line unit output terminal 331. The line unit 30 is connected in parallel with the second main output terminal 2112 and the second slave output terminal 2212, and is electrically connected to the second line unit output terminal 332. The line unit 30 is connected in parallel with the third main output terminal 2113 and the third slave output terminal 2213, and is electrically connected to the third line unit output terminal 333. The line unit 30 is connected in parallel with the fourth main output terminal 2114 and the fourth slave output terminal 2214, and is electrically connected to the fourth line unit output terminal 334.

[0031] In this embodiment, the line unit 30 is also a line unit 30 with direct parallel output. The first power management circuit unit 21 serves as a master power management circuit unit, and the second power management circuit unit 22 serves as a slave power management circuit unit.

[0032] Similarly, in the embodiment of the output direct parallel type line unit 30, only the first power management circuit unit 21, which is the main power management circuit unit, needs to reply with the response signal when it receives and completes the instruction.

[0033] Similarly, in this embodiment, the first power management circuit unit 21 further includes a first interrupt signal output terminal 212, and the first interrupt signal output terminal 212 is electrically connected to the timing control circuit unit 10 to output a first interrupt signal to the timing control circuit unit 10.

[0034] Please see Figure 4 As shown, in a third embodiment, the plurality of first output ports 211 of the first power management circuit unit 21 include at least one first output terminal 2111 and one second output terminal 2112. The plurality of second output ports 221 of the second power management circuit unit 22 include at least one first output terminal 2211 and one second output terminal 2212. The plurality of line unit output ports 330 of the line unit 30 include at least one first line unit output terminal 331 and one second line unit output terminal 332. The plurality of first line unit input ports 310 of the line unit 30 include at least one first line unit input terminal 311 and one second line unit input terminal 312, and the plurality of second line unit input ports 320 include at least one first line unit input terminal 321 and one second line unit input terminal 322.

[0035] The first output terminal 2111 of the first power management circuit unit 21 is electrically connected to the first line unit input terminal 311 of the plurality of first line unit input ports 310 of the line unit 30, and the second output terminal 2112 of the first power management circuit unit 21 is electrically connected to the second line unit input terminal 312 of the plurality of first line unit input ports 310 of the line unit 30. The first output terminal 2211 of the second power management circuit unit 22 is electrically connected to the first line unit input terminal 321 of the plurality of second line unit input ports 320 of the line unit 30, and the second output terminal 2212 of the second power management circuit unit 22 is electrically connected to the second line unit input terminal 322 of the plurality of second line unit input ports 320 of the line unit 30.

[0036] The line unit 30 is connected in parallel to the first output terminal 2111 and the second output terminal 2112 of the first power management circuit unit 21, and is then electrically connected to the output terminal 331 of the first line unit. The line unit 30 is also connected in parallel to the first output terminal 2211 and the second output terminal 2212 of the second power management circuit unit 22, and is then electrically connected to the output terminal 332 of the second line unit.

[0037] In this embodiment, the line unit 30 is a combined channel type line unit 30. This line unit 30 is used to control the merging of output channels. Each power management circuit unit has an independent address. When an instruction matches the address of the corresponding device, the corresponding device executes the instruction and replies with a response signal upon completion. Because each power management circuit unit has an independent address, the protection mechanism is also independent. When a power management circuit unit triggers its protection mechanism, that power management circuit unit will be independently shut down. Since the line unit 30 can control the number of channel merges, as the number of merged channels increases, the power flow also increases to meet the needs of the panel unit 40 at high loads.

[0038] Furthermore, in this embodiment, the first power management circuit unit further includes a first interrupt signal output terminal 212, and the first interrupt signal output terminal 212 is electrically connected to the timing control circuit unit 10 to output a first interrupt signal to the timing control circuit unit 10. The second power management circuit unit 22 further includes a second interrupt signal output terminal 222, and the second interrupt signal output terminal 222 is electrically connected to the timing control circuit unit 10 to output a second interrupt signal to the timing control circuit unit. For example, the first interrupt signal output terminal 212 and the second interrupt signal output terminal 222 are each an INTB output terminal, used to output an INTB signal.

[0039] Please see Figure 5 As shown, in a fourth embodiment, the plurality of first output ports 211 of the first power management circuit unit 21 include at least a first output terminal 2111, a second output terminal 2112, a third output terminal 2113, and a fourth output terminal 2114. The plurality of second output ports 221 of the second power management circuit unit 22 include at least a first output terminal 2211, a second output terminal 2212, a third output terminal 2213, and a fourth output terminal 2214. The plurality of line unit output ports 330 of the line unit 30 include at least a first line unit output terminal 331, a second line unit output terminal 332, a third line unit output terminal 333, and a fourth line unit output terminal 334.

[0040] The plurality of first line unit input ports 310 of the line unit 30 include at least a first line unit input terminal 311, a second line unit input terminal 312, a third line unit input terminal 313 and a fourth line unit input terminal 314, and the plurality of second line unit input ports 320 include at least a first line unit input terminal 321, a second line unit input terminal 322, a third line unit input terminal 323 and a fourth line unit input terminal 324.

[0041] The first output terminal 2111 of the first power management circuit unit 21 is electrically connected to the first line unit input terminal 311 of the plurality of first line unit input ports 310 of the line unit 30. The second output terminal 2112 of the first power management circuit unit 21 is electrically connected to the second line unit input terminal 312 of the plurality of first line unit input ports 310 of the line unit 30. The third output terminal 2113 of the first power management circuit unit 21 is electrically connected to the third line unit input terminal 313 of the plurality of first line unit input ports 310 of the line unit 30. The fourth output terminal 2114 of the first power management circuit unit 21 is electrically connected to the fourth line unit input terminal 314 of the plurality of first line unit input ports 310 of the line unit 30. The first output terminal 2211 of the second power management circuit unit 22 is electrically connected to the first line unit input terminal 321 of the plurality of second line unit input ports 320 of the line unit 30; the second output terminal 2212 of the second power management circuit unit 22 is electrically connected to the second line unit input terminal 322 of the plurality of second line unit input ports 320 of the line unit 30; the third output terminal 2213 of the second power management circuit unit 22 is electrically connected to the third line unit input terminal 323 of the plurality of second line unit input ports 320 of the line unit 30; and the fourth output terminal 2214 of the second power management circuit unit 22 is electrically connected to the fourth line unit input terminal 324 of the plurality of second line unit input ports 320 of the line unit 30.

[0042] The line unit 30 is connected in parallel to the first output terminal 2111 and the second output terminal 2112 of the first power management circuit unit 21, and is then electrically connected to the first line unit output terminal 331. The line unit 30 is connected in parallel to the third output terminal 2113 and the fourth output terminal 2114 of the first power management circuit unit 21, and is then electrically connected to the second line unit output terminal 332. The line unit 30 is connected in parallel to the first output terminal 2211 and the second output terminal 2212 of the second power management circuit unit 22, and is then electrically connected to the third line unit output terminal 333. The line unit 30 is connected in parallel to the third output terminal 2213 and the fourth output terminal 2214 of the second power management circuit unit 22, and is then electrically connected to the fourth line unit output terminal 334.

[0043] Similarly, in the embodiment of the combined channel type line unit 30, each power management circuit unit, such as the first power management circuit unit 21 and the second power management circuit unit 22, will receive an instruction respectively, and will also reply with a response signal when the instruction is completed.

[0044] Furthermore, in this embodiment, the first power management circuit unit 21 further includes a first interrupt signal output terminal 212, and the first interrupt signal output terminal 212 is electrically connected to the timing control circuit unit 10 to output a first interrupt signal to the timing control circuit unit 10. The second power management circuit unit 22 further includes a second interrupt signal output terminal 222, and the second interrupt signal output terminal 222 is electrically connected to the timing control circuit unit 10 to output a second interrupt signal to the timing control circuit unit 10.

[0045] Please see Figure 6 As shown, in a fifth embodiment, the power drive circuit of the display panel includes a timing control circuit unit 10, a first power management circuit unit 21, and a line unit 30.

[0046] The first power management circuit unit 21 has a first input port 210 and several first output ports 211. The first input port 210 is electrically connected to the timing control circuit unit 10 to receive a timing control signal. The line unit 30 has several first line unit input ports 310 and several line unit output ports 330. The several first line unit input ports 310 are respectively electrically connected to the several first output ports 211 to receive several power management signals output by the first power management circuit unit 21. The several first output ports 211 of the first power management circuit unit 21 include at least a first output terminal 2111, a second output terminal 2112, a third output terminal 2113, and a fourth output terminal 2114. The several line unit output ports 330 of the line unit 30 include at least a first line unit output terminal 331 and a second line unit output terminal 332.

[0047] The plurality of first line unit input ports 310 of the line unit 30 include at least a first line unit input terminal 311, a second line unit input terminal 312, a third line unit input terminal 313 and a fourth line unit input terminal 314.

[0048] The first output terminal 2111 of the first power management circuit unit 21 is electrically connected to the first line unit input terminal 311 of the plurality of first line unit input ports 310 of the line unit 30. The second output terminal 2112 of the first power management circuit unit 21 is electrically connected to the second line unit input terminal 312 of the plurality of first line unit input ports 310 of the line unit 30. The third output terminal 2113 of the first power management circuit unit 21 is electrically connected to the third line unit input terminal 313 of the plurality of first line unit input ports 310 of the line unit 30. The fourth output terminal 2114 of the first power management circuit unit 21 is electrically connected to the fourth line unit input terminal 314 of the plurality of first line unit input ports 310 of the line unit 30.

[0049] The line unit 30 is connected in parallel to the first output terminal 2111 and the second output terminal 2112 of the first power management circuit unit 21, and then electrically connected to the first line unit output terminal 331. The line unit 30 is also connected in parallel to the third output terminal 2113 and the fourth output terminal 2114 of the first power management circuit unit 21, and then electrically connected to the second line unit output terminal 332. These multiple line unit output ports 330 are powered and connected to a panel unit 40, and output a parallel drive signal to the panel unit.

[0050] In this embodiment, the line unit 30 is a combined channel type line unit 30. Therefore, the first power management circuit unit 21 further includes a first interrupt signal output terminal 212, and the first interrupt signal output terminal 212 is electrically connected to the timing control circuit unit 10 to output a first interrupt signal to the timing control circuit unit 10. For example, the first interrupt signal output terminal 212 is an INTB output terminal, used to output an INTB signal.

[0051] In the first to fifth embodiments, the architecture of the first power management circuit unit 21 or the second power management circuit unit 22 is determined by I 2 C is connected to the timing control circuit unit 10 at the front end to receive instructions from the timing control circuit unit 10, but is not limited thereto.

[0052] Please see Figure 7 As shown, in a sixth embodiment, the first power management circuit unit 21 of the power drive circuit of the display panel includes a first temporary register 213, and the first input port 210 has a first input terminal 2101 and a second input terminal 2102. The timing control circuit unit 10 is connected to the first input terminal 2101 and the second input terminal 2102 respectively through two lines, so as to... 2Taking the C architecture as an example, the first input terminal 2101 is a serial data line (Serial Data; SDA) pin, and the second input terminal 2102 is a serial clock (Serial Clock; SCL) pin. Furthermore, the first power management circuit unit 21 also has a first buffer output terminal 2141, a second buffer output terminal 2142, and a third buffer output terminal 2143. In this embodiment, the plurality of first output ports 211 of the first power management circuit unit 21 include at least a first main output terminal 2111, a second main output terminal 2112, and a third main output terminal 2113. The first main output terminal 2111 is electrically connected to the first buffer output terminal 2141, the second main output terminal 2112 is electrically connected to the second buffer output terminal 2142, and the third main output terminal 2113 is electrically connected to the third buffer output terminal 2143.

[0053] The second power management circuit unit 22 of the power drive circuit of the display panel includes a second temporary register 223, and the second input port 220 has a first input terminal 2201 and a second input terminal 2202. The timing control circuit unit 10 is connected to the first input terminal 2201 and the second input terminal 2202 through two lines respectively, so as to I 2 Taking the C architecture as an example, the first input terminal 2201 is a serial data line pin, and the second input terminal 2202 is a serial clock pin. Furthermore, the second power management circuit unit 22 also has a first buffer output terminal 2241, a second buffer output terminal 2242, and a third buffer output terminal 2243. In this embodiment, the plurality of second output ports 221 of the second power management circuit unit 22 include at least a first slave output terminal 2211, a second slave output terminal 2212, and a third slave output terminal 2213. The first slave output terminal 2211 is electrically connected to the first buffer output terminal 2241, the second slave output terminal 2212 is electrically connected to the second buffer output terminal 2242, and the third slave output terminal 2213 is electrically connected to the third buffer output terminal 2243.

[0054] Furthermore, in this embodiment, the line unit 30 is the output direct parallel type line unit 30. (The last part, "i," appears to be a typo and can be omitted.) 2 Taking the C architecture as an example, the timing control circuit unit 10 controls the combined mode of the first buffer output terminal 2141, the second buffer output terminal 2142, and the third buffer output terminal 2143 of the first power management circuit unit 21 and the first buffer output terminal 2241, the second buffer output terminal 2242, and the third buffer output terminal 2243 of the second power management circuit unit 22 through the first input terminal 2101 of the first temporary register 213, i.e. the serial data line pin.

[0055] For example, the timing control circuit unit 10 can control the first power management circuit unit 21 and the second power management circuit unit 22 to not combine, combine two channels, or combine three channels. Assuming two-channel combining is selected, the output value of the first buffer output terminal 2141 of the first power management circuit unit 21 determines the output value of the first buffer output terminal 2241 of the second power management circuit unit 22. For example, the output voltage of the first buffer output terminal 2141 of the first power management circuit unit 21 can be controlled to be 16 volts (V) and the current to be 300 milliamps (mA), and the output voltage of the first buffer output terminal 2241 of the second power management circuit unit 22 can also be 16 volts (V) and the current to be 300 milliamps (mA). Next, the first buffer output terminal 2141 of the first power management circuit unit 21 and the first buffer output terminal 2241 of the second power management circuit unit 22 are connected in parallel through the line unit 30, and the output terminal 331 of the first line unit provides an output value of 600 (mA).

[0056] Please see Figure 8 As shown, in a seventh embodiment, the power management circuit unit 21 of the display panel's power driving circuit includes a first register 213, and the first input port 210 has a first input terminal 2101 and a second input terminal 2102. The timing control circuit unit 10 is connected to the first input terminal 2101 and the second input terminal 2102 respectively through two lines, so as to... 2 Taking the C architecture as an example, the first input terminal 2101 is a serial data line pin, and the second input terminal 2102 is a serial clock pin. The first power management circuit unit 21 has a first buffer output terminal 2141, a second buffer output terminal 2142, a third buffer output terminal 2143, and a fourth buffer output terminal 2144. In this embodiment, the plurality of first output ports 211 of the first power management circuit unit 21 include at least a first output terminal 2111, a second output terminal 2112, a third output terminal 2113, and a fourth output terminal 2114. The first output terminal 2111 is electrically connected to the first buffer output terminal 2141, the second output terminal 2112 is electrically connected to the second buffer output terminal 2142, the third output terminal 2113 is electrically connected to the third buffer output terminal 2143, and the fourth output terminal 2114 is electrically connected to the fourth buffer output terminal 2144.

[0057] The second power management circuit unit 22 of the power drive circuit of the display panel includes a second temporary register 223, and the second input port 220 has a first input terminal 2201 and a second input terminal 2202. The timing control circuit unit 10 is connected to the first input terminal 2201 and the second input terminal 2202 through two lines respectively, so as to I 2Taking the C architecture as an example, the first input terminal 2201 is a serial data line pin, and the second input terminal 2202 is a serial clock pin. The second power management circuit unit 22 has a first buffer output terminal 2241, a second buffer output terminal 2242, a third buffer output terminal 2243, and a fourth buffer output terminal 2244. In this embodiment, the plurality of second output ports 221 of the second power management circuit unit 22 include at least a first output terminal 2211, a second output terminal 2212, a third output terminal 2213, and a fourth output terminal 2214. The first output terminal 2211 is electrically connected to the first buffer output terminal 2241, the second output terminal 2212 is electrically connected to the second buffer output terminal 2242, the third output terminal 2213 is electrically connected to the third buffer output terminal 2243, and the fourth output terminal 2214 is electrically connected to the fourth buffer output terminal 2244.

[0058] Furthermore, in this embodiment, the line unit 30 is the combined channel type line unit 30. (Using I...) 2 Taking the C architecture as an example, the timing control circuit unit 10 controls the combined mode of the first buffer output terminal 2141, the second buffer output terminal 2142, the third buffer output terminal 2143 and the fourth buffer output terminal 2144 of the first power management circuit unit 21, and the first buffer output terminal 2241, the second buffer output terminal 2242, the third buffer output terminal 2243 and the fourth buffer output terminal 2244 of the second power management circuit unit 22 through the first input terminal 2101 of the first temporary register 213, i.e. the serial data line pin.

[0059] For example, the timing control circuit unit 10 can control the first power management circuit unit 21 and the second power management circuit unit 22 to not be combined, to combine two channels, or to combine three channels. Assuming two-channel combining is selected, the output value of the second buffer output terminal 2142 of the first power management circuit unit 21 is determined by the first buffer output terminal 2141 of the first power management circuit unit 21. For example, the output voltage of the first buffer output terminal 2141 of the first power management circuit unit 21 is 16 volts (V) and the current is 300 milliamps (mA), and the output voltage of the second buffer output terminal 2142 of the first power management circuit unit 21 is also 16 volts (V) and the current is also 300 milliamps (mA). Then, the first buffer output terminal 2141 and the second buffer output terminal 2142 of the first power management circuit unit 21 are connected in parallel through the line unit 30, and the output terminal 331 of the first line unit provides an output value of 600 (mA).

[0060] For example, the first temporary register 213 and the second temporary register 223 are both 2-bit registers. The truth table of these 2-bit registers is shown in Table 1 below:

[0061] Table 1

[0062] When the register is set to 00h, the direct parallel output type is enabled.

[0063] When the hardware pin is set to 00, the device status is set to the power management circuit unit, and its device address is set to 62h. At this time, it is a silent device, only writing instructions and not replying with information.

[0064] When the hardware pins are set to 01, 10, and 11, the device status is set to the main power management circuit unit, and only three device addresses, 63h and 65h, can be set.

[0065] INTB is an interrupt signal, and in the direct parallel output type, it is only connected to the main power management circuit unit. When INTB is 1'b1, the timing control circuit unit accesses the power management circuit unit through the bus to learn about the status and determine whether to trigger the protection mechanism. The protection mechanisms of these power management circuit units are all linked.

[0066] When the temporary register is set to 01h~03h, the merged channel type is enabled.

[0067] When the register is set to 2'b01, the output is not merged (default).

[0068] When the register is set to 2'b10, the two channels are merged.

[0069] When the register is set to 2'b11, the three channels are merged.

[0070] At this time, the device address can be reserved for 62 to 65 hours.

[0071] INTB is an interrupt signal, and all of them are connected in parallel. The timing control circuit unit reads the status of the temporary register in a polling manner.

[0072] When INTB is 1'b1, the timing control circuit unit accesses each power management circuit unit sequentially via the bus to determine which protection mechanism is triggered, and each protection mechanism is independent based on the number of power management circuit units.

[0073] Furthermore, INTB is an interrupt signal that serves to provide protection mechanisms, functioning the same in both direct parallel and combined channel output types. For example, it can trigger undervoltage lockout (UVLO), over-temperature protection (OTP), overvoltage protection (OVP), or overcurrent protection (OCP), thereby allowing the timing control circuit unit to determine subsequent processing.

[0074] Furthermore, in the first to seventh embodiments, the timing control circuit unit 10, the first power management circuit unit 21, the second power management circuit unit 22, and the line unit 30 are all disposed on the same circuit board, and the line unit 30 is the trace on the circuit board, but is not limited thereto.

[0075] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A power drive circuit for a display panel, characterized in that, Includes: One timing control circuit unit; A first power management circuit unit has a first input port and several first output ports; wherein the first input port is electrically connected to the timing control circuit unit to receive a timing control signal; A second power management circuit unit has a second input port and several second output ports; wherein the second input port is electrically connected to the timing control circuit unit to receive the timing control signal; A line unit has several first line unit input ports, several second line unit input ports, and several line unit output ports; wherein the several first line unit input ports are electrically connected to the several first output ports, and the several second line unit input ports are electrically connected to the several second output ports, so as to receive several power management signals output by the first power management circuit unit and the second power management circuit unit; The line unit is electrically connected to the line unit output ports after being connected in parallel with the first power management circuit unit's first output ports and the second power management circuit unit's second output ports through the first line unit input ports and the second line unit input ports. The output ports of these line units are powered and connected to a panel unit, and output a parallel drive signal to the panel unit.

2. The power drive circuit for the display panel as described in claim 1, characterized in that, The plurality of first output ports of the first power management circuit unit include at least a first main output terminal and a second main output terminal; The plurality of second output ports of the second power management circuit unit include at least a first slave output terminal and a second slave output terminal; Among them, the output ports of the line unit include at least a first line unit output terminal and a second line unit output terminal; Specifically, the line unit is electrically connected to the first main output terminal and the first slave output terminal after being connected in parallel through the plurality of first line unit input ports and the plurality of second line unit input ports, and is electrically connected to the second line unit output terminal after being connected in parallel through the plurality of first line unit input ports and the plurality of second line unit input ports.

3. The power drive circuit for the display panel as described in claim 1, characterized in that, The plurality of first output ports of the first power management circuit unit include at least a first main output terminal, a second main output terminal, a third main output terminal and a fourth main output terminal; The second power management circuit unit includes at least a first slave output terminal, a second slave output terminal, a third slave output terminal, and a fourth slave output terminal among its plurality of second output ports. Among them, the output ports of the line unit include at least a first line unit output terminal, a second line unit output terminal, a third line unit output terminal and a fourth line unit output terminal; Specifically, the line unit is electrically connected to the first main output terminal and the first slave output terminal after being connected in parallel through the plurality of first line unit input ports and the plurality of second line unit input ports; the line unit is electrically connected to the second main output terminal and the second slave output terminal after being connected in parallel through the plurality of first line unit input ports and the plurality of second line unit input ports; the line unit is electrically connected to the third main output terminal and the third slave output terminal after being connected in parallel through the plurality of first line unit input ports and the plurality of second line unit input ports; and the line unit is electrically connected to the fourth line unit output terminal after being connected in parallel through the plurality of first line unit input ports and the plurality of second line unit input ports.

4. The power drive circuit for the display panel as described in claim 2 or 3, characterized in that, The first power management circuit unit further includes a first interrupt signal output terminal, and the first interrupt signal output terminal is electrically connected to the timing control circuit unit to output a first interrupt signal to the timing control circuit unit.

5. The power drive circuit for the display panel as described in claim 1, characterized in that, The plurality of first output ports of the first power management circuit unit include at least one first output terminal and one second output terminal; The plurality of second output ports of the second power management circuit unit include at least a first output terminal and a second output terminal; Among them, the output ports of the line unit include at least a first line unit output terminal and a second line unit output terminal; Specifically, the line unit is electrically connected to the output terminal of the first line unit after being connected in parallel with the first output terminal and the second output terminal of the first power management circuit unit through the plurality of first line unit input ports, and the line unit is electrically connected to the output terminal of the second line unit after being connected in parallel with the first output terminal and the second output terminal of the second power management circuit unit through the plurality of second line unit input ports.

6. The power drive circuit for the display panel as described in claim 1, characterized in that, The plurality of first output ports of the first power management circuit unit include at least a first output terminal, a second output terminal, a third output terminal and a fourth output terminal; The plurality of second output ports of the second power management circuit unit include at least a first output terminal, a second output terminal, a third output terminal and a fourth output terminal; Among them, the output ports of the line unit include at least a first line unit output terminal, a second line unit output terminal, a third line unit output terminal and a fourth line unit output terminal; Specifically, the line unit is electrically connected to the output terminal of the first power management circuit unit after being connected in parallel to the first output terminal and the second output terminal of the first power management circuit unit through the plurality of first line unit input ports; the line unit is electrically connected to the output terminal of the second line unit after being connected in parallel to the third output terminal and the fourth output terminal of the first power management circuit unit through the plurality of first line unit input ports; the line unit is electrically connected to the output terminal of the third line unit after being connected in parallel to the first output terminal and the second output terminal of the second power management circuit unit through the plurality of second line unit input ports; and the line unit is electrically connected to the output terminal of the fourth line unit after being connected in parallel to the third output terminal and the fourth output terminal of the second power management circuit unit through the plurality of second line unit input ports.

7. The power drive circuit for the display panel as described in claim 5 or 6, characterized in that, The first power management circuit unit further includes a first interrupt signal output terminal, and the first interrupt signal output terminal is electrically connected to the timing control circuit unit to output a first interrupt signal to the timing control circuit unit. The second power management circuit unit further includes a second interrupt signal output terminal, and the second interrupt signal output terminal is electrically connected to the timing control circuit unit to output a second interrupt signal to the timing control circuit unit.

8. A power drive circuit for a display panel, characterized in that, Includes: One timing control circuit unit; A first power management circuit unit has a first input port and several first output ports; wherein the first input port is electrically connected to the timing control circuit unit to receive a timing control signal; A line unit has several first line unit input ports and several line unit output ports; wherein the several first line unit input ports are electrically connected to the several first output ports respectively to receive several power management signals output by the first power management circuit unit; The plurality of first output ports of the first power management circuit unit include at least a first output terminal, a second output terminal, a third output terminal and a fourth output terminal; Among them, the output ports of the line unit include at least a first line unit output terminal and a second line unit output terminal; The line unit is electrically connected to the output terminal of the first line unit after being connected in parallel with the first output terminal and the second output terminal of the first power management circuit unit through the plurality of first line unit input ports, and the line unit is electrically connected to the output terminal of the second line unit after being connected in parallel with the third output terminal and the fourth output terminal of the first power management circuit unit through the plurality of first line unit input ports. The output ports of these line units are powered and connected to a panel unit, and output a parallel drive signal to the panel unit.

9. The power drive circuit for the display panel as described in claim 8, characterized in that, The first power management circuit unit further includes a first interrupt signal output terminal, and the first interrupt signal output terminal is electrically connected to the timing control circuit unit to output a first interrupt signal to the timing control circuit unit.

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