Gate drive circuit and display device

Abstract

The invention relates to a gate drive circuit and a display device. The gate driving circuit is used for receiving a scanning control signal of a time schedule controller in the display panel and outputting a driving signal, the gate driving circuit comprises a plurality of cascaded gate driving units, each gate driving unit comprises at least one phase inverter, and the gate driving circuit comprises a first metal layer, a second metal layer and a third metal layer, grid electrodes of partial transistor units of the grid electrode driving unit are formed on the grid electrode driving unit; a second metal layer on which the source electrode and the drain electrode of a part of the transistor unit of the gate driving unit are formed; a gate voltage signal transmission line, a control signal transmission line and a clock signal transmission line are formed on the third metal layer; wherein at least an area where the N-type transistor is located in the phase inverter is shielded by at least one of a grid voltage signal transmission line, a control signal transmission line and a clock signal transmission line. The display device comprises the gate drive circuit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a gate driving circuit and a display device. Background Technology

[0002] In display devices, to reduce power consumption, the driving circuit can use complementary metal-oxide-semiconductor (CMOS) transistors, also known as inverters. An inverter is composed of both P-type and N-type transistors. N-type transistors are more sensitive to light, and their threshold voltage fluctuates significantly, affecting the stability of their operating performance. Summary of the Invention

[0003] Therefore, it is necessary to provide a gate driving circuit and a display device, which aims to improve the stability of the operating performance of the N-type transistor in the gate driving circuit.

[0004] In a first aspect, embodiments of this application provide a gate driving circuit for receiving scan control signals from a timing controller in a display panel and outputting drive signals. The gate driving circuit includes multiple cascaded gate driving units, and each gate driving unit includes at least one inverter. The gate driving circuit includes:

[0005] The first metal layer, on which the gates of some transistor units of the gate driving unit are formed;

[0006] The second metal layer is on which the source and drain of some transistor cells of the gate driving unit are formed;

[0007] A third metal layer is formed thereon, on which gate voltage signal transmission lines, control signal transmission lines and clock signal transmission lines are formed;

[0008] In this inverter, the region containing at least the N-type transistor is shielded by a target transmission line, which is at least one of a gate voltage signal transmission line, a control signal transmission line, and a clock signal transmission line.

[0009] Secondly, embodiments of this application also provide a gate driving circuit for receiving scan control signals from a timing controller in a display panel and outputting drive signals. The gate driving circuit includes multiple cascaded gate driving units, and each gate driving unit includes at least one inverter. The gate driving circuit includes:

[0010] The first metal layer, on which the gates of some transistor units of the gate driving unit are formed;

[0011] The second metal layer is on which the source and drain of some transistor cells of the gate driving unit are formed;

[0012] A third metal layer is formed thereon, on which gate voltage signal transmission lines, control signal transmission lines and clock signal transmission lines are formed;

[0013] The fourth metal layer is on which the working voltage transmission line is formed;

[0014] In this inverter, at least the area containing the N-type transistors is shielded using the operating voltage transmission line.

[0015] Thirdly, embodiments of this application also provide a display device, including:

[0016] The timing controller is used to output scan control signals and data latch timing signals;

[0017] The gate driving circuit, which adopts the gate driving circuit described in any one of the first aspects of this application, is used to receive the scan control signal of the timing controller and output the scan driving signal.

[0018] The source drive circuit is used to receive the data latch timing signal output by the timing controller and output the data drive signal.

[0019] The gate driving circuit provided in this application embodiment is used to receive scanning control signals from a timing controller and output driving signals in a display panel. The gate driving circuit includes multiple cascaded gate driving units, and each gate driving unit includes at least one inverter. Since the gate driving circuit includes a first metal layer, a second metal layer, and a third metal layer, at least one of the gate voltage signal transmission line, control signal transmission line, and clock signal transmission line formed on the third metal layer can be used to block the area where at least the N-type transistor in the inverter is located. Based on this, the voltage threshold of the N-type transistor can be kept stable by ensuring that the N-type transistor is not affected by light factors during operation, thereby improving the stability of the operating performance of the N-type transistor in the gate driving circuit. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of an inverter.

[0021] Figure 2 This is a top view schematic diagram of a display panel provided in an embodiment of this application;

[0022] Figure 3 for Figure 2 A partially enlarged schematic diagram of section A within the dashed frame of the central display panel;

[0023] Figure 4 for Figure 3 A cross-sectional schematic diagram of section A within the dashed box in the middle;

[0024] Figure 5for Figure 2 Another enlarged view of part A within the dashed frame of the central display panel;

[0025] Figure 6 for Figure 2 Another enlarged view of part A within the dashed frame of the central display panel;

[0026] Figure 7 for Figure 2 Another enlarged view of part A within the dashed frame of the central display panel;

[0027] Figure 8 for Figure 2 Another enlarged view of part A within the dashed frame of the central display panel;

[0028] Figure 9 for Figure 8 A cross-sectional schematic diagram of section A within the dashed box in the middle;

[0029] Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0030] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0032] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate elements present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate elements present.

[0033] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0034] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0035] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0036] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0037] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0038] As described in the background section, in order to reduce the power consumption of the display device, the gate drive circuit included in the display device can use a CMOS transistor, also known as an inverter. Figure 1 This is a schematic diagram of an inverter, such as... Figure 1As shown, the inverter is composed of a P-type transistor 102 and an N-type transistor 104. The N-type MOSFET 104 is more sensitive to light from the external environment. Specifically, when light shines on the N-type MOSFET 104, additional electron-hole pairs are generated in the channel of the N-type MOSFET 104. The additional electron-hole pairs cause the threshold voltage of the N-type MOSFET 104 to shift in the negative direction and the off-state leakage current to increase. At the same time, the subthreshold swing of the N-type MOSFET 104 will increase (i.e., the slope will become slower) and the switching ratio will decrease. Furthermore, even if the light is removed from the N-type MOSFET 104, some of the carriers in the N-type MOSFET 104 will still be trapped by deep traps, causing the leakage current of the N-type MOSFET to remain high. This leads to a decrease in the pixel voltage retention rate and causes image retention. Furthermore, when the N-type MOSFET 104 is exposed to backlight or ambient light for a long time, the synergistic effect between light and heat will accumulate on the N-type MOSFET, which will affect the stability of the N-type MOSFET's operating performance. Obviously, this will also affect the operating performance of the inverter.

[0039] Based on the aforementioned technical problems, the inventors discovered that by shielding the area where the N-type MOS transistor is located, the influence of light on the N-type MOS transistor can be effectively avoided. Based on this, the inventors further developed the technical solution of the embodiments of this application. Specifically, the gate driving circuit provided in the embodiments of this application includes a first metal layer on which the gates of some transistor units of the gate driving unit are formed; a second metal layer on which the sources and drains of some transistor units of the gate driving unit are formed; and a third metal layer on which gate voltage signal transmission lines, control signal transmission lines, and clock signal transmission lines are formed; wherein, the area where at least the N-type transistor in the inverter is located is shielded by at least one of the gate voltage signal transmission lines, control signal transmission lines, and clock signal transmission lines. By employing the above technical solution, by using at least one of the gate voltage signal transmission lines, control signal transmission lines, and clock signal transmission lines formed in the third metal layer to shield the area where at least the N-type transistor in the inverter is located, the influence of light on the operating performance of the N-type MOS transistor can be effectively avoided. This improves the problem of voltage threshold fluctuations in the N-type MOS transistor caused by light affecting its operating performance.

[0040] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0041] Figure 2This is a top view schematic diagram of a display panel provided in an embodiment of this application. Figure 3 for Figure 2 A partially enlarged schematic diagram of section A within the dashed frame of the central display panel. Figure 4 for Figure 3 A cross-sectional view of section A within the dashed box. (Combined with...) Figure 2 , Figure 3 and Figure 4 As shown in the embodiment of this application, the gate driving circuit is used to receive scan control signals from a timing controller in a display panel and output drive signals. The gate driving circuit includes multiple cascaded gate driving units, and each gate driving unit includes at least one inverter. The gate driving circuit includes:

[0042] The first metal layer M1 is on which the gate 402-2 of part of the transistor unit 402 of the gate driving unit is formed;

[0043] The second metal layer M2 is on which the source 402-4 and drain 402-6 of some transistor units 402 of the gate driving unit are formed;

[0044] The third metal layer M3 is formed on which the gate voltage signal transmission line VG, the control signal transmission line CTRL and the clock signal transmission line CK are formed.

[0045] In this inverter, the region containing at least the N-type transistor is shielded by a target transmission line 404, which is at least one of the gate voltage signal transmission line VG, the control signal transmission line CTRL, and the clock signal transmission line CK.

[0046] Among them, the gate driving circuit corresponds to multiple pixel circuits, that is, each gate driving unit in the multiple cascaded gate driving units corresponds to multiple pixel circuits in a certain row.

[0047] Cascading multiple gate drive units means that the input terminal IN of one gate drive unit is connected to the output terminal OUT of the previous gate drive unit, and the output terminal OUT of the gate drive unit is connected to the input terminal IN of the next gate drive unit.

[0048] When multiple pixel circuits in a corresponding row are arranged horizontally, multiple cascaded gate driving units are arranged vertically; conversely, when multiple pixel circuits in a corresponding row are arranged vertically, multiple cascaded gate driving units are arranged horizontally.

[0049] Optionally, the display panel may be an organic light-emitting diode (OLED) display panel, a light-emitting diode (LED) display panel, or a liquid crystal display panel.

[0050] The display panel includes a display area AA and a non-display area NA. The display area AA is the portion of the display panel used for image display, while the non-display area NA can be understood as the border area of ​​the display panel. Therefore, multiple pixel circuits are located in the display area AA, and the gate driving circuit is located in the non-display area NA.

[0051] A timing controller is a device located within the driver chipset of a display panel, used to generate scanning control signals according to the line frequency and frame frequency.

[0052] Scan control signals are low-voltage logic signals generated by the timing controller and sent to the gate drive circuit. They enable the gate drive circuit to accurately output drive signals. Scan control signals include the frame start signal (STV).

[0053] A drive signal is a signal generated by the gate drive unit under the triggering action of the scan control signal and directly applied to the gate of the pixel switching transistor in the pixel circuit. The drive signal is used to turn multiple pixel circuits on or off line by line, so as to write a frame of image data into multiple pixel circuits or to keep a frame of image data in multiple pixel circuits.

[0054] An inverter is a logic gate composed of P-type and N-type transistors located in a gate drive unit. It is used to flip the level of a received voltage signal. Level flipping means converting a high voltage level to a low voltage level or vice versa.

[0055] The first metal layer M1, in addition to forming the gate 402-2 of the partial transistor unit 402 of the gate driving unit, may also form the gate of each type of transistor in each pixel circuit, or may also form the first plate of the capacitor in each pixel circuit.

[0056] In addition to the source 402-4 and drain 402-6 of the partial transistor unit 402 with gate driving unit, the second metal layer M2 may also have a transmission line for transmitting the first power signal PVDD.

[0057] The third metal layer M3, in addition to forming the gate voltage signal transmission line VG, the control signal transmission line CTRL, and the clock signal transmission line CK, can also form the source or drain of various types of transistors in each pixel circuit.

[0058] The second metal layer M2 is located between the first metal layer M1 and the third metal layer M3.

[0059] like Figure 4 As shown, the gate drive circuit also includes a semiconductor layer ACT, in which a channel region CH is formed. A gate insulating layer may also be disposed between the semiconductor layer and the first metal layer M1. Optionally, the region where at least the N-type transistors in the inverter are located is shielded by the target transmission line 404, meaning that the region where the channel region CH of at least the N-type transistors in the inverter is located is shielded by the target transmission line 404.

[0060] like Figure 4 As shown, the gate drive circuit also includes a substrate 406, and a semiconductor layer ACT, a first metal layer M1, a second metal layer M2 and a third metal layer M3 are stacked along a direction away from the substrate 406.

[0061] Transistor unit 402 refers to a P-type MOS transistor or an N-type MOS transistor in the gate drive unit. Transistor unit 402 includes a gate, a source, a drain, and a channel region CH.

[0062] Optionally, the transistor unit 402 may be manufactured based on amorphous indium gallium zinc oxide (In-Ga-ZnO, IGZO) semiconductor material or based on low temperature polycrystalline silicon (LTPS) semiconductor material.

[0063] The gate voltage signal transmission line (VG) is a transmission line used to transmit gate on-level signals or gate off-level signals. A gate on-level signal enables the gate driver unit to enter the on state, while a gate off-level signal enables the gate driver unit to enter the off state.

[0064] The control signal transmission line CTRL refers to the transmission line used to transmit scan control signals.

[0065] Optionally, the control signal transmission line CTRL can be a transmission line used to transmit the set scan control signal SP and the reset scan control signal SN. In this case, the node line used to transmit the set scan control signal SP and the node line used to transmit the reset scan control signal SN are combined into a single control signal transmission line CTRL. In other words, in this case, the control signal transmission line CTRL includes two node lines respectively used to transmit the set scan control signal SP and the reset scan control signal SN, and the two node lines are arranged adjacent to each other.

[0066] The clock signal transmission line CK refers to the transmission line used to transmit clock signals.

[0067] When the gate drive circuit adopts a four-phase clock architecture, the clock signal transmission line CK can be at least one of the first clock signal transmission line CK1, the second clock signal transmission line CK2, the third clock signal transmission line CK3, and the fourth clock signal transmission line CK4. The phase of the first clock signal transmitted by the first clock signal transmission line CK1, the phase of the second clock signal transmitted by the second clock signal transmission line CK2, the phase of the third clock signal transmitted by the third clock signal transmission line CK3, and the phase of the fourth clock signal transmitted by the fourth clock signal transmission line CK4 are successively 90° apart, that is, successively 1 / 4 row cycle apart.

[0068] like Figure 3 As shown, the distance between the clock signal transmission line CK and the display area can be less than the distance between the control signal transmission line CTRL and the display area; the distance between the control signal transmission line CTRL and the display area can be less than the distance between the gate voltage signal transmission line VG and the display area.

[0069] The region containing at least the N-type transistor in the inverter can refer to the region containing the gate, source, drain, and channel region CH of the N-type transistor in the inverter, as well as the region projected directly above it. In addition, it can also include the peripheral region of the N-type transistor reserved to reduce the possibility of light leakage at the edge.

[0070] The region containing at least the N-type transistor in the inverter is shielded by at least one of the gate voltage signal transmission line VG, the control signal transmission line CTRL, and the clock signal transmission line CK. The specific transmission line used for shielding, whether it is one, two, or all of them, is determined by the location of the N-type transistor in the inverter.

[0071] It can also be understood that it is jointly determined by the area where the N-type transistor of the inverter is projected onto the display panel, the area where the gate voltage signal transmission line VG is projected onto the display panel, the area where the control signal transmission line CTRL is projected onto the display panel, and the area where the clock signal transmission line CK is projected onto the display panel.

[0072] Optionally, the shielding can be achieved using at least one transmission line whose projection on the display panel is closest to the projection of the N-type transistor of the inverter onto the display panel; alternatively, the shielding can be achieved using at least one transmission line whose projection on the display panel overlaps with the projection of the N-type transistor of the inverter onto the display panel. For example, if the transmission line whose projection on the display panel is closest to the projection of the N-type transistor of the inverter onto the display panel is the gate voltage signal transmission line VG, then the gate voltage signal transmission line VG is used to shield the N-type transistor in the inverter.

[0073] Alternatively, if the width of the N-type transistor in the inverter is large, at least two of the gate voltage signal transmission line VG, the control signal transmission line CTRL, and the clock signal transmission line CK can be used for shielding.

[0074] Optionally, the edge positions of the blocking region formed by at least one of the gate voltage signal transmission line VG, control signal transmission line CTRL, and clock signal transmission line CK used to block at least the N-type transistors in the inverter can each extend beyond the corresponding edge position of the at least N-type transistor in the inverter by at least 3.5 µm, thereby ensuring that the N-type transistors can be completely blocked. The at least 3.5 µm can be understood as the size of the light-blocking margin. Due to the existence of the light-blocking margin, it can be ensured that light incident at any angle will not illuminate the N-type transistors in the inverter. That is, the edge positions of the target transmission line 404 can each extend beyond the distance of at least the light-blocking margin corresponding to the corresponding edge position of the at least N-type transistor in the inverter.

[0075] Optionally, the edge positions of the blocking regions formed by at least one of the gate voltage signal transmission line VG, control signal transmission line CTRL, and clock signal transmission line CK used to block at least N-type transistors in the inverter can extend at least 3.5 µm beyond the corresponding edge positions of the channel region CH of at least N-type transistors in the inverter.

[0076] When the gate driving circuit includes a first metal layer M1, a second metal layer M2 and a third metal layer M3, and the data lines in the display panel are located on the third metal layer M3, the display panel including the gate driving circuit can be a dual-source-drain (2SD) process.

[0077] In summary, the gate driving circuit provided in this application embodiment is used to receive scanning control signals from a timing controller and output driving signals in a display panel. The gate driving circuit includes multiple cascaded gate driving units, and each gate driving unit includes at least one inverter. Since the gate driving circuit includes a first metal layer M1, a second metal layer M2, and a third metal layer M3, at least one of the gate voltage signal transmission line VG, the control signal transmission line CTRL, and the clock signal transmission line CK formed on the third metal layer M3 can be used to block the area where at least the N-type transistor in the inverter is located. Based on this, by ensuring that the N-type transistor is not affected by light factors during operation, the voltage threshold of the N-type transistor can be kept stable, thereby improving the stability of the operating performance of the N-type transistor in the gate driving circuit.

[0078] Figure 5 for Figure 2 Another enlarged view of the dashed frame A of the display panel. In an exemplary embodiment, when the area where the N-type transistor to be shielded overlaps with the gate voltage signal transmission line VG, such as... Figure 5 As shown, the gate voltage signal transmission line VG is formed as a solid metal layer with a width larger than the area where the N-type transistor to be shielded is located, and an exhaust hole K is formed on the solid metal layer.

[0079] In one exemplary embodiment, such as Figure 5 As shown, the exhaust port K is a long strip with multiple intervals.

[0080] In this context, the area where the N-type transistor to be shielded overlaps with the gate voltage signal transmission line VG, which means that the N-type transistor is shielded using the gate voltage signal line, i.e., the target transmission line is the gate voltage signal line.

[0081] Vent hole K refers to a location on the metal layer that is created to ensure that gases released from organic residues such as photoresist and cleaning solvent residues remaining under the entire metal layer do not accumulate.

[0082] Alternatively, while forming a whole metal layer with a width larger than the area where the N-type transistor to be shielded is located, multiple spaced elongated strips can be formed on the whole metal layer using laser etching technology to achieve the opening of exhaust holes K.

[0083] Multiple spaced elongated exhaust holes K can be arranged horizontally or vertically.

[0084] Optionally, the multiple spaced elongated exhaust holes K can be arranged at equal intervals.

[0085] Optionally, the multiple spaced strips may have the same shape or at least two different shapes.

[0086] In this embodiment, when the area where the N-type transistor to be shielded is located overlaps with the gate voltage signal transmission line VG, the gate voltage signal transmission line VG is formed as a solid metal layer with a width larger than the area where the N-type transistor to be shielded is located. This not only effectively and sufficiently shields the N-type transistor but also reduces the resistance of the gate voltage signal. To prevent the accumulation of gas released from organic residues under the large solid metal layer, multiple spaced elongated exhaust holes K are formed on the solid metal layer. This effectively prevents gas accumulation and avoids damage to the gate drive circuit caused by bulging or film peeling, thereby ensuring the reliability of the gate drive circuit.

[0087] In one exemplary embodiment, the gate voltage signal transmission line VG is either a gate high voltage signal transmission line or a gate low voltage signal transmission line.

[0088] Specifically, when the gate voltage signal transmission line VG is a gate high voltage signal transmission line, it is used to transmit the gate on level signal; when the gate voltage signal transmission line VG is a gate low voltage signal transmission line, it is used to transmit the gate off level signal.

[0089] In this embodiment, since both the gate high voltage signal transmission line and the gate low voltage signal transmission line can be used to block the area where at least the N-type transistor is located in the inverter, the stability of the operating performance of the N-type transistor in the gate drive circuit is improved.

[0090] In an exemplary embodiment, when the area where the N-type transistor to be shielded is located overlaps with the gate low-voltage signal transmission line, the gate low-voltage signal transmission line is formed as a whole metal layer with a width larger than the area where the N-type transistor to be shielded is located, and vent holes are formed on the whole metal layer.

[0091] Figure 6 for Figure 2 Another enlarged view of the dashed frame A of the central display panel, in an exemplary embodiment, such as... Figure 6 As shown, when the area where the N-type transistor to be shielded is located overlaps with the control signal transmission line CTRL, the control signal transmission line CTRL extends from the original trace to cover the area where the N-type transistor to be shielded is located, forming an extended metal layer CTRL-P.

[0092] Easy to understand, such as Figure 6The area below the extended metal layer CTRL-P corresponding to the control signal transmission line CTRL shown is the area where the N-type MOS transistor that needs to be shielded is located.

[0093] In an exemplary embodiment, if there are two or more control signal transmission lines CTRL that overlap with the area of ​​the N-type transistor to be shielded, the area of ​​the extended metal layer CTRL-P of each control signal transmission line CTRL is the same, so that the capacitance of each control signal transmission line CTRL is the same.

[0094] The area where the N-type transistor to be shielded overlaps with the control signal transmission line CTRL means that the N-type transistor is shielded by the control signal transmission line CTRL, i.e., the target transmission line is the control signal transmission line CTRL.

[0095] The control signal transmission line CTRL extends from the original trace to form an extended metal layer CTRL-P covering the area where the N-type transistor to be shielded is located. This refers to laterally widening the control signal transmission line CTRL at a certain location within the area where the N-type transistor to be shielded is located, thus obtaining the extended metal layer CTRL-P. Based on this, it is easy to understand that the extended metal layer CTRL-P corresponding to the control signal transmission line CTRL is located in the same film layer as the control signal transmission line CTRL.

[0096] In this embodiment, when the area of ​​the N-type transistor to be shielded overlaps with the control signal transmission line CTRL, i.e., when the N-type transistor is shielded by the control signal transmission line CTRL, the control signal transmission line CTRL extends from the original trace to cover the area of ​​the N-type transistor to be shielded by an extended metal layer CTRL-P. Thus, the extended metal layer CTRL-P can completely shield the N-type transistor in the inverter, ensuring that the illumination factor will not affect the voltage threshold of the N-type transistor, thereby improving the stability of the N-type transistor's operating performance. Furthermore, when there are two or more control signal transmission lines CTRL overlapping the area of ​​the N-type transistor to be shielded, the area of ​​the extended metal layer CTRL-P of each control signal transmission line CTRL is the same. Based on this, it can be ensured that the capacitance of each control signal transmission line CTRL is the same. Thus, by ensuring the consistency of the operating performance of each control signal transmission line CTRL, the stability of the gate drive circuit's operating performance can be improved.

[0097] Figure 7 for Figure 2 Another enlarged view of the dashed frame A of the central display panel, in an exemplary embodiment, such as... Figure 7As shown, when the area where the N-type transistor to be shielded is located overlaps with the clock signal transmission line CK, the clock signal transmission line CK extends from the original trace to cover the area where the N-type transistor to be shielded is located by an extended metal layer CK-P.

[0098] The area where the N-type transistor to be shielded overlaps with the clock signal transmission line CK means that the N-type transistor is shielded by the clock signal transmission line CK, i.e., the target transmission line is the clock signal transmission line CK.

[0099] The clock signal transmission line CK extends from the original trace to cover the area where the N-type transistor to be shielded is located. This means that the clock signal transmission line CK-P is laterally widened at a certain location within the area where the N-type transistor to be shielded, thus obtaining the extended metal layer CK-P. Based on this, it is easy to understand that the extended metal layer CK-P corresponding to the clock signal transmission line CK is located in the same film layer as the clock signal transmission line CK.

[0100] Easy to understand, such as Figure 7 The area below the extended metal layer CK-P corresponding to the clock signal transmission line CK shown is the area where the N-type MOS transistor that needs to be shielded is located.

[0101] In this embodiment, when the area where the N-type transistor to be shielded is located overlaps with the clock signal transmission line CK, that is, when the clock signal transmission line CK is used to shield the N-type transistor, the clock signal transmission line CK extends from the original trace to cover the area where the N-type transistor to be shielded is located. Thus, the extended metal layer CK-P can completely shield the N-type transistor in the inverter, ensuring that the illumination factor will not affect the voltage threshold of the N-type transistor, thereby improving the stability of the working performance of the N-type transistor.

[0102] The gate voltage signal transmission line is formed into a solid metal layer with a width larger than the area where the N-type transistor to be shielded is located. This is larger than the size of the extended metal layer that the control signal transmission line extends from the original trace to cover the area where the N-type transistor to be shielded is located, and the size of the extended metal layer that the clock signal transmission line extends from the original trace to cover the area where the N-type transistor to be shielded is located.

[0103] Figure 8 for Figure 2 Another enlarged view of part A within the dashed frame of the central display panel. Figure 9 for Figure 8 A cross-sectional view of section A within the dashed box. (Combined with...) Figure 2 , Figure 8 and Figure 9As shown in the embodiment of this application, another gate driving circuit is also provided for receiving scan control signals from a timing controller in a display panel and outputting drive signals. The gate driving circuit includes multiple cascaded gate driving units, and each gate driving unit includes at least one inverter. The gate driving circuit includes:

[0104] The first metal layer M1 has the gates of some transistor units of the gate driving unit formed thereon.

[0105] The second metal layer M2 is on which the source and drain of some transistor units of the gate driving unit are formed;

[0106] The third metal layer M3 is formed on which the gate voltage signal transmission line VG, the control signal transmission line CTRL and the clock signal transmission line CK are formed.

[0107] The fourth metal layer M4' is on which the working voltage transmission line 408 is formed;

[0108] In this circuit, the area containing at least the N-type transistors in the inverter is shielded by the operating voltage transmission line 408.

[0109] Optionally, the fourth metal layer M4' may include a first sub-metal layer and a second sub-metal layer. Optionally, the first sub-metal layer may be the M4 metal layer, and the second sub-metal layer may be a reflective electrode (RE).

[0110] Optionally, by alternately drilling holes in the first sub-metal layer and the second sub-metal layer, and the holes on the first sub-metal layer and the holes on the second sub-metal layer are staggered and do not overlap, it can be ensured that there is at least one working voltage transmission line 408 formed in the first sub-metal layer or at least one working voltage transmission line 408 formed in the second sub-metal layer, which can shield the area where at least the N-type transistor in the inverter is located.

[0111] Optionally, the operating voltage transmission line 408 can be a transmission line for transmitting the second power signal PVEE or a transmission line for transmitting the third power signal VSS.

[0112] In an exemplary embodiment, when the region where the N-type transistor to be shielded is located overlaps with the working voltage transmission line 408, the working voltage transmission line 408 is formed as a solid metal layer with a width larger than the region where the N-type transistor to be shielded is located.

[0113] Optionally, the third metal layer M3 also includes a light-emitting control signal line for controlling the light-emitting state of the pixel circuit. The operating voltage transmission line 408 formed in the fourth metal layer M4' can not only block the area where at least the N-type transistors in the inverter are located, but also block the light-emitting control signal line in the third metal layer M3.

[0114] Optionally, the operating voltage transmission line 408 formed in the fourth metal layer M4' can not only block the area where at least the N-type transistors in the inverter are located, but also block the control signal transmission line CTRL in the third metal layer M3. Optionally, it can block the node line in the control signal transmission line CTRL used to transmit the reset scan control signal SN.

[0115] When the gate driving circuit includes a first metal layer M1, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4', and the data lines in the display panel are located on the fourth metal layer M4', the display panel including the gate driving circuit can be a three-source-drain (3SD) process.

[0116] Compared to 2SD display panels, 3SD process display panels can place the data lines in the fourth metal layer M4', eliminating the need for the data lines to be placed in the third metal layer M3 like the gate voltage signal transmission line VG, control signal transmission line CTRL, and clock signal transmission line CK. This helps to reduce the width of the bezel area (i.e., the non-display area) where the gate drive circuit is located, enabling a narrow bezel display panel while maintaining the stability of the N-type transistor's performance in the inverter.

[0117] The gate driving circuit provided in this application embodiment is used to receive scanning control signals from a timing controller and output driving signals in a display panel. The gate driving circuit includes multiple cascaded gate driving units, and each gate driving unit includes at least one inverter. Since the gate driving circuit includes a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4', the operating voltage transmission line 408 formed on the fourth metal layer M4' can be used to block the area where at least the N-type transistor in the inverter is located. Based on this, the voltage threshold of the N-type transistor can be kept stable by ensuring that the N-type transistor is not affected by light factors during operation, thereby improving the stability of the operating performance of the N-type transistor in the gate driving circuit.

[0118] In one exemplary embodiment, the operating voltage transmission line 408 is formed as a single metal layer that shields the entire area where the N-type transistors are located.

[0119] In one exemplary embodiment, vent holes are formed on the solid metal layer formed by the working voltage transmission line 408.

[0120] In this embodiment, the working voltage transmission line 408 formed on the fourth metal layer is formed as a large, solid metal layer that shields the area where all N-type transistors are located. Therefore, in addition to shielding the area where at least the N-type transistors are located in the inverter, it can also completely shield the light-emitting control signal line and the control signal transmission line CTRL in the third metal layer M3.

[0121] Based on the same concept, this application also provides a display device. Figure 10 This is a schematic diagram of the structure of a display device provided in an embodiment of this application, such as... Figure 10 As shown, the display device 1000 includes a timing controller for outputting scan control signals and data latch timing signals;

[0122] The gate driving circuit adopts the gate driving circuit as described in any one of the above-described gate driving circuit embodiments, and is used to receive the scan control signal of the timing controller and output the scan driving signal.

[0123] The source drive circuit is used to receive the data latch timing signal output by the timing controller and output a data drive signal. The display device 1000 also has the beneficial effects of the gate drive circuit in the above embodiments. The similarities can be understood by referring to the explanation of the gate drive circuit above, and will not be repeated below.

[0124] The display device 1000 provided in this application embodiment can be a mobile phone or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, industrial control equipment, medical display screen, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0125] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0126] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A gate driving circuit for receiving scan control signals from a timing controller and outputting drive signals in a display panel, characterized in that, The gate driving circuit includes multiple cascaded gate driving units, and each gate driving unit includes at least one inverter. The gate driving circuit includes: A first metal layer, on which the gates of some transistor units of the gate driving unit are formed; A second metal layer is formed thereon on which the source and drain of some transistor units of the gate driving unit are formed; A third metal layer is formed thereon, on which gate voltage signal transmission lines, control signal transmission lines and clock signal transmission lines are formed; In this inverter, the region containing at least the N-type transistor is shielded by a target transmission line, which is at least one of the gate voltage signal transmission line, the control signal transmission line, and the clock signal transmission line.

2. The gate driving circuit according to claim 1, characterized in that, When the area where the N-type transistor to be shielded is located overlaps with the gate voltage signal transmission line, the gate voltage signal transmission line is formed as a whole metal layer with a width larger than the area where the N-type transistor to be shielded is located, and an exhaust hole is opened on the whole metal layer.

3. The gate driving circuit according to claim 2, characterized in that, The gate voltage signal transmission line can be either a high-voltage gate signal transmission line or a low-voltage gate signal transmission line.

4. The gate driving circuit according to claim 2, characterized in that, The exhaust vents are multiple spaced elongated strips.

5. The gate driving circuit according to claim 1, characterized in that, When the area where the N-type transistor to be shielded is located overlaps with the control signal transmission line, the control signal transmission line extends from the original trace to cover the area where the N-type transistor to be shielded is located with an extended metal layer.

6. The gate driving circuit according to claim 5, characterized in that, If there are two or more control signal transmission lines that overlap with the area of ​​the N-type transistor to be shielded, the area of ​​the extended metal layer of each control signal transmission line shall be the same, so that the capacitance of each control signal transmission line shall be the same.

7. The gate driving circuit according to claim 1, characterized in that, When the area where the N-type transistor to be shielded is located overlaps with the clock signal transmission line, the clock signal transmission line extends from the original trace to cover the area where the N-type transistor to be shielded is located in an extended metal layer.

8. A gate driving circuit for receiving scan control signals from a timing controller and outputting drive signals in a display panel, characterized in that, The gate driving circuit includes multiple cascaded gate driving units, and each gate driving unit includes at least one inverter. The gate driving circuit includes: A first metal layer, on which the gates of some transistor units of the gate driving unit are formed; A second metal layer is formed thereon on which the source and drain of some transistor units of the gate driving unit are formed; A third metal layer is formed thereon, on which gate voltage signal transmission lines, control signal transmission lines and clock signal transmission lines are formed; The fourth metal layer is on which the working voltage transmission line is formed; The region containing at least the N-type transistors in the inverter is shielded by the operating voltage transmission line.

9. The gate driving circuit according to claim 8, characterized in that, The operating voltage transmission line is formed as a single metal layer that shields the area where all N-type transistors are located.

10. A display device, characterized in that, include: The timing controller is used to output scan control signals and data latch timing signals; The gate driving circuit, using the gate driving circuit according to any one of claims 1 to 9, is used to receive the scan control signal from the timing controller and output the scan driving signal. The source drive circuit is used to receive the data latch timing signal output by the timing controller and output the data drive signal.

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