Display device and driving method thereof

Abstract

According to the display device and the driving method thereof, in the display device, a gate driving circuit comprises a first signal generation circuit and a second signal generation circuit which generate different light-emitting control signals, each pixel driving circuit comprises at least two sub-pixel driving circuits, each pixel driving circuit corresponds to different gray-scale value ranges, and the pixel driving circuits are connected with the gate driving circuit through the first signal generation circuit and the second signal generation circuit. All the sub-pixel driving circuits are electrically connected with the same first signal generation circuit, obtained first light-emitting control signals can regulate and control the driving duration of all the sub-pixel driving circuits in a unified mode, and at least one sub-pixel driving circuit is electrically connected with the second signal generation circuit. The driving duration of the driving tube can be further adjusted by respectively obtaining the corresponding second light-emitting control signals, the normal expansion of the gray scale is ensured, and the adopted driving duration adjustment strategies are mutually independent, so that the condition that the gray scale value exceeds the gray scale value range provided by the controller does not occur, and the service life of the controller is prolonged. It can be ensured that each pixel driving circuit receives accurate analog voltage data, and the light emitting accuracy of pixels is ensured.

Description

Technical Field

[0001] Embodiments of this application relate to the field of display technology, and more particularly to a display device and its driving method. Background Technology

[0002] In recent years, due to the advantages of micro-LEDs over AMOLEDs (Active-matrix organic light emitting diodes), such as smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer lifespan, the application of micro-LEDs in displays has developed rapidly and has become a research hotspot in display devices.

[0003] The display panel contains multiple pixel units arranged in an array. Each pixel unit includes multiple pixel circuits, and the pixels in each pixel circuit are driven to emit light by a pixel driving circuit. The pixel driving circuit includes driving transistors. Due to the characteristics of driving transistors, low grayscale levels are prone to not expanding. By compressing the driving time of the pixel driving circuit and simultaneously increasing the analog voltage data to increase the driving current provided by the pixel driving circuit, the low grayscale levels can be expanded normally.

[0004] When the full frame of the display device contains both low and high grayscale, the driving time of all pixel driving circuits in the display panel needs to be uniformly compressed. For the pixel driving circuit that obtains the analog voltage data corresponding to the high grayscale, if the corresponding increased analog voltage data exceeds the range of analog voltage data that the data driving circuit can provide, the driving current provided by the pixel driving circuit will be inaccurate, affecting the accuracy of pixel light emission. Summary of the Invention

[0005] In a first aspect, this application provides a display device, comprising:

[0006] A gate driving circuit, a data driving circuit, multiple pixels, and pixel driving circuits connected to each of the pixels, wherein the pixel driving circuits are arrayed.

[0007] The gate driving circuit includes at least one first signal generation circuit and at least one second signal generation circuit;

[0008] The first signal generation circuit is configured to output a first light emission control signal, and the second signal generation circuit is configured to output a second light emission control signal. The light emission control signal is a signal that limits the driving duration of the driving signal.

[0009] The pixel driving circuit includes a first sub-pixel driving circuit and a second sub-pixel driving circuit; the size of the first driving transistor in the first sub-pixel driving circuit is larger than that of the second driving transistor in the second sub-pixel driving circuit; each sub-pixel driving circuit corresponds to a different grayscale range.

[0010] Both the first sub-pixel driving circuit and the second sub-pixel driving circuit are electrically connected to the same first signal generating circuit; different second sub-pixel driving circuits are electrically connected to different second signal generating circuits respectively.

[0011] The sub-pixel driving circuit is also electrically connected to the data driving circuit and is configured to obtain a data analog voltage and the light emission control signal, wherein the data analog voltage includes a display data analog voltage.

[0012] The first target sub-pixel driving circuit is a sub-pixel driving circuit whose grayscale value range includes the grayscale value corresponding to the display data analog voltage. The first target sub-pixel driving circuit is configured to receive the display data analog voltage and output the driving signal; the driving signal is a signal that drives the pixel to emit light.

[0013] In the above technical solution, the pixel driving circuit includes a first sub-pixel driving circuit and a second sub-pixel driving circuit. The gate driving circuit electrically connected to the pixel driving circuit includes a first signal generation circuit and a second signal generation circuit. Different signal generation circuits generate different light emission control signals, and the duration for which the pixel driving circuit drives the pixel to emit light is also different. Both the first sub-pixel driving circuit and the second sub-pixel driving circuit are electrically connected to the first signal generation circuit. The first light emission control signal output by the first signal generation circuit can uniformly regulate the driving duration of each sub-pixel driving circuit. Since the size of the driving transistor in the second sub-pixel driving circuit is smaller than the size of the driving transistor in the first sub-pixel driving circuit, the second sub-pixel driving circuit... The pixel driving circuit is also electrically connected to the second signal generation circuit. The driving duration of the driving transistor can be further adjusted by the driving duration set by the second light emission control signal to ensure normal grayscale expansion. The second signal generation circuits connected to each second sub-pixel driving circuit are different, and the driving duration adjustment strategies adopted are independent of each other. After each pixel driving circuit obtains the analog voltage data, it selects the appropriate first target sub-pixel driving circuit to drive the pixel to emit light. The light emission time does not need to be compressed simultaneously using the same compression strategy, so there will be no situation where the grayscale value exceeds the grayscale value range that the controller can provide. This can ensure that each pixel driving circuit receives accurate analog voltage data and ensure the accuracy of pixel light emission.

[0014] Secondly, this application provides a display device, comprising:

[0015] The array includes a gate driving circuit, a data driving circuit, multiple pixels and corresponding pixel driving circuits, wherein the pixel driving circuits are distributed in an array.

[0016] The gate driving circuit includes at least one first signal generation circuit and at least one second signal generation circuit;

[0017] The first signal generation circuit is configured to output a first light emission control signal, and the second signal generation circuit is configured to output a second light emission control signal. The light emission control signal is a signal that limits the driving duration of the driving signal.

[0018] The pixel driving circuit includes at least two sub-pixel driving circuits, and the at least two sub-pixel driving circuits are electrically connected to the same pixel; each sub-pixel driving circuit corresponds to a different grayscale range.

[0019] Each of the sub-pixel driving circuits is electrically connected to the same first signal generation circuit and electrically connected to different second signal generation circuits respectively;

[0020] The sub-pixel driving circuit and the data driving circuit are electrically connected and configured to obtain a data analog voltage and the light emission control signal, wherein the data analog voltage includes a display data analog voltage.

[0021] The first target sub-pixel driving circuit is a sub-pixel driving circuit whose grayscale value range includes the grayscale value corresponding to the display data analog voltage. The first target sub-pixel driving circuit is configured to receive the display data analog voltage and output the driving signal.

[0022] The driving signal is the signal that drives the pixel to emit light.

[0023] In the above technical solution, the pixel driving circuit includes at least two sub-pixel driving circuits. The gate driving circuit electrically connected to the pixel driving circuit includes a first signal generation circuit and a second signal generation circuit. Different signal generation circuits generate different light emission control signals, and the duration for which the pixel driving circuit drives the pixel to emit light is also different. Each sub-pixel driving circuit is electrically connected to the same first signal generation circuit. The first light emission control signal output by the first signal generation circuit can uniformly regulate the driving duration of each sub-pixel driving circuit. The second signal generation circuits electrically connected to each sub-pixel driving circuit are different, and the driving duration adjustment strategies adopted are independent of each other. The driving duration set by the second light emission control signal can further adjust the driving duration of the driving transistor in the sub-pixel driving circuit to ensure normal grayscale expansion. After each pixel driving circuit obtains the analog voltage data, it selects a suitable first target sub-pixel driving circuit to drive the pixel to emit light. The emission time does not need to be compressed simultaneously using the same compression strategy, so there will be no situation where the grayscale value exceeds the grayscale value range that the controller can provide. This can ensure that each pixel driving circuit receives accurate analog voltage data and ensure the accuracy of pixel emission.

[0024] Thirdly, a driving method for a display device, the method being applied to the display device according to any one of the claims in the first aspect, the method comprising:

[0025] The data driving circuit is controlled to output a data analog voltage, the data analog voltage including a display data analog voltage;

[0026] When the grayscale value corresponding to the display data analog voltage is within the grayscale range corresponding to the first sub-pixel driving circuit, the first sub-pixel driving circuit obtains the first light emission control signal from the first signal generation circuit, and outputs the driving signal based on the first light emission control signal and the display data analog voltage.

[0027] When the grayscale value corresponding to the display data analog voltage is within the grayscale range corresponding to the second sub-pixel driving circuit, the second sub-pixel driving circuit obtains a first light emission control signal from the first signal generation circuit, obtains a second light emission control signal from the second signal generation circuit, and outputs the driving signal based on the first light emission control signal, the second light emission control signal and the display data analog voltage.

[0028] The pixel is controlled to emit light based on the driving signal.

[0029] Fourthly, this application provides a driving method for a display device, the method being applied to the display device according to the second aspect, the method comprising:

[0030] The data driving circuit is controlled to output a data analog voltage, the data analog voltage including a display data analog voltage;

[0031] Control the first signal generation circuit to output the first light-emitting control signal;

[0032] Control the second signal generation circuit to output a second light-emitting control signal;

[0033] The target sub-pixel driving circuit outputs the driving signal based on the first light emission control signal, the second light emission control signal, and the analog voltage of the display data.

[0034] The pixel is controlled to emit light based on the driving signal.

[0035] This application provides a display device and its driving method. In the display device, the gate driving circuit includes a first signal generation circuit and a second signal generation circuit to generate different light emission control signals. Each pixel driving circuit includes at least two sub-pixel driving circuits, each corresponding to a different grayscale value range. Each sub-pixel driving circuit is electrically connected to the same first signal generation circuit. The obtained first light emission control signal can uniformly regulate the driving duration of each sub-pixel driving circuit. At least one sub-pixel driving circuit is electrically connected to the second signal generation circuit, and the corresponding second light emission control signal can be obtained to further adjust the driving duration of the driving transistor, ensuring normal grayscale expansion. Moreover, the driving duration adjustment strategies adopted are independent of each other, so there will be no situation where the grayscale value exceeds the grayscale value range that the controller can provide. This can ensure that each pixel driving circuit receives accurate analog voltage data and ensure the accuracy of pixel light emission. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0037] Figure 1 This is a schematic diagram of the structure of a display device provided in accordance with an exemplary embodiment of this application;

[0038] Figure 2 This is a schematic diagram of the structure of a display device provided in this application according to another exemplary embodiment;

[0039] Figure 3A , Figure 3B and Figure 3C This is the characteristic transfer curve of a P-type transistor;

[0040] Figure 4 This is a schematic diagram of the structure of a display device provided in this application according to another exemplary embodiment;

[0041] Figure 5 for Figure 4 A circuit diagram of the pixel circuit in the display device provided in the illustrated embodiment;

[0042] Figure 6 This is a schematic diagram of the structure of a display device provided in this application according to another exemplary embodiment;

[0043] Figure 7 for Figure 6 A circuit diagram of the pixel circuit in the display device provided in the illustrated embodiment;

[0044] Figure 8A and Figure 8B This is a timing diagram of a display device provided according to an exemplary embodiment of this application;

[0045] Figure 9 for Figure 4 Another circuit diagram of the pixel circuit in the display device provided in the illustrated embodiment;

[0046] Figure 10 This is a schematic diagram of the structure of a display device provided in this application according to another exemplary embodiment;

[0047] Figure 11 for Figure 10 A circuit diagram of the pixel circuit in the display device provided in the illustrated embodiment;

[0048] Figure 12 This is a schematic diagram of the structure of a display device provided in this application according to another exemplary embodiment;

[0049] Figure 13 for Figure 12 A circuit diagram of the pixel circuit in the display device provided in the illustrated embodiment;

[0050] Figure 14A and Figure 14B This is a timing diagram of a display device provided according to an exemplary embodiment of this application;

[0051] Figure 15 for Figure 12 Another circuit diagram of the pixel circuit in the display device provided in the illustrated embodiment.

[0052] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0053] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0054] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment. It should be further understood that the terms "comprising" or "including" indicate the presence of features, steps, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups.

[0055] In the description of this disclosure, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0056] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0057] In recent years, due to the advantages of micro-LEDs over AMOLEDs (Active-matrix organic light emitting diodes), such as smaller device size, faster response speed, higher luminous efficiency, stronger stability and longer lifespan, the application of micro-LEDs in displays has developed rapidly and has become a research hotspot in display devices.

[0058] A schematic diagram of the display device is shown below. Figure 1 and Figure 2 As shown, the system includes a control circuit 250, a data drive circuit 20, a gate drive circuit 30, a display panel 40, and a power supply circuit 280. The control circuit 250 and the data drive circuit 20 are electrically connected, as are the gate drive circuit 30 and the display panel 40.

[0059] The display panel has a power line 90, multiple gate lines 60, multiple data lines 50 and multiple pixel units 80. The multiple pixel units 80 are arranged in an array, and each pixel unit 80 is located in the area where the gate line 60 and the data line 50 intersect.

[0060] The gate driving circuit 30 is electrically connected to the gate line 60. The gate driving circuit 30 is configured to obtain clock signals and trigger signals from the control circuit 250, generate gate driving signals according to the clock signals and trigger signals, and transmit the gate driving signals to the corresponding pixel unit 80 through the gate line 60 to control the transistors in the pixel unit 80 to be turned on or off.

[0061] More specifically, the gate driving circuit 30 can be fabricated as a separate gate driver integrated circuit (GDIC). Alternatively, the gate driving circuit 30 can be integrated into the display panel; this integration is called gate-in-panel (GIP). In some cases, the GDIC can be electrically connected to the display panel 40 via a COG (Chip on Glass) process, or via a COF (Chipon Film) process. In the COF process, the component is electrically connected to the display panel 40 via a flexible printed circuit (FPC).

[0062] The data driving circuit 20 is a circuit that drives the data line 50. It is configured to acquire display data from the control circuit 250, convert it into an analog data voltage (Vdata), and transmit the analog data voltage to the corresponding pixel unit 80 through the data line 50, so that the pixel 802 in the pixel unit 80 emits light according to the analog data voltage. The magnitude of the analog data voltage determines the transient brightness of the pixel 802.

[0063] The data driving circuit 20 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit (SDIC) may include a shift register, latch circuit, digital-to-analog converter, and output buffer, etc.

[0064] The power supply circuit 280 is a circuit that provides stable electrical signals and is configured to provide the corresponding power signals to the display panel 40, control circuit 250, data drive circuit 20 and gate drive circuit 30.

[0065] In one configuration, each pixel unit 80 includes three pixel circuits 810, used to display red, blue, and green light respectively. In another configuration, each pixel unit 80 includes four pixel circuits 810, used to display red, blue, green, and white light respectively. No specific limitation is made here.

[0066] The color of light emitted by each pixel unit 810 is determined by the properties of its pixel 802. Pixel 802 can be any light-emitting device, including but not limited to OLED and micro LED.

[0067] A micro LED is a miniature light-emitting device manufactured using inorganic semiconductor layers. A micro LED typically includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. The structure of such micro LEDs can be diverse, including vertical, horizontal, and flip-chip types, and is not particularly limited to a specific structure.

[0068] More specifically, a pixel circuit 810 includes a pixel driving circuit 801 and a pixel 802. The pixel driving circuit 801 is electrically connected to the pixel 802 and is configured to drive the pixel 802 to emit light. The signals required by the pixel driving circuit 801 include a driving signal, a scan signal, and an emission control signal (EM control signal).

[0069] The drive signal can be generated by the control circuit 250 or obtained from an external source. It includes, but is not limited to, start pulse signal, clock signal, and enable signal.

[0070] The EM control signal is configured to control the driving duration of the pixel driving circuit. The luminescence control signal can be a global signal provided by the control circuit 250 or a signal generated by the gate driving circuit 30; no specific limitation is made here.

[0071] The scan signal is configured to initialize the pixel drive circuit and store analog voltage data.

[0072] If the EM control signal is a global signal generated by the control circuit 250, the gate drive circuit 30 obtains the EM control signal from the control circuit 250 and transmits the EM control signal to the corresponding pixel drive circuit 814 through the gate line 60.

[0073] If both the EM control signal and the scan signal are generated by the gate drive circuit 30, the gate drive circuit 30 includes a scan signal generation circuit 301 and an EM control signal generation circuit 302. The scan signal is output by the scan signal generation circuit 301, and the EM control signal is output by the EM control signal generation circuit 302.

[0074] Both the scan signal and the EM control signal are shift signals. The scan signal is used as an example to explain the shift signal. The scan signal includes multiple scan signals with different phases. The scan signal generation circuit 301 includes multiple serially connected scan signal generation sub-circuits, each outputting a scan signal of one phase. Each scan signal generation sub-circuit is configured to obtain a clock signal from the control circuit 250, obtain a scan signal from the output of its preceding scan signal generation sub-circuit, or obtain a trigger signal from the control circuit 10, generate a scan signal corresponding to the scan signal generation sub-circuit, and transmit the scan signal through the corresponding gate line 60 to the corresponding pixel driving circuit 814 to control the pixel driving circuit 814 to acquire display data at regular intervals.

[0075] The phase of the output signal of each scan signal generation sub-circuit lags behind the phase of the input signal. The pixel driving circuit 814 in each pixel unit 80 can be electrically connected to the scan signal generation circuit 301 through at least one gate line 60 to obtain a scan signal of at least one phase.

[0076] Typically, the pixel driving circuit 801 includes a driving transistor and a storage capacitor. In some embodiments, the pixel driving circuit 801 further includes at least one control transistor. For simplicity, the driving transistor is simply referred to as the driving transistor, and the control transistor is simply referred to as the control transistor. The storage capacitor is configured to store a display data analog voltage Vdata. The control transistor writes the data analog voltage to the storage capacitor. The data analog voltage is configured to be applied to the control terminal of the driving transistor, controlling the driving transistor to conduct, and the driving transistor outputs a driving current.

[0077] The display data includes grayscale values. The higher the grayscale value, the brighter the pixel 802. The lower the grayscale value, the lower the brightness of the pixel 802. The data driving circuit is configured to convert the grayscale values ​​into a data analog voltage output. When the driving transistor is a P-type transistor, the higher the grayscale value, the lower the data analog voltage, the higher the driving current output by the driving transistor, and the higher the brightness of the pixel 802. When the driving transistor is an N-type transistor, the higher the grayscale value, the higher the data analog voltage, the higher the driving current output by the driving transistor, and the higher the brightness of the pixel 802.

[0078] Figure 3A and Figure 3B This is the characteristic transfer curve of a P-type transistor. Figure 3A The size of the transistor is larger than Figure 3B The transistor size. Figure 3A and Figure 3B The x-axis represents the gate voltage Vg, and the y-axis represents the source-drain current I. Only the voltage range that allows the P-type transistor to conduct is considered, that is, the range where the gate voltage is less than 0.7V. This range is divided into a first voltage range ΔV1 and a second voltage range ΔV2.

[0079] In practice, due to limitations in voltage accuracy, not all gate voltages can be captured. For the driving transistor, when the analog data voltage is within the first voltage range ΔV1, i.e., when the driving current is relatively large, decreasing the analog data voltage by one unit results in a smaller increase in the output driving current, leading to higher driving current accuracy and thus higher brightness accuracy. Conversely, when the analog data voltage is within the second voltage range ΔV2, i.e., when the driving current is relatively small, decreasing the analog data voltage by one unit results in a larger increase in the output driving current, leading to lower driving current accuracy and thus lower brightness accuracy.

[0080] Since the simulated voltage is related to the grayscale value, the phenomenon of relatively low accuracy in luminance within the second voltage range ΔV2 is called the grayscale unexpandable grayscale value region. Typically, the grayscale value region corresponding to the second voltage range ΔV2 is a low grayscale region, also known as the low grayscale unexpandable problem.

[0081] The light intensity of each pixel 802 within a frame display cycle is determined by its average brightness within that frame display cycle. Therefore, when calculating the average brightness, the cumulative value of the transient brightness of pixel 802 during its emission period is divided by the duration of the frame display cycle to determine the average brightness. The transient brightness of pixel 802 is determined by the driving current of the driving transistor; the larger the instantaneous driving current, the brighter the transient brightness.

[0082] Based on the aforementioned light-emitting principle, the average brightness of the transistor can be maintained by shortening the driving duration of the driving transistor and increasing its transient driving current. Furthermore, the driving transistor can be switched from operating in the second current range ΔI2 to operating in the first current range ΔI1, thus resolving the issue of grayscale not expanding. More specifically, the EM control signal is configured to control the driving duration of the driving transistor, and the analog data voltage Vdata is configured to control the transient driving current of the driving transistor. By adjusting the EM control signal and the analog data voltage, the driving duration of the driving transistor can be shortened, and the transient driving current can be increased.

[0083] However, when a display device displays a frame, some pixel driving circuits may be able to perform grayscale expansion on the displayed data, while others may not. This means some pixel driving circuits have a larger driving current, while others have a smaller driving current. Since all pixel driving circuits in the display device use the same EM control signal, it is necessary to compress the emission duration of each pixel driving circuit. This allows the pixel driving circuits with smaller driving currents to obtain a data analog voltage Vdata within the first grayscale range ΔV1, thereby increasing the driving current of the pixel driving circuits and overcoming the problem of grayscale expansion.

[0084] Meanwhile, the pixel driving circuit, which originally had a large driving current, needs the grayscale value provided by the control circuit 10 to be closer to the limit value after the driving time is compressed. This limit value can be the maximum limit value or the minimum limit value. The data driving circuit provides the limit data analog voltage. When the data analog voltage required after time compression exceeds the range of data analog voltage that the data driving circuit can provide, the data driving circuit cannot provide an accurate data analog voltage, resulting in an inaccurate driving current provided by the pixel driving circuit, which affects the light emission accuracy of the pixel 802.

[0085] Considering the operating characteristics of transistors, such as Figure 3C As shown, when operating at high drive current for extended periods, characteristic curve drift is prone to occur, resulting in drive current drift. For example, when the gate voltage of the drive transistor is 0.4V, the drive current is 2.2μA without drift, but 2.3μA with drift. This application further addresses the aforementioned characteristic curve drift problem.

[0086] It should also be noted that the P-type transistor is used as an example here; the principle of the N-type transistor is similar and will not be described in detail here.

[0087] like Figure 4 As shown, one embodiment of this application provides a display device, which includes a data driving circuit and a display panel. The display panel is provided with a plurality of gate lines 60, a plurality of data lines 50, and a plurality of pixel units 80. Each pixel unit 80 includes at least one pixel circuit 810.

[0088] Each pixel circuit 810 includes a pixel 802 and a corresponding pixel driving circuit 801. The pixel driving circuit includes at least two sub-pixel driving circuits. Each sub-pixel driving circuit is electrically connected to the pixel 802. Each sub-pixel driving circuit corresponds to a different grayscale range.

[0089] The pixel driving circuit 801 is configured to receive a data analog voltage, and the first target sub-pixel driving circuit in at least two sub-pixel driving circuits outputs a driving signal to drive pixel 802 to emit light; the second target sub-pixel driving circuit is turned off, does not output a driving signal, and does not cause pixel 802 to emit light.

[0090] The grayscale range corresponding to the first target sub-pixel driving circuit includes the grayscale value corresponding to the data analog voltage.

[0091] The grayscale range corresponding to the second target sub-pixel driving circuit does not include the grayscale value corresponding to the data analog voltage.

[0092] In some embodiments, the gate driving circuit includes at least one first signal generation circuit 3021 and at least one second signal generation circuit 3022;

[0093] The first signal generation circuit 3021 is configured to output a first light-emitting control signal;

[0094] The second signal generation circuit 3022 is configured to output a second light emission control signal;

[0095] Among them, the light emission control signal is a signal that limits the driving duration of the driving signal.

[0096] In some embodiments, at least two sub-pixel driving circuits include a first sub-pixel driving circuit and a second sub-pixel driving circuit.

[0097] The first sub-pixel driving circuit includes a first driving transistor, and the second sub-pixel driving circuit includes a second driving transistor, wherein the size of the first driving transistor is larger than the size of the second driving transistor.

[0098] The first sub-pixel driving circuit and the second sub-pixel driving circuit are both electrically connected to the same first signal generation circuit 3021; ​​different second sub-pixel driving circuits are electrically connected to different second signal generation circuits 3022 respectively.

[0099] At least two sub-pixel driving circuits are also electrically connected to data line 50 and are configured to obtain data analog voltage and light emission control signals.

[0100] In some embodiments, the data analog voltage includes the display data analog voltage, which is the analog voltage corresponding to the grayscale value to be displayed.

[0101] The first target sub-pixel driving circuit is configured to receive display data analog voltage and output a driving signal; the driving signal is the signal that drives the pixel to emit light.

[0102] More specifically, when the first target sub-pixel driving circuit is only electrically connected to the first signal generation circuit 3021, the driving duration of its output driving signal is adjusted based on the first light emission control signal.

[0103] When the first target sub-pixel driving circuit is electrically connected to the first signal generation circuit 3021 and the second signal generation circuit 3022, the driving duration of the output driving signal is jointly controlled based on the first light emission control signal and the second light emission control signal.

[0104] In some embodiments, the data analog voltage further includes a shutdown data analog voltage, which is the analog voltage of the sub-pixel driving circuit in the pixel driving circuit that does not perform grayscale expansion of the display data analog voltage.

[0105] The second target sub-pixel driving circuit is configured to receive the shutdown data analog voltage and not output a driving signal.

[0106] In the above technical solution, each sub-pixel driving circuit is electrically connected to the same signal generation circuit. The obtained first light emission control signal can uniformly regulate the driving duration of each sub-pixel driving circuit. At least one sub-pixel driving circuit is electrically connected to the second signal generation circuit. The obtained second light emission control signal can further adjust the driving duration of the driving transistor to ensure normal grayscale expansion. The second signal generation circuits connected to each second sub-pixel driving circuit are different, and the driving duration adjustment strategies adopted are independent of each other. After each pixel driving circuit obtains the analog voltage data, it selects a suitable first target sub-pixel driving circuit to drive the pixel to emit light. The light emission time does not need to be compressed simultaneously using the same compression strategy, so there will be no situation where the grayscale value exceeds the grayscale value range that the controller can provide. This can ensure that each pixel driving circuit receives accurate analog voltage data and ensure the accuracy of pixel light emission.

[0107] The structure of the pixel driving circuit will be explained further below.

[0108] refer to Figure 4 The circuit structure shown includes a first sub-pixel driving circuit 8011, which includes a reference driving unit 8013, and the reference driving unit includes a driving transistor.

[0109] The reference drive unit is a unit that processes data and simulates voltage based on drive transistors;

[0110] In some embodiments, in the first sub-pixel driving circuit, the reference driving unit 8013 is electrically connected to the data line 50, the first signal generation circuit 3021, and the pixel 802, and is configured to obtain a first light emission control signal, and output a first driving signal when it obtains the display data analog voltage to drive the pixel 802 to emit light.

[0111] When it receives the analog voltage of the shutdown data, it does not output the first driving signal and does not affect the light emission state of pixel 802.

[0112] In some embodiments, in the second sub-pixel driving circuit, the reference driving unit 8013 is electrically connected to the data line 50 and the first signal generation circuit 3021, and is configured to obtain a first light emission control signal and output a second driving signal when it obtains the display data analog voltage.

[0113] It does not output a second drive signal when it obtains the analog voltage of the shutdown data;

[0114] The second driving signal is not a signal that directly acts on pixel 802.

[0115] In some embodiments, the second sub-pixel driving circuit further includes an emissivity adjustment unit 8014, which is electrically connected to its corresponding reference driving unit 8013, second signal generation circuit 3022, and pixel 802, and is configured to obtain a second emissivity control signal and output a third driving signal when the second driving signal is obtained.

[0116] More specifically, the light-emitting adjustment unit 8014 is configured to control its conduction state based on the second light-emitting control signal, and when it is on, it outputs the second driving signal it has obtained as the third driving signal;

[0117] When it is turned off, no third drive signal is output;

[0118] It will not output a third drive signal if it does not receive a second drive signal.

[0119] The driving period of the third driving signal is the sum of the driving period of the second driving signal and the conduction period of the light-emitting adjustment unit 8014.

[0120] In some embodiments, the reference driving unit 8013 is configured to store data analog voltage during the non-display phase of the display cycle;

[0121] During the display phase of the display cycle, a drive signal is generated based on the simulated voltage of the display data, or the drive transistor is turned off based on the simulated voltage of the shutdown data, and no drive signal is output.

[0122] In some embodiments, the reference driving unit 8013 includes a driving transistor and a light-emitting control transistor;

[0123] When the reference driving unit 8013 is in the first sub-pixel driving circuit 8011, the light-emitting control transistor is electrically connected between the output terminal of the driving transistor and the pixel 802.

[0124] When the reference driving unit 8013 is in the second sub-pixel driving circuit 8012, the light-emitting control transistor is electrically connected between the output terminal of the driving transistor and the light-emitting adjustment unit 8014.

[0125] In some embodiments, the reference driving unit 8013 is configured to obtain the display data analog voltage and control the driving transistor to generate a driving signal based on the display data analog voltage.

[0126] In other embodiments, the reference drive unit 8013 is configured to obtain a shutdown data analog voltage, control the drive transistor to turn off based on the shutdown data analog voltage, and not output a drive signal.

[0127] In some embodiments, the reference driving unit 8013 is configured to obtain a first light emission control signal and control the light emission control transistor to turn off during the non-display phase of the display cycle based on the first light emission control signal.

[0128] It is activated during the display phase;

[0129] More specifically, during the display phase, after the driving transistor of the reference driving unit 8013 outputs a driving signal, it outputs the aforementioned driving signal based on the first light emission control signal.

[0130] It is worth noting that in the reference driving unit 8013, which is electrically connected to the same first signal generation unit, the light-emitting control transistors have the same on-time.

[0131] When the reference drive unit 8013 outputs a drive signal, the reference drive unit 8013, which is electrically connected to the same first signal generation unit, outputs the drive signal at the same time.

[0132] In some embodiments, the light-emitting adjustment unit 8014 includes a light-emitting adjustment transistor, a first terminal of which is electrically connected to the output terminal of a light-emitting control transistor, a control terminal of which is electrically connected to a second signal generation circuit 3022, and an output terminal of which is electrically connected to a pixel 802. It is configured to obtain a second light-emitting control signal from its control terminal and control its conduction state by the second light-emitting control signal.

[0133] When the second driving signal is obtained from the output of the light-emitting control transistor at its first terminal, a third driving signal is output from its second terminal during its conduction process.

[0134] In the sub-pixel driving circuit, each pixel driving unit generates a driving signal during the display phase through the driving transistor. The driving duration of the driving signal is compressed by the light-emitting adjustment unit. Since the light-emitting control transistor is turned off during the non-display phase, the process of the driving transistor processing the analog voltage of the display data is separated from the duration compression operation of the light-emitting adjustment unit. Therefore, the duty cycle of the compression duration is no longer affected by the non-display phase of the display cycle, ensuring that the compression duty cycle of the driving duration has a large adjustable range.

[0135] Taking the pixel circuit 810, which includes two pixel driving circuits, as an example, please refer to [link / reference]. Figure 4 As shown, the pixel circuits are arrayed in the display panel. The two sub-pixel driving circuits can be arranged in the same row or in the same column. The two sub-pixel driving circuits are a first sub-pixel driving circuit 8011 and a second sub-pixel driving circuit 8012. The first sub-pixel driving circuit 8011 is electrically connected to pixel 802, and the second sub-pixel driving circuit 8012 is electrically connected to pixel 802.

[0136] When the two sub-pixel driving circuits are arranged in the same row, the data line 50 electrically connected to the first sub-pixel driving circuit 8011 is different from the data line 50 electrically connected to the second sub-pixel driving circuit 8012; the first pixel driving circuit 8011 and the second pixel driving circuit 8012 also receive different analog data voltages.

[0137] When the two sub-pixel driving circuits are arranged in the same row, the data line 50 electrically connected to the first sub-pixel driving circuit 8011 is the same as the data line 50 electrically connected to the second sub-pixel driving circuit 8012; the first pixel driving circuit 8011 and the second pixel driving circuit 8012 receive different analog data voltages in a time-division manner.

[0138] The analog voltage Vdata received by the first pixel driving circuit 811 controls whether the first pixel driving circuit 811 drives the light-emitting unit 813 to emit light. The analog voltage received by the second pixel driving circuit 812 controls whether the second pixel driving circuit 812 drives the light-emitting unit 813 to emit light.

[0139] The data analog voltage includes either the displayed data analog voltage or the off data analog voltage;

[0140] In some embodiments, in the pixel driving circuit, only one sub-pixel driving circuit obtains the display data analog voltage in each display cycle, while the voltages obtained by other sub-pixel driving circuits are the shutdown data analog voltages.

[0141] The sub-pixel driving circuit that obtains the display data analog voltage is the first target sub-pixel driving circuit. The grayscale value corresponding to the display data analog voltage is within the grayscale range corresponding to the target sub-pixel driving circuit. The first target sub-pixel driving circuit outputs a driving signal based on the display data analog voltage to drive pixel 802 to emit light.

[0142] The other sub-pixel driving circuits are the second target sub-pixel driving circuits. Based on the shutdown data, they simulate voltage and do not output driving signals, so they will not affect the luminous brightness of pixel 802.

[0143] In some embodiments, when two sub-pixel driving circuits are arranged in the same row, the data analog voltages obtained simultaneously by the first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 have the same phase.

[0144] In some embodiments, when two sub-pixel driving circuits are arranged in the same column, the phases of the analog data voltages obtained simultaneously by the first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 are different.

[0145] In some embodiments, the gate driving circuit is electrically connected to the pixel driving circuit 801 via multiple gate lines 60; the multiple gate lines 60 include multiple first gate lines. The first gate lines are configured to transmit a second light emission control signal.

[0146] In some embodiments, the second signal generation circuit 3022 electrically connected to the second sub-pixel driving circuit 8012 corresponding to the same grayscale range in different pixel driving circuits is the same.

[0147] Among them, the first gate lines of the second sub-pixel driving circuit 8012 located in the same row and corresponding to the same grayscale range are the same, and the phase of the obtained second light emission control signal is the same.

[0148] The second sub-pixel driving circuit 8012, which is located in the same column and corresponds to the same grayscale range, has different first gate lines, resulting in different phases of the obtained second light emission control signals.

[0149] When the display panel is scanning line by line from top to bottom, the second light emission control signals obtained by the second sub-pixel driving circuits 8012 in the first row and the second sub-pixel driving circuits 8012 in the second row of the same column have the same phase difference.

[0150] In some embodiments, the second light emission control signal received by the second sub-pixel driving circuit 8012 may be after driving time compression processing or without driving time compression processing, depending on the characteristics of the driving transistor in the second sub-pixel driving circuit 8012 and the displayed grayscale value.

[0151] In some embodiments, considering the different source-drain current ranges in the unexpandable grayscale value regions of different sized driving transistors, such as... Figure 3A As shown, the source-drain current range of the unexpandable grayscale region of the large-size driving transistor is ΔI1, as... Figure 3B As shown, the source-drain current range of the grayscale value region that cannot be expanded by the small-sized driving transistor is ΔI2. Different sizes of driving transistors are used for different luminous brightness so that the driving transistors work in the region with high driving current accuracy.

[0152] It can be assumed that the size of the driving transistor in the first sub-pixel driving circuit 8011 is larger than the size of the driving transistor in the second sub-pixel driving circuit 8012. The second sub-pixel driving circuit 8012 is also provided with a light emission adjustment unit 8014. The grayscale value range corresponding to the first sub-pixel driving circuit is the first grayscale range, and the grayscale value range corresponding to the second sub-pixel driving circuit is the second grayscale range. The lower limit of the first grayscale range is greater than or equal to the upper limit of the second grayscale range.

[0153] When the grayscale value of the display data is within the first grayscale range, the pixel driving circuit controls the first sub-pixel driving circuit 8011 to receive the display data analog voltage and output a driving signal based on the display data analog voltage.

[0154] The second sub-pixel driving circuit 8012 receives the shutdown data analog voltage and does not output a driving signal based on the shutdown data analog voltage.

[0155] When the grayscale value corresponding to the analog voltage of the display data is within the second grayscale range, the pixel driving circuit controls the second sub-pixel driving circuit 8012 to receive the second light emission control signal, thereby regulating the time compression of the second sub-pixel driving circuit 8012.

[0156] The data driving circuit can adjust the voltage value of the display data analog voltage based on the time compression duty cycle, so that the second sub-pixel driving circuit 8012 drives the brightness of the pixel to correspond to the grayscale value based on the driving signal generated by the display data analog voltage and the second light emission control signal.

[0157] The control circuit 8011 for the first sub-pixel receives the shutdown data analog voltage and does not output a drive signal based on the shutdown data analog voltage.

[0158] In other words, if the grayscale value in the display data allows the driving transistor in the sub-pixel driving circuit to operate within the first voltage range ΔV1, then there is no need to compress the driving time. If the grayscale value in the display data allows the driving transistor in the sub-pixel driving circuit to operate within the second voltage range ΔV2, then it is necessary to compress the driving time and increase the transient driving current to allow the driving transistor in the sub-pixel driving circuit 8012 to switch from the second voltage range V2 to the first voltage range V1, ensuring that the grayscale can be properly expanded, thereby ensuring the accuracy of the display.

[0159] In other embodiments, the size of the driving transistor in the first sub-pixel driving circuit and the size of the driving transistor in the second sub-pixel driving circuit can be the same, and the second sub-pixel driving circuit performs time compression processing on grayscale values ​​that the first sub-pixel driving circuit cannot process based on the second light emission control signal.

[0160] In some embodiments, the plurality of gate lines 60 includes a plurality of second gate lines configured to transmit scan signals.

[0161] In some embodiments, the reference driving unit 8013 may be initialized based on the first scan signal;

[0162] In other embodiments, the reference drive unit 8013 may simulate voltage based on data processed by the second scan signal.

[0163] The initialization and data simulation voltage processing are both performed during the non-display phase of the display cycle, and the processing timing and process of each sub-pixel driving circuit are the same.

[0164] In some embodiments, the second gate line that transmits the same type of scan signal is electrically connected to the first sub-pixel driving circuit and the second sub-pixel driving circuit located in the same row, and the same type of scan signal is obtained by the first sub-pixel driving circuit and the second sub-pixel driving circuit.

[0165] The second gate lines of the first sub-pixel driving circuit and the second sub-pixel driving circuit, which are located in the same column and are electrically connected to transmit the same type of scan signal, are different, but they are both signals generated by the same scan signal generation circuit. The same type of scan signal obtained by the first sub-pixel driving circuit and the second sub-pixel driving circuit have a phase shift.

[0166] More specifically, the second gate lines for transmitting the first scan signal that are electrically connected to the first sub-pixel driving circuit and the second sub-pixel driving circuit located in the same row are the same, and the second gate lines for transmitting the second scan signal that are electrically connected are the same.

[0167] The first sub-pixel driving circuit and the second sub-pixel driving circuit, located in the same column, share the same first scan signal generation circuit, but their second gate lines for transmitting the first scan signal are different. The first scan signals obtained by the two sub-pixel driving circuits have a phase difference, which is determined by the scan delay. The first scan signal generation circuit outputs first scan signals with multiple phases.

[0168] Similarly, the second scan signal generation circuits electrically connected to the first and second sub-pixel driving circuits in the same column are identical, but the second gate lines for transmitting the second scan signals are different. The second scan signals obtained by the two sub-pixel driving circuits have a phase difference, which is determined by the scan delay. The second scan signal generation circuit outputs second scan signals with multiple phases.

[0169] In some embodiments, the phase difference between the first scan signal obtained by the first sub-pixel driving circuit and the second sub-pixel driving circuit located in the same column and the phase difference between the obtained second scan signal are the same.

[0170] In some embodiments, the plurality of gate lines 60 further include a plurality of third gate lines, the third gate lines being configured to transmit a first light emission control signal;

[0171] During the non-display phase of the display cycle, the reference driving unit 8013 can perform data analog voltage processing based on one type of first light emission control signal, and can also isolate the reference driving unit and the light emission adjustment unit based on another type of first light emission control signal. The processing timing and processing procedure of the same type of first light emission control signal are the same.

[0172] The third gate line that transmits the same type of first light emission control signal is the same for the first sub-pixel driving circuit and the second sub-pixel driving circuit located in the same row, and the first sub-pixel driving circuit and the second sub-pixel driving circuit obtain the same type of first light emission control signal.

[0173] The first signal generation circuit 3021, which generates the same type of first light emission control signal, is electrically connected to the first sub-pixel driving circuit and the second sub-pixel driving circuit located in the same column. However, the third gate line that transmits the same type of first light emission control signal is different. The same type of first light emission control signal obtained by the first sub-pixel driving circuit and the second sub-pixel driving circuit has a phase shift.

[0174] In some embodiments, reference Figure 6 The circuit structure shown includes at least two sub-pixel driving circuits, each of which is electrically connected to the same pixel; each sub-pixel driving circuit corresponds to a different grayscale range.

[0175] Each sub-pixel driving circuit is electrically connected to the same first signal generation circuit and electrically connected to different second signal generation circuits respectively.

[0176] The sub-pixel driving circuit and the data driving circuit are electrically connected and configured to obtain data analog voltage and light emission control signal, the data analog voltage including display data analog voltage and turn-off data analog voltage;

[0177] The first target sub-pixel driving circuit is a sub-pixel driving circuit whose grayscale value range includes the grayscale value corresponding to the display data analog voltage. The first target sub-pixel driving circuit is configured to receive the display data analog voltage and output a driving signal.

[0178] The driving signal is the signal that drives the pixel to emit light.

[0179] The second target sub-pixel driving circuit is configured to receive the shutdown data analog voltage and not output a driving signal.

[0180] In some embodiments, both the first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 include a reference driving unit 8013 and a light-emitting adjustment unit 8014, wherein the circuit connection relationship and driving process of the reference driving unit 8013 and the light-emitting adjustment unit 8014 are consistent with... Figure 4The description of the second sub-pixel driving circuit 8012 in the corresponding embodiment is the same, and will not be repeated here.

[0181] exist Figure 6 In the circuit structure shown, the first gate lines electrically connected to the first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 are different, the duty cycles of the obtained second light emission control signals do not affect each other, and the time compression strategies used are unrelated.

[0182] When the sub-pixel driving circuits are arranged in the same row, the second light emission control signal obtained by the first sub-pixel driving circuit and the second light emission control signal obtained by the second sub-pixel driving circuit are in phase.

[0183] When the sub-pixel driving circuits are arranged in the same column, the phases of the second light emission control signal obtained by the first sub-pixel driving circuit and the second light emission control signal obtained by the second sub-pixel driving circuit are different.

[0184] Since the first sub-pixel driving circuit and the second sub-pixel driving circuit are connected to different first gate lines configured to transmit the second light emission control signal, the first sub-pixel driving circuit and the second sub-pixel driving circuit can receive different second light emission control signals. The driving time of the first sub-pixel driving circuit and the second sub-pixel driving circuit in different sub-pixel driving circuits does not need to be compressed at the same time. Therefore, the grayscale value will not exceed the grayscale value range that the controller can provide. This can ensure that each pixel driving circuit receives accurate data analog voltage and ensure the light emission accuracy of the pixel.

[0185] In other embodiments, taking into account the operating characteristics of the transistor, such as Figure 3C As shown, when operating at high drive current for extended periods, characteristic curve drift can easily occur, leading to drive current drift. This can cause the drive transistor to fail to output accurate drive current, resulting in pixels not emitting light at the corresponding brightness. To address this issue, the drive current of the drive transistor in each pixel drive circuit is varied, partially offsetting or eliminating the inaccurate drive current caused by characteristic curve drift.

[0186] The sub-pixel driving circuit in the controllable pixel driving circuit cannot continuously drive the pixel to emit light in two adjacent display cycles.

[0187] To simplify the control logic, the size of the driving transistor in the first sub-pixel driving circuit 8011 and the size of the driving transistor in the second sub-pixel driving circuit 8012 can be set to be the same. Then, the first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 are respectively provided with light-emitting adjustment units 8014. Each sub-pixel driving circuit can determine whether it is necessary to control the light-emitting adjustment unit 8014 to compress the driving time of the driving signal based on the voltage range of the analog voltage of the display data.

[0188] During the current frame display cycle, the pixel driving circuit controls the first sub-pixel driving circuit to obtain the first display data analog voltage, the first light emission control signal, and the second light emission control signal, and outputs the first driving signal based on the first display data analog voltage and the two light emission control signals.

[0189] The second sub-pixel driving circuit is controlled to obtain the shutdown data analog voltage and does not output a driving signal;

[0190] In the next frame display cycle, the pixel driving circuit controls the first sub-pixel driving circuit to obtain the shutdown data analog voltage and stop outputting the driving signal;

[0191] The second sub-pixel driving circuit is controlled to obtain the second display data analog voltage, the first light emission control signal, and the second light emission control signal, and outputs the second driving signal based on the second display data analog voltage and the two light emission control signals.

[0192] With this configuration, during two consecutive display cycles corresponding to a pixel unit, the sub-pixel driving circuit can stop outputting the driving current during the display data display of a certain frame, which can partially offset or eliminate the problem of inaccurate driving current of the driving transistor caused by the drift of the characteristic curve of the driving transistor.

[0193] The following is for reference. Figure 4 The circuit structure shown is used as an example with two sub-pixel driving circuits located in the same row to explain the operation of a multi-row pixel driving circuit.

[0194] The first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 are located in the same row. The data lines electrically connected to the first sub-pixel driving circuit 8011 are different from those electrically connected to the second sub-pixel driving circuit 8012. Both the first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 are electrically connected to three types of gate lines, which respectively transmit the first light emission control signal, the scan signal, and the light emission control signal.

[0195] More specifically, such as Figure 4 As shown in the figure, only the pixel unit (1, j) in the j-th column of the first row and the pixel unit (2, j) in the j-th column of the second row are shown. The two pixel units are described below one by one.

[0196] The pixel unit (1, j) located in the j-th column of the first row includes two pixel circuits 810. The first pixel circuit 810 is a red light pixel circuit 810(R), and the second pixel circuit 810 is a green light pixel circuit 810(G). It should be noted that the pixel unit may also include three or more pixel circuits 810. The three pixel circuits 810 can be a red light pixel circuit 810(R), a green light pixel circuit 810(G), and a blue light pixel circuit 810(B), respectively.

[0197] In the first pixel circuit 810 of the pixel unit (1, j) in the jth column of the first row, the pixel circuit 810 includes a first sub-pixel driving circuit 8011, a second sub-pixel driving circuit 8012 and a pixel 802. The first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 are both electrically connected to the pixel 802, and the pixel 802 emits red light.

[0198] In the first pixel circuit 810 of the j-th column pixel unit (1, j) in the first row, the first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 are located in the same row. The data lines electrically connected to the first sub-pixel driving circuit 8011 are different from those electrically connected to the second sub-pixel driving circuit 8012. The data lines electrically connected to the first sub-pixel driving circuit 8011 transmit the analog data voltage VdataRj_A, and the data lines electrically connected to the second sub-pixel driving circuit 8012 transmit the analog data voltage VdataRj_B. R represents the analog data voltage generated based on the red light data in the display data, j represents the j-th column pixel unit, _A indicates electrical connection to the first sub-pixel driving circuit 8011, and _B indicates electrical connection to the second sub-pixel driving circuit 8012.

[0199] In the pixel circuit 810 of the pixel unit (1, j) in the jth column of the first row, the first sub-pixel driving circuit 8011 includes a reference driving unit 8013, which is not electrically connected to the first gate line that transmits the second light emission control signal E1_B, but is electrically connected to the third gate line E1_A that transmits the first light emission control signal.

[0200] The second sub-pixel driving circuit 8012 includes a reference driving unit 8013 and a light emission adjustment unit 8014, which is electrically connected to the third gate line E1_A that transmits the first light emission control signal. In different pixel circuits 810, the second sub-pixel driving circuits 8012 corresponding to the same grayscale range are electrically connected to the same gate line.

[0201] In the signal labels, the numbers correspond to the signal generation circuits. When the numbers are the same, the signal generation circuits are the same. When the corresponding letters are the same, the signals have the same phase. When the corresponding letters are different, the signals have different phases.

[0202] The second gate lines electrically connected to the first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 located in the same row are the same. That is, the second gate lines electrically connected to the two sub-pixel driving circuits for transmitting the first scan signal S1 are the same, and the second gate lines electrically connected to the two sub-pixel driving circuits for transmitting the second scan signal S2 are the same. The first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 can perform the same operations based on the above two scan signals, such as initialization operations, data writing operations, data compensation operations, etc.

[0203] The first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 may be located in the same pixel circuit 810 or in different pixel circuits 810.

[0204] The first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012, which are located in the same row, share the same third gate line for transmitting the light emission control signal. The first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 can generate a driving signal based on the first light emission control signal E1_A and the pre-stored display data analog voltage. The driving signal has the same driving duration in each sub-pixel driving circuit.

[0205] In the two pixel circuits 810 of the pixel unit (1, j) in the jth column of the first row, the first sub-pixel driving circuit 8011 of the first pixel circuit 810 is not electrically connected to the first gate line that transmits the second light emission control signal E1_B, and the second sub-pixel driving circuit 8012 is electrically connected to the first gate line that transmits the second light emission control signal E1_B. The sub-pixel driving circuit can compress the driving duration of the driving signal based on the corresponding obtained light emission control signal to meet the requirements of expanding the grayscale value corresponding to the analog voltage of the display data.

[0206] In some embodiments, the first sub-pixel driving circuit 8011 can process display data analog voltage with uniform time compression, and the second sub-pixel driving circuit 8012 can process various types of display data analog voltage.

[0207] The second pixel circuit 810 of the first ...

[0208] The difference is that the received data is different, and the color of the pixel emission is also different.

[0209] The following explains the relationship between the pixel circuits 810 in different rows.

[0210] The first pixel circuit 810 of the second row and the first pixel circuit 810 of the first ...

[0211] The data lines electrically connected to the first sub-pixel driving circuit 8011 of different rows all transmit analog data voltage VdataBj_A. Since the display device scans line by line, there is a time delay between the data reception and display of each row of pixel circuits and the previous row of pixel circuits. The data lines can transmit different analog data voltages to the pixel circuits of different rows based on this time delay. Therefore, the phase of the analog data voltages received by the pixel circuits of different rows is different.

[0212] Similar to data transmission, the gate lines of the first sub-pixel driving circuit 8011 in different rows that transmit the same type of signal are different. That is, the first scan signal, the second scan signal, and the light emission control signal obtained are also signals with different phases relative to other rows, but the signal generation circuits that are electrically connected are the same.

[0213] Figure 5 for Figure 4 A circuit diagram of the pixel circuit 810 in the display device provided in the illustrated embodiment. (See diagram for reference.) Figure 5 As shown, the pixel circuit 810 includes a first sub-pixel driving circuit 8011 and a second sub-pixel driving circuit 8012.

[0214] The first sub-pixel driving circuit 8011 includes a reference driving unit, which includes a first initialization circuit 821 and a first driving circuit 822.

[0215] The first initialization circuit 821 is electrically connected to a second gate line and is configured to receive a first scan signal S1 from the gate line. Under the control of the first scan signal S1, the voltage of the data storage terminal G_A and the output terminal of the first driving circuit 822 is set to the reference voltage Vref.

[0216] The first driving circuit 822 is electrically connected to the first initialization circuit 821 and another second gate line, a third gate line, and a data line. It is configured to receive a second scan signal S2 from the second gate line, obtain a first light emission control signal E1_A from the third gate line, obtain a data analog voltage VdataRj_A from the data line, write the data analog voltage VdataRj_A to the storage capacitor C11 in the first driving circuit 822 based on the second scan signal S2, and determine whether to output a driving signal based on the first light emission control signal E1_A and the data analog voltage VdataRj_A.

[0217] The second sub-pixel driving circuit 8012 includes a reference driving unit. The reference driving unit includes a second initialization circuit 823 and a second driving circuit 824.

[0218] In some embodiments, the second sub-pixel driving circuit 8012 further includes a second light-emitting adjustment unit 80142.

[0219] The difference between the reference driving unit in the second sub-pixel driving circuit 8012 and the reference driving unit in the first sub-pixel driving circuit 8011 lies in the different data lines connected electrically, resulting in different display analog voltages and different output driving signals.

[0220] In the second sub-pixel driving circuit 8012, the second light emission adjustment unit 80142 is connected in series between the output terminal of the second driving circuit 824 and the pixel 802, and is electrically connected to the first gate line. It is configured to obtain the second light emission control signal E1_B from the first gate line, and adjust its conduction duration based on the second light emission control signal E1_B, thereby adjusting the duration of the second sub-pixel driving circuit 8012 outputting the driving signal to the pixel 802, so as to achieve compression of the driving time of the driving signal.

[0221] More specifically, the first driving circuit 822 includes an output terminal Ano_A and a data storage terminal G_A, and the first initialization circuit 821 includes a first output terminal and a second output terminal.

[0222] The first output terminal of the first initialization circuit 821 is electrically connected to the data storage terminal G_A of the first driving circuit 822, and the second output terminal of the first initialization circuit 821 is electrically connected to the output terminal Ano_A of the first driving circuit 822.

[0223] The first initialization circuit 821 is configured to set the voltage of the data storage terminal G_A and the output terminal Ano_A of the first driving circuit 822 to the reference voltage Vref, and the voltage of the driving terminal of the pixel 802 electrically connected to the output terminal Ano_A is also initialized to the reference voltage Vref.

[0224] The first initialization circuit 821 includes a first transistor M11 and a fourth transistor M14.

[0225] The first terminal of the first transistor M11 is electrically connected to the power supply line 90, and the voltage of the power supply line 90 is the reference voltage Vref. The second terminal of the first transistor M11 is electrically connected to the output terminal Ano_A of the first driving circuit 822.

[0226] The control terminal of the first transistor M11 receives the first scan signal S1. Under the control of the first scan signal S1, the first transistor M11 is turned on, so that the output terminal Ano_A of the first driving circuit 822 is connected to the reference voltage Vref.

[0227] When the first transistor M11 is a P-type transistor, it is turned on when the first scan signal S1 is low and turned off when it is high.

[0228] When the first transistor M11 is an N-type transistor, it is turned on when the first scan signal S1 is high and turned off when it is low.

[0229] The following explanations will all use P-type transistors in the pixel driving circuit as an example.

[0230] The first terminal of the fourth transistor M14 is electrically connected to the data storage terminal Ano_A of the first driving circuit 822, and the second terminal of the fourth transistor M14 is electrically connected to the power supply line 90, the voltage of the power supply line 90 being the reference voltage Vref.

[0231] The control terminal of the fourth transistor M14 receives the first scan signal S1. Under the control of the first scan signal S1, the fourth transistor M14 is turned on, so that the output terminal Ano_A of the first driving circuit 822 is connected to the reference voltage Vref.

[0232] The fourth transistor M14 is turned on when the first scan signal S1 is low and turned off when it is high.

[0233] Therefore, the voltages of the data storage terminal G_A and the output terminal Ano_A of the first driving circuit 822 are made to be the reference voltage Vref.

[0234] The first driving circuit 822 includes a second transistor M12, a third transistor M13, a fifth transistor M15, a sixth transistor M16, a first driving transistor M17, and a first storage capacitor C11.

[0235] The first terminal of the fifth transistor M15 is electrically connected to the power supply line 90, and the voltage of the power supply line 90 is the power supply voltage VDD. The second terminal of the fifth transistor M15 is electrically connected to the first terminal of the first driving transistor M17.

[0236] The control terminal of the fifth transistor M15 is configured to receive the first light-emitting control signal E1_A. Under the control of the first light-emitting control signal E1_A, the fifth transistor M15 connects the first terminal of the first driving transistor M17 to the power supply voltage VDD.

[0237] The fifth transistor M15 is turned on when the first light-emitting control signal E1_A is low and turned off when it is high.

[0238] The first terminal of the second transistor M12 is electrically connected to the first terminal of the first driving transistor M17, and the second terminal of the second transistor M12 is configured to receive the analog data voltage VdataRj_A.

[0239] The control terminal of the second transistor M12 is configured to receive the second scan signal S2. Under the control of the second scan signal S2, the second terminal of the second transistor M12 and the first terminal of the first driving transistor M17 are connected, so that the data analog voltage VdataRj_A is transmitted to the first terminal of the first driving transistor M17.

[0240] The second transistor M12 is turned on when the second scan signal S2 is low and turned off when it is high.

[0241] The first terminal of the first storage capacitor C11 is electrically connected to the power supply line 90, and the second terminal of the first storage capacitor C11 is the data storage terminal G_A of the first driving circuit 822. The voltage at the second terminal of the first storage capacitor C11 is the reference voltage Vref or the data analog voltage VdataRj_A after threshold voltage compensation. This threshold voltage is the threshold voltage of the first driving transistor M17.

[0242] The second terminal of the third transistor M13 is connected to the second terminal of the first driving transistor M17. The first terminal of the third transistor M13 is electrically connected to the second terminal of the first storage capacitor C11, and also electrically connected to the control terminal of the first driving transistor M17.

[0243] The control terminal of the third transistor M13 is configured to receive the second scan signal S2. Under the control of the second scan signal S2, the second terminal of the third transistor M13 and the control terminal are short-circuited to construct a threshold compensation structure.

[0244] After the voltage at the second terminal of the first storage capacitor C11 is initialized to the reference voltage Vref, the first driving transistor M17 is turned on, and a threshold compensation structure can be constructed with the turned-on third transistor M13. This threshold compensation structure is a diode structure.

[0245] The diode structure and the second transistor M12 form a discharge path between the first storage capacitor C11 and the data line 50, discharging the electrical signal stored in the first storage capacitor C11 until the voltage difference across the diode structure is the conduction voltage of the diode structure.

[0246] Since data line 50 is active and its voltage remains constant, when the diode structure is turned off, the voltage stored in the first storage capacitor C11 is the sum of the data analog voltage and the threshold voltage of the first driving transistor M17.

[0247] The first driving transistor M17 is configured to receive the power supply voltage VDD when the fifth transistor M15 is turned on. It is turned on by the power supply voltage VDD and the voltage stored at the second terminal of the first storage capacitor C11, and the current when it is turned on is determined by the power supply voltage VDD and the data analog voltage VdataRj_A.

[0248] Since the threshold voltage has been compensated during the data analog voltage writing, the current value of the drive signal determined by the first drive transistor M17 is no longer affected by the threshold voltage.

[0249] The sixth transistor M16 serves as a light-emitting control transistor. Its first terminal is connected to the second terminal of the first driving transistor M17. The second terminal of the sixth transistor M16 serves as the output terminal Ano_A of the first driving circuit 822. The control terminal of the sixth transistor M16 is configured to receive the first light-emitting control signal E1_A and conduct under the control of the first light-emitting control signal E1_A, outputting the current when the first driving transistor M17 is turned on.

[0250] The difference between the circuit of the second sub-pixel driving circuit 8012 and the circuit of the first sub-pixel driving circuit 8011 is that the first output terminal of the second initialization circuit 823 is electrically connected to the data storage terminal G_B of the second driving circuit 824, and the second output terminal of the second initialization circuit 823 is electrically connected to the output terminal Ano_C of the second light-emitting adjustment unit 80142.

[0251] When the second initialization circuit 823 is turned on for initialization, it adjusts the voltage values ​​of the data storage terminal G_B and the output terminal Ano_C to the reference voltage Vref. Since the output terminal Ano_C is electrically connected to the driving terminal of the pixel 802, the driving terminal of the pixel 802 is also initialized to the reference voltage Vref, and the initialization target of the two initialization circuits 823 remains unchanged.

[0252] The connection relationships and driving processes of the devices in the second driving circuit 824 are the same as those of the corresponding devices in the first driving circuit 822, and will not be repeated here. The corresponding relationships of the devices are as follows: eighth transistor M22 and second transistor M12, ninth transistor M23 and third transistor M13, eleventh transistor M25 and fifth transistor M15, twelfth transistor M26 and sixth transistor M16, second driving transistor M27 and first driving transistor M17, and second storage capacitor C21 and first storage capacitor C11.

[0253] The second light-emitting adjustment unit 80142 includes a second light-emitting adjustment transistor M28, whose first terminal is electrically connected to the second terminal of the twelfth transistor M26, and whose second terminal is electrically connected to the pixel 802. Its control terminal is electrically connected to the first gate line. It is configured to obtain a driving signal from its first terminal and a second light-emitting control signal E1_B from its control terminal. The second light-emitting control signal E1_B controls its conduction state. When it is on, it outputs a driving signal to drive the pixel 802 to emit light; when it is off, it stops outputting the driving signal and the pixel 802 does not emit light.

[0254] In some embodiments, the second light emission control signal is a multi-pulse signal within a frame display cycle, which is used by the sub-pixel driving circuit to uniformly output driving current at intervals within the time period of a frame display data, so as to reduce the probability of screen flickering.

[0255] The pulse period of the second light-emitting control signal is shorter than the display period.

[0256] It is worth noting that the twelfth transistor M26 and the sixth transistor M16 are both turned off during data writing and initialization. Therefore, voltage changes at their second terminals will not affect voltage changes at their first terminals. When their second terminals are electrically connected to the light-emitting adjustment unit, the conduction status of the light-emitting adjustment unit will not affect the accuracy of data writing and initialization. Thus, the duty cycle of the second light-emitting control signal can be adjusted within the range of 0 to 1. When the second driving transistor M27 is writing data, the conduction of the light-emitting adjustment unit will not affect the accuracy of data writing, ensuring a wide range of adjustable drive compression signals.

[0257] In some embodiments, when the second sub-pixel driving circuit 8012 includes a second light-emitting adjustment unit 80142, the first sub-pixel driving circuit 8011 also includes a first light-emitting adjustment unit 80141. A schematic diagram of this circuit structure is shown below. Figure 7 As shown, in the first sub-pixel driving circuit 8011, the electrical connection relationship between the first light-emitting adjustment unit 80141, the first driving circuit 822, and the pixel 802 is the same as the electrical connection relationship between the second light-emitting adjustment unit 80142, the second driving circuit 824, and the pixel 802. The difference lies in the different first gate lines of the electrical connection, resulting in different second light-emitting control signals.

[0258] The following is combined Figure 8A , Figure 8B Taking the example that all transistors in the pixel driving circuit are P-type transistors, the driving process of the pixel driving circuit will be explained.

[0259] The driving cycle T of the pixel driving circuit includes the initialization phase t1, the data writing phase t2, and the display phase t3.

[0260] During the initialization phase t1, the first scan signal S1 is at a low level, the second scan signal S2 and the first light emission control signal E1_A are at a high level, and each second light emission control signal E1_B is a pulse signal with an arbitrary duty cycle.

[0261] Since the first scan signal S1 is low, the first transistor M11 and the seventh transistor M21 are turned on, and the reference voltage Vref obtained at their first terminals is output to initialize the driving terminal of pixel 802.

[0262] Since the first scan signal S1 is low, the fourth transistor M14 and the tenth transistor M24 are turned on, outputting the reference voltage Vref obtained at their first terminals, and initializing the driving terminals of the corresponding driving transistors.

[0263] Since the reference voltage Vref is low, the drive transistor is turned on.

[0264] Since the first light-emitting control signal E1_A is high, the eleventh transistor M25, the fifth transistor M15, the twelfth transistor M26, and the sixth transistor M16 are all turned off. Therefore, the conduction of the first light-emitting regulating transistor M18 and the second light-emitting regulating transistor M28 based on the second light-emitting control signal E1_B will not affect the initial potential change, nor will it affect the potential change of the driving transistor.

[0265] During the data writing phase t2, the second scan signal S2 is at a low level, the first scan signal S1 and the first light emission control signal E1_A are at a high level, and each second light emission control signal E1_B is a pulse signal with an arbitrary duty cycle.

[0266] Since the second scan signal S2 is low, the third transistor M13 is turned on, which turns on the driving terminal and the second terminal of the first driving transistor M17, thus constructing a threshold compensation structure.

[0267] Since the second scan signal S2 is low, the ninth transistor M23 is turned on, which turns on the driving terminal and the second terminal of the second driving transistor M27 to construct the threshold compensation structure.

[0268] Since the second scan signal S2 is low, the second transistor M12 and the eighth transistor M22 are turned on, transmitting the analog voltage of the data provided by the data line to the first end of the corresponding driving transistor.

[0269] The first storage capacitor C11, which is electrically connected to the driving terminal of the first driving transistor M17, discharges through the threshold compensation structure and the second transistor M12 until the voltage at the driving terminal of the first driving transistor M17 is the data analog voltage for its threshold voltage compensation.

[0270] The second storage capacitor C21, which is electrically connected to the driving terminal of the second driving transistor M17, discharges through the threshold compensation structure and the eighth transistor M22 until the voltage at the driving terminal of the second driving transistor M27 is the data analog voltage for its threshold voltage compensation.

[0271] When the grayscale value corresponding to the data analog voltage is within the first grayscale range corresponding to the first sub-pixel driving circuit 8011, the data analog voltage VdataRj_A obtained by the second transistor M12 is the display data analog voltage, and the data analog voltage VdataRj_B obtained by the eighth transistor M22 is the shutdown data analog voltage. The potential of the two data analog voltages is as follows: Figure 8A As shown, VdataRj_A is the voltage corresponding to the grayscale value during the data writing phase t2.

[0272] In some embodiments, VdataRj_A jumps from voltage H to the voltage value corresponding to the grayscale value within the initialization phase t1 before the data writing phase t2, and jumps from the voltage value corresponding to the grayscale value to voltage H within the display phase t3 after the data writing phase t2, in order to prevent the voltage jump within the data writing phase t2 from causing erroneous data reading.

[0273] Continue to refer to Figure 8A The voltage value of VdataRj_B during the data writing phase t2 remains unchanged compared to the voltage value during the initialization phase t1, and is still voltage H. Here, voltage H is the voltage value corresponding to the simulated voltage for data shutdown.

[0274] In some embodiments, the voltage value of voltage H is the same as the power supply voltage VDD.

[0275] When the grayscale value corresponding to the data analog voltage is within the second grayscale range corresponding to the second sub-pixel driving circuit 8011, the data analog voltage VdataRj_A obtained by the second transistor M12 is the off data analog voltage, and the data analog voltage VdataRj_B obtained by the eighth transistor M22 is the display data analog voltage. The potential of the two data analog voltages is as follows: Figure 8B As shown, the level change state of VdataRj_B is related to... Figure 8A The level change state of VdataRj_A is the same as that of VdataRj_A. Figure 8A The level changes of VdataRj_B are the same, so they will not be described again here.

[0276] Since the first light-emitting control signal E1_A is high, the twelfth transistor M26 and the sixth transistor M16 are turned off. The conduction of the first light-emitting regulating transistor M18 and the second light-emitting regulating transistor M28 based on the second light-emitting control signal E1_B will not affect the accuracy of writing the data analog voltage.

[0277] During the time period corresponding to the display phase t3, the first light emission control signal E1_A is at a low level, the first scan signal S1 and the second scan signal S2 are at a high level, and each second light emission control signal E1_B is a pulse signal with an arbitrary duty cycle.

[0278] Since the first light-emitting control signal E1_A is at a low level, the fifth transistor M15 is turned on, and the power supply voltage VDD is written to the first terminal of the first driving transistor M17.

[0279] The first driving transistor M17 determines the current value of the driving signal based on the power supply voltage VDD and the voltage value stored at the second terminal of the first storage capacitor C11.

[0280] Since the first light-emitting control signal E1_A is low, the eleventh transistor M25 is turned on, writing the power supply voltage VDD to the first terminal of the second driving transistor M27.

[0281] The second driving transistor M27 determines the current value of the driving signal based on the power supply voltage VDD and the voltage value stored at the second terminal of the second storage capacitor C21.

[0282] exist Figure 8A In the waveform diagram shown, the voltage obtained by the first driving transistor M17 from the first storage capacitor C11 is the display data analog voltage compensated by its threshold voltage, and then the first driving transistor M17 outputs a driving signal.

[0283] When the voltage obtained by the second driving transistor M27 from the second storage capacitor C21 is high, the second driving transistor M27 is turned off.

[0284] Since the first light-emitting control signal E1_A is low, the sixth transistor M16 is turned on, obtains a drive signal at its first terminal, and outputs a drive signal from its second terminal.

[0285] Since the first light-emitting control signal E1_A is low, the twelfth transistor M26 is turned on. Since the second driving transistor M27 is turned off and does not receive a driving signal, it does not output a driving signal.

[0286] In the sixth transistor M16, such as Figure 5 When electrically connected to pixel 802, the driving signal output by the sixth transistor M16 drives pixel 802 to emit light.

[0287] exist Figure 8B In the waveform diagram shown, the voltage obtained by the first driving transistor M17 from the first storage capacitor C11 is a high-level voltage, so the first driving transistor M17 is turned off.

[0288] The voltage obtained by the second driving transistor M27 from the second storage capacitor C11 is the display data analog voltage compensated by its threshold voltage. Then, the second driving transistor M27 determines the current value of the driving signal, and the twelfth transistor M26 outputs the driving signal.

[0289] The second light-emitting regulating transistor M28 changes its conduction state based on the changing second light-emitting control signal E1_B. When the second light-emitting control signal E1_B is low, it conducts and outputs a driving signal to drive pixel 802 to emit light; when the second light-emitting control signal E1_B is high, it turns off, stops outputting the driving signal, and pixel 802 stops emitting light.

[0290] The second signal generation circuit 3022 adjusts the duty cycle of the second light emission control signal E1_B, compresses the driving duration of the driving signal, and increases the transient current value of the driving signal, which helps with grayscale expansion.

[0291] In some embodiments, when the circuit structure of the first sub-pixel driving circuit 8011 is as follows: Figure 7 As shown, when the first light-emitting regulating transistor M18 is also included, the first light-emitting regulating transistor M18 obtains the second light-emitting control signal E1_C, and its conduction state is controlled by the second light-emitting control signal E1_C to compress the driving duration of the driving signal output by the first driving transistor M17.

[0292] In some embodiments, the duty cycles of the second light emission control signals E1_B and E1_C are different, and different time compression strategies are employed.

[0293] In some embodiments, the first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 may share the same initialization circuit. Figure 7 for Figure 4 A circuit diagram of the pixel circuit 810 in the display device provided in the illustrated embodiment.

[0294] like Figure 7 As shown, the first pixel driving circuit 811 includes a first initialization circuit 821 and a first driving circuit 822, and the second pixel driving circuit 812 includes a second driving circuit 824 and a second light emission adjustment unit 80142.

[0295] The first initialization circuit 821, the first driving circuit 822, and the pixel 802 are electrically connected, and the first initialization circuit 821 and the second driving circuit 824 are electrically connected.

[0296] The first initialization circuit 821 is configured to set the voltages of the data storage terminal G_A and the output terminal Ano_A of the first driving circuit 822 to the reference voltage Vref, and the voltages of the data storage terminal G_B and the driving terminal of the pixel 802 of the second driving circuit 824 to the reference voltage Vref. This configuration simplifies the pixel circuit structure, reduces the number of gate lines, and decreases the chip area.

[0297] The initialization process of the initialization circuit has been explained in the previous embodiments and will not be repeated here.

[0298] In other embodiments, the first sub-pixel driving circuit 811 and the second sub-pixel driving circuit 812 are located in the same column. Figure 9 As shown. Figure 9 The display device shown is Figure 4 The difference in the display device shown is that, Figure 9In the display device shown, the data lines electrically connected to the first sub-pixel driving circuit 811 are the same as those electrically connected to the second sub-pixel driving circuit 812, but the gate lines electrically connected to transmit the same type of gate signal are different.

[0299] Among them, Figure 4 In the pixel circuit 810 shown, the first sub-pixel driving circuit 8011, the second sub-pixel driving circuit 8012 and the second gate line that transmits the first scan signal S1 are electrically connected, and initialization is performed based on the first scan signal S1.

[0300] The first sub-pixel driving circuit 8011, the second sub-pixel driving circuit 8012 and the second gate line that transmits the second scan signal S2 are electrically connected, and data is written based on the second scan signal S2.

[0301] The first sub-pixel driving circuit 8011, the second sub-pixel driving circuit 8012, and the third gate line that transmits the first light emission control signal E1_A are electrically connected, and a driving signal is generated based on the first light emission control signal E1_A.

[0302] If both the first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 include a light emission adjustment unit, the two light emission adjustment units obtain the second light emission control signal at the same time.

[0303] exist Figure 9 In the pixel circuit 810 shown, since the first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 share the data line 50, the analog data voltage of the first sub-pixel driving circuit 8011 and the analog data voltage of the second sub-pixel driving circuit 8012 need to be transmitted in a time-division manner.

[0304] Furthermore, in each frame display cycle, only one sub-pixel driving circuit obtains the display data analog voltage, while the other voltages are the shutdown data analog voltages.

[0305] Accordingly, the phase of the initialization scan signal applied by the first sub-pixel driving circuit 8011 is different from the phase of the initialization scan signal applied by the second sub-pixel driving circuit 8012, the phase of the data writing scan signal applied by the first sub-pixel driving circuit 8011 is different from the phase of the data writing scan signal applied by the second sub-pixel driving circuit 8012, the phase of the light emission control signal applied by the first sub-pixel driving circuit 8011 is different from the phase of the light emission control signal applied by the second sub-pixel driving circuit 8012, and the corresponding gate lines are also different.

[0306] The circuit connection relationship of multiple pixel driving circuits located in a column will be explained below with reference to a specific circuit structure.

[0307] Figure 11 This application provides a schematic diagram of the circuit connection relationship between two sub-pixel driving circuits located in a column, as shown below. Figure 11 As shown, it includes a first sub-pixel driving circuit 8011 and a second sub-pixel driving circuit 8012, wherein the components included in the two sub-pixel driving circuits and their interconnections are as follows: Figure 5 The two sub-pixel driving circuits shown have the same components and interconnections, but differ in their connections to the gate lines and data lines, and their driving processes.

[0308] In the first sub-pixel driving circuit 8011, the first initialization circuit 821 is electrically connected to the gate line that transmits the first scan signal S1, and the first driving circuit 822 is electrically connected to the gate line that transmits the second scan signal S2 and the gate line that transmits the first light emission control signal E1_A. The first scan signal S1 and the second scan signal S2 are signals output by the same scan signal generation circuit, and the phase of the second scan signal S2 lags behind the first scan signal S1.

[0309] The phase relationship between the first scan signal S1 and the second scan signal S2 can be referenced. Figure 14A The waveform diagram shown is shown below.

[0310] The first initialization circuit 821 is configured to initialize the first driving circuit 822 and the pixel 802 based on the first scan signal S1.

[0311] The first driving circuit 822 is configured to obtain a data analog voltage and store the data analog voltage based on the second scan signal S2.

[0312] The first driving circuit 822 determines whether to output a driving signal based on the analog voltage data. When it outputs a driving signal, the first light-emitting control signal E1_A controls it to output the driving signal.

[0313] In the second sub-pixel driving circuit 8012, the second initialization circuit 823 is electrically connected to the gate line that transmits the first scan signal S3, and the second driving circuit 824 is electrically connected to the gate line that transmits the second scan signal S4 and the gate line that transmits the first light emission control signal E2_A. The first scan signal S3 and the second scan signal S4 are signals output by the same scan signal generation circuit, and the phase of the second scan signal S4 lags behind the first scan signal S3.

[0314] In some embodiments, the first scan signal S1, the second scan signal S2, the first scan signal S3, and the second scan signal S4 are all signals output by the same scan signal generation circuit.

[0315] Since the second sub-pixel driving circuit 8012 is located below the first sub-pixel driving circuit 8011, when the display device scans line by line from top to bottom, the phase of the first scanning signal S3 lags behind the phase of the second scanning signal S2.

[0316] The phase relationship of the four scanning signals mentioned above can be referenced. Figure 14A The waveform diagram shown is shown below.

[0317] The second initialization circuit 823 is configured to initialize the second driving circuit 824 and the pixel 802 based on the first scan signal S3.

[0318] The second drive circuit 824 is configured to obtain a data analog voltage and store the data analog voltage based on the second scan signal S4.

[0319] The second driving circuit 824 determines whether to output a driving signal based on the analog voltage of the data. When it outputs a driving signal, the first light-emitting control signal E2_A controls it to output the driving signal.

[0320] In some embodiments, the first light emission control signals E1_A and E2_A are signals output by the same first signal generation circuit 3021, and the phase of signal E2_A lags behind the phase of signal E1_A.

[0321] The second sub-pixel driving circuit 8012 also includes a second light emission adjustment unit 80142, which is electrically connected to the first gate line and is configured to obtain a second light emission control signal E1_B, which controls the driving duration of the compression driving signal of the second sub-pixel driving circuit 8012.

[0322] It is worth noting that the second light emission control signal E1_B adjusts its duty cycle within each frame pixel period, wherein the phase start position of the adjustment waveform is the same as the phase start position of the first light emission control signal E2_A.

[0323] In some embodiments, the first sub-pixel driving circuit 8011 includes a first light-emitting adjustment unit 80141, the circuit structure of which is as follows: Figure 13 As shown, the first light-emitting adjustment unit 80141 is electrically connected to another first gate line and is configured to obtain a second light-emitting control signal E1_C, which controls the driving duration of the first sub-pixel driving circuit 8011 to compress the driving signal.

[0324] The starting position of the phase of the duty cycle adjustment of the second light emission control signal E1_C is the same as the starting position of the phase of the first light emission control signal E1_A.

[0325] The following is combined Figure 14A and Figure 14B ,right Figure 13The operation of the circuit structure shown will be explained.

[0326] The driving cycle T of the pixel driving circuit includes six stages: stage t1, stage t2, stage t3, stage t4, stage t5, and stage t6. Stage t2 is the first data writing stage; stages t3, t4, t5, and t6 constitute the display stage of the first sub-pixel driving circuit; stage t5 is the second data writing stage; and stage t6 of the current cycle, along with stages t1, t2, and t3 of the next cycle, constitute the first light-emitting stage of the second sub-pixel driving circuit.

[0327] During the time period corresponding to the first stage t1, the first scan signal S1 and the first light emission control signal E1_A are at low level, while the second scan signal S2, the first scan signal S3, the second scan signal S4, and the first light emission control signal E2_A are at high level. Each second light emission control signal is a pulse signal with an arbitrary duty cycle.

[0328] Since the first scan signal S1 is low, the first transistor M11 and the fourth transistor M14 are turned on, and the reference voltage Vref obtained at their first terminals is output to initialize the driving terminals of pixel 802 and the first driving transistor M17.

[0329] Since the reference voltage Vref is low, the first driving transistor M17 is turned on.

[0330] Since the first light-emitting control signal E1_A is at a high level, the fifth transistor M15 and the sixth transistor M16 are both turned off. Therefore, the conduction of the first light-emitting regulating transistor M18 based on the second light-emitting control signal will not affect the initial potential change, nor will it affect the potential change of the first driving transistor M17.

[0331] Since the first transistor M11 resets pixel 802, pixel 802 does not emit light.

[0332] During the time period corresponding to the second stage t2, the second scanning signal S2 and the first light emission control signal E2_A are at low level, while the first scanning signal S1, the first scanning signal S3, the second scanning signal S4, and the first light emission control signal E1_A are at high level. Each second light emission control signal is a pulse signal with an arbitrary duty cycle.

[0333] Since the second scan signal S2 is low, the second transistor M12 is turned on, writing a data analog voltage to the first terminal of the first driving transistor M17. When the grayscale value corresponding to the data analog voltage is within the first grayscale range corresponding to the first sub-pixel driving circuit 8011, the first driving transistor M17 obtains the display data analog voltage, such as... Figure 14AAs shown, otherwise, the analog voltage is turned off, such as... Figure 14B As shown.

[0334] Since the second scan signal S2 is low, the third transistor M13 is turned on, which turns on the driving terminal and the second terminal of the first driving transistor M17, thus constructing a threshold compensation structure.

[0335] When the first driving transistor M17 obtains the display data analog voltage, the threshold compensation structure and the turned-on second transistor discharge the voltage value stored in the first storage capacitor C11 until the display data analog voltage compensated by the threshold voltage of the first driving transistor M17 is obtained.

[0336] When the first driving transistor M17 obtains the shutdown data analog voltage, the threshold compensation structure and the turned-on second transistor discharge the voltage value stored in the first storage capacitor C11 until the threshold voltage compensation shutdown data analog voltage of the first driving transistor M17 is obtained.

[0337] When the second sub-pixel driving circuit 8012 drives pixel 802 to emit light in the previous display cycle, it will continue to drive pixel 802 to emit light in this stage.

[0338] During the time period corresponding to the third stage t3, the first light emission control signal E1_A and the first light emission control signal E2_A are at low level, while the first scan signal S1, the second scan signal S2, the first scan signal S3, and the second scan signal S4 are at high level, and each second light emission control signal is a pulse signal with an arbitrary duty cycle.

[0339] Since the first light-emitting control signal E1_A is at a low level, the fifth transistor M15 is turned on, and the power supply voltage VDD is written to the first terminal of the first driving transistor M17.

[0340] When the first driving transistor M17 receives the display data analog voltage in the second stage t2, the first driving transistor M17 determines the current value of the driving signal based on the power supply voltage VDD and the voltage value stored at the second terminal of the first storage capacitor C11.

[0341] When the first driving transistor M17 receives the shutdown data analog voltage in the second stage t2, the first driving transistor M17 is turned off and no driving signal is output.

[0342] Since the first light-emitting control signal E1_A is low, the sixth transistor M16 is turned on. Figure 14A In the waveform diagram shown, the sixth transistor M16 outputs the driving signal obtained at its first terminal, driving pixel 802 to emit light; in Figure 14B In the waveform diagram shown, the sixth transistor M16 does not output a drive signal, and therefore does not drive pixel 802 to emit light.

[0343] When the second sub-pixel driving circuit 8012 drives pixel 802 to emit light in the previous display cycle, it will continue to drive pixel 802 to emit light in this stage.

[0344] The first light-emitting regulating transistor M18 receives the second light-emitting control signal E1_C, and the second light-emitting control signal E1_C controls the conduction state of the first light-emitting regulating transistor M18.

[0345] When the first light-emitting regulating transistor M18 receives a driving signal, the second light-emitting control signal E1_C compresses the driving duration of the driving signal by regulating the on / off state of the first light-emitting regulating transistor M18, so as to ensure that the grayscale of the analog voltage of the display data can be expanded.

[0346] During the time period corresponding to the fourth stage t4, the first scan signal S1 and the first light emission control signal E1_A are at low level, the first scan signal S1, the second scan signal S2, the second scan signal S4 and the first light emission control signal E2_A are at high level, and each second light emission control signal is a pulse signal with an arbitrary duty cycle.

[0347] Since the first scan signal S3 is low, the seventh transistor M21 and the tenth transistor M24 are turned on, outputting the reference voltage Vref obtained at their first terminals to initialize the driving terminals of pixel 802 and the second driving transistor M27.

[0348] Since the reference voltage Vref is low, the second driving transistor M27 is turned on, and pixel 802 stops emitting light.

[0349] Even if the first driving tube M17 drives pixel 802 to start emitting light in the third stage t3, the emitting state will be interrupted in the fourth stage t4 until the current stage ends.

[0350] During the time period corresponding to the fifth stage t5, the second scanning signal S4 and the first light emission control signal E1_A are at low level, while the first scanning signal S1, the second scanning signal S2, the third scanning signal S3, and the first light emission control signal E2_A are at high level. Each second light emission control signal is a pulse signal with an arbitrary duty cycle.

[0351] Since the second scan signal S4 is low, the eighth transistor M22 is turned on, writing a data analog voltage to the first terminal of the second driving transistor M27. When the grayscale value corresponding to the data analog voltage is within the second grayscale range corresponding to the second sub-pixel driving circuit 8011, the second driving transistor M27 obtains the display data analog voltage, such as... Figure 14B As shown, otherwise, the analog voltage is turned off, such as... Figure 14A As shown.

[0352] Since the second scan signal S4 is low, the ninth transistor M23 is turned on, which turns on the driving terminal and the second terminal of the second driving transistor M27, thus constructing a threshold compensation structure.

[0353] When the second driving transistor M27 obtains the display data analog voltage, the threshold compensation structure and the turned-on eighth transistor M22 discharge the voltage value stored in the second storage capacitor C21 until the display data analog voltage compensated by the threshold voltage of the second driving transistor M27 is obtained.

[0354] When the first driving transistor M17 outputs a driving signal, pixel 802 emits light during this stage.

[0355] During the time period corresponding to the sixth stage t6, the first light emission control signal E1_A and the first light emission control signal E2_A are at low level, while the first scan signal S1, the second scan signal S2, the first scan signal S3, and the second scan signal S4 are at high level, and each second light emission control signal is a pulse signal with an arbitrary duty cycle.

[0356] Since the first light-emitting control signal E2_A is low, the eleventh transistor M25 is turned on, writing the power supply voltage VDD to the first terminal of the second driving transistor M27.

[0357] When the second driving transistor M27 receives the display data analog voltage in the fifth stage t5, the second driving transistor M27 determines the current value of the driving signal based on the power supply voltage VDD and the voltage value stored at the second terminal of the second storage capacitor C21.

[0358] When the second driving transistor M27 receives the shutdown data analog voltage in the fifth stage t5, the second driving transistor M27 is turned off and no driving signal is output.

[0359] Since the first light-emitting control signal E2_A is low, the twelfth transistor M26 is turned on. Figure 14A In the waveform diagram shown, the twelfth transistor M26 outputs the driving signal obtained at its first terminal, driving pixel 802 to emit light; in Figure 14B In the waveform diagram shown, the twelfth transistor M26 does not output a drive signal, and therefore does not drive pixel 802 to emit light.

[0360] The second light-emitting regulating transistor M28 receives the second light-emitting control signal E1_B, and the second light-emitting control signal E1_B controls the conduction state of the second light-emitting regulating transistor M28.

[0361] When the second light-emitting regulating transistor M28 receives a driving signal, the second light-emitting control signal E1_B compresses the driving duration of the driving signal by regulating the on / off state of the second light-emitting regulating transistor M28, so as to ensure that the grayscale of the analog voltage of the display data can be expanded.

[0362] When the second light-emitting regulating transistor M28 does not receive a driving signal, the first light-emitting regulating transistor M18 outputs a driving signal to drive pixel 802 to emit light.

[0363] In some embodiments, the first sub-pixel driving circuit 8011 and the second sub-pixel driving circuit 8012 may share the same initialization circuit. Figure 15 for Figure 11 A circuit diagram of the pixel circuit 810 in the display device provided in the illustrated embodiment.

[0364] like Figure 15 As shown, the first sub-pixel driving circuit 8011 includes a first initialization circuit 821 and a first driving circuit 822, and the second sub-pixel driving circuit 8012 includes a second driving circuit 824 and a second light-emitting adjustment unit 80142.

[0365] The first initialization circuit 821, the first driving circuit 822, and the pixel 802 are electrically connected, and the first initialization circuit 821 and the second driving circuit 824 are electrically connected.

[0366] The first initialization circuit 821 is configured to set the voltages of the data storage terminal G_A and the output terminal Ano_A of the first driving circuit 822 to the reference voltage Vref, and the voltages of the data storage terminal G_B and the driving terminal of the pixel 802 of the second driving circuit 824 to the reference voltage Vref. This configuration simplifies the pixel circuit structure, reduces the number of gate lines, and decreases the chip area.

[0367] The initialization process of the initialization circuit has been explained in the previous embodiments and will not be repeated here.

[0368] When the pixel driving circuit includes only one initialization circuit 821, the display stage of the sub-pixel driving circuit containing the initialization circuit will not be affected by the initialization operation of the other sub-pixel driving circuit, and it will still emit light in the initialization stage adjacent to the display stage; the process of the other sub-pixel driving circuit driving the pixel 802 to emit light will still be affected by the initialization operation of the initialization circuit 821.

[0369] For example, if the first sub-pixel driving circuit 8011 includes a first initialization circuit 821, then after the first sub-pixel driving circuit 8011 drives the pixel 802 to emit light in the third stage t3, the initialization operation will not be performed in the fourth stage t4, and the first sub-pixel driving circuit 8011 will still drive the pixel 802 to emit light in the fourth stage t4.

[0370] After the second sub-pixel driving circuit 8012 drives pixel 802 to emit light in the sixth stage t6, the initialization operation of the first stage t1 of the next display cycle will cause pixel 802 to stop emitting light until the second stage t2 of the next cycle is entered.

[0371] It is worth noting that the above-described driving circuit structure is only an example. Pixel driving circuits with other circuit structures are within the scope of protection of this application, and will not be explained in detail here.

[0372] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0373] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A display device, comprising: A gate driving circuit, a data driving circuit, multiple pixels, and pixel driving circuits connected to each of the pixels, wherein the pixel driving circuits are arrayed. The gate driving circuit is characterized in that it includes at least one first signal generation circuit and at least one second signal generation circuit; The first signal generation circuit is configured to output a first light emission control signal, and the second signal generation circuit is configured to output a second light emission control signal. The light emission control signal is a signal that limits the driving duration of the driving signal. The pixel driving circuit includes a first sub-pixel driving circuit and a second sub-pixel driving circuit; the size of the first driving transistor in the first sub-pixel driving circuit is larger than that of the second driving transistor in the second sub-pixel driving circuit; each sub-pixel driving circuit corresponds to a different grayscale range. Both the first sub-pixel driving circuit and the second sub-pixel driving circuit are electrically connected to the same first signal generating circuit; different second sub-pixel driving circuits are electrically connected to different second signal generating circuits respectively. The sub-pixel driving circuit is also electrically connected to the data driving circuit and is configured to obtain a data analog voltage and the light emission control signal, wherein the data analog voltage includes a display data analog voltage. The first target sub-pixel driving circuit is a sub-pixel driving circuit whose grayscale value range includes the grayscale value corresponding to the display data analog voltage. The first target sub-pixel driving circuit is configured to receive the display data analog voltage and output the driving signal; the driving signal is a signal that drives the pixel to emit light.

2. The display device according to claim 1, characterized in that, The data simulation voltage also includes the data shutdown simulation voltage; The second target sub-pixel driving circuit is a sub-pixel driving circuit whose grayscale value range does not include the grayscale value corresponding to the display data analog voltage. The second target sub-pixel driving circuit is configured to receive the shutdown data analog voltage and not output the driving signal.

3. The display device according to claim 2, characterized in that, The first sub-pixel driving circuit includes a first reference driving unit, and the first reference driving unit includes the first driving transistor; The first reference driving unit, the data driving circuit, the first signal generation circuit, and the pixel are electrically connected and configured to obtain the first light emission control signal, and to obtain the display data analog voltage or the shutdown data analog voltage, and to output the first driving signal when the display data analog voltage is obtained, and not to output the first driving signal when the shutdown data analog voltage is obtained.

4. The display device according to claim 2, characterized in that, The second sub-pixel driving circuit includes a second reference driving unit and an emissivity adjustment unit, wherein the second reference driving unit includes the second driving transistor; The second reference driving unit is electrically connected to the data driving circuit and the first signal generation circuit, and is configured to obtain the first light emission control signal, and to obtain the display data analog voltage or the turn-off data analog voltage, and to output the second driving signal when the display data analog voltage is obtained, and not to output the second driving signal when the turn-off data analog voltage is obtained; The light emission adjustment unit, the second reference driving unit, the second signal generation circuit, and the pixel are electrically connected and configured to obtain the second light emission control signal and output a third driving signal when the second driving signal is obtained.

5. The display device according to claim 4, characterized in that, The reference driving unit also includes a light-emitting control transistor; The first terminal of the light-emitting control transistor is electrically connected to the second terminal of the driving transistor, its control terminal is electrically connected to the first signal generation circuit, and its second terminal is electrically connected to the light-emitting adjustment unit or the pixel. It is configured to obtain the first light-emitting control signal from its control terminal, obtain the electrical signal output by the driving transistor from its first terminal, and output the driving signal from its second terminal. The light-emitting adjustment unit includes a light-emitting adjustment transistor, whose first terminal is electrically connected to the output terminal of the light-emitting control transistor, whose control terminal is electrically connected to the second signal generation circuit, and whose output terminal is electrically connected to the pixel. It is configured to obtain the second driving signal from its first terminal, obtain the second light-emitting control signal from its control terminal, and output a third driving signal from its second terminal.

6. The display device according to claim 3, characterized in that, The data driving circuit is electrically connected to multiple data lines and multiple sub-pixel driving circuits. The first sub-pixel driving circuit and the second sub-pixel driving circuit are located in the same row; The data lines electrically connected to the first reference driving unit are different from the data lines electrically connected to the second reference driving unit. The analog voltages obtained by the first sub-pixel driving circuit and the second sub-pixel driving circuit are in phase. The gate driving circuit includes at least one scan signal generation circuit, which is electrically connected to multiple sub-pixel driving circuits via multiple gate lines. The scan signal generation circuit is configured to output a scan signal; The first reference driving unit and the second reference driving unit are electrically connected to the same gate line that transmits the same type of scan signal; The first light emission control signal obtained by the first sub-pixel driving circuit is the same as the first light emission control signal obtained by the second sub-pixel driving circuit.

7. The display device according to any one of claims 1-3, characterized in that, The pixel driving circuit includes at least two second sub-pixel driving circuits, and the second light emission control signals obtained by the at least two second sub-pixel driving circuits are in phase.

8. The display device according to claim 4, characterized in that, The data driving circuit is electrically connected to multiple data lines and multiple sub-pixel driving circuits. The gate driving circuit includes at least one scan signal generation circuit, which is electrically connected to multiple sub-pixel driving circuits via multiple gate lines. The scan signal generation circuit is configured to output a scan signal; The first sub-pixel driving circuit and the second sub-pixel driving circuit are located in the same column; The data lines electrically connected to the first reference drive unit are the same as those electrically connected to the second reference drive unit. The phases of the analog voltages obtained by the first sub-pixel driving circuit and the second sub-pixel driving circuit are different; The first reference driving unit and the second reference driving unit have different gate lines for transmitting the same type of scan signal, but the scan signal generation circuits for generating the same type of scan signal are the same. The first reference driving unit and the second reference driving unit have different gate lines for transmitting the first light emission control signal, but the first signal generation circuits they are electrically connected to are the same.

9. A display device, comprising: The array includes a gate driving circuit, a data driving circuit, multiple pixels and corresponding pixel driving circuits, wherein the pixel driving circuits are distributed in an array. The gate driving circuit is characterized in that it includes at least one first signal generation circuit and at least one second signal generation circuit; The first signal generation circuit is configured to output a first light emission control signal, and the second signal generation circuit is configured to output a second light emission control signal. The light emission control signal is a signal that limits the driving duration of the driving signal. The pixel driving circuit includes at least two sub-pixel driving circuits, and the at least two sub-pixel driving circuits are electrically connected to the same pixel; each sub-pixel driving circuit corresponds to a different grayscale range. Each of the sub-pixel driving circuits is electrically connected to the same first signal generation circuit and electrically connected to different second signal generation circuits respectively; The sub-pixel driving circuit and the data driving circuit are electrically connected and configured to obtain a data analog voltage and the light emission control signal, wherein the data analog voltage includes a display data analog voltage. The first target sub-pixel driving circuit is a sub-pixel driving circuit whose grayscale value range includes the grayscale value corresponding to the display data analog voltage. The first target sub-pixel driving circuit is configured to receive the display data analog voltage and output the driving signal. The driving signal is the signal that drives the pixel to emit light.

10. The display device according to claim 9, characterized in that, The data simulation voltage also includes the data shutdown simulation voltage; The sub-pixel driving circuit includes a reference driving unit and an emissivity adjustment unit, wherein the reference driving unit includes a driving transistor; The reference driving unit is electrically connected to the data driving circuit and the first signal generation circuit, and is configured to obtain the first light emission control signal, and to obtain the display data analog voltage or the turn-off data analog voltage, and to output a second driving signal when the display data analog voltage is obtained, and not to output the second driving signal when the turn-off data analog voltage is obtained; The light emission adjustment unit, the reference driving unit, the second signal generation circuit, and the pixel are electrically connected and configured to obtain the second light emission control signal and output a third driving signal when the second driving signal is obtained. The sub-pixel driving circuit will not continuously receive the display data analog voltage in two adjacent display cycles.

11. A driving method for a display device, characterized in that, The method is applied to the display device according to any one of claims 1 to 8, the method comprising: The data driving circuit is controlled to output a data analog voltage, the data analog voltage including a display data analog voltage; When the grayscale value corresponding to the display data analog voltage is within the grayscale range corresponding to the first sub-pixel driving circuit, the first sub-pixel driving circuit obtains the first light emission control signal from the first signal generation circuit, and outputs the driving signal based on the first light emission control signal and the display data analog voltage. When the grayscale value corresponding to the display data analog voltage is within the grayscale range corresponding to the second sub-pixel driving circuit, the second sub-pixel driving circuit obtains a first light emission control signal from the first signal generation circuit, obtains a second light emission control signal from the second signal generation circuit, and outputs the driving signal based on the first light emission control signal, the second light emission control signal and the display data analog voltage. The pixel is controlled to emit light based on the driving signal.

12. The driving method according to claim 11, characterized in that, The data simulation voltage includes the displayed data simulation voltage or the data shutdown simulation voltage; The first sub-pixel driving circuit and the second sub-pixel driving circuit are located in the same row; The display cycle of the pixel includes a data writing phase and a display phase; When the grayscale value corresponding to the display data analog voltage is within the grayscale range corresponding to the first sub-pixel driving circuit, during the data writing stage, the first sub-pixel driving circuit is controlled to obtain the display data analog voltage, and the second sub-pixel driving circuit is controlled to obtain the shutdown data analog voltage. During the display phase, the first sub-pixel driving circuit is controlled to obtain the first light emission control signal, and the current value of the driving signal is determined based on the simulated voltage of the display data. Based on the first light emission control signal, the duration of its output driving signal is adjusted to drive the pixel to emit light; The second sub-pixel driving circuit is controlled to obtain the first light emission control signal and the second light emission control signal, and the driving signal is not output based on the analog voltage of the shutdown data; When the grayscale value corresponding to the display data analog voltage is within the grayscale range corresponding to the second sub-pixel driving circuit, during the data writing stage, the first sub-pixel driving circuit is controlled to obtain the shutdown data analog voltage, and the second sub-pixel driving circuit is controlled to obtain the display data analog voltage. During the display phase, the first sub-pixel driving circuit is controlled to obtain the first light emission control signal, and based on the shutdown data, the analog voltage is simulated, and no driving signal is output; The second sub-pixel driving circuit is controlled to obtain the first light emission control signal and the second light emission control signal, and the current value of the driving signal is determined based on the shutdown data analog voltage. Based on the first light emission control signal and the second light emission control signal, the duration of the output driving signal is adjusted to drive the pixel to emit light.

13. The driving method according to claim 11, characterized in that, The data simulation voltage includes the displayed data simulation voltage or the data shutdown simulation voltage; The first sub-pixel driving circuit and the second sub-pixel driving circuit are located in the same column, and the display delay time corresponding to the first sub-pixel driving circuit is less than the display delay time of the second sub-pixel driving circuit. The display cycle of the pixel includes a first data writing stage and a display stage, wherein the display stage includes a second data writing stage and a first light emission stage; When the grayscale value corresponding to the display data analog voltage is within the grayscale range corresponding to the first sub-pixel driving circuit, during the first data writing stage, the first sub-pixel driving circuit is controlled to obtain the display data analog voltage. During the display phase, the first sub-pixel driving circuit is controlled to obtain the first light emission control signal, and the current value of the driving signal is determined based on the simulated voltage of the display data. Based on the first light emission control signal, the duration of its output driving signal is adjusted to drive the pixel to emit light; During the second data writing phase, the second sub-pixel driving circuit is controlled to obtain the shutdown data analog voltage; During the first light emission stage, the second sub-pixel driving circuit is controlled to obtain the first light emission control signal and the second light emission control signal, and the driving signal is not output based on the shutdown data analog voltage. When the grayscale value corresponding to the display data analog voltage is within the grayscale range corresponding to the second sub-pixel driving circuit, during the first data writing stage, the first sub-pixel driving circuit is controlled to obtain the shutdown data analog voltage. During the display phase, the first sub-pixel driving circuit is controlled to obtain the first light emission control signal, and based on the shutdown data, the analog voltage is simulated, and no driving signal is output; During the second data writing phase, the second sub-pixel driving circuit is controlled to obtain the display data analog voltage; During the first light emission stage, the second sub-pixel driving circuit is controlled to obtain the first light emission control signal and the second light emission control signal, and the current value of the driving signal is determined based on the shutdown data analog voltage. Based on the first light emission control signal and the second light emission control signal, the duration of the output driving signal is adjusted to drive the pixel to emit light.

14. A driving method for a display device, characterized in that, The method is applied to the display device according to claim 9 or 10, and the method includes: The data driving circuit is controlled to output a data analog voltage, the data analog voltage including a display data analog voltage; Control the first signal generation circuit to output the first light-emitting control signal; Control the second signal generation circuit to output a second light-emitting control signal; The target sub-pixel driving circuit outputs the driving signal based on the first light emission control signal, the second light emission control signal, and the analog voltage of the display data. The pixel is controlled to emit light based on the driving signal.

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