VCSEL wafer heterogeneous integrated system chip and manufacturing method thereof
By heterogeneously integrating VCSEL wafers with ASICs and sensors, a VCSEL wafer heterogeneous integrated system chip is formed, which solves the problems of high price and high power consumption of VCSEL light sources, realizes system miniaturization and high performance, and reduces power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-29
- Publication Date
- 2026-03-13
AI Technical Summary
While VCSEL light sources outperform LDs in terms of performance, they are expensive and consume a lot of power, making it difficult to meet the demands of high bandwidth and low power consumption for the growth of internet traffic and large-scale language models in artificial intelligence.
By heterogeneously integrating VCSEL wafers with ASICs and sensors, VCSEL wafer heterogeneous integrated system chips are formed, shortening the signal transmission path, increasing integration, and reducing power consumption.
This system achieves miniaturization, lightweight design, and high performance, while reducing power consumption and meeting the requirements for high data transmission efficiency.
Smart Images
Figure CN121663323A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor optoelectronic device technology, specifically to a VCSEL wafer heterogeneous integrated system chip and its manufacturing method. Background Technology
[0002] VCSEL, short for Vertical Cavity Surface Emitting Laser, is a surface-emitting laser used in fiber optic communication. Unlike LEDs (Light Emitting Diodes) and LDs (Laser Diodes), VCSELs can be tuned to frequencies of several giga Hz, resulting in transmission rates of giga bps. While traditional LDs also offer similar performance, they are significantly more expensive and have much lower luminous efficiency than VCSELs. Furthermore, VCSELs require very low driving voltage and current, resulting in a lifespan exceeding tens of millions of hours, more than 100 times that of other light sources.
[0003] The continued growth of internet traffic and the rapid expansion of large-scale language models in artificial intelligence have increased the demand for interconnect bandwidth. However, increased bandwidth usually means increased power consumption, thus the industry is seeking higher energy efficiency for data transmission. Summary of the Invention
[0004] To address the aforementioned technical challenges, this invention provides a VCSEL wafer heterogeneous integrated system-on-a-chip (SoC). By heterogeneously integrating VCSEL wafers, ASICs, and sensors, it reduces system size, increases integration density, shortens signal transmission paths, improves performance, and lowers power consumption. This further meets the requirements for lightweight, miniaturized, and high-performance devices.
[0005] The VCSEL wafer heterogeneous integrated system chip of the present invention includes: Compared with the prior art, the present invention has the following advantages: This invention heterogeneously integrates a VCSEL wafer and a core wafer with a reflective structure and an optical waveguide. ASICs or other devices can be formed in the core wafer, or other devices, such as sensors, can be integrated on the core wafer. Through heterogeneous integration of bare cores, the signal transmission path is greatly shortened and power consumption is reduced. Attached Figure Description
[0006] Figure 1 This is a schematic diagram of the structure of a VCSEL wafer heterogeneous integrated system chip according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a VCSEL wafer heterogeneous integrated system chip according to another embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a VCSEL wafer heterogeneous integrated system chip according to another embodiment of the present invention; Figure 4 This is a flowchart illustrating a method for manufacturing a VCSEL wafer heterogeneous integrated system chip according to an embodiment of the present invention. Figure 5 This is a schematic diagram of a method for manufacturing a VCSEL wafer heterogeneous integrated system chip according to an embodiment of the present invention; Figure 6 This is a schematic diagram illustrating a method for manufacturing a VCSEL wafer heterogeneous integrated system chip according to another embodiment of the present invention. Detailed Implementation
[0007] The invention will now be described more fully below with reference to the accompanying drawings, which illustrate some, but not all, embodiments of the invention. In fact, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to enable this disclosure to meet applicable legal requirements. Similar numerals refer to similar elements throughout the text.
[0008] In various embodiments, reference is made to the accompanying drawings. However, some embodiments may be implemented without one or more of these specific details, or in combination with other known methods and configurations. Numerous specific details, such as specific configurations, dimensions, and processes, are set forth in the following description to provide a thorough understanding of the embodiments. In other instances, well-known processes and manufacturing techniques have not been described in particular detail to avoid unnecessarily obscuring the embodiments. The reference to “one embodiment” throughout the specification means that a particular feature, structure, configuration, or characteristic described in connection with an embodiment is included in at least one embodiment. Therefore, the appearance of the phrase “in one embodiment” in various places throughout the specification does not necessarily refer to the same embodiment. Furthermore, features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments. Similarly, unless otherwise stated, the term “exemplary” is used to describe exemplary embodiments and does not imply that the described embodiments are superior to other embodiments.
[0009] As used herein, the terms “above,” “across,” “to,” “between,” and “above” can refer to the relative position of one layer with respect to other layers. A layer that is “above,” “across,” or “above,” or “bonded” or “in contact” with another layer can be in direct contact with that layer or can have one or more intermediate layers. A layer that is “between” layers can be in direct contact with those layers or can have one or more intermediate layers.
[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the scope of protection of the present invention. Obviously, the embodiments described in this invention are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0011] like Figure 1 As shown, in one embodiment, a VCSEL wafer heterogeneous integrated system chip includes: a mother wafer and VCSEL chips overlaid on the mother wafer. The top surface of the VCSEL chips is bonded to the upper surface of the mother wafer, and the top electrode and interconnect electrodes are vertically interconnected. The VCSEL chips are bare chips before packaging, containing an array of VCSEL pixels. A top electrode is provided on the top surface. The top electrode is annular, and each VCSEL pixel corresponds to a ring-shaped top electrode. The interior of the ring-shaped top electrode is a light-transmitting area. In this embodiment, a PNP excitation layer, specifically an indium phosphide (IP) chip, is provided between the top and bottom electrodes. A bottom electrode is disposed on the bottom surface, and its vertical projection covers the light-transmitting area of the top surface. An optical modulation structure is disposed within the mother core wafer, and an optical waveguide is disposed on the same layer as the optical modulation structure, so that the incident light from the VCSEL chip to the mother core wafer is modulated onto the optical waveguide. Several interconnect electrodes are provided on the upper surface of the mother core wafer. The interconnect electrodes corresponding to the top electrode are annular, with a light-transmitting area inside. The position of the light-transmitting area surrounded by the interconnect electrodes is perpendicular to the light-transmitting area surrounded by the top electrode of the VCSEL chip. The position of the interconnect electrodes corresponds to the top electrode of the VCSEL chip. The mother core wafer is specifically a silicon wafer. In a preferred embodiment, a bonding layer is provided between the mother core wafer and the VCSEL. The bonding layer may be located around the annular top electrode, and the light-transmitting area surrounded by the annular top electrode is located in a cavity. The location of the bonding layer is not limited. In other embodiments, a light-transmitting bonding layer, such as SiO2, can also be used, so that there is no cavity and the bonding layer material can be directly formed in the light-transmitting area of the mother core wafer and the light-transmitting area of the VCSEL.
[0012] In one embodiment, the VCSEL pixel array corresponds to an optical modulation structure and an optical waveguide, in Figure 1 The illustrated optical modulation structure is specifically a grating reflective array. The light-transmitting area surrounded by interconnecting electrodes and the light-transmitting area surrounded by top electrodes constitute an optical channel. Because this embodiment has multiple VCSEL pixels and multiple top electrodes, it has multiple optical channels. The optical channels are perpendicular to the interval positions of the grating reflective array, and the optical waveguides are SiO2 or SiN optical waveguides. Figure 2As shown, a microlens array is further provided between the VCSEL core and the reflected light modulation structure, with each microlens corresponding to a light-transmitting area surrounded by each interconnecting electrode. The microlenses can modulate the incident laser beam.
[0013] In one embodiment, the bottom electrode is interconnected with the interconnect electrode via a metal interconnect plug, specifically as follows: Figure 1 As shown, through an interconnect structure, the bottom electrode is interconnected to the interconnect structure via metal bumps, and then interconnected via metal interconnect plugs, metal bumps, and interconnect electrodes within the interconnect structure. Alternatively, it can be as follows: Figure 2 The bottom electrode shown is directly interconnected to the interconnect electrode via a metal interconnect plug.
[0014] In one embodiment, the VCSEL pixels are arranged in an array within the VCSEL core, and the optical modulation structure and optical waveguide are also arranged in an array. The optical modulation structure is a mirror, wherein the tilt angle of the reflective surface of the mirror is 45°~54°, and the light-transmitting area surrounded by the interconnecting electrode and the light-transmitting area surrounded by the top electrode constitute an optical channel, which is perpendicular to the reflective surface.
[0015] In one embodiment, the optical modulation structure is a mirror array, wherein the tilt angle of the reflective surface of the mirror array is 45°~54°, the light-transmitting area surrounded by the interconnecting electrode and the light-transmitting area surrounded by the top electrode constitute an optical channel, and each optical channel corresponds vertically to the reflective surface of a mirror.
[0016] In one embodiment, such as Figure 1 As shown, a master core is formed within the master core wafer. The master core includes one or more of the following: controller, processor, memory, filter, digital-to-analog / analog-to-digital converter, optical processing module, MEMS optical switch array, photoelectric / electro-optical conversion module, and photodetector array module. The master core can be formed directly in the silicon wafer of the master core wafer using semiconductor technology.
[0017] In one embodiment, such as Figure 3 As shown, one or more of the following components are bonded and interconnected on the mother core wafer: controller, processor, memory, filter, digital-to-analog / analog-to-digital converter, optical processing module, MEMS optical switch array, photoelectric / electro-optical conversion module, and photoelectric detection module, which are electrically interconnected with the mother core. Figure 3 Specifically, taking the photodetector chip as an example, it can be a bare chip before packaging. For instance, in the mother core wafer, another structure is used to redirect the light from the optical waveguide to the outside for emission. A lens can be placed on the surface of the mother core wafer to modulate the emitted light again before emission. The photodetector chip can receive the emitted light, thereby using the VCSEL wafer heterogeneous integrated system chip of the present invention to complete the operation of the entire laser display system.
[0018] In one embodiment, other functional chips may also be bonded to the mother core wafer, wherein one mother core chip may be interconnected with one or more other functional chips, or two mother core chips may be interconnected with one or more other functional chips in an alternating manner.
[0019] In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a method for manufacturing a vertical-cavity surface-emitting laser is provided, with reference to... Figure 1 As shown, Figure 4 This is a flowchart of the present invention. Figures 5-6 This is a schematic diagram of the manufacturing process according to an embodiment of this application.
[0020] refer to Figure 1 The manufacturing method of VCSEL wafer heterogeneous integrated system chip in this embodiment includes the following steps: S10: Provides VCSEL core, with a top electrode on the top surface of the VCSEL core. The top electrode is annular and has a light-transmitting area inside. A bottom electrode is provided on the bottom surface of the VCSEL core, and the bottom electrode's vertical projection covers the light-transmitting area of the top surface.
[0021] Specifically, the VCSEL core is a bare core diced from the InP wafer after fabrication. The bottom electrode is also the bottom reflective electrode, and its PNP excitation layer is, for example, a lower P layer, 50nm p-InP, with a doping concentration of 1×10⁻⁶. c ³; N active layer: 100nm; InGaAsP multiple quantum well; upper P layer: 50nm p-InP, doping concentration 1×10 c ³. A VCSEL core contains multiple pixels, each pixel including a ring-shaped top electrode with a light-transmitting area inside, so that the light-transmitting area inside the pixel emits a light beam.
[0022] S20: Provides a master core wafer, in which an optical modulation structure is set, and an optical waveguide is set on the same layer as the optical modulation structure. The optical modulation structure directs incident light perpendicular to the master core wafer into the optical waveguide.
[0023] Specifically, in this embodiment, the steps include: providing a master core carrier and multiple master core granules, and bonding the master core granules onto the master core carrier to form a master core wafer. Alternatively, the master core granules can also be bare granules directly manufactured from silicon wafers without being cut, meaning that no reconstruction of the master core wafer is performed.
[0024] The optical waveguide and optical modulation structure can be completed in a process compatible with the formation of the parent core, or they can be completed first and then reconstructed with the parent core. For example, a grating is fabricated with a 200nm thick SiN layer, and the grating pattern has the following characteristics: period: 240nm, duty cycle: 50%, depth: 80nm. In one embodiment, the optical waveguide structure is optimized using a SiO / SiN composite waveguide: lower layer: 100nm Si Top layer: 150nm SiN.
[0025] The fabrication of optical waveguide layers and gratings may include: PECVD deposition of 300nm SiON waveguide layer: Gas flow rate: Si 50 sccm, O 150sccm,N 10 sccm; RF power: 300W, temperature: 350℃; refractive index controlled within the range of 1.55-1.60; Electron beam lithography defines the grating as follows: Photoresist: ZEP520A, thickness 200nm; Accelerating voltage: 100kV, dose 180μC / cm²; Grating period: 210nm, duty cycle 45%; ICP etching is used to transfer the grating pattern: C / CH Mixed gas, pressure 10mTorr; RF power: 200W, bias power 50W; etching depth: 120nm.
[0026] S30: Interconnect electrodes are formed on the upper surface of the mother core wafer. The interconnect electrodes are ring-shaped and have a light-transmitting area inside. The position of the light-transmitting area allows the incident light of the VCSEL pixel to be incident on the light modulation structure.
[0027] In this embodiment, a dielectric layer is first formed on the upper surface of the mother core wafer, and a groove pattern is formed by etching the dielectric layer. The groove pattern may include linear grooves and annular grooves that are connected to the inside of the mother core. Then, metal, such as copper, is deposited in the groove pattern to form annular interconnect electrodes that are interconnected with the inside.
[0028] In another embodiment, a metal interconnect layer interconnecting with the interior is formed on the upper surface of the mother core wafer; the metal interconnect layer is etched to form a ring-shaped interconnect electrode. Specifically, a metal layer can be deposited on the mother core wafer, and the interconnect electrode is formed after etching. The position of the interconnect electrode needs to be determined based on the top electrode of the VCSEL chip to be bonded and the electrode positions of other chips to be bonded.
[0029] In one embodiment, the master die has metal interconnect plugs that interconnect with internal circuitry. In a preferred embodiment, this includes forming curved metal solder balls on the master die wafer as interconnect electrodes that interconnect with the metal interconnect plugs within the master die.
[0030] In one embodiment, the method further includes forming microlenses or lens arrays on the master core wafer.
[0031] S40: As Figure 5 As shown, the top surface of the VCSEL chip is bonded to the upper surface of the mother core wafer, wherein the top electrode position of the VCSEL chip corresponds perpendicularly to the interconnect electrode; the light-transmitting area of the VCSEL chip corresponds to the light-transmitting area of the mother core wafer.
[0032] Specifically, the VCSEL die is inverted onto the mother wafer with its top surface facing down. Because the top and bottom electrodes of the VCSEL die are at different distances from the interconnect electrodes of the mother wafer in this embodiment, the subsequent interconnect formation process cannot be completed in one step due to the steps involved. Therefore, the following solution can be adopted in this invention: The first method involves simultaneously bonding interconnect structures on the mother core wafer. Metal interconnect plugs can be pre-formed in the interconnect structure, and electrodes are formed on the surfaces of both ends of the metal interconnect plugs. Thus, during bonding in this step, the bottom electrode and the electrode at one end of the metal interconnect plug of the interconnect structure are perpendicularly aligned, and correspondingly, the interconnect electrode of the mother core wafer and the electrode at the other end of the metal interconnect plug of the interconnect structure are perpendicularly aligned.
[0033] Another method is to form vias in the bonding layer or to form a dielectric layer and form vias therein, and then form metal interconnect plugs in the vias.
[0034] Bonding methods include metal bonding, dielectric bonding, hybrid bonding, compound bonding, or glue bonding.
[0035] In one embodiment, one or more of the following components are bonded to the mother core wafer: a controller, a processor, a memory, a filter, a digital-to-analog / analog-to-digital converter, an optical processing module, a MEMS optical switch array, a photoelectric / electro-optical conversion module, and a photodetector array module, which are electrically interconnected with the mother core.
[0036] S50: such as Figure 6 As shown, the top electrode, bottom electrode, and interconnect electrode are electrically interconnected.
[0037] Interconnection methods include direct connection via metal bonding, microbonding, or hybrid bonding; interconnection via electroplating / chemical plating after bonding; or interconnection via through-hole plugs after bonding. For example, liquid materials containing metal ions can be introduced between electrodes, and metal bumps can be grown on the surfaces of the bottom electrode, top electrode, interconnection structure electrodes, and interconnection electrodes through chemical plating or electroplating, thereby forming an interconnect.
[0038] Specifically, the interconnection of the top electrode and the interconnect electrode, as well as the bottom electrode and the interconnect electrode, is achieved by simultaneously growing metal on the top electrode, the bottom electrode, and the interconnect electrode in the same step until the interconnection is completed.
[0039] Alternatively, when an interconnect structure is also bonded between the bottom electrode and the interconnect electrode, during the interconnection step between the top electrode and the interconnect electrode, the metal interconnect plug and the bottom electrode in the interconnect structure, as well as the metal interconnect plug and the interconnect electrode, simultaneously form an interconnect.
[0040] Alternatively, after bonding the VCSEL core, a dielectric layer, such as silicon dioxide or silicon nitride, is deposited on the mother core wafer in the region corresponding to the bottom electrode. Then, vias are etched to form vias, and metal is filled into the vias to form metal interconnect plugs. Then, in the interconnection step of the top electrode and the interconnect electrode, the metal interconnect plugs and the bottom electrode in the interconnect structure, as well as the metal interconnect plugs and the interconnect electrodes, are interconnected.
[0041] In this embodiment, a hemispherical electrode with a curved surface is formed on the metal interconnect plug of the interconnect electrode and the interconnect structure, thereby making it possible to form a gap between the electrodes, which facilitates the use of electroplating or chemical plating methods to make the liquid flow uniformly in the gap.
[0042] Benefiting from the teachings presented in the foregoing description and the accompanying drawings, those skilled in the art will conceive of many modifications and other embodiments of the invention set forth herein. Therefore, it should be understood that the invention is not limited to the specific embodiments disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terminology is used herein, it is used only in a general and descriptive sense and is not intended to be limiting.
Claims
1. A VCSEL wafer heterogeneous integrated system chip, characterized in that, include: The system consists of a mother wafer and VCSEL chips overlaid on the mother wafer. The top surface of the VCSEL chips is bonded to the upper surface of the mother wafer, and the top electrode and interconnect electrodes are vertically interconnected. The VCSEL core contains an array of VCSEL pixels. A top electrode is provided on the top surface of the VCSEL core. The top electrode is annular and has a light-transmitting area inside. A bottom electrode is provided on the bottom surface of the VCSEL core. The bottom electrode's vertical projection covers the light-transmitting area of the top surface. An optical modulation structure is set inside the mother core wafer, and an optical waveguide is set on the same layer as the optical modulation structure, so that the incident light from the VCSEL chip to the mother core wafer is injected into the optical waveguide. The upper surface of the mother core wafer has several interconnect electrodes. The interconnect electrodes connected to the top electrode are ring-shaped, with a light-transmitting area inside. The light-transmitting area surrounded by the interconnect electrodes is perpendicular to the light-transmitting area surrounded by the top electrode of the VCSEL chip.
2. The VCSEL wafer heterogeneous integrated system chip according to claim 1, characterized in that... The light modulation structure is a reflector, wherein the tilt angle of the reflective surface of the reflector is 45°~54°, and the light-transmitting area surrounded by the interconnecting electrodes and the light-transmitting area surrounded by the top electrode constitute a light channel, which is perpendicular to the reflective surface.
3. The VCSEL wafer heterogeneous integrated system chip according to claim 1, characterized in that, Corresponding to the VCSEL pixel, there is a microlens array between the VCSEL core and the optical modulation structure, with each light-transmitting area surrounded by the interconnecting electrode corresponding to a microlens.
4. The VCSEL wafer heterogeneous integrated system chip according to claim 1, characterized in that, The optical modulation structure is a grating reflection array. The light-transmitting area surrounded by interconnecting electrodes and the light-transmitting area surrounded by the top electrode constitute an optical channel. The optical channel is perpendicular to the interval position of the grating reflection array.
5. The VCSEL wafer heterogeneous integrated system chip according to claim 1, characterized in that, The optical modulation structure is a mirror array, wherein the tilt angle of the reflective surface of the mirror array is 45°~54°, and the light-transmitting area surrounded by the interconnecting electrode and the light-transmitting area surrounded by the top electrode constitute an optical channel, and each optical channel corresponds vertically to the reflective surface of a mirror.
6. A VCSEL wafer heterogeneous integrated system chip according to any one of claims 1 to 5 The method for manufacturing the sheet is characterized by, Including the following steps: S10: Provides VCSEL core, with a top electrode on the top surface of the VCSEL core. The top electrode is annular and has a light-transmitting area inside. A bottom electrode is provided on the bottom surface of the VCSEL core, and the bottom electrode's vertical projection covers the light-transmitting area of the top surface. S20: Provides a master core wafer, in which an optical modulation structure is set, and an optical waveguide is set on the same layer as the optical modulation structure. The optical modulation structure directs incident light perpendicular to the master core wafer into the optical waveguide. S30: Interconnect electrodes are formed on the upper surface of the mother core wafer. The interconnect electrodes are ring-shaped and have a light-transmitting area inside. The position of the light-transmitting area allows the incident light of the VCSEL pixel to be incident on the light modulation structure. S40: Bond the top surface of the VCSEL chip to the upper surface of the mother core wafer, wherein the top electrode position of the VCSEL chip corresponds perpendicularly to the interconnect electrode; the light-transmitting area of the VCSEL chip corresponds to the light-transmitting area of the mother core wafer; S50: Conductively interconnect the top electrode, bottom electrode, and interconnect electrode.
7. The manufacturing method according to claim 6, characterized in that, Step S20 includes: A master core carrier and multiple master core granules are provided. The master core granules are bonded to the master core carrier to form a master core wafer.
8. The manufacturing method according to claim 6, characterized in that, Step S30 includes: forming a dielectric layer on the upper surface of the mother core wafer, etching the dielectric layer to form a groove pattern, depositing metal in the groove pattern, and forming annular interconnect electrodes that are interconnected with the interior.
9. The manufacturing method according to claim 6, characterized in that, Step S30 includes: forming a metal interconnect layer on the upper surface of the mother core wafer to interconnect with the interior; etching the metal interconnect layer to form a ring-shaped interconnect electrode.
10. The manufacturing method according to claim 8 or 9, characterized in that, It also includes forming a lens at a location inside the ring interconnect electrode.