Operational amplifier input bias current compensation circuit, operational amplifier and method

Abstract

The invention discloses an operational amplifier input bias current compensation circuit, an operational amplifier and a method, and belongs to the field of high-precision operational amplifiers, a base electrode of a normal-phase input tube is connected with a normal-phase input end of the operational amplifier, and a base electrode of an inverted-phase input tube is connected with an inverted-phase input end of the operational amplifier; the high-impedance current source structure is connected with the input stage differential structure and is used for providing stable static working current for the normal-phase input tube and the inverted-phase input tube through an external current generation circuit; the input bias current sampling compensation structure comprises a normal-phase sampling tube, an inverted-phase sampling tube and a high-side current mirror structure and is used for respectively sampling base current of the normal-phase input tube and the inverted-phase input tube through the normal-phase sampling tube and the inverted-phase sampling tube; and the current is compensated to a normal-phase input end and an inverted-phase input end of the operational amplifier through the high-side current mirror structure. According to the invention, the problem that the input bias current is obviously increased after the total dose radiation in the prior art can be solved.

Description

Technical Field

[0001] This invention belongs to the field of high-precision operational amplifiers, specifically relating to an operational amplifier input bias current compensation circuit, operational amplifier, and method. Background Technology

[0002] In analog signal processing systems, high-precision operational amplifiers are gradually replacing general-purpose operational amplifiers due to their lower input offset voltage and input bias / offset current. To reduce input bias current, the mainstream techniques currently include two main categories: process optimization and circuit structure optimization. In terms of process technology, super-β transistors are commonly used as input stage devices, which can reduce the input bias current to approximately 10nA. At the circuit design level, Darlington input stage structures or self-compensating input bias current structures are widely adopted. The latter, by sampling the base current of the input transistor and performing mirror compensation, can further control the input bias current below 5nA and exhibits good stability under variations in temperature, power supply voltage, and common-mode input range, becoming an important technical path for achieving low input bias current.

[0003] However, existing input bias current compensation methods still have significant shortcomings in terms of resistance to total radiation dose. In the space radiation environment, as the cumulative radiation dose increases, the performance degradation of internal circuit components leads to a significant increase in input bias current. For example, after experiencing a total radiation dose of 100 klad (Si) to 300 klad (Si), the input bias current may increase by an order of magnitude or even more, severely affecting the accuracy and reliability of operational amplifiers under radiation conditions. Therefore, how to improve the stability of the input bias current compensation structure under radiation conditions has become a key technical problem that urgently needs to be solved in the design of high-precision operational amplifiers, especially in aerospace analog signal processing systems. Summary of the Invention

[0004] This invention provides an operational amplifier input bias current compensation circuit, an operational amplifier, and a method to solve the problem of a significant increase in input bias current after total dose radiation in the prior art.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, an operational amplifier input bias current compensation circuit includes: an input stage differential structure, a high-impedance current source structure, and an input bias current sampling compensation structure. The input-stage differential structure includes a non-inverting input transistor and an inverting input transistor. The base of the non-inverting input transistor is connected to the non-inverting input terminal of the operational amplifier, and the base of the inverting input transistor is connected to the inverting input terminal of the operational amplifier. A high-impedance current source structure is connected to the input stage differential structure to provide a stable static operating current for the non-inverting and inverting input transistors through an external current generation circuit. The input bias current sampling compensation structure includes a non-inverting sampling transistor, an inverting sampling transistor, and a high-side current mirror structure. It is used to sample the base current of the non-inverting input transistor and the inverting input transistor respectively through the non-inverting sampling transistor and the inverting sampling transistor, and to compensate the non-inverting input terminal and the inverting input terminal of the operational amplifier through the high-side current mirror structure.

[0006] In some embodiments, the high-side current mirror structure includes a first high-side current mirror and a second high-side current mirror, which are used for the positive-phase sampling tube and the negative-phase sampling tube, respectively. The first high-side current mirror includes transistors QP6, QP7, QP8, and QP9. The base of transistor QP6 is connected to the base of transistor QP7, the emitter of transistor QP6 is connected to the collector of transistor QP8, the collector of transistor QP6 is connected to the base of the non-inverting sampling transistor, and the base and collector of transistor QP6 are interconnected. The collector of transistor QP7 is connected to the non-inverting input terminal of the operational amplifier, the emitter of transistor QP7 is connected to the collector of transistor QP9, the base of transistor QP8 is connected to the base of transistor QP9, the emitter of transistor QP8 is connected to the emitter of transistor QP9, and the base and collector of transistor QP9 are interconnected. The second high-side current mirror includes transistors QP10, QP11, QP12, and QP13. The base of transistor QP10 is connected to the base of transistor QP11, the emitter of transistor QP10 is connected to the collector of transistor QP12, the collector of transistor QP10 is connected to the base of the inverting sampling transistor, the base and collector of transistor QP10 are interconnected, the collector of transistor QP11 is connected to the inverting input of the operational amplifier, the emitter of transistor QP11 is connected to the collector of transistor QP13, the base of transistor QP12 is connected to the base of transistor QP13, the emitter of transistor QP12 is connected to the emitter of transistor QP13, and the base and collector of transistor QP13 are interconnected.

[0007] In some embodiments, the input bias current sampling compensation structure further includes: transistor QN6B, transistor QN6A, transistor QN7B, transistor QN7A, laser trimming resistor R1B, and laser trimming resistor R1A. The bases of transistors QN6B, QN6A, QN7B, and QN7A are all connected to an external current generation circuit. The collector of transistor QN6B is connected to the emitter of the non-inverting sampling transistor. The emitter of transistor QN6B is connected to the collector of transistor QN7B. The collector of transistor QN6A is connected to the emitter of the inverting sampling transistor. The emitter of transistor QN6A is connected to the collector of transistor QN7A. The emitter of transistor QN7B is connected to laser trimming resistor R1B. The emitter of transistor QN7A is connected to laser trimming resistor R1A.

[0008] In some embodiments, the input bias current sampling compensation structure further includes a voltage clamping structure, which includes transistors QP3A, QN5A, QN4A, QP4B, and QP5B. The base of transistor QP3A is connected to the emitter of the non-inverting sampling transistor. The emitter of transistor QP3A is connected to the emitter of transistor QN5A. The collector of transistor QP3A is connected to the negative power supply. The base of transistor QN5A is connected to the base of transistor QN4A. The base and collector of transistor QN5A are interconnected. The collector of transistor QN5A is connected to the collector of transistor QP4B. The emitter of transistor QN4A is connected to the collectors of both the non-inverting and inverting sampling transistors. The bases of transistors QP4B and QP5B are connected to a bias voltage. The emitters of transistors QP4B and QP5B are connected to a positive power supply. The collector of transistor QN4A is connected to a positive power supply. The collector of transistor QP5B is connected to the high-side current mirror structure.

[0009] In some embodiments, the input bias current sampling compensation structure further includes: a global voltage clamping transistor QP14, the collector of which is connected to the collector of transistor QP3A, the emitter of which is connected to the high-side current mirror structure, and the base of which is connected to the input stage differential structure.

[0010] In some embodiments, the input stage differential structure includes: transistor QP3, transistor QN3, transistor QN4 and transistor QN5, transistor QP4, transistor QP1, transistor QP2, resistor R5 and resistor R6; The base of transistor QP3 is connected to the emitters of the non-inverting and inverting input transistors. The collector of transistor QP3 is connected to the negative power supply. The emitter of transistor QP3 is connected to the emitter of transistor QN5. The collector and base of transistor QN5 are connected to each other. The collector of transistor QN5 is connected to the collector of transistor QP4. The base of transistor QN5 is connected to the bases of transistor QN4 and QN3. The collector of transistor QN4 is connected to the collector of transistor QP2. The emitter of transistor QN4 is connected to the collector of the inverting input transistor. The collector of transistor QN3 is connected to the collector of transistor QP1. The emitter of transistor QN3 is connected to the collector of the non-inverting input transistor. The bases of transistors QP4, QP1, and QP2 are connected to a bias voltage. The emitter of transistor QP4 is connected to the positive power supply. The emitter of transistor QP2 is connected to the positive power supply through resistor R6. The emitter of transistor QP1 is connected to the positive power supply through resistor R5.

[0011] In some embodiments, the high-impedance current source structure includes: transistor QN6, transistor QN7, and resistor R1; The bases of transistors QN6 and QN7 are connected to an external current generation circuit. The collector of transistor QN6 is connected to the emitter of the non-inverting and inverting input transistors. The emitter of transistor QN6 is connected to the collector of transistor QN7. The emitter of transistor QN7 is connected to the negative power supply through resistor R1.

[0012] In some implementations, the input stage differential structure further includes a PJFET transistor; The source of the PJFET is connected to the collector of transistor QP4, the drain of the PJFET is connected to the collector of transistor QN5, and the gate of the PJFET is connected to a positive power supply.

[0013] Secondly, an operational amplifier includes the aforementioned operational amplifier input bias current compensation circuit.

[0014] Thirdly, a method for operating an operational amplifier input bias current compensation circuit, based on an operational amplifier input bias current compensation circuit, includes the following steps: A high-impedance current source structure is used to provide a stable static operating current for the input stage differential structure. The base currents of the non-inverting and inverting input transistors are sampled by the non-inverting and inverting sampling transistors, respectively. The base currents are then mirrored by the high-side current mirror structure and compensated to the non-inverting and inverting input terminals of the operational amplifier, respectively, to complete the compensation.

[0015] Compared with the prior art, the present invention has the following beneficial effects: This invention provides an operational amplifier input bias current compensation circuit. Through an input bias current sampling compensation structure, the input stage and compensation stage can respond to the radiation environment as a whole, avoiding compensation failure caused by the independent degradation of the two parts in traditional designs. This solves the problem of a significant increase in input bias current after irradiation. A high-impedance current source ensures stable operating current, and the input bias current sampling compensation structure achieves real-time cancellation. Together, they reduce the input bias current and maintain stability over a wide temperature and voltage range.

[0016] Furthermore, the base current loss during the mirroring process is internally canceled by the high-side current mirror structure, which improves the absolute accuracy of the current mirror. In addition, the compensation current is not affected by the common-mode voltage that changes with the input of the operational amplifier, ensuring the compensation consistency across the entire common-mode input range.

[0017] Furthermore, by using laser trimming resistors R1B and R1A, not only can the input bias current be adjusted to the optimal value, but the compensation amount of the positive and negative channels can also be finely adjusted independently. This allows for a synchronous and effective reduction of the input offset current, achieving comprehensive optimization that cannot be achieved by a single trimming.

[0018] Furthermore, the input bias current sampling compensation structure also includes a voltage clamping structure, which enables the sampling tube and the input tube to operate at the same voltage, ensuring long-term accuracy and temperature stability of the compensation.

[0019] Furthermore, the collector of the global voltage clamping transistor QP14 is connected to the collector of the transistor QP3A, the emitter of the global voltage clamping transistor QP14 is connected to the high-side current mirror structure, and the base of the global voltage clamping transistor QP14 is connected to the input stage differential structure. This dynamically locks the critical operating point voltages of the input stage and the compensation stage together. When radiation causes device parameter degradation, the transistor QP14 forces the operating voltages of the two circuit modules to drift synchronously and in the same direction, maintaining a dynamic compensation balance at the system level. This ensures that even after high-dose radiation, the change in input bias current can still be limited to an extremely low level.

[0020] Furthermore, the source of the PJFET is connected to the collector of transistor QP4, the drain of the PJFET is connected to the collector of transistor QN5, and the gate of the PJFET is connected to the positive power supply, which can improve the stability and temperature performance of the clamping node, thereby making the current source purer and more stable. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the input-level differential structure provided in an embodiment of the present invention; Figure 2A schematic diagram of a PTAT current generation circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the input bias current sampling compensation structure provided in an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] To improve the performance of the input stage of a high-precision operational amplifier and reduce the impact of input bias / offset current on system accuracy, especially to ensure high performance even in space applications, this embodiment proposes an operational amplifier input bias current compensation circuit. Through precise current sampling, a rigorous mirror structure, sufficient accuracy compensation, and consistent design of key component operating states, the circuit solves the problems of insufficient and unstable input bias current in operational amplifiers, particularly addressing the issue of a significant increase in input bias current after total dose radiation.

[0024] An operational amplifier input bias current compensation circuit includes: an input stage differential structure, a high-impedance current source structure, and an input bias current sampling compensation structure. The input stage differential structure includes a non-inverting input transistor QN1 and an inverting input transistor QN2, with the base of QN1 connected to the non-inverting input terminal of the operational amplifier and the base of QN2 connected to the inverting input terminal. The high-impedance current source structure is connected to the input stage differential structure and is used to provide a stable static operating current to QN1 and QN2 through an external current generation circuit. The input bias current sampling compensation structure includes a non-inverting sampling transistor QN1A, an inverting sampling transistor QN2A, and a high-side current mirror structure, used to sample the base currents of QN1 and QN2 through QN1A and QN2 respectively, and compensate them to the non-inverting and inverting input terminals of the operational amplifier through the high-side current mirror structure.

[0025] like Figure 1 As shown, the input stage differential structure uses an NPN transistor as the input stage. The input stage operating current is provided by a high-impedance current source consisting of QN6, QN7, and R1. VB1 and VB2 are provided by... Figure 2 The typical PTAT current bias shown is generated. VO- is the inverting output terminal, VO+ is the non-inverting output terminal, and VB3 and VB4 are stable voltages generated by the bias circuit.

[0026] The input stage differential structure includes: transistors QP3, QN3, QN4 and QN5, transistor QP4, transistor QP1, transistor QP2, resistor R5 and resistor R6; The base of transistor QP3 is connected to the emitters of the non-inverting input transistor QN1 and the inverting input transistor QN2. The collector of transistor QP3 is connected to the negative power supply. The emitter of transistor QP3 is connected to the emitter of transistor QN5. The collector and base of transistor QN5 are connected to each other. The collector of transistor QN5 is connected to the collector of transistor QP4. The base of transistor QN5 is connected to the bases of transistor QN4 and transistor QN3. The collector of transistor QN4 is connected to the collector of transistor QP2. The emitter of transistor QN4 is connected to the collector of the inverting input transistor QN2. The collector of transistor QN3 is connected to the collector of transistor QP1. The emitter of transistor QN3 is connected to the collector of the non-inverting input transistor QN1. The bases of transistors QP4, QP1, and QP2 are connected to a bias voltage. The emitter of transistor QP4 is connected to the positive power supply. The emitter of transistor QP2 is connected to the positive power supply through resistor R6. The emitter of transistor QP1 is connected to the positive power supply through resistor R5.

[0027] The high-impedance current source structure includes: transistor QN6, transistor QN7, and resistor R1; the bases of transistors QN6 and QN7 are connected to an external current generation circuit, the collector of transistor QN6 is connected to the emitters of the non-inverting input transistor QN1 and the inverting input transistor QN2, the emitter of transistor QN6 is connected to the collector of transistor QN7, and the emitter of transistor QN7 is connected to a negative power supply through resistor R1.

[0028] The output impedance of this high-impedance current source structure can reach tens of megaohms, and the quiescent current of the input stage remains very stable even when the input voltage varies across the entire common-mode range. To avoid the impact of input transistor CE voltage changes caused by power supply voltage variations on the current amplification factor, an input transistor CE voltage clamping structure composed of QP3, QN3, QN4, and QN5 is designed, making the input transistor CE voltage approximately equal to the BE junction turn-on voltage, and almost unaffected by power supply voltage and common-mode input voltage.

[0029] With this clamping structure, clamping transistor QP3 will provide additional base current to the current source. If the input pair of transistors is perfectly symmetrical, the input bias current at the positive and negative input terminals will be:

[0030] In the formula, β1 is the current amplification factor of the differential input transistors (QN1, QN2), β2 is the current amplification factor of the QP3 transistor, and I BThe current supplied to the current sink, I BIAS1 This is the operating current of the clamping structure.

[0031] As can be seen from the formula, the operating current I of the QP3 transistor is... BIAS1 This will also affect the input bias current. To improve I... BIAS1 To ensure current stability, a PJFET (PJ1) is connected between the collectors of QP4 and QN5 transistors. The source of PJ1 is connected to the collector of QP4, the drain to the collector of QN5, and the gate to the positive power supply (V+). This structure clamps the collector-emitter voltage (CE) of QP4 through the gate-source voltage (GS) of PJ1, making the CE voltage of QP4 almost unaffected by the power supply voltage, thus ensuring stable current output. BIAS1 The current is very stable, which helps improve the stability of the input bias current. The source of PJFET PJ1 is connected to the collector of transistor QP4, the drain of PJFET PJ1 is connected to the collector of transistor QN5, and the gate of PJFET PJ1 is connected to the positive power supply.

[0032] like Figure 3 As shown, this is the input bias current sampling and compensation structure. Transistors QN1A and QN2A sample the base currents of the non-inverting input transistor QN1 and the inverting input transistor QN2, respectively. The sampled base currents are then compensated to the bases of the operational amplifier input transistors (QN1 and QN2) (the positive and negative input ports of the operational amplifier) ​​through high-side current mirror structures (QP6~QP9 and QP10~QP13), thereby reducing the operational amplifier's input bias current. Ideally, if the compensated base current equals the required base current for the input stage, the input bias current measured at the operational amplifier input port will be zero.

[0033] In practical design and application, it is difficult to achieve the ideal current compensation effect. Therefore, the input bias current compensation structure in this embodiment adopts the following scheme to improve the bias current compensation accuracy.

[0034] 1) An independent sampling and compensation method is adopted for positive and negative phases. Two high-impedance constant current sources are used to mirror the operating current of the input stage, and then supplied to two current sampling transistors respectively. Furthermore, by using laser high-precision adjustment of resistors R1A and R1B below the constant current sources, the current sampling accuracy of the positive and negative input transistors can be adjusted to compensate for interference. This achieves synchronous adjustment and optimization of input bias current and input offset current.

[0035] 2) Voltage clamping design for the CE voltage of the sampling transistors. Using the same design approach as the input stage, a voltage clamping structure is formed by QP3A, QN4A, and QN5A. This ensures that the CE junction voltage of the sampling transistors QN1A and QN2A is approximately equal to the BE junction turn-on voltage, and remains almost unchanged with the power supply voltage and common-mode input voltage.

[0036] 3) A negative feedback current source with base current compensation, consisting of four PNP transistors, is employed. This current source structure has two significant advantages. Firstly, it has base current compensation capability, making the sampled base current and the current compensated to the input more accurate, almost unaffected by the current amplification factor of the PNP transistors. Secondly, negative feedback can significantly improve the output impedance, making the image accuracy almost unaffected by the common-mode voltage of the operational amplifier input.

[0037] 4) Actual measurements confirmed that the three optimization measures described above were sufficient to reduce the input bias current and input offset current of the operational amplifier to less than 0.5 nA. However, tests after total dose irradiation revealed a significant deterioration in the input bias current and input offset current. The input bias current increased by an order of magnitude after 100 klad (Si) total dose irradiation, and even reached 30 nA after 300 klad (Si) total dose irradiation, which completely failed to meet the performance requirements of a high-precision operational amplifier.

[0038] Therefore, this embodiment addresses the issue of significant degradation of the input bias current after total dose radiation by employing a QP14 transistor as a global voltage clamping device, with the base of the QP14 connected to... Figure 3 At VA, the emitter of the QP14 transistor is connected to the collector of the QP5B transistor.

[0039] QP5B is a PNP transistor current source, providing base current to QN1A and QN2A, and also providing compensation current to the positive and negative input terminals. During normal operation, the power supply to QP5B exceeds the required base current and compensation current; the excess current is discharged through transistor QP14. Therefore, transistor QP14 determines the base voltage of QN1A and QN2A, ensuring that the base voltages of QN1A and QN2A always follow the base voltages of the operational amplifier input transistors QN1 and QN2.

[0040] The QP14 transistor tightly integrates the input stage clamping structure and the current compensation structure through a low-resistance channel. This ensures that the total dose radiation effect has a similar impact on the operational amplifier input stage circuit and the bias current sampling compensation circuit, avoiding significant changes in the input bias current due to radiation effects caused by differences in device performance degradation.

[0041] Transistors QP6, QP7, QP8, and QP9 are used. The base of transistor QP6 is connected to the base of transistor QP7. The emitter of transistor QP6 is connected to the collector of transistor QP8. The collector of transistor QP6 is connected to the base of the non-inverting sampling transistor QN1A. The base and collector of transistor QP6 are connected to each other. The collector of transistor QP7 is connected to the non-inverting input terminal of the operational amplifier. The emitter of transistor QP7 is connected to the collector of transistor QP9. The base of transistor QP8 is connected to the base of transistor QP9. The emitter of transistor QP8 is connected to the emitter of transistor QP9. The base and collector of transistor QP9 are connected to each other. The base of transistor QP10 is connected to the base of transistor QP11, the emitter of transistor QP10 is connected to the collector of transistor QP12, the collector of transistor QP10 is connected to the base of the inverting sampling transistor QN2A, the base and collector of transistor QP10 are interconnected, the collector of transistor QP11 is connected to the inverting input terminal of the operational amplifier, the emitter of transistor QP11 is connected to the collector of transistor QP13, the base of transistor QP12 is connected to the base of transistor QP13, the emitter of transistor QP12 is connected to the emitter of transistor QP13, and the base and collector of transistor QP13 are interconnected.

[0042] The bases of transistors QN6B, QN6A, QN7B, and QN7A are all connected to an external current generation circuit. The collector of transistor QN6B is connected to the emitter of the non-inverting sampling transistor QN1A. The emitter of transistor QN6B is connected to the collector of transistor QN7B. The collector of transistor QN6A is connected to the emitter of the inverting sampling transistor QN2A. The emitter of transistor QN6A is connected to the collector of transistor QN7A. The emitter of transistor QN7B is connected to the laser trimming resistor R1B. The emitter of transistor QN7A is connected to the laser trimming resistor R1A.

[0043] The base of transistor QP3A is connected to the emitter of the non-inverting sampling transistor QN1A. The emitter of transistor QP3A is connected to the emitter of transistor QN5A. The collector of transistor QP3A is connected to the negative power supply. The base of transistor QN5A is connected to the base of transistor QN4A. The base and collector of transistor QN5A are interconnected. The collector of transistor QN5A is connected to the collector of transistor QP4B. The emitter of transistor QN4A is connected to the collectors of the non-inverting sampling transistor QN1A and the inverting sampling transistor QN2A. The bases of transistors QP4B and QP5B are connected to the bias voltage. The emitters of transistors QP4B and QP5B are connected to the positive power supply. The collector of transistor QN4A is connected to the positive power supply. The collector of transistor QP5B is connected to the high-side current mirror structure.

[0044] The collector of the global voltage clamping transistor QP14 is connected to the collector of the transistor QP3A, the emitter of the global voltage clamping transistor QP14 is connected to the high-side current mirror structure, and the base of the global voltage clamping transistor QP14 is connected to the input stage differential structure.

[0045] The circuit structure of this embodiment was used to develop a high-precision operational amplifier. The initial input bias / offset current of the circuit is ≤3nA, and can be ≤0.2nA after online wafer trimming; the variation is ≤0.7nA in the temperature range of -55℃ to 125℃; the variation of the power supply voltage is ≤0.2nA in the range of ±2 to ±18V; the variation after 100krad (Si) total dose radiation is ≤0.3nA, and the variation after 300krad (Si) total dose radiation is ≤0.5nA.

[0046] Evaluation results show that the circuit in this embodiment can effectively reduce the input bias current of the high-precision operational amplifier and maintain a high parameter level in the full operating environment.

[0047] The advantages of this embodiment compared to the prior art are as follows: (1) This embodiment uses a standard NPN transistor as the input stage of the operational amplifier, which reduces the dependence on advanced processes and makes it easier to port and use; (2) Compared with the existing input bias current compensation structure, this embodiment adds an independent sampling and adjustment structure for the positive and negative terminals, which reduces the input bias current and the input offset current. (3) This embodiment has designed the key components to be consistent in their working state, and the input bias current is more stable with respect to working temperature, voltage and external environment compared with the prior art.

[0048] (4) The most prominent advantage of this embodiment is that it has the ability to resist total dose radiation. The input bias / offset current will not show significant degradation after 300 klad (Si) total dose radiation, and it can be applied to the space environment, especially the field of deep space exploration.

[0049] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An operational amplifier input bias current compensation circuit, characterized in that, include: Input stage differential structure, high impedance current source structure and input bias current sampling compensation structure; The input-stage differential structure includes a non-inverting input transistor and an inverting input transistor. The base of the non-inverting input transistor is connected to the non-inverting input terminal of the operational amplifier, and the base of the inverting input transistor is connected to the inverting input terminal of the operational amplifier. A high-impedance current source structure is connected to the input stage differential structure to provide a stable static operating current for the non-inverting and inverting input transistors through an external current generation circuit. The input bias current sampling compensation structure includes a non-inverting sampling transistor, an inverting sampling transistor, and a high-side current mirror structure. It is used to sample the base current of the non-inverting input transistor and the inverting input transistor respectively through the non-inverting sampling transistor and the inverting sampling transistor, and to compensate the non-inverting input terminal and the inverting input terminal of the operational amplifier through the high-side current mirror structure.

2. The operational amplifier input bias current compensation circuit according to claim 1, characterized in that, The high-side current mirror structure includes a first high-side current mirror and a second high-side current mirror, which are used for the positive-phase sampling tube and the negative-phase sampling tube, respectively. The first high-side current mirror includes transistors QP6, QP7, QP8, and QP9. The base of transistor QP6 is connected to the base of transistor QP7, the emitter of transistor QP6 is connected to the collector of transistor QP8, the collector of transistor QP6 is connected to the base of the non-inverting sampling transistor, and the base and collector of transistor QP6 are interconnected. The collector of transistor QP7 is connected to the non-inverting input terminal of the operational amplifier, the emitter of transistor QP7 is connected to the collector of transistor QP9, the base of transistor QP8 is connected to the base of transistor QP9, the emitter of transistor QP8 is connected to the emitter of transistor QP9, and the base and collector of transistor QP9 are interconnected. The second high-side current mirror includes transistors QP10, QP11, QP12, and QP13. The base of transistor QP10 is connected to the base of transistor QP11, the emitter of transistor QP10 is connected to the collector of transistor QP12, the collector of transistor QP10 is connected to the base of the inverting sampling transistor, the base and collector of transistor QP10 are interconnected, the collector of transistor QP11 is connected to the inverting input of the operational amplifier, the emitter of transistor QP11 is connected to the collector of transistor QP13, the base of transistor QP12 is connected to the base of transistor QP13, the emitter of transistor QP12 is connected to the emitter of transistor QP13, and the base and collector of transistor QP13 are interconnected.

3. The operational amplifier input bias current compensation circuit according to claim 1, characterized in that, The input bias current sampling compensation structure also includes: transistor QN6B, transistor QN6A, transistor QN7B, transistor QN7A, laser trimming resistor R1B, and laser trimming resistor R1A. The bases of transistors QN6B, QN6A, QN7B, and QN7A are all connected to an external current generation circuit. The collector of transistor QN6B is connected to the emitter of the non-inverting sampling transistor. The emitter of transistor QN6B is connected to the collector of transistor QN7B. The collector of transistor QN6A is connected to the emitter of the inverting sampling transistor. The emitter of transistor QN6A is connected to the collector of transistor QN7A. The emitter of transistor QN7B is connected to laser trimming resistor R1B. The emitter of transistor QN7A is connected to laser trimming resistor R1A.

4. The operational amplifier input bias current compensation circuit according to claim 1, characterized in that, The input bias current sampling compensation structure also includes a voltage clamping structure, which includes: transistor QP3A, transistor QN5A, transistor QN4A, transistor QP4B, and transistor QP5B. The base of transistor QP3A is connected to the emitter of the non-inverting sampling transistor. The emitter of transistor QP3A is connected to the emitter of transistor QN5A. The collector of transistor QP3A is connected to the negative power supply. The base of transistor QN5A is connected to the base of transistor QN4A. The base and collector of transistor QN5A are interconnected. The collector of transistor QN5A is connected to the collector of transistor QP4B. The emitter of transistor QN4A is connected to the collectors of both the non-inverting and inverting sampling transistors. The bases of transistors QP4B and QP5B are connected to a bias voltage. The emitters of transistors QP4B and QP5B are connected to a positive power supply. The collector of transistor QN4A is connected to a positive power supply. The collector of transistor QP5B is connected to the high-side current mirror structure.

5. The operational amplifier input bias current compensation circuit according to claim 4, characterized in that, The input bias current sampling compensation structure further includes: a global voltage clamping transistor QP14, the collector of the global voltage clamping transistor QP14 is connected to the collector of the transistor QP3A, the emitter of the global voltage clamping transistor QP14 is connected to the high-side current mirror structure, and the base of the global voltage clamping transistor QP14 is connected to the input stage differential structure.

6. An operational amplifier input bias current compensation circuit according to claim 1, characterized in that, The input stage differential structure includes: transistors QP3, QN3, QN4 and QN5, transistor QP4, transistor QP1, transistor QP2, resistor R5 and resistor R6. The base of transistor QP3 is connected to the emitters of the non-inverting and inverting input transistors. The collector of transistor QP3 is connected to the negative power supply. The emitter of transistor QP3 is connected to the emitter of transistor QN5. The collector and base of transistor QN5 are connected to each other. The collector of transistor QN5 is connected to the collector of transistor QP4. The base of transistor QN5 is connected to the bases of transistor QN4 and QN3. The collector of transistor QN4 is connected to the collector of transistor QP2. The emitter of transistor QN4 is connected to the collector of the inverting input transistor. The collector of transistor QN3 is connected to the collector of transistor QP1. The emitter of transistor QN3 is connected to the collector of the non-inverting input transistor. The bases of transistors QP4, QP1, and QP2 are connected to a bias voltage. The emitter of transistor QP4 is connected to the positive power supply. The emitter of transistor QP2 is connected to the positive power supply through resistor R6. The emitter of transistor QP1 is connected to the positive power supply through resistor R5.

7. The operational amplifier input bias current compensation circuit according to claim 6, characterized in that, The high-impedance current source structure includes: transistor QN6, transistor QN7, and resistor R1; The bases of transistors QN6 and QN7 are connected to an external current generation circuit. The collector of transistor QN6 is connected to the emitter of the non-inverting and inverting input transistors. The emitter of transistor QN6 is connected to the collector of transistor QN7. The emitter of transistor QN7 is connected to the negative power supply through resistor R1.

8. The operational amplifier input bias current compensation circuit according to claim 6, characterized in that, The input stage differential structure also includes a PJFET transistor; The source of the PJFET is connected to the collector of transistor QP4, the drain of the PJFET is connected to the collector of transistor QN5, and the gate of the PJFET is connected to a positive power supply.

9. An operational amplifier, characterized in that, The operational amplifier input bias current compensation circuit includes any one of claims 1 to 8.

10. A method for operating an operational amplifier input bias current compensation circuit, characterized in that, An operational amplifier input bias current compensation circuit based on any one of claims 1 to 8 includes the following steps: A high-impedance current source structure is used to provide a stable static operating current for the input stage differential structure. The base currents of the non-inverting and inverting input transistors are sampled by the non-inverting and inverting sampling transistors, respectively. The base currents are then mirrored by the high-side current mirror structure and compensated to the non-inverting and inverting input terminals of the operational amplifier, respectively, to complete the compensation.

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