Variable fractional delay filter based on symmetric structure and weighted least square method
By using a variable fractional delay filter based on a symmetric structure and weighted least squares method, the problems of time-consuming phase angle calibration, large phase shift error, and high hardware cost in electricity metering are solved. This achieves high-precision, low-overhead, and stable electricity metering, adapts to fundamental frequency fluctuations, simplifies the meter calibration process, and improves metering fairness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-14
- Publication Date
- 2026-03-13
AI Technical Summary
Existing technologies in electricity metering suffer from problems such as time-consuming and cumbersome phase angle calibration, large phase shift error, high hardware cost, and poor adaptability to fundamental frequency fluctuations, making it difficult to achieve a filter design that balances high precision and stability.
A variable fractional delay filter based on symmetric structure and weighted least squares method is adopted. Through signal parameter pre-calculation, symmetric structure FIR coefficient construction, WLS coefficient optimization, phase shift execution, and adaptive calibration and frequency tracking unit, the joint phase shift of integer and fractional delay is realized to adapt to fundamental frequency fluctuations and optimize the coefficient matrix to reduce hardware overhead.
It effectively reduces phase shift error and reactive power residue, meets the requirements of high-precision power metering, has low hardware overhead, good stability, fast response, adapts to base frequency fluctuations, simplifies the meter calibration process, reduces miscompensation problems, and improves metering fairness.
Smart Images
Figure CN121664149A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electricity metering, specifically to a variable fractional delay filter based on a symmetric structure and weighted least squares method. Background Technology
[0002] In the field of electricity metering, phase angle calibration is a crucial step in ensuring metering accuracy. Phase angle errors directly lead to power factor errors, which can cause significant deviations in electricity billing, especially for high-load industrial users. Currently, phase angle calibration is affected by the nonlinearity of current transformers and peripheral circuits over high current ranges, often requiring segmented operations, which is time-consuming and cumbersome. Meanwhile, traditional reactive power metering often uses Hilbert filters, which, while meeting certain accuracy requirements, have significant shortcomings: firstly, phase shift errors increase after fixed-point implementation, easily generating reactive power residue and affecting metering accuracy; secondly, increasing the filter order to improve accuracy not only significantly increases hardware costs but may also adversely affect filter stability, making it difficult to balance accuracy and stability.
[0003] Furthermore, in practical applications, voltage and current paths are prone to phase shift due to issues with peripheral circuits or transformers. When correcting phase shifts using traditional pulse calibration methods, if the phase shift is slightly large, inaccurate calculations can lead to miscompensation, resulting in increased reactive power residue. Moreover, traditional solutions often rely on segmented calibration coefficients at a fixed power frequency. When the fundamental frequency fluctuates, timely adjustments are impossible, hindering high-precision metering across all operating conditions. Therefore, a filter design that overcomes these limitations while balancing high-precision phase shifting, low hardware overhead, and strong fundamental frequency adaptability is urgently needed. Summary of the Invention
[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a variable fractional delay filter based on a symmetric structure and weighted least squares method to solve the problems mentioned in the background art.
[0005] The variable fractional delay filter based on symmetric structure and weighted least squares method of the present invention includes: The signal parameter pre-calculation unit is used to provide delay parameters for the filter; Symmetric FIR coefficient building blocks are used to compute symmetric FIR coefficient frames. WLS coefficient optimization unit, used to calculate the fixed-point optimization coefficient matrix; The phase-shifting execution unit is used to achieve integer delay for the current signal through the buffer length and fractional delay compensation for the voltage signal through the VFD filter. The two work together to complete the "integer + fractional" joint phase shift. The adaptive calibration and frequency tracking unit is used to calculate the angle difference between voltage and current. The calculated angle difference is added to the original phase shift angle to obtain the updated phase shift angle. When the absolute value of the difference between the current base frequency and the historical base frequency is detected to be greater than the base frequency fluctuation threshold, the integer part of the delay, the fractional delay, and the current path signal buffer length are updated synchronously.
[0006] Furthermore, providing delay parameters for the filter includes first determining the sampling rate, initial value of the fundamental frequency, initial phase shift angle, and VFD filter order of the voltage and current signals; calculating the delay length based on the formula constructed from the initial phase shift angle, sampling rate, and fundamental frequency; splitting the delay length into an integer part obtained by rounding down and a fractional part of the delay length minus the integer part; and then determining the buffer length of the current path based on the sum of the VFD filter order and the integer part.
[0007] Furthermore, the calculation of the symmetric FIR coefficient framework includes first determining the order of the VFD filter coefficient polynomial and the range of fractional delay as the basic input conditions for coefficient construction, then deriving the coefficient symmetry relationship and using this relationship to reduce the total number of coefficients, and then further eliminating invalid coefficients based on the conclusion that the coefficients at specific positions are 0 when the polynomial order is odd, finally forming a symmetric FIR coefficient framework that includes the positions of non-zero coefficients and sign correlation.
[0008] Furthermore, the calculation of the fixed-point optimization coefficient matrix includes: first, determining the target frequency response range and the normalized value of the passband cutoff frequency to ensure the filter's phase shift direction, accuracy, and stable frequency response within the passband; using the weighted square integral of the actual and target frequency response errors as the optimization objective to ensure that the optimization revolves around the optimal phase shift accuracy within the passband; then solving the weighted least squares problem and adjusting the coefficients to make the filter frequency response approximate the target frequency response to obtain the coefficient matrix; finally, performing fixed-point processing on the coefficient matrix to adapt it to the hardware without requiring an additional floating-point arithmetic module.
[0009] Furthermore, the implementation of integer delay for current signals via buffer length and fractional delay compensation for voltage signals via VFD filters, with both working together to complete "integer + fractional" joint phase shifting, involves first acquiring delay parameters, the obtained optimized coefficient matrix, and real-time voltage and current signals. The current signal is input into a buffer module with a preset buffer length to achieve integer delay, and the voltage signal is input into a VFD filter loaded with the optimized coefficient matrix and combined with fractional delay parameters for fractional delay compensation. During compensation, the two signals are processed and then synchronously integrated to achieve the preset phase shift relationship, ultimately completing the joint phase shifting operation.
[0010] Furthermore, the calculation of the angle difference between voltage and current involves first acquiring real-time active and reactive power data and defining the system's rated power as the benchmark reference value for angle difference calculation. Combining the numerical relationship between real-time active and reactive power, the angle difference is derived. First, the amplitude gain is calculated using the ratio of rated power to real-time active power to eliminate the influence of ratio difference. Then, taking advantage of the characteristic that when the angle difference is small, its tangent is approximately equal to itself and equal to the ratio of reactive power to active power, combined with amplitude gain correction, the angle difference between voltage and current is finally obtained.
[0011] Furthermore, the calculated angle difference is added to the original phase shift angle to obtain the updated phase shift angle. When the fundamental frequency fluctuation exceeds the threshold, the relevant parameters are updated synchronously. This includes first summing the calculated angle difference with the original phase shift angle to obtain the updated phase shift angle to correct the phase shift deviation. After the update, the trigger signal parameter pre-calculation unit and the WLS coefficient optimization unit recalculate the delay parameters and the optimization coefficient matrix, respectively. At the same time, the absolute value of the current and historical fundamental frequency difference is monitored in real time and compared with the fundamental frequency fluctuation threshold. When the absolute value exceeds the threshold, the parameter update process is started to recalculate the integer part of the delay, the fractional delay, and the current path signal buffer length. The updated parameters immediately replace the original parameters and are applied to the subsequent process.
[0012] In addition, this invention discloses an electronic device, including one or more processors or processing units, wherein the processor implements the variable fractional delay filter based on symmetric structure and weighted least squares method provided in the above embodiments of this invention by running a program stored in a memory.
[0013] In addition, this invention discloses a computer-readable storage medium storing a computer program that, when executed by a processor, implements a variable fractional delay filter based on a symmetric structure and weighted least squares method as provided in the embodiments of this invention.
[0014] The beneficial effects of this invention are: Compared to traditional filters, it can effectively reduce phase shift error and residual reactive power, meeting the requirements of higher precision power metering; it has lower hardware overhead, reducing the number of coefficients through a symmetrical structure, and the coefficients after fixed-point processing can be directly adapted to the hardware, reducing hardware storage and computing costs; it has better stability performance, adopting an FIR structure, with faster response speed, shortening the reactive power calculation stabilization time, and avoiding the stability risks of traditional IIR structures.
[0015] Superior technical performance (enhanced): Strong base frequency adaptability, capable of stably tracking base frequency fluctuations, and able to quickly update parameters when the base frequency changes, adapting to different regional power frequency standards; Simplified calibration process, eliminating the need for traditional segmented calibration operations, achieving full current range coverage calibration through adaptive calibration, reducing calibration time; Excellent error robustness, when facing voltage and current angle differences, reactive residual power can be controlled through angle difference correction, avoiding the miscompensation problem of traditional calibration methods, and improving metering fairness. Attached Figure Description
[0016] Figure 1 This is a block diagram of the variable fractional delay filter based on symmetric structure and weighted least squares method of the present invention. Detailed Implementation
[0017] like Figure 1 This application discloses a variable fractional delay filter based on a symmetric structure and weighted least squares method. This variable fractional delay filter includes: The signal parameter pre-calculation unit 100 is used to provide delay parameters for the filter. Specifically, providing delay parameters for the filter involves first determining the sampling rate of the voltage and current signals to be 6400Hz, the initial fundamental frequency to be 50Hz, the initial phase shift angle to be π / 2, and the VFD filter order to be 10. Then, the delay length is calculated according to a specific formula constructed using the initial phase shift angle, sampling rate, and fundamental frequency. The calculated delay length is split into an integer part and a fractional part, where the integer part is the floor function of the delay length, and the fractional part is the delay length minus the integer part. The buffer length of the current path is then determined based on the sum of the VFD filter order and the integer part. For example, when the fundamental frequency is 50Hz, the calculated integer delay is 32, the fractional delay is 0, and the current path buffer length is the sum of 32 and 10, i.e., 42. This provides the necessary delay parameters for the subsequent precise phase shifting of the filter.
[0018] Therefore, in this embodiment, providing delay parameters for the filter includes first determining the sampling rate of the voltage and current signals, the initial value of the fundamental frequency, the initial phase shift angle, and the order of the VFD filter; calculating the delay length based on the formula constructed from the initial phase shift angle, the sampling rate, and the fundamental frequency; splitting the delay length into an integer part obtained by rounding down and a fractional part of the delay length minus the integer part; and then determining the buffer length of the current path based on the sum of the VFD filter order and the integer part.
[0019] A symmetric FIR coefficient construction unit 200 is used to calculate the symmetric FIR coefficient framework. Specifically, the calculation of the symmetric FIR coefficient framework involves first determining that the order of the VFD filter coefficient polynomial is 4, and clarifying that the fractional delay is within the range of 0 to 1, using this as the basic input condition for coefficient construction. Then, through mathematical derivation, the symmetric relationship of the coefficients is obtained, that is, the coefficients at specific positions satisfy the rule that "the coefficient at the negative position is equal to the power of the polynomial order (-1) multiplied by the coefficient at the corresponding positive position." This rule is used to reduce the original total number of coefficients, decreasing the initial total number of coefficients from the product of (2 times the VFD filter order plus 1) and (the polynomial order plus 1) to the size of the product of (the VFD filter order plus 0.5) and (the polynomial order plus 1). Subsequently, based on the derivation of the conclusion that "when the polynomial order is odd, the coefficient corresponding to the zero position is 0", invalid coefficients are further eliminated. For example, when the polynomial order is 4, only the non-zero coefficients of orders 0, 2, and 4 are retained, and the coefficients of orders 1 and 3 are no longer retained. Finally, a symmetric FIR coefficient framework containing the specific positions of non-zero coefficients and the sign correlation between coefficients is formed. The number of coefficients under this framework is only 50% of that of ordinary FIR filters, which not only ensures the effectiveness of the coefficients, but also greatly reduces the subsequent hardware operation and storage overhead, and provides a reasonable coefficient structure support for the subsequent realization of precise phase shifting of VFD filters.
[0020] Therefore, in the embodiment, calculating the symmetric FIR coefficient framework includes first determining the order of the VFD filter coefficient polynomial and the fractional delay range as the basic input conditions for coefficient construction, then deriving the coefficient symmetry relationship and using this relationship to reduce the total number of coefficients, and then further eliminating invalid coefficients based on the conclusion that the coefficients at specific positions are 0 when the polynomial order is odd, and finally forming a symmetric FIR coefficient framework that includes the positions and sign associations of non-zero coefficients.
[0021] The WLS coefficient optimization unit 300 is used to calculate the fixed-point optimization coefficient matrix. Specifically, the calculation involves first defining the target frequency response range, setting the normalized angular frequency between 0 and π, and ensuring the target frequency response conforms to a specific exponential form to guarantee that the filter's phase shift direction and accuracy meet design expectations. Simultaneously, the normalized passband cutoff frequency is determined to be 0.9π, a value that ensures a stable frequency response within the effective passband. Next, the weighted square integral of the error between the actual filter frequency response and the target frequency response is used as the optimization objective. This objective function measures the deviation of the filter frequency response from the ideal state, ensuring the optimization direction always revolves around "optimal phase shift accuracy within the passband." Subsequently, a weighted least squares problem is solved using specialized numerical calculation tools. Through iterative calculations, the filter coefficients are continuously adjusted to make the designed filter frequency response as close as possible to the preset target frequency response, ultimately obtaining a coefficient matrix that meets the accuracy requirements. After obtaining the coefficient matrix, it is processed into 18-bit fixed-point format. This fixed-point format allows the coefficients to be directly adapted to the hardware device without the need for an additional floating-point arithmetic module. In this form, the matrix can control the phase shift error of the filter to within 0.001°, which is far better than the 0.02° phase shift error of the traditional Hilbert filter. At the same time, due to the use of the FIR structure, there is no stability risk of the IIR structure, which provides reliable coefficient support for the subsequent phase shifting execution unit to achieve high-precision phase shifting.
[0022] Therefore, in this embodiment, calculating the fixed-point optimization coefficient matrix includes: first, determining the target frequency response range and the normalized value of the passband cutoff frequency to ensure the filter's phase shift direction, accuracy, and stable frequency response within the passband; using the weighted square integral of the actual and target frequency response errors as the optimization objective to ensure that the optimization revolves around the optimal phase shift accuracy within the passband; then, solving the weighted least squares problem and adjusting the coefficients to make the filter frequency response approximate the target frequency response to obtain the coefficient matrix; and finally, performing fixed-point processing on the coefficient matrix to adapt it to the hardware without requiring an additional floating-point arithmetic module.
[0023] The phase-shifting execution unit 400 is used to achieve integer delay for the current signal through a buffer length and fractional delay compensation for the voltage signal through a VFD filter. These two components work together to complete a combined "integer + fractional" phase shift. Specifically, this involves first acquiring the integer delay, fractional delay, and current path buffer length output by the signal parameter pre-calculation unit, as well as the 18-bit fixed-point optimization coefficient matrix obtained by the WLS coefficient optimization unit. Simultaneously, real-time voltage and current signals are input. For the current signal, it is input into a buffer module with a preset buffer length. This buffer length is determined by the sum of the integer delay and the VFD filter order; for example, at a base frequency of 50Hz, the buffer length is 42. The current signal remains in the buffer module for the duration corresponding to the buffer length, thus achieving precise integer delay. For the voltage signal, it is input into a VFD filter loaded with an 18-bit fixed-point optimized coefficient matrix. The VFD filter performs fractional delay compensation on the voltage signal based on the fractional delay parameter and the optimized coefficients. During the compensation process, the low-overhead advantage of the symmetrical FIR coefficient framework is fully utilized to ensure the accuracy of the fractional delay. After completing the integer delay compensation for the current signal and the fractional delay compensation for the voltage signal, the two processed signals are synchronously integrated to achieve a preset phase shift relationship in time. For example, with an initial phase shift angle of π / 2, the required phase shift between the voltage and current signals is achieved, ultimately completing the joint phase shift operation of "integer + fractional". In a scenario with 1 times the rated power, through this joint phase shift processing, the reactive residual power of the input signal can be controlled within 0.05W, far superior to the 1.9W reactive residual power of the traditional Hilbert filter bank, meeting the high-precision phase shift requirements of power metering.
[0024] Therefore, in this embodiment, the process of achieving integer delay for the current signal through the buffer length and fractional delay compensation for the voltage signal through the VFD filter, with both working together to complete the "integer + fractional" joint phase shift, includes: first, acquiring the delay parameters, the obtained optimized coefficient matrix, and the real-time voltage and current signals; inputting the current signal into a buffer module with a preset buffer length to achieve integer delay; inputting the voltage signal into a VFD filter loaded with the optimized coefficient matrix and combining it with the fractional delay parameters for fractional delay compensation; after processing the two signals during compensation, synchronous integration is performed to achieve the preset phase shift relationship, and finally, the joint phase shift operation is completed.
[0025] The adaptive calibration and frequency tracking unit 500 is used to calculate the angle difference between voltage and current. Specifically, this calculation involves first acquiring real-time active and reactive power data, and determining the system's rated power. This rated power is calculated based on a rated voltage and current of 220V and 10A, specifically 2200W, which serves as the reference value for angle difference calculation. Next, combining the real-time active and reactive power values, the angle difference between voltage and current is derived according to a specific angle difference calculation logic. In a scenario with 1 times the rated power, it is known that active power equals the product of rated power, ratio difference, and the cosine of the angle difference, and reactive power equals the product of rated power, ratio difference, and the sine of the angle difference. The amplitude gain is first calculated using the ratio of rated power to real-time active power; this amplitude gain is used to eliminate the influence of the ratio difference on subsequent angle difference calculations. When the angle difference is small, its tangent is approximately equal to the angle difference itself. Since the tangent is equal to the ratio of reactive power to active power, the angle difference between voltage and current can be obtained by combining the ratio of real-time reactive power to real-time active power with the previously calculated amplitude gain. Therefore, in this embodiment, calculating the angle difference between voltage and current involves: first, acquiring real-time active and reactive power data and defining the system's rated power as the reference value for angle difference calculation; deriving the angle difference based on the real-time active and reactive power relationship; first, calculating the amplitude gain using the ratio of rated power to real-time active power to eliminate the influence of the ratio difference; and then, utilizing the characteristic that the tangent of the angle difference is approximately equal to itself and equal to the ratio of reactive power to active power when small, combined with amplitude gain correction, finally obtaining the angle difference between voltage and current.
[0026] The adaptive calibration and frequency tracking unit 500 adds the calculated angle difference to the original phase shift angle to obtain the updated phase shift angle. When it detects that the absolute value of the difference between the current base frequency and the historical base frequency is greater than the base frequency fluctuation threshold, it synchronously updates the integer part of the delay, the fractional delay, and the current path signal buffer length.
[0027] The calculated phase difference is added to the original phase shift angle to obtain the updated phase shift angle. When the absolute value of the difference between the current base frequency and the historical base frequency is detected to be greater than the base frequency fluctuation threshold, the integer part of the delay, the fractional delay, and the current path signal buffer length are updated synchronously. Specifically, after obtaining the phase difference between voltage and current, this phase difference value is directly summed with the original phase shift angle currently used by the system to obtain the updated phase shift angle, thereby correcting the phase shift deviation between voltage and current signals. For example, if the original phase shift angle is π / 2 and the calculated phase difference is 2°, then the updated phase shift angle is π / 2 plus the radian value corresponding to 2°. After updating the phase shift angle, the signal parameter pre-calculation unit is immediately triggered to work again. According to the new phase shift angle, the original sampling rate, the current base frequency, and other parameters, the integer delay, fractional delay, and current path buffer length are recalculated. At the same time, the WLS coefficient optimization unit is triggered to re-optimize the coefficient matrix based on the new parameters to ensure that subsequent phase shift operations can achieve accurate phase shifting based on the updated parameters. Throughout the process, the values of the current baseband frequency and the historical baseband frequency are monitored in real time. The absolute value of the difference between the two is compared with the set baseband frequency fluctuation threshold (set to 1Hz). When the absolute value is detected to be greater than 1Hz (for example, the historical baseband frequency is 50Hz, the current baseband frequency becomes 52Hz, and the absolute value of the difference is 2Hz), the parameter update process is started synchronously. Based on the new baseband frequency value, combined with the sampling rate, the updated phase shift angle, and the VFD filter order, the integer part of the delay, the fractional delay, and the current path signal buffer length are recalculated. For example, when the baseband frequency becomes 45Hz, the recalculated integer delay, fractional delay, and buffer length are updated to 35, 0.556, and 35, respectively. The updated parameters will immediately replace the original parameters and be applied to the subsequent phase shift execution and power metering process. There is no need to store multi-group segmented calibration coefficients, which simplifies the calibration process and ensures that the system can still maintain high-precision phase shift and metering effects when the baseband frequency fluctuates.
[0028] Therefore, in this embodiment, the calculated angle difference is added to the original phase shift angle to obtain the updated phase shift angle. When the base frequency fluctuation exceeds the threshold, the relevant parameters are updated synchronously. This includes first summing the calculated angle difference with the original phase shift angle to obtain the updated phase shift angle to correct the phase shift deviation. After the update, the trigger signal parameter pre-calculation unit and the WLS coefficient optimization unit recalculate the delay parameters and the optimization coefficient matrix, respectively. At the same time, the absolute value of the current and historical base frequency difference is monitored in real time and compared with the base frequency fluctuation threshold. When the absolute value exceeds the threshold, the parameter update process is started. The integer part of the delay, the fractional delay, and the current path signal buffer length are recalculated. The updated parameters immediately replace the original parameters and are applied to the subsequent process.
[0029] This application also provides an embodiment of an electronic device. The electronic device is manifested in the form of a general-purpose computing device. The components of the electronic device may include, but are not limited to: one or more processors or processing units, memory, and buses connecting different components (including memory and processing units).
[0030] A bus refers to one or more of several bus architectures, including memory buses or memory controllers, peripheral buses, graphics acceleration ports, processors, or local buses using any of the various bus architectures. Examples of these architectures include, but are not limited to, Industry Standard Architecture (ISA) buses, Micro Channel Architecture (MCA) buses, Enhanced ISA buses, Video Electronics Standards Association (VESA) local buses, and Peripheral Component Interconnect (PCI) buses.
[0031] Electronic devices typically include a variety of computer-readable media. These media can be any available media that can be accessed by the electronic device, including volatile and non-volatile media, and removable and non-removable media.
[0032] The memory may include computer-readable media in the form of volatile memory, such as random access memory (RAM) and / or cache memory. Electronic devices may further include other removable / non-removable, volatile / non-volatile computer device storage media. By way of example only, the storage system may be used to read and write non-removable, non-volatile magnetic media.
[0033] The electronic device can also communicate with one or more external devices (e.g., keyboard, pointing device, camera, etc.), may include a display, and may communicate with one or more devices that enable a user to interact with the electronic device, and / or with any device that enables the electronic device to communicate with one or more other computing devices (e.g., network card, modem, etc.). This communication can be performed via an input / output (I / O) interface. Furthermore, the electronic device can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN) and / or public networks, such as the Internet) via a network adapter. The network adapter communicates with other modules of the electronic device via a bus. The processor executes various functional applications and data processing by running programs stored in memory, such as implementing the variable fractional delay filter based on symmetric structure and weighted least squares method provided in the above embodiments of the present invention.
[0034] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the variable fractional delay filter based on symmetric structure and weighted least squares method as provided in the embodiments of the present invention.
[0035] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, system, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, system, or device.
[0036] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit programs for use by or in conjunction with an instruction execution system, system, or device.
[0037] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.
[0038] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
[0039] The above are all preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Therefore, all equivalent changes made in accordance with the structure, shape and principle of the present invention should be covered within the scope of protection of the present invention.
Claims
1. A variable fractional delay filter based on a symmetric structure and weighted least squares method, characterized in that, include: The signal parameter pre-calculation unit is used to provide delay parameters for the filter; Symmetric FIR coefficient building blocks are used to compute symmetric FIR coefficient frames. WLS coefficient optimization unit, used to calculate the fixed-point optimization coefficient matrix; The phase-shifting execution unit is used to achieve integer delay for the current signal through the buffer length and fractional delay compensation for the voltage signal through the VFD filter. The two work together to complete the "integer + fractional" joint phase shift. The adaptive calibration and frequency tracking unit is used to calculate the angle difference between voltage and current. The calculated angle difference is added to the original phase shift angle to obtain the updated phase shift angle. When the absolute value of the difference between the current base frequency and the historical base frequency is detected to be greater than the base frequency fluctuation threshold, the integer part of the delay, the fractional delay, and the current path signal buffer length are updated synchronously.
2. The variable fractional delay filter based on symmetric structure and weighted least squares method according to claim 1, characterized in that, Providing delay parameters for the filter involves first determining the sampling rate of the voltage and current signals, the initial value of the fundamental frequency, the initial phase shift angle, and the order of the VFD filter. Then, the delay length is calculated based on the formula constructed from the initial phase shift angle, sampling rate, and fundamental frequency. This delay length is then split into an integer part obtained by rounding down and a fractional part of the delay length minus the integer part. Finally, the buffer length of the current path is determined based on the sum of the VFD filter order and the integer part.
3. The variable fractional delay filter based on symmetric structure and weighted least squares method according to claim 1, characterized in that, The calculation of the symmetric FIR coefficient framework involves first determining the order of the VFD filter coefficient polynomial and the fractional delay range as the basic input conditions for coefficient construction. Then, the coefficient symmetry relationship is derived and the total number of coefficients is reduced using this relationship. Subsequently, invalid coefficients are further eliminated based on the conclusion that coefficients at specific positions are 0 when the polynomial order is odd. Finally, a symmetric FIR coefficient framework containing the positions and sign correlations of non-zero coefficients is formed.
4. The variable fractional delay filter based on symmetric structure and weighted least squares method according to claim 1, characterized in that, The calculation of the fixed-point optimization coefficient matrix includes: first, determining the target frequency response range and the normalized value of the passband cutoff frequency to ensure the phase shift direction, accuracy, and stable frequency response within the passband of the filter; then, using the weighted square integral of the error between the actual and target frequency responses as the optimization objective to ensure that the optimization revolves around the optimal phase shift accuracy within the passband; subsequently, solving the weighted least squares problem and adjusting the coefficients to make the filter frequency response approximate the target frequency response to obtain the coefficient matrix; and finally, performing fixed-point processing on the coefficient matrix to adapt it to the hardware without requiring an additional floating-point arithmetic module.
5. The variable fractional delay filter based on symmetric structure and weighted least squares method according to claim 1, characterized in that, The method for achieving integer delay of current signal through buffer length and fractional delay compensation of voltage signal through VFD filter, with both working together to complete "integer + fractional" joint phase shift, includes: first, acquiring delay parameters, the obtained optimized coefficient matrix, and real-time voltage and current signals; inputting the current signal into a buffer module with a preset buffer length to achieve integer delay; inputting the voltage signal into a VFD filter loaded with the optimized coefficient matrix and combining it with fractional delay parameters for fractional delay compensation; after processing the two signals during compensation, they are synchronously integrated to achieve the preset phase shift relationship, and finally completing the joint phase shift operation.
6. The variable fractional delay filter based on symmetric structure and weighted least squares method according to claim 1, characterized in that, The calculation of the angle difference between voltage and current involves first acquiring real-time active and reactive power data and defining the system's rated power as the reference value for angle difference calculation. Then, based on the numerical relationship between real-time active and reactive power, the angle difference is derived. The amplitude gain is first calculated using the ratio of rated power to real-time active power to eliminate the influence of the ratio difference. Then, taking advantage of the characteristic that when the angle difference is small, its tangent is approximately equal to itself and equal to the ratio of reactive power to active power, combined with amplitude gain correction, the angle difference between voltage and current is finally obtained.
7. The variable fractional delay filter based on symmetric structure and weighted least squares method according to claim 1, characterized in that, The calculated angle difference is added to the original phase shift angle to obtain the updated phase shift angle. When the fundamental frequency fluctuation exceeds the threshold, the relevant parameters are updated synchronously. This includes first summing the calculated angle difference with the original phase shift angle to obtain the updated phase shift angle to correct the phase shift deviation. After the update, the trigger signal parameter pre-calculation unit and the WLS coefficient optimization unit recalculate the delay parameters and the optimization coefficient matrix, respectively. At the same time, the absolute value of the current and historical fundamental frequency difference is monitored in real time and compared with the fundamental frequency fluctuation threshold. When the absolute value exceeds the threshold, the parameter update process is started. The integer part of the delay, the fractional delay, and the current path signal buffer length are recalculated. The updated parameters immediately replace the original parameters and are applied to the subsequent process.
8. An electronic device, characterized in that, It includes one or more processors or processing units, and the processor implements the variable fractional delay filter based on symmetric structure and weighted least squares method as described in claim 1 by running a program stored in memory.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the variable fractional delay filter based on symmetric structure and weighted least squares method as described in claim 1.