Intermediate-frequency circuit common-mode level adjusting method and system for wireless transmitting chip

Abstract

The invention relates to the technical field of transmitter circuits, and discloses an intermediate-frequency circuit common-mode level adjusting method and system for a wireless transmitting chip, and the method is based on a digital-to-analog conversion module and an intermediate-frequency circuit module, and comprises the steps: connecting terminals of the digital-to-analog conversion module and the intermediate-frequency circuit module through resistors with opposite polarities; internal terminals of the intermediate-frequency circuit operational amplifier are also connected through the resistor in opposite polarities; adjustable current is injected into the input terminal of the operational amplifier, a third common-mode level is regulated, and the difference value between the first common-mode level and the third common-mode level of the digital-to-analog conversion module is made to be within the preset range. According to the invention, the problem of level mismatching between modules is effectively solved, the degree of freedom of device model selection is greatly improved, and the system integration and debugging cost is reduced.

Description

Technical Field

[0001] This application relates to the technical field of transmitter circuits, and in particular to a method and system for adjusting the common-mode level of an intermediate frequency circuit for a wireless transmitter chip. Background Technology

[0002] In large-scale wireless transmitter systems, to reduce system design complexity and facilitate debugging, not all modules are typically integrated; instead, discrete modules are used, such as a DAC + intermediate frequency module + radio frequency module. These modules require compatible and standardized interfaces, but inconsistencies between interfaces from different manufacturers inevitably arise, limiting the system integrator's freedom of choice when selecting components.

[0003] The core function of a large-scale wireless transmitter system is to efficiently transmit baseband signals after processing. Its basic principle is as follows: the digital signal output by the baseband processing unit is first converted into an analog signal by a digital-to-analog converter (DAC), then passed to the intermediate frequency module for filtering, amplification, and frequency conversion, and then sent to the radio frequency module to complete up-conversion to the radio frequency band and power amplification. Finally, the signal is radiated into space by the antenna to achieve long-distance signal transmission.

[0004] In the design of large-scale wireless transmitter systems, integrating all functional modules would significantly increase the system design complexity due to complex signal coupling between modules and mutual interference during debugging, and would also make fault location difficult during later maintenance. To reduce design complexity and improve debugging convenience, the industry typically adopts a discrete module approach, such as using an independent DAC module to perform digital-to-analog conversion, an intermediate frequency module to handle intermediate frequency signal processing, and an RF module to generate and amplify RF signals, with each module performing its specific function. When assembling a system from discrete modules, interface matching and parameter standardization between modules are crucial, directly impacting signal transmission quality and overall system performance. It's essential to ensure that the output signal of one module is compatible with the input requirements of the next. However, discrete modules designed and manufactured by different companies often differ in key parameters such as common-mode levels, making unified compatibility difficult. This forces system integrators to expend considerable effort searching for modules with matching parameters, significantly limiting the range of options and increasing the difficulty and cost of system integration. Summary of the Invention

[0005] To reduce the inconsistency in interface levels between the DAC module and the intermediate frequency module, this application provides a method and system for adjusting the common-mode level of the intermediate frequency circuit for a wireless transmitter chip.

[0006] In a first aspect, this application provides a method for adjusting the common-mode level of an intermediate frequency circuit for a wireless transmitter chip, employing the following technical solution: A common-mode level adjustment method for intermediate frequency circuits in wireless transmitter chips, based on a digital-to-analog converter module and an intermediate frequency circuit module, includes the following steps: The digital-to-analog converter module has an output interface, which includes a first output terminal and a second output terminal. The operating level of the output interface is a first common-mode level. The intermediate frequency circuit module has an input interface, which includes a first input terminal and a second input terminal. The input interface is the input terminal of the operational amplifier in the intermediate frequency circuit module. The operating level of the input terminal is a second common-mode level. The first common-mode level and the second common-mode level have different level ratings. The first output terminal is used to be electrically connected to the first input terminal through the first input resistor, and the polarity of the first output terminal is opposite to that of the first input terminal; the second output terminal is used to be electrically connected to the second input terminal through the second input resistor, and the polarity of the second output terminal is opposite to that of the second input terminal. The operational amplifier in the intermediate frequency circuit module has an output terminal, which includes a first internal terminal and a second internal terminal. The first input terminal is electrically connected to the first internal terminal through a first internal resistor, and the polarity of the first input terminal is opposite to that of the first internal terminal. The second input terminal is electrically connected to the second internal terminal through a second internal resistor, and the polarity of the second input terminal is opposite to that of the second internal terminal. A first current is injected into the first input terminal, and a second current is injected into the second input terminal, such that the operating level at the endpoints of the first and second input resistors used for electrical connection with the output interface is a third common-mode level; the level difference between the first common-mode level and the third common-mode level is less than a preset level range.

[0007] By adopting the above technical solution, by injecting adjustable first and second currents into the first and second input terminals of the operational amplifier of the intermediate frequency circuit module, respectively, the third common-mode level is precisely controlled, so that the difference between the first common-mode level and the third common-mode level of the output interface of the digital-to-analog converter module is controlled within a preset range. This effectively solves the problem of inconsistent common-mode levels between the interfaces of discrete digital-to-analog converter modules and intermediate frequency circuit modules from different manufacturers, greatly improves the system integrator's freedom of component selection, and reduces the difficulty and cost of system integration.

[0008] Optionally, the method further includes the following step: the first common-mode level is the same as the third common-mode level.

[0009] By adopting the above technical solution, the mismatch between the common mode levels of the digital-to-analog converter module and the adjusted third common mode level can be made completely consistent, thus eliminating the potential risk of mismatch between the common mode levels of the two interfaces. This allows the level adaptation during signal transmission to reach the optimal state, further reducing the risk of signal distortion. At the same time, it greatly simplifies the level debugging process during system integration, eliminating the need for integrators to consider whether the level difference meets the standard.

[0010] Optionally, the method further includes the following steps: The first difference is calculated as the difference between the operating level of the first output terminal and the operating level of the first input resistance and the terminal used for electrical connection with the output interface. The adjustment range of the first current is adjusted according to the positive correlation of the first difference. The larger the first difference, the larger the adjustment range of the first current; the smaller the first difference, the smaller the adjustment range of the first current.

[0011] By adopting the above technical solution, the larger the difference, the larger the adjustment range, quickly reducing significant level differences; the smaller the difference, the smaller the adjustment range, avoiding excessive adjustment that could cause level fluctuations. Simultaneously, it achieves individual and precise control of the channel corresponding to the first terminal, without interfering with the level adaptation process of other terminals, while also specifically addressing the level mismatch problem of a single channel.

[0012] Optionally, the method further includes the following steps: The adjustment range of the first current and the second current is positively correlated with the absolute value of the level difference between the first common-mode level and the third common-mode level; the larger the absolute value of the level difference, the larger the adjustment range of the first current and the second current; the smaller the absolute value of the level difference, the smaller the adjustment range of the first current and the second current.

[0013] By adopting the above technical solution, the larger the difference, the larger the adjustment range to quickly reduce significant level differences, and the smaller the difference, the smaller the adjustment range to finely adjust and avoid level fluctuations. This achieves coordinated control of the corresponding channels of the two terminals, which not only ensures the consistency and synchronization of dual-channel level adaptation and avoids channel imbalance problems that may be caused by single-channel adjustment, but also efficiently and smoothly promotes the overall interface common-mode level to approach the target value.

[0014] Optionally, the method further includes the following steps: When the first current remains constant, increasing the level difference between the second common-mode level and the third common-mode level increases the number of first input resistors connected in series or decreases the number of first input resistors connected in parallel. When the first current remains constant, and the level difference between the second common-mode level and the third common-mode level is reduced, the number of first input resistors connected in series is reduced or the number of first input resistors connected in parallel is increased.

[0015] By adopting the above technical solution, under the premise that the first current remains unchanged, the number of series and parallel connections of the first input resistors can be adjusted in a targeted manner. When the level difference increases, the number of series connections is increased or the number of parallel connections is decreased; when the level difference decreases, the number of series connections is decreased or the number of parallel connections is increased. This approach does not require modification of the core current injection main regulation strategy, and can dynamically adapt to changes in the difference between the first common-mode level and the second common-mode level through convenient adjustment of the number of resistors, effectively avoiding interface adaptation imbalance caused by level difference fluctuations. At the same time, the series and parallel adjustment of resistors is simple to operate, especially the parallel method, which is easier to implement without complex circuit modifications, and can quickly respond to the level difference adaptation requirements in different scenarios.

[0016] Optionally, the method further includes the following steps: The second difference is calculated as the difference between the operating level of the second output terminal and the second input resistance and the operating level at the endpoint used for electrical connection with the output interface. The adjustment range of the second current is adjusted according to the second difference: the larger the second difference, the larger the adjustment range of the second current; the smaller the second difference, the smaller the adjustment range of the second current.

[0017] By adopting the above technical solution, the larger the difference, the greater the adjustment range, quickly reducing significant level differences; the smaller the difference, the smaller the adjustment range, avoiding over-adjustment and level fluctuations, thus achieving individual and precise control of the corresponding channel of the second terminal. At the same time, it does not interfere with the adjustment process of the first terminal, and can specifically solve the level mismatch problem of the second channel, allowing the two channels to be optimized independently, effectively improving the balance and accuracy of interface level adaptation.

[0018] Optionally, the method further includes the following steps: When the second current remains constant, increasing the level difference between the second common-mode level and the third common-mode level increases the number of series-connected second input resistors or decreases the number of parallel-connected second input resistors. When the second current remains constant, reducing the level difference between the second common-mode level and the third common-mode level reduces the number of second input resistors connected in series or increases the number of second input resistors connected in parallel.

[0019] By adopting the above technical solution, when the difference between the second common-mode level and the third common-mode level increases, the number of series connections is increased or the number of parallel connections is decreased to enhance the resistance regulation and avoid mismatch; when the difference decreases, the number of series connections is decreased or the number of parallel connections is increased to slow down the adjustment range and prevent over-adjustment interference.

[0020] Optionally, the method further includes the following steps: Calculate the first fluctuation value of the first current and the second fluctuation value of the second current within a preset set time period; The fluctuation ratio is calculated based on the first fluctuation value and the second fluctuation value. The volatility difference value is calculated based on the volatility ratio and the preset reference ratio; The preset level range between the first common-mode level and the third common-mode level is adjusted based on the negative correlation between the absolute values ​​of the fluctuation differences.

[0021] By adopting the above technical solution, when the fluctuation difference is large, the level range is widened to avoid adaptation oscillation caused by frequent adjustments; when the fluctuation difference is small, the level range is tightened to improve the common mode level matching accuracy.

[0022] Secondly, this application provides a common-mode level adjustment system for intermediate frequency circuits of wireless transmission chips, employing the following technical solution: A common-mode level adjustment system for an intermediate frequency circuit of a wireless transmitter chip includes a processor, wherein the processor performs the steps of the common-mode level adjustment method for an intermediate frequency circuit of a wireless transmitter chip as described in any of the preceding claims.

[0023] In summary, this application includes at least one of the following beneficial technical effects: By injecting adjustable first and second currents into the first and second input terminals of the intermediate frequency circuit operational amplifier, the third common-mode level is precisely controlled, so that the difference between the first common-mode level and the third common-mode level of the digital-to-analog converter module output interface is controlled within a preset range. This effectively solves the problem of inconsistent common-mode levels between discrete digital-to-analog converter modules and intermediate frequency circuit modules from different manufacturers, significantly improving the system integrator's freedom in selecting components and reducing the difficulty and cost of system integration. At the same time, combined with single-channel differential positive correlation adjustment, dual-channel collaborative control, resistor series and parallel auxiliary adjustment, and dynamic optimization of the level range based on current fluctuations, the accuracy and stability of level adaptation are further guaranteed, signal distortion and fluctuations are reduced, and different module characteristics and complex operating conditions are adapted. Attached Figure Description

[0024] Figure 1 This is a circuit diagram of the digital-to-analog converter module, intermediate frequency module, and radio frequency module used in wireless transmitter chips. Detailed Implementation

[0025] The embodiments of this application are described in detail below, and examples of the embodiments are shown in the accompanying drawings.

[0026] In the description of this specification, the references to "certain embodiments," "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples" refer to specific features, structures, materials, or characteristics described in connection with the described embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0027] This application discloses a method for adjusting the common-mode level of an intermediate frequency circuit for a wireless transmitter chip, referring to... Figure 1 Based on a digital-to-analog converter module and an intermediate frequency circuit module, the method includes the following steps: The BLOCK_A digital-to-analog converter module is an independent module with an output interface. The output interface includes a first output terminal (negative output port - VCOM_P_DAC) and a second output terminal (positive output port - VCOM_N_DAC). The operating level of the output interface is the first common-mode level. The BLOCK_B module is an intermediate frequency (IF) circuit module, which incorporates an operational amplifier BUF1. The IF circuit module also has an input interface, including a first input terminal (positive input port - VCOM_P) and a second input terminal (negative input port - VCOM_N). The input interface is the input terminal of the operational amplifier BUF1 in the IF circuit module, and the operating level of the input terminal is the second common-mode level. The first and second common-mode levels have different voltage levels, resulting in a natural compatibility difference.

[0028] The first output terminal is electrically connected to the first input terminal via a first input resistor Rp_2, and the current through the first input resistor Rp_2 is Ip_2. The polarity of the first output terminal is opposite to that of the first input terminal. The second output terminal is electrically connected to the second input terminal via a second input resistor Rn_2, and the current through the second input resistor Rn_2 is In_2. The polarity of the second output terminal is opposite to that of the second input terminal.

[0029] In the intermediate frequency circuit module, operational amplifier BUF1 has an output terminal, which includes a first internal terminal and a second internal terminal. The first input terminal is electrically connected to the first internal terminal through a first internal resistor Rp_1, and the current in the first internal resistor Rp_1 is Ip_1. The polarity of the first input terminal is opposite to that of the first internal terminal. The second input terminal is electrically connected to the second internal terminal through a second internal resistor Rn_1, and the current in the second internal resistor Rn_1 is In_1. The polarity of the second input terminal is opposite to that of the second internal terminal. The operating level of the first output terminal of the digital-to-analog converter module BLOCK_A is VCOM_P_DAC, and the operating level of the first input resistor Rp_2 connected to the output interface terminal (i.e., the end of Rp_2 closer to BLOCK_A) is VCOM_P_BUF1.

[0030] A first current ICOM_P is injected into the first input terminal, and a second current ICOM_N is injected into the second input terminal, so that the working level at the endpoints of the first input resistor Rp_2 and the second input resistor Rn_2 used for electrical connection with the output interface is the third common-mode level; the level difference between the first common-mode level and the third common-mode level is less than a preset level range.

[0031] Inject currents ICOM_P and ICOM_N into the two input terminals of the BUF1 operational amplifier in BLOCK_B, respectively. When the common-mode level flows across the input resistor of BUF1, the common-mode level at the interface between BUF1 and DAC will change, thus matching the voltage interface requirements between the two well.

[0032] ICOM_P = Ip_1 + Ip_2 (1) ICOM_N = In_1 + In_2 (2) VCOM_P_BUF1=Ip_2×Rp_2+VCOM_P (3) VCOM_N_BUF1=In_2×Rn_2+VCOM_N (4) For operational amplifiers, under their own feedback mechanism, the common-mode levels at their input ports are equal, therefore: VCOM_P=VCOM_N=VCOM (5) As can be seen from the expressions in formulas (1) to (5), the values ​​of VCOM_P_BUF1 and VCOM_N_BUF1 can be changed by adjusting the values ​​of ICOM_P and ICOM_N.

[0033] By injecting adjustable first and second currents into the first and second input terminals of the operational amplifier in the intermediate frequency circuit module, respectively, the third common-mode level is precisely controlled. This ensures that the difference between the first common-mode level and the third common-mode level at the output interface of the digital-to-analog converter module is controlled within a preset range. This effectively solves the problem of inconsistent common-mode levels between discrete digital-to-analog converter modules and intermediate frequency circuit modules from different manufacturers, significantly improving the system integrator's freedom in selecting components and reducing the difficulty and cost of system integration.

[0034] In one implementation, the first common-mode level is the same as the third common-mode level. By making the first common-mode level of the digital-to-analog converter module completely consistent with the adjusted third common-mode level, the potential mismatch between the interface common-mode levels can be eliminated, allowing the level adaptation during signal transmission to reach the optimal state, further reducing the risk of signal distortion. At the same time, it greatly simplifies the level debugging process during system integration, so that integrators do not need to consider whether the level difference meets the standard.

[0035] In this embodiment, in order to achieve the independence of the first channel level adjustment, the method further includes the following steps: The high-precision voltage sampling unit built into the intermediate frequency circuit module BLOCK_B collects the operating level VCOM_P_DAC of the first output terminal of the digital-to-analog converter module BLOCK_A and the operating level VCOM_P_BUF1 of the electrical connection point between the first input resistor Rp_2 and the output interface (i.e., the end of Rp_2 closer to BLOCK_A) in real time. The sampling unit transmits the two level signals to the signal processing unit built into the module. The unit calculates the first difference ΔV1 according to the formula: First difference ΔV1=|VCOM_P_DAC-VCOM_P_BUF1|, and the calculation result is synchronously fed back to the current regulation and control unit.

[0036] In this embodiment, the current regulation control unit pre-stores amplitude regulation rules based on the first difference. According to the logic that the difference is positively correlated with the regulation amplitude, combined with the circuit response characteristics and level adaptation requirements, it divides the regulation into three levels: When the first difference ΔV1 > 0.4V, in a scenario of significant level difference, the external precision current source is controlled to set the adjustment range of the first current ICOM_P to 0.15mA / step. By adjusting the current by a large range, the level difference between VCOM_P_DAC and VCOM_P_BUF1 is quickly reduced, the adaptation efficiency is improved, and signal transmission distortion is avoided due to excessive difference. When 0.1V≤ΔV1≤0.4V, in a medium level difference scenario, the adjustment range of the first current is adjusted to 0.04mA / step to balance the adjustment efficiency and level stability. This avoids level overshoot due to excessive amplitude and steadily promotes level adaptation, thus shortening the debugging cycle. When ΔV1 < 0.1V, in scenarios with minute level differences, the adjustment range of the first current is reduced to 0.008mA / step. Precise level alignment is achieved through fine-tuning, preventing level fluctuations caused by over-adjustment and ensuring that the level of the first channel remains stable within the target range.

[0037] This step utilizes a dedicated voltage sampling channel, an independent signal processing link, and a separate current regulation control branch to achieve individual control of the channel corresponding to the first terminal. During the first current adjustment process, the voltage sampling, difference calculation, and second current regulation of the second channel all operate independently without interference, effectively avoiding the influence of single-channel adjustment on the level state of the other channel.

[0038] In this embodiment, efficient overall level adaptation is achieved through dual-channel collaborative control logic. The specific method also includes the following steps: The dual-channel synchronous voltage sampling unit built into the intermediate frequency circuit module BLOCK_B collects the first common-mode level VCOM_A from the output interface of the digital-to-analog converter module BLOCK_A, and the third common-mode level VCOM_C formed by the connection points of the first and second input resistors and the output interface in real time. After the sampled signals are transmitted to the core control unit, the overall level difference ΔV_total=|VCOM_A-VCOM_C| is calculated. The absolute value of the level difference is calculated in real time, and the calculation result serves as the basis for the dual current adjustment amplitude, ensuring that the adjustment command and the actual level deviation are accurately matched.

[0039] The core control unit pre-stores three levels of amplitude adjustment rules. Based on the principle that the absolute value of the level difference is positively correlated with the adjustment amplitude, and combined with the requirements of circuit response speed and level stability, the parameters are optimized. When ΔV_total>0.5V, in scenarios with significant overall level deviation, the external precision current source is controlled to set the adjustment range of the first current ICOM_P and the second current ICOM_N to 0.18mA / step. Through dual-channel synchronous large-scale adjustment, the overall level difference is quickly reduced, avoiding signal transmission link distortion due to excessive deviation, and greatly improving adaptation efficiency. When 0.08V≤ΔV_total≤0.5V, in a medium overall level deviation scenario, the dual current regulation amplitude is synchronously adjusted to 0.05mA / step. This ensures the adjustment progress while avoiding level overshoot or fluctuations caused by excessive amplitude, thus achieving a balance between efficiency and stability. When ΔV_total < 0.08V, in scenarios with small overall level deviation, the dual current adjustment amplitude is synchronously reduced to 0.006mA / step. Through dual-channel fine-tuning, precise level alignment is achieved, preventing level oscillation caused by over-adjustment and ensuring that the overall common-mode level stably approaches the target value.

[0040] To ensure consistent control, the adjustment commands issued by the core control unit are simultaneously transmitted to the current drive branches corresponding to ICOM_P and ICOM_N, with no time difference in the adjustment actions of the two currents. During the adjustment process, the current detection module provides real-time feedback on the actual changes in the two currents. If a synchronization deviation occurs, the control unit immediately triggers a calibration command to ensure that the two currents always maintain a consistent adjustment rhythm, avoiding the channel level imbalance problem caused by the "one fast and one slow" that may occur when adjusting a single channel individually.

[0041] To further optimize the regulation of current injection, the method also includes the following steps: The high-precision differential voltage detection unit built into the intermediate frequency circuit module BLOCK_B is used to acquire the second common-mode level VCOM_B (operational amplifier input level) and the third common-mode level VCOM_C (input resistor and output interface connection level) in real time, and calculate the level difference between them ΔV_BC=|VCOM_B-VCOM_C|.

[0042] To avoid circuit instability caused by frequent adjustments, a preset adjustment trigger threshold is established: when the change in ΔV_BC exceeds ±0.05V (i.e., ΔV_BC increases or decreases by more than 0.05V compared to its initial stable value), the series-parallel connection quantity of the first input resistor Rp_2 is adjusted; if the change does not reach the threshold, the current resistor configuration is maintained to ensure the stability of the circuit operation. Simultaneously, the first current ICOM_P remains unchanged at its initial calibration value, for example, fixed at 0.2mA, without altering the core current injection strategy, thus avoiding secondary adaptation deviations caused by current adjustments.

[0043] When an increase in ΔV_BC is detected, for example, from the initial 0.1V to 0.3V, exceeding the trigger threshold, the total resistance of Rp_2 needs to be increased to adapt to the change in level difference. There are two possible implementation methods: Increasing the number of series resistors: Rp_2 adopts a modular series design, initially configured with one 1kΩ resistor, for a total resistance Rp_total = 1kΩ. At this point, an additional 1kΩ resistor of the same specification can be connected through the circuit's reserved series interface, increasing the total resistance to 2kΩ. If ΔV_BC continues to increase, such as reaching 0.5V, the number of series resistors can be further increased to three, reaching a total resistance of 3kΩ. Increasing the resistance indirectly reduces the impact of current on the voltage level, suppressing further expansion of ΔV_BC.

[0044] Reducing the number of parallel resistors: Rp_2 is initially configured with two 1kΩ resistors in parallel, for a total resistance of Rp_total = 500Ω. When ΔV_BC increases, one parallel resistor can be removed using a pluggable design, increasing the total resistance to 1kΩ. If a further increase in resistance is required, all parallel resistors can be removed, leaving only one 1kΩ resistor, for a total resistance of 1kΩ. This method does not require modification of the series connection; the resistance can be adjusted simply by adding or removing parallel branches, making operation more convenient and not affecting the connection stability of other nodes in the circuit.

[0045] When a decrease in ΔV_BC is detected, for example, from the initial 0.2V to 0.03V, exceeding the trigger threshold, it is necessary to adapt by reducing the total resistance of Rp_2. This also corresponds to two implementation methods: Reduce the number of series resistors: If Rp_2 currently consists of three 1kΩ resistors in series, with a total resistance of 3kΩ, one series resistor can be removed to reduce the total resistance to 2kΩ; if ΔV_BC continues to decrease, such as to 0.01V, it can be further removed until only one 1kΩ resistor remains, with a total resistance of 1kΩ. Reducing the resistance enhances the sensitivity of the level response and avoids level adaptation lag caused by excessive resistance.

[0046] Increasing the number of parallel resistors: If Rp_2 currently has one 1kΩ resistor, with a total resistance of 1kΩ, you can connect one more 1kΩ resistor of the same specification through the parallel interface to reduce the total resistance to 500Ω. If a further reduction is needed, you can connect two parallel resistors to reduce the total resistance to 333Ω. This method quickly reduces the total resistance by increasing the current sharing of parallel branches. Furthermore, the parallel interface uses a standardized design, supports hot-swapping, and can be adjusted quickly in a power-off state without the need for complex tools or circuit modifications.

[0047] Rp_1 is also an adjustable resistor, which can be implemented by connecting it in series or in parallel to keep the amplification factor of the operational amplifier constant.

[0048] Using the above method, the first current remains constant, avoiding the tedious process of recalibrating current parameters and protecting the debugging results of the core adjustment strategy. The series and parallel resistor adjustment is achieved simply by adding or removing standardized resistor modules, without requiring modification of circuit wiring, soldering, or PCB redesign. The parallel method, in particular, is simple to operate due to ample interface space. From the adaptation logic perspective, the total resistance value is positively correlated with the level difference: when ΔV_BC increases, increasing the resistance value reduces the rate of level change, avoiding adaptation imbalance; when ΔV_BC decreases, decreasing the resistance value increases the level response speed, ensuring accurate adaptation. This design can quickly respond to level difference fluctuations in different scenarios, such as VCOM_B drift caused by module aging and VCOM_C fluctuations caused by changes in ambient temperature, effectively broadening the method's adaptability range while reducing the difficulty and cost of system debugging and subsequent maintenance.

[0049] This step focuses on the independent and precise control of the second channel. Through differential-driven amplitude adjustment logic, it optimizes the level of the corresponding channel of the second terminal. The specific method also includes the following steps: The intermediate frequency circuit module BLOCK_B is a dedicated high-precision voltage sampling unit configured for the second channel. It collects the working level VCOM_N_DAC of the second output terminal of the digital-to-analog converter module BLOCK_A in real time, as well as the working level VCOM_N_BUF1 of the electrical connection point between the second input resistor Rn_2 and the output interface (i.e., the end of Rn_2 closer to BLOCK_A).

[0050] The sampling unit transmits the two level signals to an independent signal processing branch to avoid interference with the first channel signal. Based on the formula: Second Difference ΔV2 = |VCOM_N_DAC - VCOM_N_BUF1|, the second difference ΔV2 is calculated in real time. The calculation result is synchronously fed back to the second dedicated current adjustment control unit to ensure the accuracy and real-time nature of the adjustment.

[0051] The second current regulation control unit pre-stores a three-level amplitude regulation rule adapted to the characteristics of the second channel circuit. According to the logic that the second difference is positively correlated with the regulation amplitude, the steps are as follows: When the second difference ΔV2 > 0.4V, in the scenario of significant level difference in the second channel, the external precision current source is controlled to adjust the second current ICOM_N to 0.16mA / step. By adjusting the current by a large margin, the level difference between VCOM_N_DAC and VCOM_N_BUF1 is quickly reduced, avoiding signal transmission distortion in the second channel due to excessive difference, and ensuring the overall signal quality of the dual channels. When 0.1V≤ΔV2≤0.4V, in the medium level difference scenario of the second channel, the adjustment range of the second current is adjusted to 0.045mA / step. While steadily promoting level adaptation, it avoids level overshoot or fluctuation caused by excessive amplitude, balances adjustment efficiency and stability, and shortens the debugging cycle of the second channel. When ΔV2 < 0.1V, in the scenario of a small level difference in the second channel, the adjustment range of the second current is reduced to 0.009mA / step. Through fine-tuning, the level of the second channel is accurately aligned, preventing level oscillation caused by over-adjustment and ensuring that the level of the second channel is stable within the target range.

[0052] The second channel's voltage sampling, difference calculation, and current regulation are all equipped with independent hardware units and signal links, physically isolated and logically independent from the first channel's control system. During the second current adjustment process, the level state and regulation command execution of the first channel are unaffected, avoiding the problem of cross-interference between the two channels.

[0053] The above method can specifically address the potential level deviation issues of the second channel in modules from different manufacturers. For example, when the level of the second output terminal of BLOCK_A is offset while the level of the first output terminal is normal, this step can be used to optimize the second channel independently without additional adjustments to the first channel, allowing both channels to independently complete level adaptation optimization. This not only improves the balance and accuracy of interface level adaptation but also simplifies the troubleshooting and debugging process for single-channel faults.

[0054] As a dedicated auxiliary adjustment strategy for the second channel, while keeping the core current adjustment logic unchanged, it dynamically adapts to level difference fluctuations by flexibly adjusting the number of series and parallel connections of the second input resistors. The specific method includes the following steps: The intermediate frequency circuit module BLOCK_B is an independent differential voltage detection unit configured for the second channel. It acquires the second common-mode level VCOM_B (operational amplifier input level) and the third common-mode level VCOM_C (input resistor and output interface connection level) in real time, and calculates the level difference between the two ΔV_BC2=|VCOM_B-VCOM_C|.

[0055] To avoid circuit oscillations caused by frequent adjustments, a preset adjustment trigger threshold is established: when the change in ΔV_BC2 compared to the initial stable value exceeds ±0.05V, the series-parallel connection quantity of the second input resistor Rn_2 is adjusted; if the change does not reach the threshold, the current resistor configuration is maintained to ensure the stability of the second channel's operating state. Simultaneously, the second current ICOM_N remains unchanged from its initial calibration value, for example, fixed at 0.2mA, without altering the core current injection strategy, thus avoiding secondary adaptation deviations caused by current adjustments.

[0056] When an increase in ΔV_BC2 is detected, for example, from an initial 0.12V to 0.35V, exceeding the trigger threshold, the level difference needs to be suppressed by increasing the total resistance of Rn_2. Specifically, there are two optional implementation methods: Increasing the number of series resistors: Rn_2 adopts a standardized modular series design, initially configured with one 1kΩ resistor, for a total resistance Rn_total = 1kΩ. At this point, an additional 1kΩ resistor of the same specification can be connected through the circuit's reserved standardized series interface, increasing the total resistance to 2kΩ. If ΔV_BC2 continues to increase, such as to 0.55V, the number of series resistors can be further increased to three, reaching a total resistance of 3kΩ. Increasing the resistance indirectly reduces the rate of level change, avoiding mismatch.

[0057] Reducing the number of parallel resistors: Rn_2 is initially configured with two 1kΩ resistors in parallel, for a total resistance of Rn_total = 500Ω. When ΔV_BC2 increases, one parallel resistor can be removed using a plug-in design, increasing the total resistance to 1kΩ. If a further increase in resistance is required, all parallel resistors can be removed, leaving only one 1kΩ resistor, for a total resistance of 1kΩ. This method requires no modification to the series connection, is simple to operate, and does not affect the connection stability of other nodes in the circuit.

[0058] When a decrease in ΔV_BC2 is detected, for example, from an initial 0.22V to 0.03V, exceeding the trigger threshold, the level adaptation sensitivity needs to be improved by reducing the total resistance of Rn_2. This corresponds to two implementation methods: Reduce the number of series resistors: If Rn_2 is currently composed of three 1kΩ resistors in series, with a total resistance of 3kΩ, one series resistor can be removed to reduce the total resistance to 2kΩ; if ΔV_BC2 continues to decrease, such as to 0.01V, it can be further removed until only one 1kΩ resistor remains, with a total resistance of 1kΩ. Reducing the resistance will speed up the level response and avoid adaptation lag caused by excessive resistance.

[0059] Increasing the number of parallel resistors: If Rn_2 currently contains a single 1kΩ resistor with a total resistance of 1kΩ, a second 1kΩ resistor of the same specification can be connected via a standardized parallel interface to reduce the total resistance to 500Ω. For further reduction, two parallel resistors can be connected, lowering the total resistance to 333Ω. This method achieves rapid resistance reduction by adding parallel branches for current sharing. The parallel interface supports hot-swapping during power-off, requiring no complex tools or circuit modifications, and adjustments can be completed quickly.

[0060] Rn_1 is also an adjustable resistor, which can be implemented by connecting it in series or in parallel to keep the amplification factor of the operational amplifier constant.

[0061] Using the above method, the second current remains fixed, eliminating the need to recalibrate the core current parameters and protecting the debugging results of the main regulation strategy. The series-parallel adjustment of Rn_2 is only for the second channel and is completely independent of the resistor configuration of the first channel, avoiding cross-interference between the two channels. From the perspective of adaptation logic, the total resistance of Rn_2 is positively correlated with ΔV_BC2: when ΔV_BC2 increases, increasing the resistance can suppress the level difference expansion; when ΔV_BC2 decreases, decreasing the resistance can avoid over-adaptation. This design can quickly respond to level difference fluctuations in the second channel, such as VCOM_B drift caused by module aging and VCOM_C fluctuations caused by changes in ambient temperature, without modifying the core circuit structure. It is convenient to operate and low in cost, further broadening the adaptability of the method to complex operating conditions, while reducing the difficulty of later system maintenance.

[0062] In this embodiment, the preset level range is optimized by dynamically monitoring the current fluctuation state, thereby achieving an intelligent balance between adaptation accuracy and system stability. The specific implementation process is as follows: The preset duration is set to 10ms, which balances data reliability and response time; it can collect enough current samples to reflect the real fluctuation state, while avoiding adjustment lag due to excessive duration. The preset reference ratio k_ref=1.0 corresponds to the ideal state of complete synchronization of the current fluctuations of the two channels, that is, the stability of the first current and the second current is consistent. The initial preset level range is ±0.1V, that is, the difference between the first common-mode level VCOM_A and the third common-mode level VCOM_C must satisfy |VCOM_A-VCOM_C|<0.1V, which serves as the basic adaptation standard; A dual-channel synchronous current detection module is configured, specifically for acquiring real-time data of the first current ICOM_P and the second current ICOM_N, to ensure the accuracy of fluctuation detection.

[0063] Within a preset 10ms duration, the current detection module synchronously collects current data of ICOM_P and ICOM_N at a sampling frequency of 10kHz, collecting 100 sample points per channel, totaling 10ms × 10kHz = 100 samples.

[0064] The first fluctuation value σ1 is calculated by the signal processing unit using the standard deviation of 100 sample points of ICOM_P. The formula is σ1=√[Σ(ICOM_Pi-ICOM_Pavg)² / 100], where ICOM_Pi is a single sample value, ICOM_Pavg is the average value of ICOM_P within 10ms, and σ1 reflects the severity of the fluctuation of the first current. The second fluctuation value σ2: The standard deviation of the sample points of ICOM_N is calculated using the same operation logic, that is, σ2=√[Σ(ICOM_Ni-ICOM_Navg)² / 100]. σ2 reflects the severity of the fluctuation of the second current.

[0065] The signal processing unit performs two operations sequentially according to preset logic, providing a basis for level range adjustment: Calculate the fluctuation ratio k: k = σ1 / σ2. If σ2 is 0, there is theoretically no fluctuation, so k = 1.0 by default. This ratio directly reflects the consistency of the current fluctuations in the two channels. The closer k is to 1.0, the more synchronized the fluctuations in the two channels are. Calculate the fluctuation difference value Δk: Δk = |k - k_ref|, which is the absolute difference between the fluctuation ratio and the reference ratio; the larger Δk is, the more significant the difference in current fluctuation between the two channels, and the weaker the system stability; the smaller Δk is, the more synchronized the fluctuations of the two channels, and the more stable the system state.

[0066] The core control unit follows the adjustment rule that "the absolute value of the fluctuation difference is negatively correlated with the level range," and dynamically adjusts the preset level range in three levels to ensure the adaptation effect. When Δk > 0.3, significant fluctuation differences occur, indicating inconsistent current fluctuations in the two channels and weak system stability. In this case, the preset level range is widened from ±0.1V to ±0.2V. By expanding the allowable level difference range for the adapter, frequent adjustments caused by current fluctuations are reduced, adapter oscillations are avoided, and the continuity of signal transmission is ensured. When 0.1≤Δk≤0.3, in moderate fluctuation scenarios: maintain the initial preset level range of ±0.1V, and maintain a balance between stability and adaptation accuracy, so as not to reduce the matching quality due to an excessively wide range, nor to cause unnecessary adjustment actions due to an excessively narrow range; When Δk < 0.1, indicating minimal fluctuation differences, it signifies that the dual-channel current fluctuations are synchronized and stable, and the system is in good condition. In this case, the preset level range is tightened from ±0.1V to ±0.05V. By reducing the allowable level difference range, the matching accuracy of VCOM_A and VCOM_C is improved, further reducing the risk of signal distortion.

[0067] Through the above steps, without manual intervention, the current fluctuation status is monitored in real time to dynamically optimize the level range, ensuring that the adjustment strategy always matches the actual operation of the system. From the perspective of adaptation logic, the difference in current fluctuation essentially reflects the collaborative stability of the dual channels and the working status of the modules; large fluctuation differences may stem from factors such as module aging and environmental interference, and widening the level range is a trade-off between moderate accuracy and stability; small fluctuation differences indicate that the system is stable, and tightening the level range is a way to improve accuracy based on stability. This dynamic adjustment method avoids the limitations of fixed level ranges under complex operating conditions, such as oscillation caused by a fixed narrow range or insufficient accuracy caused by a fixed wide range, and further improves the robustness and adaptability of the method. This allows the common-mode level adjustment to cope with complex fluctuation scenarios and achieve high-precision matching under stable operating conditions, thus balancing system reliability and signal transmission quality.

[0068] This application also discloses a common-mode level adjustment system for an intermediate frequency circuit of a wireless transmitter chip, including a processor, wherein the processor performs the steps of the common-mode level adjustment method for an intermediate frequency circuit of a wireless transmitter chip as described in any of the preceding embodiments.

[0069] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A method for adjusting the common-mode level of an intermediate frequency circuit for a wireless transmitter chip, characterized in that, Based on a digital-to-analog converter module and an intermediate frequency circuit module, the method includes the following steps: The digital-to-analog converter module has an output interface, which includes a first output terminal and a second output terminal. The operating level of the output interface is a first common-mode level. The intermediate frequency circuit module has an input interface, which includes a first input terminal and a second input terminal. The input interface is the input terminal of the operational amplifier in the intermediate frequency circuit module. The operating level of the input terminal is the second common-mode level. The level levels of the first common-mode level and the second common-mode level are different. The first output terminal is used to be electrically connected to the first input terminal through the first input resistor, and the polarity of the first output terminal is opposite to that of the first input terminal. The second output terminal is used to be electrically connected to the second input terminal through the second input resistor, and the polarity of the second output terminal is opposite to that of the second input terminal; The operational amplifier in the intermediate frequency circuit module has an output terminal, which includes a first internal terminal and a second internal terminal; the first input terminal is electrically connected to the first internal terminal through a first internal resistor, and the polarity of the first input terminal is opposite to that of the first internal terminal. The second input terminal is electrically connected to the second internal terminal through a second internal resistor, and the polarity of the second input terminal is opposite to that of the second internal terminal. A first current is injected into the first input terminal, and a second current is injected into the second input terminal, such that the operating level at the endpoints of the first and second input resistors used for electrical connection with the output interface is a third common-mode level; The level difference between the first common-mode level and the third common-mode level is less than the preset level range.

2. The method for adjusting the common-mode level of an intermediate frequency circuit for a wireless transmitting chip according to claim 1, characterized in that, The method also includes the following steps: the first common-mode level is the same as the third common-mode level.

3. The method for adjusting the common-mode level of the intermediate frequency circuit for a wireless transmitting chip according to claim 1, characterized in that, The method also includes the following steps: The first difference is calculated as the difference between the operating level of the first output terminal and the operating level of the first input resistance and the terminal used for electrical connection with the output interface. The adjustment range of the first current is adjusted according to the positive correlation of the first difference; the larger the first difference, the larger the adjustment range of the first current. The smaller the first difference, the smaller the adjustment range of the first current.

4. The method for adjusting the common-mode level of an intermediate frequency circuit for a wireless transmitter chip according to claim 1, characterized in that, The method also includes the following steps: The adjustment range of the first current and the second current is adjusted in a positive correlation with the absolute value of the level difference between the first common-mode level and the third common-mode level; the larger the absolute value of the level difference, the larger the adjustment range of the first current and the second current. The smaller the absolute value of the level difference, the smaller the adjustment range of the first and second currents.

5. The method for adjusting the common-mode level of an intermediate frequency circuit for a wireless transmitting chip according to claim 1, characterized in that, The method also includes the following steps: When the first current remains constant, increasing the level difference between the second common-mode level and the third common-mode level increases the number of first input resistors connected in series or decreases the number of first input resistors connected in parallel. When the first current remains constant, and the level difference between the second common-mode level and the third common-mode level is reduced, the number of first input resistors connected in series is reduced or the number of first input resistors connected in parallel is increased.

6. The method for adjusting the common-mode level of an intermediate frequency circuit for a wireless transmitter chip according to claim 1, characterized in that, The method also includes the following steps: The second difference is calculated as the difference between the operating level of the second output terminal and the second input resistance and the operating level at the endpoint used for electrical connection with the output interface. The adjustment range of the second current is adjusted according to the second difference: the larger the second difference, the larger the adjustment range of the second current. The smaller the second difference, the smaller the adjustment range of the second current.

7. The method for adjusting the common-mode level of an intermediate frequency circuit for a wireless transmitter chip according to claim 1, characterized in that, The method also includes the following steps: When the second current remains constant, increasing the level difference between the second common-mode level and the third common-mode level increases the number of series-connected second input resistors or decreases the number of parallel-connected second input resistors. When the second current remains constant, reducing the level difference between the second common-mode level and the third common-mode level reduces the number of second input resistors connected in series or increases the number of second input resistors connected in parallel.

8. The method for adjusting the common-mode level of an intermediate frequency circuit for a wireless transmitter chip according to claim 1, characterized in that, The method also includes the following steps: Calculate the first fluctuation value of the first current and the second fluctuation value of the second current within a preset set time period; The fluctuation ratio is calculated based on the first fluctuation value and the second fluctuation value. The volatility difference value is calculated based on the volatility ratio and the preset reference ratio; The preset level range between the first common-mode level and the third common-mode level is adjusted based on the negative correlation between the absolute values ​​of the fluctuation differences.

9. A common-mode level adjustment system for intermediate frequency circuits of wireless transmitter chips, characterized in that, Includes a processor, wherein the steps of the common-mode level adjustment method for intermediate frequency circuits of a wireless transmitter chip as described in any one of claims 1-8 are executed.

Images