Memory device and forming method thereof

Abstract

The embodiment of the invention discloses a memory device and a forming method thereof. The memory device includes a memory cell formed on a first side of a substrate and powered by a supply voltage; a third metallization layer formed on the first side and including third metal tracks, at least one of the third metal tracks being configured to carry only non-supply signals rather than supply voltages; a fourth metallization layer formed on the first side and including fourth metal tracks, each fourth metal track configured only as a word line; a fifth metallization layer formed on the second side of the substrate and including fifth metal tracks, each of the fifth metal tracks configured to carry a supply voltage or a ground voltage; and a sixth metallization layer formed on the second side and including sixth metal tracks, each sixth metal track configured to carry a supply voltage or a ground voltage.

Description

Technical Field

[0001] Embodiments of this application relate to memory devices and methods of forming the same. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. To a large extent, this increase in integration density stems from the repeated reduction in the size of the smallest components, allowing more components to be integrated into a given area. Summary of the Invention

[0003] According to one aspect of the embodiments of this application, a memory device is provided, comprising: a plurality of memory cells physically formed on a first side of a substrate; peripheral circuitry operatively coupled to the plurality of memory cells and physically formed on the first side of the substrate; a first metallization layer physically formed on the first side of the substrate and including a plurality of first metal rails, each of the plurality of first metal rails extending along a first lateral direction and configured to carry a supply voltage or a ground voltage, the first supply voltage being configured to supply power to the plurality of memory cells; a second metallization layer physically formed on the first side of the substrate and including a plurality of second metal rails, each of the plurality of second metal rails extending along a second lateral direction and configured to be operatively coupled to one or more word lines of the plurality of memory cells; and a third metallization layer physically formed on the first side of the substrate. The substrate comprises: a first metallization layer, and a plurality of third metal rails, each of which extends along a first lateral direction, at least one of which is configured to carry only non-power signals and not power supply voltages; a fourth metallization layer, physically formed on a first side of the substrate, and comprising a plurality of fourth metal rails, each of which extends along a second lateral direction and is configured only as word lines; a fifth metallization layer, physically formed on a second side of the substrate, and comprising a plurality of fifth metal rails, each of which extends along a first lateral direction and is configured to carry power supply voltages or ground voltages; and a sixth metallization layer, physically formed on a second side of the substrate, and comprising a plurality of sixth metal rails, each of which extends along a second lateral direction and is configured to carry power supply voltages or ground voltages.

[0004] According to another aspect of the embodiments of this application, a memory device is provided, comprising: a memory cell powered by a first supply voltage; peripheral circuitry operably coupled to the memory cell and powered by a second supply voltage; a first metal rail and a second metal rail disposed in a first front metallization layer among a plurality of front metallization layers and extending in a first lateral direction, the first metal rail and the second metal rail being configured to respectively carry the first supply voltage and a ground voltage, providing the supply voltage to power the memory cell; and a third metal rail disposed in a second front metallization layer among a plurality of front metallization layers and extending in a second lateral direction, the third metal rail being configured to be operably coupled to the memory cell. The cell has word lines; a fourth metal rail and a fifth metal rail, disposed in a third front metallization layer among a plurality of front metallization layers and extending in a first lateral direction, the fourth metal rail and the fifth metal rail being configured to carry a virtual supply voltage and a ground voltage respectively, selectively providing a virtual supply voltage to power the memory cell; a sixth metal rail, disposed in a first back metallization layer among a plurality of back metallization layers and extending in a first lateral direction, the sixth metal rail being configured to carry a first supply voltage; and a seventh metal rail, disposed in a second back metallization layer among a plurality of back metallization layers and extending in a second lateral direction, the seventh metal rail being configured to carry a first supply voltage.

[0005] According to another aspect of the embodiments of this application, a method for forming a memory device is provided, comprising: forming a memory array on a first side of a substrate, the memory array including a plurality of memory cells powered by a first supply voltage; forming peripheral circuitry on the first side of the substrate, the peripheral circuitry being operatively coupled to the memory array and powered by a second supply voltage different from the first supply voltage; forming a first metallization layer on the first side and over the memory array and the peripheral circuitry, the first metallization layer including a plurality of first metal rails, each of the plurality of first metal rails extending along a first lateral direction and configured to carry the first supply voltage or a ground voltage; forming a second metallization layer on the first side and over the first metallization layer, the second metallization layer including a plurality of second metal rails, each of the plurality of second metal rails extending along a second lateral direction and configured to be operatively coupled to one or more word lines of the plurality of memory cells; A third metallization layer is formed over the first side and the second metallization layer. The third metallization layer includes a plurality of third metal rails, each of which extends along a first lateral direction and is configured to carry only non-power signals and not a first power supply voltage. A fourth metallization layer is formed over the first side and the third metallization layer. The fourth metallization layer includes a plurality of fourth metal rails, each of which extends along a second lateral direction and is configured only as a word line. A fifth metallization layer is formed on the second side of the substrate. The fifth metallization layer includes a plurality of fifth metal rails, each of which extends along a first lateral direction and is configured to carry either a first power supply voltage or a ground voltage. A sixth metallization layer is formed over the second side and the fifth metallization layer. The sixth metallization layer includes a plurality of sixth metal rails, each of which extends along a second lateral direction and is configured to carry either a first power supply voltage or a ground voltage. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 An example block diagram of a memory device according to some embodiments is shown.

[0008] Figure 2 Illustrations are shown according to some embodiments Figure 1 An example circuit diagram of a memory cell of a memory device.

[0009] Figure 3A and Figure 3B Together, we illustrate methods for forming according to some embodiments. Figure 1Example layout of memory devices.

[0010] Figure 4A and Figure 4B Together, we illustrate methods for forming according to some embodiments. Figure 1 Another example layout of the memory device.

[0011] Figure 5A and Figure 5B Together, we illustrate methods for forming according to some embodiments. Figure 1 Another example layout of memory devices.

[0012] Figure 6 Illustrations are shown according to some embodiments Figure 2 Example layout of memory cells.

[0013] Figure 7 The following are examples of methods for manufacturing, according to some embodiments. Figure 1 A flowchart of an example method for a memory device. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0016] Static Random Access Memory (SRAM) is a volatile semiconductor memory device comprising multiple SRAM cells configured to store individual data bits using bistable circuitry without requiring refresh. An SRAM cell (often called a bit cell) stores one bit of information, represented by the logic states of two cross-coupled inverters. Multiple of these bit cells are typically formed as a memory array with rows and columns. Each bit cell in the memory array typically includes connections to a supply voltage and a reference voltage (e.g., ground). Logic signals on the bit lines control the reading and writing of the bit cells, where word lines control the bit lines connected (originally floating) to the inverters, which would otherwise float. Word lines can be coupled to bit cells in rows of the memory array, providing different word lines for different rows. A pair of bit lines can be coupled to each column of bit cells.

[0017] For a bit cell read operation, the corresponding bit line can be precharged high (e.g., to the logic value "1"), and the corresponding word line can be asserted. The resulting value at the bit line can correspond to the logic value of the information bit stored at the bit cell. To write "1" to the bit cell, one of the corresponding bit lines (which can be represented as BL (which can represent "bit line")) can be set to "1", the other line (which can be represented as BLB (which can represent "out-of-phase line")) can be set to "0", and the word line can be asserted. To write a logic low value, BL and BLB can be set to "0" and "1" respectively, and the word line can be asserted. A pair of bit lines BL and BLB can be called a complementary bit line pair. However, it is understood that the values ​​at BL and BLB do not need to be logically complementary to each other; for example, in the read operation described above, both BL and BLB are set to "1".

[0018] To improve memory access performance (e.g., write operations), dual-rail power supply techniques have been proposed. In this power supply method, a first supply voltage (e.g., VDD) powers peripheral circuitry configured to control bit cells, and a second supply voltage (e.g., VDDM) powers the bit cells. Existing memory devices are limited to carrying both supply voltages (VDD and VDDM) via metal tracks formed on the front side of the substrate. For example, multiple first metal tracks formed in a first front-side metallization layer are configured to carry the first supply voltage (VDD), and multiple second metal tracks formed in a second front-side metallization layer are configured to carry the second supply voltage (VDDM). This constraint disadvantageously affects the flexibility of the front-side metal wiring while adhering to the scaling trend of increasing numbers of bit cells in a given area. Therefore, it is understandable that existing memory devices are not entirely satisfactory in some respects.

[0019] This disclosure provides various embodiments of a memory device having a reduced number of front-side metal tracks configured to carry a supply voltage or a ground voltage. In various embodiments, as disclosed herein, the memory device includes a memory array and peripheral circuitry operatively coupled to each other. The memory array includes a plurality of memory cells. The peripheral circuitry is configured to operate or control the memory array, which may include various circuit components such as driver circuitry, input / output circuitry, etc. Each memory cell may be operatively formed by a plurality of first transistors, and the peripheral circuitry may be operatively formed by a plurality of second transistors. These first / second transistors may be formed along a main surface on the front side of a substrate. In some embodiments, the peripheral circuitry may be powered by a first supply voltage (sometimes referred to as VDD), and the memory cell may be powered by a second supply voltage (sometimes referred to as VDDM).

[0020] Unlike existing memory devices, the disclosed memory device may include a plurality of first metal tracks formed on the front side of a substrate and a plurality of second metal tracks formed on the back side of a substrate. By repositioning some of the metal tracks configured to carry a second supply voltage VDDM from the front side to the back side, a significant amount of space on the front side of the substrate for metal wiring can be freed up. This can advantageously reduce capacitive coupling between the front metal tracks of word lines configured as a memory array. Furthermore, in existing memory devices, a plurality of third metal tracks carrying a ground voltage are confined to the front side and located in the same metallization layer as the word lines; these can be repositioned to the back side in the currently disclosed memory device. By repositioning these metal tracks to the back side, word lines with wider widths can be formed, which can advantageously reduce the resistance of these word lines. Therefore, various performance characteristics of the disclosed memory device (e.g., speed, maximum frequency, etc.) can be significantly improved.

[0021] Figure 1 A block diagram of a memory system, circuit, or device 100 according to various embodiments is shown. The memory device 100 is implemented as an integrated circuit. Figure 1 As illustrated in the illustrative example, memory device 100 includes a memory controller 105, a memory array 120, and optional voltage control circuitry 116. Memory array 120 may include a plurality of storage circuits, memory cells, memory bits, or bit cells 125 arranged in a two-dimensional or three-dimensional array. Each memory cell 125 can be accessed via a plurality of access lines (e.g., one or more bit lines BL and at least one word line WL). Memory controller 105 is operatively coupled to memory array 120 to control the operation of memory array 120 (e.g., read operations, write operations). Memory controller 105 is sometimes referred to as peripheral circuitry relative to memory array 120.

[0022] Memory array 120 is a hardware component for storing data. For example, memory array 120 is implemented as a semiconductor memory device. Memory array 120 typically includes a plurality of storage circuits or memory cells 125, each storage circuit or memory cell 125 being configured to store at least one data bit. In some embodiments, memory array 120 includes word lines WL0, WL1…WL J Each word line extends in the first direction, along with bit lines BL0, BL1…BL K Each bit line extends in a second direction. The word line WL and the bit line BL can each be formed as one or more metal tracks or conductive tracks. Each memory cell 125 is operatively connected to at least one corresponding word line WL and at least one pair of corresponding bit lines BL (e.g., each memory cell 125 formed at the intersection of the corresponding word line WL and the corresponding pair of bit lines BL), and can be operated according to the voltage or current passing through the corresponding word line WL and the corresponding bit line BL.

[0023] Each memory cell 125 may include a static random access memory (SRAM) cell. In one embodiment, the memory cell may be implemented as a six-transistor (6T) SRAM cell or other single-port SRAM cell. In another embodiment, the memory cell 125 may be implemented as a seven-transistor (7T) SRAM cell or a two-port SRAM cell. In yet another embodiment, the memory cell 125 may be implemented as an eight-transistor (8T) SRAM cell or other three-port SRAM cell. However, it should be understood that the memory cell 125 may be implemented in any of a variety of other memory configurations while still remaining within the scope of this disclosure.

[0024] Memory controller 105 is a hardware component configured to control the operation of memory array 120. In some embodiments, memory controller 105 includes at least bit line controller 112 and word line controller 114. In various embodiments of this disclosure, each circuit component of memory controller 105 may be powered by a first supply voltage (referred to herein as "VDD"), and memory array 120 may be powered by a second supply voltage (referred to herein as "VDDM"). The first supply voltage VDD may be different from the second supply voltage VDDM.

[0025] For example, word line controller 114 and bit line controller 112 can each be powered by VDD. Word line controller 114 can be configured to provide voltage or current signals to one or more word lines WL. Bit line controller 112 can be configured to provide voltage or current signals to one or more bit lines BL. Bit line controller 112 may also include one or more input / output circuitry (e.g., sense amplifiers, latches, etc.) configured to sense voltage or current read from memory array 120 through one or more bit lines BL. Although not shown, it should be understood that memory controller 105 may include other circuitry components to perform appropriate memory operations, such as address decoders, error correction circuitry, clock generators, etc.

[0026] Bit line controller 112 can be connected to bit line BL of memory array 120, and word line controller 114 can be connected to word line WL of memory array 120. Generally, to write data bits to memory cell 125, word line controller 114 is configured to apply a voltage or current signal (sometimes referred to as a WL signal) on the corresponding word line WL, and bit line controller 112 is configured to apply a voltage or current signal corresponding to the data bit to be stored in memory cell 125 on one of a corresponding pair of bit lines BL. To read data bits from memory cell 125, word line controller 114 is configured to apply a WL signal on the corresponding word line WL, and bit line controller 112 is configured to sense a voltage or current signal present on the corresponding bit line BL corresponding to the data bit stored in memory cell 125. In some other embodiments, memory controller 105 may include a voltage or current signal corresponding to the data bit stored in memory cell 125. Figure 1 The disclosure may include more, fewer, or different components, while still remaining within the scope of this disclosure.

[0027] Voltage control circuitry 116 is a hardware component configured to control the power supplied to memory array 120 and to memory controller (or peripheral circuitry) 105. In some embodiments, voltage control circuitry 116 may include a plurality of first heads and / or a plurality of first feet operably coupled to memory controller 105, and a plurality of second heads and / or a plurality of second feet operably connected to memory array 120. Such heads / feet are typically configured to selectively connect a supply voltage (e.g., VDD, VDDM) or a reference voltage (e.g., ground voltage) to memory array 120 or memory controller 105 based on control, enable, or tracking signals. Heads / feet are sometimes referred to as power gating devices. In addition to heads / feet, voltage control circuitry 116 may also include various other circuit components (e.g., boost converters, voltage regulators, etc.) adapted to regulate or otherwise control the supply voltages supplied to memory array 120 and / or memory controller 105.

[0028] For example, a first head (e.g., a first PMOS transistor) may receive a first supply voltage (VDD) at one source / drain terminal of the first PMOS transistor and selectively supply a virtual supply voltage (sometimes referred to as "VDDHD") to the memory controller 105 through the other source / drain terminal of the first PMOS transistor based on a signal fed into the gate terminal of the first PMOS transistor; and a second head (e.g., a second PMOS transistor) may receive a second supply voltage (VDDM) at one source / drain terminal of the second PMOS transistor and selectively supply another virtual supply voltage (sometimes referred to as "VDDAI") to the memory array 120 through the other source / drain terminal of the second PMOS transistor based on a signal fed into the gate terminal of the second PMOS transistor.

[0029] In various embodiments of this disclosure, as disclosed herein, the memory device 100 may be formed on both sides of a substrate. For example, the memory array 120 and memory controller 105 of the memory device 100 may be formed as a plurality of transistors on the front side of the substrate. On the front side of the substrate, a plurality of front-side metallization layers may be formed, each front-side metallization layer including a plurality of front-side metal tracks; on the back side of the substrate, a plurality of back-side metallization layers may be formed, each back-side metallization layer including a plurality of back-side metal tracks. Typically, the front-side metallization layers are referred to as M0 layer, M1 layer, M2 layer, M3 layer, M4 layer, etc. (in order from the substrate to the topmost front-side metallization layer), and the back-side metallization layers are referred to as BMO layer, BM1 layer, BM2 layer, etc. (in order from the substrate to the topmost back-side metallization layer).

[0030] To maximize the routing flexibility of the front metal rails and / or reduce capacitive coupling between them, some front metal rails configured to carry supply voltages or ground voltages can be partially or completely removed from the front side and relocated to the back side. In one non-limiting example, a front metal rail configured to carry a second supply voltage VDDM can be relocated from layer M2 to layers BM1 and / or BM2. In another non-limiting example, a front metal rail configured to carry a dummy supply voltage VDDAI can be relocated from layer M2 to layers BM1 and / or BM2. In yet another non-limiting example, a front metal rail configured to carry ground voltage VSS, a second supply voltage VDDM, and a dummy supply voltage VDDAI can be relocated from layer M2 to layers BM1 and / or BM2.

[0031] Despite Figure 1In this disclosure, memory device 100 is depicted as part of a dual-power-rail system (e.g., supply voltages VDD and VDDM powering memory controller 105 and memory array 120, respectively), but it should be understood that this disclosure is not limited to memory devices having a dual-power-rail system. For example, even when using a single power-rail system (e.g., using a single supply voltage VDD to power the memory controller and memory array of the memory device), the memory device may include some front-side metal rails carrying the supply voltage VDD, which are repositioned from layer M2 to layers BM1 and / or BM2, while still remaining within the scope of this disclosure.

[0032] Figure 2 Illustrations are shown according to some embodiments Figure 1 The circuit diagram 200 shows an example implementation of memory cell 125 (hereinafter referred to as "memory cell 200"). Figure 2 In the illustrative example, memory cell 200 includes a six-transistor (6T) SRAM cell. In some other embodiments, memory cell 200 may be implemented as any of a variety of other SRAM cells, such as a two-transistor two-resistor (2T-2R) SRAM cell, a four-transistor (4T) SRAM cell, an eight-transistor (8T) SRAM cell, a ten-transistor (10T) SRAM cell, etc. Furthermore, although the discussion of this disclosure pertains to SRAM cells, it should be understood that other embodiments of this disclosure may also be used for any memory cell, such as a dynamic random access (DRAM) memory cell.

[0033] As shown, memory cell 200 includes six transistors: M1, M2, M3, M4, M5, and M6. Transistors M1 and M2 are formed as a first inverter, and transistors M3 and M4 are formed as a second inverter, wherein the first and second inverters are cross-coupled to each other. For example, both the first and second inverters are coupled between a supply voltage 201 (e.g., VDDM in a dual-rail implementation) and a reference voltage 203 (e.g., VSS or ground). The first inverter (formed by transistors M1 and M2) is coupled to transistor M5, and the second inverter (formed by transistors M3 and M4) is coupled to transistor M6. In addition to being coupled to the first and second inverters, transistors M6 and M5 are each coupled to word line (WL) 205, and are also coupled to bit line (BL) 207 and complementary bit line 209 (sometimes referred to as anti-phase line or BLB), respectively.

[0034] In some embodiments, transistors M1 and M3 are referred to as pull-up transistors of memory cell 200 (hereinafter referred to as "pull-up transistor M1" and "pull-up transistor M3", respectively); transistors M2 and M4 are referred to as pull-down transistors of memory cell 200 (hereinafter referred to as "pull-down transistor M2" and "pull-down transistor M4", respectively); and transistors M5 and M6 are referred to as access transistors of memory cell 200 (hereinafter referred to as "access transistor M5" and "access transistor M6", respectively). In some embodiments, transistors M2, M4, M5, and M6 each comprise an n-type metal-oxide-semiconductor (NMOS) transistor, and M1 and M3 each comprise a p-type metal-oxide-semiconductor (PMOS) transistor. Although Figure 2 The illustrated embodiment shows that transistors M1-M6 are NMOS or PMOS transistors, but any of the various transistors or devices suitable for memory devices can be implemented as at least one of transistors M1-M6, such as bipolar junction transistors (BJTs), high electron mobility transistors (HEMTs), etc.

[0035] Access transistors M5 and M6 each have a gate terminal coupled to word line WL 205. The gate terminals of transistors M5 and M6 are configured to receive pulse signals via word line WL 205 to accordingly enable or block access to memory cell 200, which will be discussed in further detail below. Transistors M2 and M5 are coupled to each other at node 210 via the drain terminal of transistor M2 and the source terminal of transistor M5. Node 210 is also coupled to the drain terminal of transistor M1 and node 212. Transistors M4 and M6 are coupled to each other at node 214 via the drain terminal of transistor M4 and the source terminal of transistor M6. Node 214 is also coupled to the drain terminal of transistor M3 and node 216.

[0036] When a memory cell (e.g., memory cell 200) stores data bits, the first node of the bit cell is configured to be in a first logic state (logic 1 or logic 0), and the second node of the bit cell is configured to be in a second logic state (or logic 0 or logic 1). The first and second logic states are complementary to each other. In some embodiments, the first logic state at the first node may represent the logic state of the data bit stored in the memory cell. For example, in Figure 2 In the illustrated embodiment, when memory cell 200 stores data bits in a logic 1 state, node 210 is configured to be in a logic 1 state and node 214 is configured to be in a logic 0 state.

[0037] To read the logic state of a data bit stored in memory cell 200, bit line BL 207 and anti-phase line BLB 209 are precharged to VDDM (e.g., logic high, for example, using a capacitor to retain charge). Word line WL 205 is then asserted or activated to logic high via an assertion signal, which turns on access transistors M5 and M6. Specifically, rising edges of assertion signals are received at the gate terminals of access transistors M5 and M6, respectively, to turn on access transistors M5 and M6. Once access transistors M5 and M6 are turned on, the precharged bit line BL 207 or anti-phase line BLB 209 can begin to discharge based on the logic state of the data bit. For example, when memory cell 200 stores logic 0, node 214 (e.g., Q) can present a voltage corresponding to logic 1, and node 210 (e.g., Q inverted) can present a voltage corresponding to complementary logic 0. In response to the conduction of access transistors M5 and M6, a discharge path can be provided, starting from the pre-charged anti-phase line BLB 209, passing through access transistor M5 and pull-down transistor M2, to ground voltage 203. When the voltage level on the anti-phase line BLB 209 is pulled down by this discharge path, the pull-down transistor M4 can remain off. Therefore, bit line BL 207 and anti-phase line BL 209 can each present a voltage level to generate a sufficiently large voltage difference between them. Thus, a sense amplifier coupled to bit line BL 207 and anti-phase line BLB 209 can use the polarity of the voltage difference to determine whether the logic state of the data bit is logic 1 or logic 0.

[0038] To write the logic state of a data bit stored in memory cell 200, the data to be written is applied to bit line BL 207 and / or anti-phase line BLB 209. For example, anti-phase line BLB 209 is connected / short-circuited to 0V (e.g., ground voltage 203) via a low-impedance connection. Word line WL 205 is then asserted or activated to a logic high level via an assertion signal, which turns on access transistors M5 and M6. Once access transistors M5 and M6 are turned on, node 210 can begin discharging based on the logic state of anti-phase line BLB 209. For example, before M5 and M6 are turned on, anti-phase line BLB 209 may present a voltage corresponding to logic 0, and node 210 may present a voltage corresponding to complementary logic 1. In response to the turn-on of access transistors M5 and M6, a discharge path can be provided from node 210, via access transistor M5, to ground voltage 203. Once the voltage level on node 210 is pulled down below Vth (threshold voltage) of pull-down transistor M4, M4 can be turned off and M3 can be turned on, causing node 214 to be pulled up to VDDM 201. Once node 214 is less than Vth of VDD 201, M1 can be turned off and M2 can be turned off, causing node 210 to be pulled down to ground voltage 203. Then, when word line WL 205 is contact asserted, the logic state applied to bit line BL 207 and / or anti-phase line BLB 209 has been stored in memory cell 200.

[0039] Figure 3A and Figure 3B An example layout 300 according to some embodiments is shown, which can be configured to form the disclosed memory device 100 having a reduced number of front-side metal tracks carrying ground voltage, supply voltage, and / or virtual supply voltage. It should be understood that Figures 3A-3B The layout 300 shown has been simplified, and therefore layout 300 may include any of a variety of other components (e.g., patterns for forming the corresponding structure) while still within the scope of this disclosure.

[0040] Typically, layout 300 includes multiple patterns configured to form corresponding structures, such as front metal rails, rear metal rails, etc. Therefore, in the following discussion, such patterns of the disclosed layout are referred to herein as the structures to be formed. For example, Figure 3A A top view of a layout 300 including multiple front-side metal rails can be shown. Figure 3B A top (inverted) view of the wiring 300, which includes multiple back-side metal tracks, can be shown, while Figure 3A and Figure 3B Each of them includes a memory cell formed on the front side of the substrate.

[0041] First refer to Figure 3AMultiple (e.g., 16) memory cells 301 are formed or otherwise arranged in a region of the substrate. These 16 memory cells 301 may at least partially form a memory array arranged on multiple rows and columns (e.g., Figure 1 (of 120). For example, in Figure 3A In this configuration, memory cells 301 are arranged in 8 rows (e.g., extending in the Y direction) and 2 columns (e.g., extending in the X direction). Furthermore, each memory cell 301 may correspond to... Figure 2 The 6T SRAM cells 200 shown can each be implemented as standard cells in layout 300. In general semiconductor IC design, the standard cell approach uses standard cells as an abstract representation of certain functions to integrate millions of devices on a single chip.

[0042] Reference Figure 6 An example layout of the standard cell for each of these memory cells 301 is discussed in more detail. Typically, when the memory cell 301 is implemented as a standard cell based on a 6T SRAM cell structure, it may include a plurality of active regions extending along a first lateral direction and a plurality of gate structures extending along a second lateral direction. Each of these active regions may be overlaid with one or more gate structures to form six transistors M1 to M6, which operatively form a 6T SRAM cell. It should be understood that the layout of the corresponding standard cell may vary accordingly as the memory cell 301 is implemented as other SRAM cell structures.

[0043] Before, simultaneously with, or after forming the transistor configured as memory cell 301 on the front side of the substrate, multiple other transistors may also be formed on the front side of the substrate. Such transistors can at least form a memory controller operatively coupled to memory cell 301 (e.g., Figure 1 (105). In some embodiments, these transistors may be physically formed around the area forming memory cell 301 and may be implemented as various other standard cells (e.g., AND gates, OR gates, XOR gates, NOT gates, NAND gates, NOR gates and XNOR gates, as well as combinational logic circuits such as multiplexers, flip-flops, adders, counters, etc.), which are not shown for clarity.

[0044] After forming transistors that can be operatively used as memory cells and memory controllers, multiple front-side metallization layers can be formed on these transistors. Each of these front-side metallization layers can include (e.g., embed) multiple metal orbitals in one or more dielectric layers (e.g., formed of an oxide material or a low-k dielectric material). As disclosed herein, the bottommost of the front-side metallization layers is called the M0 layer, and the metal orbitals formed in the M0 layer are also called M0 orbitals. On the M0 layer, an M1 layer including multiple M1 orbitals can be formed; above the M1 layer, an M2 layer including multiple M2 orbitals can be formed; on the M2 layer, an M3 layer including multiple M3 orbitals can be formed; and so on.

[0045] Still referencing Figure 3A The layout 300 includes a plurality of first patterns for forming M0 tracks 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323 and 324. M0 tracks 310 to 324 may each extend along the X direction and are each configured to perform a specific function. For example, each of M0 rails 310-311, 317, and 323-324 can be configured to carry the ground voltage VSS; M0 rails 322 and 318 can be configured as BL and BLB, BL[0] and BLB[0] of the first column; M0 rails 312 and 316 can be configured as BL and BLB, BL[1] and BLB[1] of the second column; M0 rails 313, 315, 319, and 321 can each be configured to carry the second supply voltage VDDM; and M0 rails 314 and 320 can each be configured to carry the dummy supply voltage VDDAI. Although not shown, it should be understood that each of these M0 rails 310 to 324 can be electrically coupled to the transistor below via one or more via structures (sometimes referred to as VG or VD) and / or one or more contact structures (sometimes referred to as MD).

[0046] Above M0 tracks 310 to 324, layout 300 includes a plurality of second patterns for forming M1 tracks 330, 331, 332, 333, 334, 335, 336, and 337. M1 tracks 330 to 337 may each extend along the Y direction and are each configured to perform a specific function. For example, track 337 of M1 can be configured as the word line WL of the first line[0]; track 336 of M1 can be configured as the word line WL of the second line[1]; track 335 of M1 can be configured as the word line WL of the third line[2]; track 334 of M1 can be configured as the word line WL of the fourth line[3]; track 333 of M1 can be configured as the word line WL of the fifth line[4]; track 332 of M1 can be configured as the word line WL of the sixth line[5]; track 331 of M1 can be configured as the word line WL of the seventh line[6]; track 330 of M1 can be configured as the word line WL of the eighth line[7].

[0047] Above M1 tracks 330 to 337, multiple patterns for forming M2 tracks may exist. In the prior art, these M2 tracks are confined to the front side and each track is configured to carry one of a ground voltage VSS, a second supply voltage VDDM, or a virtual supply voltage VDDAI. However, according to this disclosure, these M2 tracks are repositioned from the front side to the back side, which will... Figure 3B This repositioning of the M2 tracks, each carrying a power supply / reference voltage, frees up significant space in the M2 layer, advantageously increasing the flexibility to place other M2 tracks (e.g., 339A, 339B, 339C, 339D, 339E, etc.) configured to carry non-power supply signals. As disclosed herein, such non-power supply signals typically refer to signals that are not directly related to (connected to) the supply voltage or reference voltage and are operatively communicated within a single circuit component (e.g., an SRAM cell) or across different circuit components (e.g., adjacent SRAM cells), such as signals present on bit line BL 207, anti-phase line BLB 209, or word line WL 205. Furthermore, without the formation of M2 tracks carrying power supply / reference voltages, the capacitive coupling between word lines formed in the M1 layer and word lines formed in the M3 layer (discussed below) can be significantly reduced.

[0048] Above the M2 layer (or M2 rails 339A-339E not configured to carry power / reference voltage), layout 300 includes a plurality of third patterns for forming M3 rails 340, 341, 342, 343, 344, 345, 346, and 347. M3 rails 340 to 347 may each extend along the Y direction and are each configured to perform a specific function. For example, M3 track 347 can be configured as the word line WL[0] of the first row; M3 track 346 can be configured as the word line WL[1] of the second row; M3 track 345 can be configured as the word line WL[2] of the third row; M3 track 344 can be configured as the word line WL of the fourth row; M3 track 343 can be configured as the word line WL of the fifth row; M3 track 342 can be configured as the word line WL of the sixth row; M3 track 341 can be configured as the word line WL of the seventh row; and M3 track 340 can be configured as the word line WL of the eighth row. In some embodiments, Figure 3A None of the M3 tracks shown are configured to carry a ground voltage VSS, which is typically limited in the prior art. Repositioning the M3 tracks that carry a ground voltage VSS, which are limited in the prior art, from the front to the back side allows each word line (e.g., M3 tracks 340 to 347) to be formed wider (in the X direction), or allows word lines to be spaced further apart. By widening the width, each word line can advantageously have lower resistance, and by widening the spacing, capacitive coupling between adjacent word lines can be advantageously suppressed.

[0049] The following are several non-limiting examples compared to existing memory devices. As a first non-limiting example, with the spacing between adjacent M3 tracks remaining constant at approximately 30 nanometers, the width of each of M3 tracks 340 to 347 can be increased from approximately 56 nanometers to approximately 66 nanometers. Therefore, the width-to-spacing ratio can be increased to greater than 2. As a second non-limiting example, with an increase in the spacing between adjacent M3 tracks of approximately 33%, the width of each of M3 tracks 340 to 347 can be increased by approximately 18%. As a third non-limiting example, with an increase in the spacing between adjacent M3 tracks of approximately 40%, the width of each of M3 tracks 340 to 347 can be reduced by approximately 4%. As a fourth non-limiting example, with an increase in the spacing between adjacent M3 tracks of approximately 47%, the width of each of M3 tracks 340 to 347 can be reduced by approximately 8%.

[0050] After forming the front-side metal orbitals, the substrate is flipped so that multiple back-side metallization layers are formed on top of each other. Each of these back-side metallization layers may include (e.g., embed) multiple metal orbitals in one or more dielectric layers (e.g., formed of an oxide material or a low-k dielectric material). As disclosed herein, the bottommost of the back-side metallization layers is called the BM0 layer, and the metal orbitals formed in the BM0 layer are called BM0 orbitals. Above the BM0 layer, a BM1 layer comprising multiple BM1 orbitals may be formed; above the BM1 layer, a BM2 layer comprising multiple BM2 orbitals may be formed; above the BM2 layer, a BM3 layer comprising multiple BM3 orbitals may be formed; and so on.

[0051] Next reference Figure 3B Referring to memory cell 301, layout 300 includes a plurality of fourth patterns for forming BM0 tracks 350, 351, 352, 353, 354, 355, and 356. BM0 tracks 350 through 356 may each extend along the X direction and are each configured to perform a specific function. For example, each of BM0 tracks 350, 353, and 356 may be configured to carry a ground voltage VSS; each of BM0 tracks 352 and 354 may be configured to carry a second supply voltage VDDM; and each of BM0 tracks 351 and 355 may be configured to carry a dummy supply voltage VDDAI. Although not shown, it should be understood that each of these BM0 tracks 350 through 356 may be electrically coupled to a transistor via one or more via structures (sometimes referred to as BV).

[0052] Above BM0 rails 350 to 356, layout 300 includes a plurality of fifth patterns for forming BM1 rails 360, 361, 362, 363, 364, 365, 366, 367, 368, 369, 370, 371, 372, and 373. BM1 rails 360 to 373 may each extend along the Y direction and are each configured to perform a specific function. For example, each of BM1 rails 361, 363-370, and 372 may be configured to carry a ground voltage VSS; each of BM1 rails 360 and 373 may be configured to carry a second supply voltage VDDM; and each of BM1 rails 362 and 371 may be configured to carry a virtual supply voltage VDDAI.

[0053] Above BM1 rails 360 to 373, layout 300 includes a plurality of sixth patterns for forming BM2 rails 380, 381, 382, ​​and 383. BM2 rails 380 to 383 may each extend along the X direction and are each configured to perform a specific function. For example, BM2 rails 380 and 382 may each be configured to carry a second supply voltage VDDM; BM2 rails 381 and 383 may each be configured to carry a ground voltage VSS.

[0054] As mentioned above, according to Figures 3A-3B In example layout 300, except for layer M0, the front metallization layers (e.g., layers M1, M2, and M3) do not include metal tracks carrying power or reference voltages. These metal tracks configured to carry power / reference voltages are repositioned to the back side. For example, layer BM1 includes multiple metal tracks (e.g., 360, 373) configured to carry a second supply voltage VDDM, multiple metal tracks (e.g., 362, 371) configured to carry a dummy supply voltage VDDAI, and multiple metal tracks (e.g., 361, 363-370, 372) configured to carry a reference / ground voltage VSS. In another example, layer BM2 includes multiple metal tracks (e.g., 380, 382) configured to carry a second supply voltage VDDM and multiple metal tracks (e.g., 381, 383) configured to carry a reference / ground voltage VSS.

[0055] It should be understood that Figures 3A-3B Layout 300 is merely one of various example layouts that can form a memory device with a reduced number of front-side metal tracks configured to carry power / reference voltages. Table 1 below summarizes some of these alternative embodiments, including the arrangement of layout 300 for reference. Each embodiment summarizes the formation locations of the metal tracks carrying VDDM / VDDAI / VSS.

[0056] Table 1

[0057]

[0058]

[0059] Figure 4A and Figure 4B A portion of an alternative layout 1 (hereinafter referred to as "layout 400") according to some embodiments is shown, which can be configured to form the disclosed memory device 100 having a reduced number of front-side metal tracks carrying ground voltage, supply voltage, and / or dummy supply voltage. Figures 3A-3B The layout is similar to 300. Figures 4A-4B A memory array with 16 memory cells 401 is shown for reference.

[0060] exist Figure 4AIn this layout, 400 includes: an M1 layer having M1 tracks 430, 431, 432, 433, 434, 435, 436, and 437, each track configured as a word line, and M1 tracks 429 and 438, each track configured to carry VDDAI; and an M2 layer having M2 tracks 439A and 439B, each track configured to carry VDDAI. Although not shown, layout 400 may include an M0 layer with metal tracks configured to carry VDDM, VSS, and VDDAI, and metal tracks not configured to carry VDDM, VDDAI, or VSS, both similar to layout 300. Figure 4B In the configuration 400, the layout includes: a BM0 layer with BM0 tracks 450, 453, and 456, each configured to carry VSS, and BM0 tracks 451, 452, 454, and 455, each configured to carry VDDM; a BM1 layer with BM1 tracks 463, 464, 465, 466, 467, 468, 469, and 470, each configured to carry VSS; and a BM2 layer with BM2 track 481 configured to carry VSS and BM2 track 482 configured to carry VDDM. Therefore, in the M2 layer, there may only be metal tracks configured to carry VDDAI; in the M3 layer, there may be no metal tracks configured to carry power or reference voltages.

[0061] Figure 5A and Figure 5B A portion of an alternative layout 3 (hereinafter referred to as "layout 500") according to some embodiments is shown, which can be configured to form the disclosed memory device 100 having a reduced number of front-side metal rails carrying ground voltage, supply voltage, and / or dummy supply voltage. Figures 3A-3B Layout 300 and Figures 4A-4B The layout is similar to 400. Figures 5A-5B A memory array with 16 memory cells 501 is shown for reference.

[0062] exist Figure 5AIn this layout, 500 includes: an M1 layer having M1 tracks 530, 531, 532, 533, 534, 535, 536, and 537, each track configured as a word line; and M1 tracks 529 and 538, each track configured to carry either VDDAI or VSS; and an M2 layer having M2 tracks 539A, 539C, and 539E, each track configured to carry VSS; and M2 tracks 539B and 539D, each track configured to carry VDDAI. Although not shown, 500 may include an M0 layer (similar to 300) having metal tracks configured to carry VDDM, VSS, and VDDAI, and an M3 layer having multiple metal tracks configured to carry VSS. Figure 5B In the layout 500, there are: a BM0 layer with BM0 tracks 551, 552, 553 and 554, each track being configured to carry VDDM; a BM1 layer with BM1 tracks 561, 562, 563, 564, 565, 566, 567 and 568, each track being configured to carry VDDM; and a BM2 layer with a BM2 track 581 configured to carry VDDM.

[0063] In this embodiment (alternative layout 500), the M2 tracks carrying VDDAI (e.g., 539B and 539D) and the M2 tracks carrying VSS (e.g., M2 tracks 539A, 539C, and 539E) can be arranged alternately along the Y direction. For example, each memory cell 501 may have a first edge extending along the X direction and covered by one of the M2 tracks 539A, 539C, or 539E, and a second edge extending along the X direction and covered by the other of the M2 tracks 539A, 539C, or 539E, wherein one of the M2 tracks 539B or 539D passes through the middle portion of the memory cell 501. Alternatively, the spacing (along the Y direction) between the M2 tracks carrying VSS and the M2 tracks carrying VDDAI is equal to half the cell height of the memory cell 501.

[0064] Figure 6 The configuration shown in some embodiments is configured to form 6T SRAM cells (e.g., Figure 2 The example layout is 600 (200). It should be understood that... Figure 6 The layout 600 shown has been simplified, and therefore layout 600 may include any of a variety of other components (e.g., patterns for forming the corresponding structure) while still remaining within the scope of this disclosure.

[0065] As shown, layout 600 includes patterns for forming active regions 602, 604, 606, and 608, respectively. Each of the active regions 602 to 608 may be formed as a fin structure or a stacked structure (having a plurality of first nanostructures and second nanostructures alternately stacked on top of each other) extending along the X direction. Active regions 602 and 608 are formed of a first conductivity type (e.g., n-type), and active regions 604 and 606 are formed of a second conductivity type (e.g., p-type). Layout 600 includes patterns for forming dummy regions 610, 612, 614, 616, and 618, each of which may extend along the same lateral direction as the active regions 602 to 608. Layout 600 includes patterns for forming gate structures 620, 622, 624, and 626, each of which may extend along the Y direction.

[0066] Each of the active regions 602 to 608 is crossed (or otherwise covered) by one or more of the gate structures 620 to 626 to define a corresponding channel for a plurality of transistors. Multiple source / drain (e.g., epitaxial) structures may be formed on opposite sides of each gate structure in the active regions. In some embodiments, each of the gate structures 620 to 626 may be diced into multiple portions by dummy regions 610 to 618. Thus, six transistors M1 to M6 of a 6T SRAM cell (e.g., 200) can be implemented. For example, access transistor M5 may be defined by a gate structure 622 and a source / drain structure formed in active region 602; pull-down transistor M2 may be defined by a gate structure 624 and a source / drain structure formed in active region 602; pull-up transistor M1 may be defined by a gate structure 624 and a source / drain structure formed in active region 604; pull-up transistor M3 may be defined by a gate structure 622 and a source / drain structure formed in active region 606; access transistor M6 may be defined by a gate structure 624 and a source / drain structure formed in active region 608; and pull-down transistor M4 may be defined by a gate structure 622 and a source / drain structure formed in active region 608.

[0067] Figure 7 A flowchart of a method 700 for manufacturing a memory device according to some embodiments is shown. Method 700 may be part of a method for manufacturing an integrated circuit. For example, the operation of method 700 may be configured based on... Figures 3A-3B The layout shown is used to manufacture integrated circuits. Therefore, the following discussion of method 700 may sometimes refer to the above figures. It should be noted that... Figure 7 Method 700 is merely an example and is not intended to limit this disclosure. Therefore, it is understood that the order of operations in method 700 can be changed; for example, additional operations may be provided before, during, and after method 700, and only a few operations may be briefly described herein.

[0068] Method 700 may begin with operation 710 of forming a memory array on the front side of a substrate. The memory array includes a plurality of memory cells (e.g., 301) powered by a first supply voltage (e.g., VDDM). Method 700 may continue to operation 520 of forming peripheral circuitry (or a memory controller) on the front side. The memory controller is operatively coupled to the memory array and powered by a second supply voltage (e.g., VDD). The second supply voltage is different from the first supply voltage.

[0069] Method 700 may continue to operation 730, forming a first metallization layer on the front side and above the memory array and peripheral circuitry, wherein the first metallization layer includes a plurality of first metal rails. In some embodiments, each of the plurality of first metal rails (e.g., M0 rails 310 to 324) may extend along a first lateral direction and be configured to carry a first supply voltage, a virtual supply voltage (e.g., VDDAI), or a ground voltage (e.g., VSS). Method 700 may continue to operation 540, forming a second metallization layer on the first side and above the first metallization layer, wherein the second metallization layer includes a plurality of second metal rails. In some embodiments, each of the plurality of second metal rails (e.g., M1 rails 330 to 337) extends along a second lateral direction perpendicular to the first lateral direction and is configured to be operatively coupled to a word line of one or more of the plurality of memory cells. Method 700 may continue to operation 750, forming a third metallization layer on the first side and the second metallization layer, wherein the third metallization layer includes a plurality of third metal rails. In some embodiments, each of the plurality of third metal rails (e.g., Figure 3A The M2 track (not shown) extends along a first lateral direction and is configured to carry only non-power signals rather than a first supply voltage. Method 700 may continue to operation 760, forming a fourth metallization layer over the first side and the third metallization layer, wherein the fourth metallization layer includes a plurality of fourth metal tracks. In some embodiments, each of the plurality of fourth metal tracks (e.g., M3 tracks 340 to 347) extends along a second lateral direction and is configured only as a word line.

[0070] Method 700 may continue to operation 770, forming a fifth metallization layer on a second side of the substrate, wherein the fifth metallization layer includes a plurality of fifth metal tracks. In some embodiments, each of the plurality of fifth metal tracks (e.g., BMO tracks 350 to 356) extends along a first lateral direction and is configured to carry a first supply voltage VDDM, a dummy supply voltage VDDAI, or a ground voltage VSS. Method 700 may continue to operation 780, forming a sixth metallization layer on the second side and the fifth metallization layer, wherein the sixth metallization layer includes a plurality of sixth metal tracks. In some embodiments, each of the plurality of sixth metal tracks (e.g., BMO tracks 260 to 373) extends along a second lateral direction and is configured to carry the first supply voltage VDDM, the dummy supply voltage VDDAI, or a ground voltage VSS. Method 700 may continue to operation 790, forming a seventh metallization layer on a second side of the substrate, wherein the seventh metallization layer includes a plurality of seventh metal tracks. In some embodiments, each of the plurality of seventh metal rails (e.g., BM2 rails 380 to 383) extends along a first lateral direction and is configured to carry a first supply voltage VDDM or ground voltage VSS.

[0071] One aspect of this disclosure discloses a memory device. The memory device includes: a plurality of memory cells physically formed on a first side of a substrate; peripheral circuitry operatively coupled to the plurality of memory cells and physically formed on the first side of the substrate; a first metallization layer physically formed on the first side of the substrate and including a plurality of first metal rails, each of the plurality of first metal rails extending along a first lateral direction and configured to carry a supply voltage or a ground voltage, the first supply voltage being configured to supply power to the plurality of memory cells; a second metallization layer physically formed on the first side of the substrate and including a plurality of second metal rails, each of the plurality of second metal rails extending along a second lateral direction and configured to be operatively coupled to one or more word lines of the plurality of memory cells; and a third metallization layer physically formed on the first side of the substrate and including a plurality of third metal rails. A metal track, each of a plurality of third metal tracks extending along a first lateral direction, at least one of the third metal tracks being configured to carry only non-power signals and not power supply voltages; a fourth metallization layer, physically formed on a first side of the substrate, and including a plurality of fourth metal tracks, each of the plurality of fourth metal tracks extending along a second lateral direction and configured only as word lines; a fifth metallization layer, physically formed on a second side of the substrate, and including a plurality of fifth metal tracks, each of the plurality of fifth metal tracks extending along the first lateral direction and configured to carry power supply voltages or ground voltages; and a sixth metallization layer, physically formed on a second side of the substrate, and including a plurality of sixth metal tracks, each of the plurality of sixth metal tracks extending along the second lateral direction and configured to carry power supply voltages or ground voltages.

[0072] In some embodiments, the memory device further includes a power switch configured to receive a supply voltage and selectively provide virtual supply voltages to a plurality of memory cells.

[0073] In some embodiments, each memory cell is covered by one of a third metal rail configured to carry a virtual power supply voltage.

[0074] In some embodiments, one of the third metal rails configured to carry ground voltage and another of the third metal rails configured to carry virtual supply voltage are spaced apart from each other by a distance along a second lateral direction.

[0075] In some embodiments, the distance is equal to half the cell height of each memory cell.

[0076] In some embodiments, no other third metal rail is inserted between one of the third metal rails configured to carry ground voltage and yet another of the third metal rails configured to carry virtual supply voltage.

[0077] In some embodiments, each memory cell is not covered by any metal rails formed in a third metallization layer and configured to carry the supply voltage.

[0078] In some embodiments, each of the plurality of memory cells includes a static random access memory cell.

[0079] In some embodiments, none of the plurality of fourth metal rails is configured to carry ground voltage.

[0080] In some embodiments, the ratio of the width of each of the plurality of fourth metal tracks along the first lateral direction to the spacing between adjacent fourth metal tracks is equal to or greater than 2.

[0081] In some embodiments, on the first side, a fourth metallization layer is disposed above a third metallization layer, the third metallization layer is disposed above a second metallization layer, the second metallization layer is disposed above a first metallization layer, and on the second side, a sixth metallization layer is disposed above a fifth metallization layer.

[0082] In another aspect of this disclosure, a memory device is disclosed. The memory device includes: a memory cell powered by a first supply voltage; peripheral circuitry operatively coupled to the memory cell and powered by a second supply voltage; a first metal rail and a second metal rail disposed in a first front metallization layer among a plurality of front metallization layers and extending in a first lateral direction, the first metal rail and the second metal rail being configured to carry the first supply voltage and a ground voltage, respectively, to provide the supply voltage to power the memory cell; a third metal rail disposed in a second front metallization layer among a plurality of front metallization layers and extending in a second lateral direction, the third metal rail being configured to be operatively coupled to a word line of the memory cell; and a fourth metal rail. A fourth and fifth metal rail are disposed in a third front metallization layer among a plurality of front metallization layers and extend in a first lateral direction; the fourth and fifth metal rails are configured to carry a virtual supply voltage and a ground voltage, respectively, and selectively provide a virtual supply voltage to power the memory cell; a sixth metal rail is disposed in a first back metallization layer among a plurality of back metallization layers and extends in a first lateral direction; the sixth metal rail is configured to carry a first supply voltage; and a seventh metal rail is disposed in a second back metallization layer among a plurality of back metallization layers and extends in a second lateral direction; the seventh metal rail is configured to carry a first supply voltage.

[0083] In some embodiments, the memory device further includes a power switch configured to receive a first supply voltage and selectively supply virtual supply voltages to memory cells.

[0084] In some embodiments, memory cells and peripheral circuitry are formed along the main surface of the substrate, wherein a plurality of front-side metallization layers and a plurality of back-side metallization layers are formed on opposite sides of the substrate.

[0085] In some embodiments, no other metal tracks are inserted between the fourth and fifth metal tracks in the third front metallization layer.

[0086] In some embodiments, the fourth and fifth metal tracks are spaced apart from each other by a distance in the second lateral direction, wherein the distance is equal to half the cell height of the memory cell.

[0087] In some embodiments, the first supply voltage and the second supply voltage are different from each other.

[0088] In another aspect of this disclosure, a method for forming a memory device is disclosed. The method includes: forming a memory array on a first side of a substrate, the memory array including a plurality of memory cells powered by a first supply voltage; forming peripheral circuitry on the first side of the substrate, the peripheral circuitry being operatively coupled to the memory array and powered by a second supply voltage different from the first supply voltage; forming a first metallization layer on the first side and over the memory array and peripheral circuitry, the first metallization layer including a plurality of first metal rails, each of the plurality of first metal rails extending along a first lateral direction and configured to carry the first supply voltage or ground voltage; forming a second metallization layer on the first side and over the first metallization layer, the second metallization layer including a plurality of second metal rails, each of the plurality of second metal rails extending along a second lateral direction and configured to be operatively coupled to one or more word lines of the plurality of memory cells; and forming a second metallization layer on the first side and over the second metallization layer. A third metallization layer is formed on the first side and above the third metallization layer. The third metallization layer includes a plurality of third metal rails, each of which extends along a first lateral direction and is configured to carry only non-power signals and not a first power supply voltage. A fourth metallization layer is formed on the second side of the substrate. The fourth metallization layer includes a plurality of fourth metal rails, each of which extends along a second lateral direction and is configured to carry only word lines. A fifth metallization layer is formed on the second side of the substrate. The fifth metallization layer includes a plurality of fifth metal rails, each of which extends along a first lateral direction and is configured to carry either a first power supply voltage or a ground voltage. A sixth metallization layer is formed on the second side and above the fifth metallization layer. The sixth metallization layer includes a plurality of sixth metal rails, each of which extends along a second lateral direction and is configured to carry either a first power supply voltage or a ground voltage.

[0089] In some embodiments, the ratio of the width of each of the plurality of fourth metal tracks along the first lateral direction to the spacing between adjacent fourth metal tracks is equal to or greater than 2.

[0090] In some embodiments, each of the plurality of memory cells includes a static random access memory cell.

[0091] As used herein, the terms “about” and “approximately” generally refer to the value of a given quantity that can vary depending on the specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term “about” can refer to a given quantity of value that varies, for example, within a range of 10-30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0092] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. A memory device, comprising: Multiple memory cells are physically formed on the first side of the substrate; Peripheral circuitry is operatively coupled to the plurality of memory cells and physically formed on the first side of the substrate; A first metallization layer is physically formed on the first side of the substrate and includes a plurality of first metal tracks, each of the plurality of first metal tracks extending along a first lateral direction and configured to carry a supply voltage or a ground voltage, the first supply voltage being configured to supply power to the plurality of memory cells. A second metallization layer is physically formed on the first side of the substrate and includes a plurality of second metal tracks, each of which extends along a second lateral direction and is configured to be operatively coupled to one or more word lines of the plurality of memory cells. A third metallization layer is physically formed on the first side of the substrate and includes a plurality of third metal tracks, each of which extends along the first lateral direction, and at least one of the third metal tracks is configured to carry only non-power signals and not the power supply voltage. A fourth metallization layer is physically formed on the first side of the substrate and includes a plurality of fourth metal tracks, each of which extends along a second lateral direction and is configured only as a word line; A fifth metallization layer is physically formed on a second side of the substrate and includes a plurality of fifth metal tracks, each of which extends along the first lateral direction and is configured to carry the supply voltage or the ground voltage. as well as A sixth metallization layer is physically formed on the second side of the substrate and includes a plurality of sixth metal tracks, each of which extends along the second lateral direction and is configured to carry the supply voltage or the ground voltage.

2. The memory device of claim 1 further includes a power switch configured to receive the power supply voltage and selectively provide virtual power supply voltages to the plurality of memory cells.

3. The memory device according to claim 2, wherein, Each of the memory cells is covered by one of the third metal rails configured to carry the virtual power supply voltage.

4. The memory device according to claim 3, wherein, Another of the third metal rails configured to carry the ground voltage and yet another of the third metal rails configured to carry the virtual power supply voltage are spaced apart from each other by a distance along the second lateral direction.

5. The memory device according to claim 4, wherein, No other third metal rail is inserted between the other of the third metal rails configured to carry the ground voltage and yet another of the third metal rails configured to carry the virtual power supply voltage.

6. The memory device according to claim 1, wherein, Each of the memory cells is not covered by any metal rails formed in the third metallization layer and configured to carry the supply voltage.

7. The memory device according to claim 1, wherein, The ratio of the width of each of the plurality of fourth metal tracks along the first lateral direction to the spacing between adjacent fourth metal tracks is equal to or greater than 2.

8. A memory device, comprising: The memory cell is powered by the first supply voltage; Peripheral circuitry is operatively coupled to the memory cell and powered by a second supply voltage; A first metal rail and a second metal rail are disposed in the first front metallization layer of the plurality of front metallization layers and extend in the first lateral direction. The first metal rail and the second metal rail are configured to carry the first power supply voltage and the ground voltage respectively, and provide the power supply voltage to power the memory cell. A third metal track is disposed in the second front metallization layer of the plurality of front metallization layers and extends in the second lateral direction, the third metal track being configured to be operatively coupled to the word line of the memory cell; A fourth metal rail and a fifth metal rail are disposed in the third front metallization layer among the plurality of front metallization layers and extend in the first lateral direction. The fourth metal rail and the fifth metal rail are configured to carry the virtual power supply voltage and the ground voltage, respectively, and selectively provide the virtual power supply voltage to power the memory cell. A sixth metal rail is disposed in a first back-side metallization layer among a plurality of back-side metallization layers and extends in the first lateral direction, the sixth metal rail being configured to carry the first power supply voltage; as well as A seventh metal track is disposed in the second back-side metallization layer of the plurality of back-side metallization layers and extends in the second lateral direction, the seventh metal track being configured to carry the first power supply voltage.

9. The memory device of claim 8, further comprising a power switch configured to receive the first supply voltage and selectively supply the virtual supply voltage to the memory cell.

10. A method for forming a memory device, comprising: A memory array is formed on a first side of a substrate, the memory array comprising a plurality of memory cells powered by a first supply voltage; A peripheral circuit is formed on the first side of the substrate, the peripheral circuit being operatively coupled to the memory array and powered by a second supply voltage different from the first supply voltage; A first metallization layer is formed on the first side and above the memory array and the peripheral circuitry. The first metallization layer includes a plurality of first metal rails, each of which extends along a first lateral direction and is configured to carry the first supply voltage or ground voltage. A second metallization layer is formed on the first side and above the first metallization layer. The second metallization layer includes a plurality of second metal rails, each of which extends along a second lateral direction and is configured to be operatively coupled to one or more word lines of a plurality of memory cells. A third metallization layer is formed above the first side and the second metallization layer. The third metallization layer includes a plurality of third metal rails, each of which extends along the first lateral direction and is configured to carry only non-power signals and not the first power supply voltage. A fourth metallization layer is formed above the first side and the third metallization layer. The fourth metallization layer includes a plurality of fourth metal tracks, each of which extends along the second lateral direction and is configured only as a word line. A fifth metallization layer is formed on the second side of the substrate. The fifth metallization layer includes a plurality of fifth metal tracks, each of which extends along the first lateral direction and is configured to carry the first supply voltage or the ground voltage. as well as A sixth metallization layer is formed on the second side and above the fifth metallization layer. The sixth metallization layer includes a plurality of sixth metal rails, each of which extends along the second lateral direction and is configured to carry the first supply voltage or the ground voltage.

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