Chip and preparation method thereof, memory and electronic equipment

Abstract

The invention provides a chip, a preparation method of the chip, a memory and electronic equipment. A second channel or a first channel can be prevented from being too thin or too thick. The chip comprises a substrate and a transistor group arranged on the substrate, and the transistor group comprises a first transistor, a dielectric layer and a second transistor which are adjacent in sequence. The first transistor comprises a first gate structure, and a first electrode, a first channel, a second electrode and a first spacing layer which are sequentially stacked, and the side walls, deviating from the dielectric layer, in the first spacing layer, the second electrode and the first channel are flush. The second transistor comprises a second gate structure, and a third electrode, a second channel, a fourth electrode and a second spacing layer which are stacked in sequence; and the side walls, deviating from the dielectric layer, in the second spacing layer, the fourth electrode and the second channel are flush. The first spacing layer and the second spacing layer as well as the first channel and the second channel are symmetrical about the dielectric layer; in a first direction, a sidewall in the first spacer layer toward the dielectric layer is gradually away from the second transistor from being flush with sidewalls of the second pole and the first channel.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip and its fabrication method, a memory, and an electronic device. Background Technology

[0002] To continuously increase memory capacity, the size of memory cells is constantly shrinking. Vertical channel transistors are a key technology for achieving the miniaturization of memory cell size. In order to further improve the density of memory cells, engineers have proposed single-sided gate vertical transistors.

[0003] Single-gate vertical transistors are grouped together, with each group including a first transistor and a second transistor. The source, channel, and drain of the first and second transistors are obtained by etching stacked first conductive structures, semiconductor structures, and second conductive structures. However, with the continuous miniaturization of transistors and the use of existing non-self-aligned etching processes for the first, semiconductor, and second conductive structures, misalignment can occur. This results in a difference in channel thickness between the first and second transistors. A thicker channel may not be fully utilized, leading to a floating body effect; a thinner channel may lose its semiconductor properties, causing either the first or second transistor to fail. Furthermore, the difference in channel thickness between the first and second transistors can easily cause threshold voltage (Vth) drift. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a chip and its fabrication method, as well as an electronic device. The chip utilizes a symmetrical first spacer layer and a second spacer layer to protect the first and second channels, resulting in first and second channels with the same width. This avoids the first or second channel being too thick, which would prevent the first or second channel from being fully utilized; and avoids the second or first channel being too thin, which would cause the second or first channel to lose its semiconductor properties.

[0005] In a first aspect, this application provides a chip including a substrate and at least one transistor group disposed on the substrate, the transistor group including a first transistor, a dielectric layer and a second transistor sequentially adjacent to each other along a second direction, the first direction intersecting the second direction.

[0006] The first transistor includes: a first electrode, a first channel, a second electrode, and a first spacer layer, which are sequentially stacked along a first direction from the substrate toward the transistor group, wherein the sidewalls of the first spacer layer, the second electrode, and the first channel facing away from the dielectric layer are all flush. The first transistor also includes a first gate structure located on the side of the first channel facing away from the second transistor.

[0007] The second transistor includes a third electrode, a second channel, a fourth electrode, and a second spacer layer stacked sequentially along a first direction, wherein the sidewalls of the second spacer layer, the fourth electrode, and the second channel facing away from the dielectric layer are all flush. The first transistor also includes a second gate structure located on the side of the second channel facing away from the first transistor.

[0008] The first spacer layer and the second spacer layer, as well as the first channel and the second channel, are symmetrical about the dielectric layer. Along the first direction, the sidewall of the first spacer layer facing the dielectric layer is flush with the sidewall of the second electrode and the first channel, and gradually moves away from the second transistor.

[0009] In this application, a first conductive layer, a semiconductor layer, and a second conductive layer can be formed sequentially. Then, a first spacer layer and a second spacer layer are formed on the second conductive layer. Under the protection of the first spacer layer and the second spacer layer, the first conductive layer, the semiconductor layer, and the second conductive layer are partially removed. After the second conductive layer is partially removed, a second electrode and a fourth electrode are formed. After the semiconductor layer is partially removed, a first channel and a second channel are formed. After the first conductive layer is partially removed, a first electrode and a third electrode are formed.

[0010] Since the sidewalls of the first spacer layer, the second electrode, and the first channel that are away from the dielectric layer are all flush, and the portion of the sidewall of the first spacer layer facing the dielectric layer that is close to the substrate is flush with the sidewalls of the second electrode and the first channel, the first spacer layer can serve as a protective layer for the second electrode, the first channel, and the first electrode during the partial removal of the first conductive layer, the semiconductor layer, and the second conductive layer.

[0011] Since the sidewalls of the second spacer layer, the fourth electrode, and the second channel that are away from the dielectric layer are all flush, and the portion of the sidewall of the second spacer layer facing the dielectric layer that is close to the substrate is flush with the sidewalls of the fourth electrode and the second channel, the second spacer layer can serve as a protective layer for the fourth electrode, the second channel, and the third electrode during the partial removal of the first conductive layer, the semiconductor layer, and the second conductive layer.

[0012] During the partial removal of the first conductive layer, semiconductor layer, and second conductive layer, the etching material will damage the first spacer layer and the second spacer layer. The portion of the first spacer layer and the second spacer layer that is further away from the substrate is more affected by the etching material. Therefore, along the first direction, the first sidewall of the first spacer layer gradually moves away from the second transistor, and the sidewall of the second spacer layer gradually moves away from the first transistor.

[0013] In this case, because the first and second spacer layers are symmetrical about the dielectric layer, their widths are the same. Thus, under the protection of the first and second spacer layers, the widths of the first and second channels obtained through the partial removal process are also the same. This solves the problem of different channel thicknesses between the first and second transistors obtained by non-self-aligned photolithography, preventing either the first or second channel from being too thick, which would result in incomplete depletion; and preventing the second or first channel from being too thin, which would result in the loss of semiconductor properties. Furthermore, because the first channel of the first transistor and the second channel of the second transistor have the same thickness in the second direction, threshold voltage Vth drift in both transistors can also be avoided.

[0014] It should be understood that during the partial removal of the second conductive layer, semiconductor layer, and first conductive layer under the protection of the first and second spacer layers, the sidewalls of the first spacer layer facing the second spacer layer and the sidewalls of the second spacer layer facing the first spacer layer will also be damaged by the etching material. Since the first and second spacer layers are disposed on the side of the stacked structure away from the substrate, the portions of the first and second spacer layers further away from the substrate are more severely damaged. This results in the sidewalls of the first spacer layer facing the second spacer layer gradually moving away from the second transistor from being flush with the second electrode along the first direction; and the sidewalls of the second spacer layer facing the first spacer layer gradually moving away from the first transistor from being flush with the fourth electrode.

[0015] Alternatively, the width of the portion of the first spacer layer closer to the substrate in the second direction is greater than or equal to the width of the portion of the first spacer layer farther from the substrate in the second direction. Furthermore, the width of the surface of the first spacer layer facing the substrate in the second direction is greater than the width of the surface of the first spacer layer facing away from the substrate in the second direction.

[0016] The width of the portion of the second spacer layer closer to the substrate in the second direction is greater than or equal to the width of the portion of the second spacer layer farther from the substrate in the second direction. Furthermore, the width of the surface of the second spacer layer facing the substrate in the second direction is greater than the width of the surface of the second spacer layer facing away from the substrate in the second direction.

[0017] Based on the above, this application does not limit the specific shape of the sidewall of the first spacer layer facing the second spacer layer, or the sidewall of the second spacer layer facing the first spacer layer, as their shapes are related to the etching material, etching conditions, etc. For example, the shape of the sidewall of the first spacer layer facing the second spacer layer, or the sidewall of the second spacer layer facing the first spacer layer, can be a slope, an arc, a step, etc.

[0018] In some possible implementations, the surfaces of the first spacer layer and the second spacer layer that contact the dielectric layer are curved. The fact that the surfaces of the first and second spacers that contact the dielectric layer are curved indicates that the first and second spacers are not etched through to form vias by the etching material. Therefore, the etching material will not etch the second conductive layer, the semiconductor layer, or the first conductive layer through these vias, thus preventing it from affecting the structure and performance of the second electrode, the fourth electrode, the first channel, the second channel, the first electrode, and the third electrode to be formed.

[0019] In some possible implementations, the chip includes multiple sets of transistors, with the first transistor further including a third spacer layer and the second transistor further including a fourth spacer layer. The third spacer layer covers the sidewall of the second transistor facing away from the fourth transistor and the surface of the first gate structure facing away from the substrate, while the fourth spacer layer covers the sidewall of the fourth transistor facing away from the second transistor and the surface of the second gate structure facing away from the substrate. The first gate structure is flush with the sidewall of the third spacer layer facing away from the dielectric layer, and the second gate structure is flush with the sidewall of the fourth spacer layer facing away from the dielectric layer. The first gate structure and the second gate structure are symmetrical about the dielectric layer.

[0020] Since the third spacer layer covers the surface of the first gate structure away from the substrate, and the fourth spacer layer covers the surface of the second gate structure away from the substrate, and the sidewalls of the first gate structure and the third spacer layer away from the dielectric layer are flush, and the sidewalls of the second gate structure and the fourth spacer layer away from the dielectric layer are flush, the third spacer layer can serve as a protective layer for the first gate structure and the fourth spacer layer can serve as a protective layer for the second gate structure during the formation of the first gate structure and the second gate structure.

[0021] During the process of forming the first gate structure and the second gate structure using photolithography, the etching material will affect the third spacer layer and the fourth spacer layer. The part of the third spacer layer that is further away from the substrate is more affected by the etching material. Therefore, along the first direction, the sidewall of the third spacer layer facing the dielectric layer gradually moves away from the second transistor, and the sidewall of the fourth spacer layer facing the dielectric layer gradually moves away from the first transistor.

[0022] In this case, by making the widths of the third and fourth spacers the same, the first gate structure and the second gate structure can be made symmetrical about the dielectric layer. That is, under the protection of the third and fourth spacers, the widths of the first gate structure and the second gate structure obtained by the partial removal process are also the same. By simply controlling the widths of the first gate dielectric and the second gate dielectric to be the same, the widths of the first gate and the second gate in the first direction can be made the same, thus avoiding the problem of threshold voltage Vth drift in the first transistor and the second transistor.

[0023] In some possible implementations, the chip also includes bit lines disposed between the substrate and the first and third electrodes, with the bit lines in direct contact with the first and third electrodes.

[0024] By placing the bit line BL on the same side of the substrate as the first electrode of the first transistor and the third electrode of the second transistor, the bit line is electrically connected to the first electrode of the first transistor and the third electrode of the second transistor. This eliminates the need for leads to achieve electrical connection, thereby avoiding the increased impedance caused by leads and the resulting RC delay.

[0025] Secondly, this application provides a memory including a controller and the chip described in the first aspect, wherein the controller is used to control the chip to read and write data.

[0026] The second aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the second aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0027] Thirdly, this application provides an electronic device including a circuit board and the memory described in the second aspect, the memory being disposed on the circuit board.

[0028] The third aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the third aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0029] Fourthly, this application provides a method for fabricating a chip, comprising: forming a plurality of stacked structures spaced apart on a substrate; the stacked structures include a first conductive pattern, a semiconductor pattern, and a second conductive pattern stacked sequentially along a first direction, and the plurality of stacked structures arranged along a second direction. A first dummy gate and a second dummy gate are formed on opposite sides of the stacked structures, respectively. A first spacer layer and a second spacer layer are formed on the side of the second conductive layer away from the substrate, the sidewall of the first spacer layer contacts the sidewall of the first dummy gate, the sidewall of the second spacer layer contacts the sidewall of the second dummy gate, and the widths of the first spacer layer and the second spacer layer are the same in the second direction. Under the protection of the first spacer layer and the second spacer layer, the stacked structures are partially removed to obtain a second electrode, a first channel, a first terminal of a first transistor, and a fourth electrode, a second channel, and a third electrode of a second transistor; the first electrode, the first channel, and the second electrode are stacked sequentially along the first direction, and the third electrode, the second channel, and the fourth electrode are stacked sequentially.

[0030] The sidewall of the first spacer layer is in contact with the sidewall of the first dummy gate. The first spacer layer is disposed on the side of the stacked structure away from the first substrate, and the first dummy gate is disposed on one side of the stacked structure. It can be concluded that the first dummy gate protrudes from the stacked structure along the first direction. In other words, the distance from the first dummy gate to the first substrate is greater than the distance from the stacked structure to the first substrate.

[0031] Similarly, the sidewall of the second spacer layer is in contact with the sidewall of the second dummy gate. The second spacer layer is disposed on the side of the stacked structure away from the first substrate, and the second dummy gate is disposed on one side of the stacked structure. It can be concluded that the second dummy gate protrudes from the stacked structure along the first direction. In other words, the distance from the second dummy gate to the first substrate is greater than the distance from the stacked structure to the first substrate.

[0032] Before the protective layer is removed, the first dummy gate and the second dummy gate are respectively located on opposite sides of the stacked structure and the protective layer located above the stacked structure. Therefore, the stacked structure and the protective layer before removal mark the setting position and height of the first dummy gate and the second dummy gate.

[0033] Furthermore, since the first dummy gate and the second dummy gate protrude from the stacked structure in the first direction, when forming the first spacer layer and the second spacer layer, the first dummy gate can be used to mark the setting position of the first spacer layer, and the second dummy gate can be used to mark the setting position of the second spacer layer.

[0034] Alternatively, the stacked structure and the removed protective layer are used to align the first and second dummy gates, the first dummy gate is used to align the first spacer layer, and the second dummy gate is used to align the second spacer layer.

[0035] Furthermore, by making the widths of the first and second spacer layers the same, and using the first and second spacer layers as masks to partially remove the stacked structure, the widths of the first and second channels obtained are the same (the widths of the first and second channels are the same as the widths of the first and second spacer layers). This solves the problem of different channel thicknesses between the first and second transistors obtained by non-self-aligned photolithography, avoiding the first or second channel being too thick, which would prevent the first or second channel from being fully utilized; and avoiding the second or first channel being too thin, which would cause the second or first channel to lose its semiconductor properties.

[0036] In some possible implementations, during the partial removal of the stacked structure under the protection of the first and second spacer layers, the sidewalls of the first spacer layer facing the second spacer layer and the sidewalls of the second spacer layer facing the first spacer layer are also damaged by the etching material. Since the first and second spacer layers are located on the side of the stacked structure away from the first substrate, the portions of the first and second spacer layers further away from the stacked structure are more severely damaged. This results in the sidewall of the first spacer layer facing the second spacer layer gradually moving away from the second transistor from being flush with the second electrode along the first direction; and the sidewall of the second spacer layer facing the first spacer layer gradually moving away from the first transistor from being flush with the fourth electrode.

[0037] In some possible implementations, along a first direction, the substrate includes a first substrate and a second substrate stacked together. Before forming the stacked structure on the substrate, the chip fabrication method further includes: sequentially forming a first conductive layer, a semiconductor layer, and a second conductive layer on the second substrate. Partial removal of the second conductive layer, the semiconductor layer, the first conductive layer, and the second substrate yields a plurality of intermediate patterns for the second conductive layer, a plurality of intermediate patterns for the semiconductor layer, a plurality of intermediate patterns for the first conductive layer, and a plurality of intermediate patterns for the substrate. The intermediate patterns for the second conductive layer, the semiconductor layer, the first conductive layer, and the substrate are all arranged along a third direction. Shallow trench isolation layers are filled between adjacent intermediate patterns for the second conductive layer, adjacent intermediate patterns for the semiconductor layer, adjacent intermediate patterns for the first conductive layer, and adjacent substrate patterns.

[0038] Forming multiple stacked structures spaced apart on a substrate includes: forming a protective layer on the side of multiple second conductive layer intermediate patterns and shallow trench isolation layers facing away from the first substrate. Under the protection of the protective layer, the intermediate patterns of multiple second conductive layers, multiple semiconductor layer intermediate patterns, and multiple first conductive layer intermediate patterns are partially etched to obtain multiple stacked structures arranged along a second direction.

[0039] Using a single photomask, partial etching is performed on the second conductive layer, semiconductor layer, first conductive layer, and second substrate. The etched second substrate can reserve space for subsequent bit lines. In the bit line formation process after removing the intermediate patterns of multiple substrates, alignment is unnecessary; multiple bit lines are simply formed at the locations where the intermediate patterns of the removed substrates were found. This eliminates the need for patterning the bit lines (BLs), thus saving fabrication costs and improving yield. Optionally, a single photomask can be used to partially etch the second conductive layer, semiconductor layer, first conductive layer, and second substrate in one operation, avoiding misalignment issues that can occur with multiple etching steps, such as the intermediate patterns of the second conductive layer, multiple semiconductor layers, multiple first conductive layers, and multiple substrates.

[0040] In some possible implementations, the substrate further includes a third substrate disposed on the side of the second substrate opposite to the first substrate, the third substrate being made of a semiconductor material. Forming a first conductive layer on the second substrate includes doping the third substrate to obtain the first conductive layer. By using the doped third substrate as the first conductive layer, the thickness of the chip can be further reduced.

[0041] For example, if the first transistor and / or the second transistor to be formed is a P-type transistor, then the third substrate can be heavily doped with boron (B) to obtain a P-type first conductive layer.

[0042] For example, if the first transistor and / or the second transistor to be formed is an N-type transistor, then the third substrate can be heavily doped with phosphorus (P) or arsenic (As) to obtain an N-type first conductive layer.

[0043] In some possible implementations, after partially removing the stacked structure under the protection of the first and second spacer layers, the chip fabrication method further includes: filling a dielectric layer between the first and third electrodes, between the first and second channels, and between the second and fourth electrodes in each stacked structure; removing the first and second dummy gates; forming a first bottom spacer layer covering the first electrode and a second bottom spacer layer covering the third electrode; forming a gate structure on the side of the first and second bottom spacers facing away from the substrate; the gate structure at least partially coincides with the orthogonal projection of the first and second channels onto the dielectric layer; forming a third and fourth spacer layers spaced apart on the side of the gate structure facing away from the substrate; the third spacer layer covers the sidewalls of the first and second electrodes; the fourth spacer layer covers the sidewalls of the second and fourth electrodes; and the third and fourth spacer layers have the same width in the second direction. Under the protection of the third and fourth spacer layers, the gate structure is partially removed to obtain the first gate structure of the first transistor and the second gate structure of the second transistor. The first gate structure includes a first gate and a first gate dielectric for isolating the first gate from the first channel. The second gate structure includes a second gate and a second gate dielectric for isolating the second gate from the second channel.

[0044] It should be understood that the first and second spacer layers protrude from the partially removed gate structure. During the formation of the third spacer layer, the first spacer layer (or the first spacer layer and the second electrode) can be used to mark the position and height of the third spacer layer. During the formation of the fourth spacer layer, the second spacer layer (or the second spacer layer and the fourth electrode) can be used to mark the position and height of the fourth spacer layer.

[0045] Alternatively, it can be said that the first spacer layer (or the first spacer layer and the second pole) is used to align the third spacer layer, and the second spacer layer (or the second spacer layer and the fourth pole) is used to align the fourth spacer layer.

[0046] Furthermore, by making the widths of the third and fourth spacer layers the same in the second direction, after partially removing the gate structure using the first and second spacer layers as masks, the thickness of the first gate structure in the second direction is the same as the thickness of the second gate structure in the second direction (the thicknesses of the first gate structure, the second gate structure, the third spacer layer, and the fourth spacer layer in the second direction are all the same).

[0047] Existing technology uses non-self-aligned photolithography to obtain the first gate structure of the first transistor and the second gate structure of the second transistor. During the etching process of the gate structure, misalignment may occur, resulting in different thicknesses of the first gate structure and the second gate structure after etching. This leads to different thicknesses of the first gate of the first transistor and the second gate of the second transistor. The first gate or the second gate may be too thick, and the second gate or the first gate may be too thin, resulting in the problem of threshold voltage Vth drift of the first transistor or the second transistor.

[0048] In this application, since the total thickness of the first gate structure in the second direction is the same as the total thickness of the second gate structure in the second direction, it is only necessary to control the width of the first gate dielectric and the second gate dielectric to be the same in the second direction, so that the width of the first gate and the second gate in the second direction is the same, thus avoiding the problem of threshold voltage Vth drift in the first transistor and the second transistor.

[0049] In some possible implementations, the materials of the first substrate and the second substrate are different; after obtaining the first gate and the second gate, the chip fabrication method further includes: removing the first substrate using the second substrate as an etch stop layer.

[0050] When using the second substrate as an etching stop layer to remove the first substrate, the etching material will not damage the first and third electrodes.

[0051] In some possible implementations, the material of the first substrate includes silicon, and the material of the second substrate includes silicon oxide.

[0052] The first and second substrates are made of different materials. When etching the first substrate, the etching material has a larger etching selectivity ratio with the material of the second substrate. Therefore, the second substrate can be used as an etching stop layer. Furthermore, for the second substrate, compared to schemes such as doping silicon carbide (SiC) into bulk silicon, heavily doping boron (B) into bulk silicon, including germanium (Ge) or germanium-silicon (SiGe) in the second substrate, and implanting other elements into the bulk silicon, the second substrate containing silicon oxide is a dielectric material. Even if some remains after removal, it will not cause short circuits in the conductive structures of the first and second transistors.

[0053] In some possible implementations, after removing the first substrate, the chip fabrication method further includes removing the second substrate. Bit lines are formed on the side of the first and third electrodes opposite to the first and second channels, and these bit lines are in direct contact with the first and third electrodes.

[0054] Using a photomask, the second conductive layer, semiconductor layer, first conductive layer, and second substrate are partially etched. Then, shallow trench isolation layers are filled between adjacent patterns in the second conductive layer, adjacent patterns in the semiconductor layer, adjacent patterns in the first conductive layer, and adjacent substrate patterns. After removing multiple substrate intermediate patterns, the shallow trench isolation layer comprises multiple grooves filled with multiple substrate intermediate patterns.

[0055] After removing the intermediate patterns of multiple substrates, bit lines can be directly filled into the grooves, eliminating the need for bit line patterning steps, thus saving fabrication costs and improving yield. Optionally, a single mask can be used to partially etch the second conductive layer, semiconductor layer, first conductive layer, and second substrate in one go, avoiding misalignment issues caused by multiple etching steps, which can result in misalignment of the intermediate patterns of the second conductive layer, multiple semiconductor layer patterns, multiple first conductive layer patterns, and multiple substrate patterns.

[0056] Meanwhile, by placing the bit line on the same side of the substrate as the first electrode of the first transistor and the third electrode of the second transistor—that is, in a buried bit line scheme—the area occupied by the bit line can be saved, effectively promoting chip miniaturization. Furthermore, the bit line can directly contact the first electrode of the first transistor and the third electrode of the second transistor to achieve electrical connection, eliminating the need for leads and thus avoiding the increased impedance caused by leads, which leads to RC delay.

[0057] The fourth aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the fourth aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here. Attached Figure Description

[0058] Figure 1a This is a diagram showing the relationship between the modules in the electronic device provided in the embodiments of this application;

[0059] Figure 1b An interaction diagram of the various modules in the memory provided in the embodiments of this application;

[0060] Figure 2 A top view of multiple storage cells in a storage array provided in an embodiment of this application;

[0061] Figure 3 A structural diagram of a single-sided gate vertical transistor provided for related technologies;

[0062] Figure 4a A diagram illustrating the fabrication process of a single-sided gate vertical transistor for related technologies;

[0063] Figure 4b A diagram illustrating the fabrication process of a single-sided gate vertical transistor for related technologies;

[0064] Figure 5 A flowchart illustrating the fabrication process of a memory chip provided in an embodiment of this application;

[0065] Figure 6a A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0066] Figure 6b A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0067] Figure 6c A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0068] Figure 6d A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0069] Figure 6e A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0070] Figure 6f A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0071] Figure 6g A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0072] Figure 6h A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0073] Figure 7a A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0074] Figure 7b A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0075] Figure 7c A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0076] Figure 7d A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0077] Figure 7e A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0078] Figure 7f A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0079] Figure 7g A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0080] Figure 7h A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0081] Figure 8a A diagram illustrating the fabrication process of a single-sided gate vertical transistor for related technologies;

[0082] Figure 8b A diagram illustrating the fabrication process of a single-sided gate vertical transistor for related technologies;

[0083] Figure 9a A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0084] Figure 9b A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0085] Figure 10a A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0086] Figure 10b A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0087] Figure 10c A process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application;

[0088] Figure 10d This is a process diagram illustrating the fabrication of a memory chip provided in an embodiment of this application.

[0089] Figure label:

[0090] Substrate - 10; 101 - First substrate; 102 - Second substrate; 1021 - Substrate center pattern; 103 - Third substrate; 11 - First conductive layer; 111 - First conductive layer center pattern; 112 - First conductive pattern; 113 - First electrode; 114 - Third electrode; 12 - Semiconductor layer; 121 - Semiconductor layer center pattern; 122 - Semiconductor pattern; 123 - First channel; 124 - Second channel; 13 - Second conductive layer; 131 - Second conductive layer center pattern; 132 - Second conductive layer Electrical pattern; 133-Second electrode; 134-Fourth electrode; 14-Gate structure; 141-First gate structure; 142-Second gate structure; 21-Shallow trench isolation layer; 22-Protective layer; 231-First dummy gate; 232-Second dummy gate; 241-First spacer layer; 242-Second spacer layer; 25-Dielectric layer; 261-First bottom spacer layer; 262-Second bottom spacer layer; 271-Third spacer layer; 272-Fourth spacer layer; 31-Dielectric material; 32-Capacitor; 40-Substrate. Detailed Implementation

[0091] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0092] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0093] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0094] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0095] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0096] This application provides an electronic device, which may be a device containing transistors, such as a consumer electronics product, a home electronics product, an automotive electronics product, a financial terminal product, or a communication electronics product.

[0097] Consumer electronics include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics include smart door locks, televisions, smart speakers, refrigerators, and robot vacuum cleaners. In-vehicle electronics include car navigation systems and in-vehicle displays. Financial terminal products include automated teller machines (ATMs) and self-service terminals. Communication electronics include servers, memory, radar, base stations, and other communication equipment containing transistors.

[0098] Figure 1a This application provides a schematic diagram of the structure of a memory in an electronic device. The electronic device includes a memory and other chips or independent devices, which may include a processor. Figure 1b As shown, the memory includes a storage array, a controller, row decoders, column decoders, etc. The processor can send the address of the selected storage cell to the row decoders and column decoders through the controller. After decoding the received address, the row decoders and column decoders determine the storage cell in the storage array as the selected storage cell, and then perform read and write operations on the selected storage cell. The storage cell includes transistors and capacitors.

[0099] To continuously increase memory capacity, the storage cells of dynamic random access memory (DRAM) are constantly shrinking, and have now increased from 8F. 2 Architecture evolution to 6F 2 Architecture, even 4F 2 Architecture. Among them, 4F 2 With minimal architectural changes and the lowest level of difficulty, it is the most likely candidate for rapid mass production. For example... Figure 2 As shown, 4F 2 This means that, assuming the pitch between adjacent memory cells is the same, if the sum of the single-side dimension of any memory cell and the pitch between that memory cell and its adjacent memory cells is 2F, then the area occupied by that memory cell is 4F. 2 .

[0100] Vertical channel transistors are used to achieve 4F 2 The most critical technology in the structure. To improve storage density, engineers proposed vertical transistors with single-sided gates. For example... Figure 3 As shown, single-sided gate vertical transistors are arranged in groups. Each group of single-sided gate vertical transistors includes a first transistor and a second transistor. Both the first and second transistors include a first electrode 011, a channel 021, a second electrode 031, and a gate structure 041. The gate structure 041 includes a gate dielectric and a gate. The first electrode 011, channel 021, and second electrode 031 of the first and second transistors are stacked sequentially. The gate structure 041 of the first transistor is located on the side of the channel 021 of the first transistor facing away from the second transistor, and the gate structure 041 of the second transistor is located on the side of the channel 021 of the second transistor facing away from the first transistor. The first electrode 011 is the source, and the second electrode 031 is the drain; or, the first electrode 011 is the drain, and the second electrode 031 is the source.

[0101] like Figure 4a and Figure 4b As shown, the first electrode 011, channel 021, and second electrode 031 of the first and second transistors are obtained by etching a stacked first conductive structure 01, semiconductor structure 02, and second conductive structure 03. With the continuous miniaturization of transistors and the use of existing non-self-aligned etching processes for the first conductive structure, semiconductor structure, and second conductive structure, misalignment can occur during the etching process. This results in a difference in the thickness of the channel 021 between the first and second transistors. A thicker channel 021 may not be fully utilized, leading to a floating body effect; a thinner channel 021 may lose its semiconductor properties, causing either the first or second transistor to fail. Furthermore, the difference in channel 021 thickness between the first and second transistors can easily cause threshold voltage Vth drift.

[0102] To address the issue of uneven channel thickness between the first and second transistors caused by existing processes, embodiments of this application provide a chip fabrication method, such as... Figure 5 As shown, this can be achieved through the following steps:

[0103] S110, such as Figure 6aand Figure 6b (In the accompanying drawings involving three views, the top view with double-headed arrows in the XY direction corresponds to the cross-section of the top view, which indicates the side view in the XZ direction and the side view in the YZ direction, respectively, and will not be described again below.) As shown, a first conductive layer 11, a semiconductor layer 12, and a second conductive layer 13 are sequentially formed on the substrate 10.

[0104] In some possible implementations, the embodiments of this application do not limit the material and structure of the substrate 10. Optionally, the substrate 10 can be a single layer or a stack.

[0105] Taking a single layer as an example, the material of substrate 10 may include silicon.

[0106] Taking substrate 10 as an example of a stack, such as Figure 6a As shown, the substrate 10 can be silicon on insulator (SOI). Along the first direction (hereinafter referred to as the Z direction) pointing from the substrate 10 to the first conductive layer 11, the silicon on insulator includes a first substrate 101, a second substrate 102, and a third substrate 103 stacked sequentially. The material of the second substrate 102 may include silicon oxide (BOX), and the materials of the first substrate 101 and the third substrate 103 may include silicon.

[0107] The thickness of the second substrate 102 and the third substrate 103 of the SOI substrate are relatively uniform, resulting in high quality. Furthermore, since the etching selectivity of the material of the second substrate 102 is relatively large compared to that of the first substrate 101 and the third substrate 103, the second substrate 102 can also be used as an etch stop layer (ESL). During the subsequent etching of the first substrate 101, the second substrate 102 can be used to protect the third substrate 103 from damage; and during the subsequent etching of the second substrate 102, the third substrate 103 (the first and third electrodes in step S220) will not be damaged.

[0108] Furthermore, the materials of the first substrate 101 and the third substrate 103 are still silicon, and the material of the second substrate 102 is bulk silicon doped with silicon carbide (SiC); or, the material of the second substrate 102 includes germanium (Ge) or germanium-silicon (SiGe); or, the material of the second substrate 102 is bulk silicon heavily doped with boron (B); or, other elements are implanted into the bulk silicon, for example, using smart-cut technology to implant elements such as hydrogen (H) or helium (He). The second substrate 102 formed using any of the above methods can serve as an etching stop layer.

[0109] Regarding the second substrate 102, compared to solutions such as doping silicon carbide (SiC) into bulk silicon, heavily doping boron (B) into bulk silicon, the second substrate 102 containing germanium (Ge) or germanium-silicon (SiGe), and implanting other elements into bulk silicon, the second substrate 102 containing silicon oxide is a dielectric material. Even if some residue remains after removal, it will not cause short circuits in the conductive structures of the first transistor and the second transistor.

[0110] For the second substrate 102, compared to schemes such as doping silicon carbide (SiC) into bulk silicon, heavily doping boron (B) into bulk silicon, the second substrate 102 containing either germanium (Ge) or germanium-silicon (SiGe), and implanting other elements into bulk silicon, the second substrate 102 containing silicon oxide has a higher etching selectivity than the first substrate 101 and the third substrate 103.

[0111] For ease of description, unless otherwise stated, the following description will use the example of a substrate 10 including a first substrate 101, a second substrate 102, and a third substrate 103.

[0112] In some possible implementations, the materials of the first conductive layer 11 and the second conductive layer 13 are not limited, as long as the materials of the first conductive layer 11 and the second conductive layer 13 include conductive materials.

[0113] In the case where the substrate 10 includes a third substrate 103, the first conductive layer 11 can be obtained by heavily doping the third substrate 103.

[0114] For example, if the first transistor and / or the second transistor to be formed is a P-type transistor, then the third substrate 103 can be heavily doped with boron (B) to obtain a P-type first conductive layer 11.

[0115] For example, if the first transistor and / or the second transistor to be formed is an N-type transistor, the third substrate 103 can be heavily doped with phosphorus P or arsenic As to obtain an N-type first conductive layer 11.

[0116] Furthermore, regardless of whether the substrate 10 includes the third substrate 103, the first conductive layer 11 can be formed directly on the substrate 10.

[0117] In some possible implementations, the material of the semiconductor layer 12 is not limited in the present application embodiments. The material of the semiconductor layer 12 may include at least one of single crystal, polycrystalline, amorphous silicon Si, germanium silicon SiGe, germanium Ge, oxide semiconductor, etc.

[0118] S120, such as Figure 6cAs shown, the second conductive layer 13, semiconductor layer 12, first conductive layer 11, and second substrate 102 are partially removed to obtain multiple intermediate patterns 131 of the second conductive layer, multiple intermediate patterns 121 of the semiconductor layer, multiple intermediate patterns 131 of the first conductive layer, and multiple intermediate patterns 1021 of the substrate. The multiple intermediate patterns 131 of the second conductive layer, the multiple intermediate patterns 121 of the semiconductor layer, the multiple intermediate patterns 111 of the first conductive layer, and the multiple intermediate patterns 1021 of the substrate are all arranged along a third direction (hereinafter collectively referred to as the X direction). Next, as... Figure 6c As shown, shallow trench isolation (STI) 21 is filled between adjacent second conductive layer intermediate patterns 131, adjacent semiconductor layer intermediate patterns 121, adjacent first conductive layer intermediate patterns 111, and adjacent substrate patterns 1021.

[0119] The chip formed in step S120 has a transistor group consisting of the first transistor and the second transistor arranged along the X direction, and adjacent transistor groups are isolated by a shallow trench isolation layer 21.

[0120] In some possible implementations, a mask is used to partially etch the second conductive layer 13, the semiconductor layer 12, the first conductive layer 11, and the second substrate 102. The etched second substrate 102 can reserve space for the bit line (BL) formed in the subsequent step S230. In the process of forming the bit line BL after removing multiple substrate intermediate patterns 1021, no alignment is required. Multiple bit lines BL only need to be formed at the locations where the multiple substrate intermediate patterns 1021 have been removed, eliminating the need for patterning the bit line BL, thereby saving fabrication costs and improving yield. Optionally, a single mask can be used to partially etch the second conductive layer 13, the semiconductor layer 12, the first conductive layer 11, and the second substrate 102 in one go, avoiding the misalignment problem caused by multiple etching steps, which could result in misalignment of the second conductive layer intermediate pattern 131, multiple semiconductor layer intermediate patterns 121, multiple first conductive layer intermediate patterns 131, and multiple substrate intermediate patterns 1021.

[0121] Of course, if the chip does not include bit lines BL, or if the chip is used in other fields and the second substrate 102 needs to be retained, then the mask can be used to partially etch the second conductive layer 13, the semiconductor layer 12, and the first conductive layer 11, without needing to partially etch the second substrate 102.

[0122] In some possible implementations, the material of the shallow trench isolation layer 21 is not limited in the embodiments of this application, as long as the material of the shallow trench isolation layer 21 is an insulating material.

[0123] For example, the material of the shallow trench isolation layer 21 may include at least one of silicon carbon nitride (SiCN), silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon boron nitride (SiBN), silicon oxycarbon nitride (SiOC), silicon oxycarbon nitride (SiOCN), and silicon boron carbon nitride (SiCBN).

[0124] S130, such as Figure 6d As shown, a protective layer 22 is formed on the side of the multiple second conductive layer intermediate patterns 131 and the shallow trench isolation layer 21 facing away from the first substrate 101. Under the protection of the protective layer 22, the multiple second conductive layer intermediate patterns 131, the multiple semiconductor layer intermediate patterns 121, and the multiple first conductive layer intermediate patterns 111 are partially etched to obtain multiple stacked structures arranged along the second direction (hereinafter collectively referred to as the Y direction). The stacked structure includes a first conductive pattern 112, a semiconductor pattern 122, and a second conductive pattern 132 sequentially stacked along the Z direction.

[0125] In some possible implementations, the material of the protective layer 22 is not limited in this application embodiment. For example, the material of the protective layer 22 includes silicon nitride (SiN). Taking the material of the protective layer 22 as silicon nitride (SiN) as an example, the subsequent step S150 can use wet etching to remove the protective layer 22.

[0126] S140, such as Figure 6e As shown, a first dummy gate 231 and a second dummy gate 232 are formed on opposite sides of the stacked structure, and the first dummy gate 231 and the second dummy gate 232 are arranged along the Y direction.

[0127] In some possible implementations, the materials of the first dummy gate 231 and the second dummy gate 232 may include polysilicon or silicon oxide. Optionally, a dielectric material (e.g., silicon dioxide) may be formed on opposite sides of the stacked structure as a spacer, and then the first dummy gate 231 and the second dummy gate 232 may be formed on the dielectric material, so that the first dummy gate 231 and the second dummy gate 232 may be selectively removed in the subsequent step S170.

[0128] S150, such as Figure 6f and Figure 6g As shown, after removing the protective layer 22, a first spacer layer 241 and a second spacer layer 242 are formed on the side of the stacked structure facing away from the first substrate 101. The sidewall of the first spacer layer 241 contacts the sidewall of the first dummy gate 231, and the sidewall of the second spacer layer 242 contacts the sidewall of the second dummy gate 232. The first spacer layer 241 and the second spacer layer 242 have the same width in the Y direction. Next, as... Figure 6hAs shown, under the protection of the first spacer layer 241 and the second spacer layer 242, the stacked structure is partially removed to obtain the second electrode 133, the first channel 123, and the first electrode 113 of the first transistor, and the fourth electrode 134, the second channel 124, and the third electrode 114 of the second transistor. Along the Z direction, the first electrode 113, the first channel 123, and the second electrode 133 are stacked sequentially, and the third electrode 114, the second channel 124, and the fourth electrode 134 are stacked sequentially.

[0129] It should be understood that the sidewall of the first spacer layer 241 is in contact with the sidewall of the first dummy gate 231. The first spacer layer 241 is disposed on the side of the stacked structure away from the first substrate 101, and the first dummy gate 231 is disposed on the side of the stacked structure. It can be concluded that the first dummy gate 231 protrudes from the stacked structure along the Z direction. In other words, the distance from the first dummy gate 231 to the first substrate 101 is greater than the distance from the stacked structure to the first substrate 101.

[0130] Similarly, the sidewall of the second spacer layer 242 is in contact with the sidewall of the second dummy gate 232. The second spacer layer 242 is disposed on the side of the stacked structure away from the first substrate 101, and the second dummy gate 232 is disposed on the side of the stacked structure. It can be concluded that the second dummy gate 232 protrudes from the stacked structure along the Z direction. In other words, the distance from the second dummy gate 232 to the first substrate 101 is greater than the distance from the stacked structure to the first substrate 101.

[0131] As can be seen from step S140, before the protective layer 22 is removed, the first dummy gate 231 and the second dummy gate 232 are respectively disposed on opposite sides of the stacked structure and the protective layer 22 located above the stacked structure. Thus, the stacked structure and the protective layer 22 before removal mark the placement position and height of the first dummy gate 231 and the second dummy gate 232.

[0132] Furthermore, since the first dummy gate 231 and the second dummy gate 232 protrude from the stacked structure in the Z direction, when forming the first spacer layer 241 and the second spacer layer 242, the first dummy gate 231 can be used to mark the setting position of the first spacer layer 241, and the second dummy gate 232 can be used to mark the setting position of the second spacer layer 242.

[0133] Alternatively, the stacked structure and the removed protective layer 22 are used to align the first dummy gate 231 and the second dummy gate 232. The first dummy gate 231 is used to align the first spacer layer 241, and the second dummy gate 232 is used to align the second spacer layer 242. In this way, the first spacer layer 241 is flush with the sidewalls of the second electrode 133, the first channel 123, and the first electrode 113 that are to be formed, on the side opposite to the dielectric layer 25. The second spacer layer 242 is flush with the sidewalls of the fourth electrode 134, the second channel 124, and the third electrode 114 that are to be formed, on the side opposite to the dielectric layer 25.

[0134] Furthermore, by making the widths of the first spacer layer 241 and the second spacer layer 242 the same in the Y direction, and after partially removing the stacked structure using the first spacer layer 241 and the second spacer layer 242 as masks, the widths of the first channel 123 and the second channel 124 obtained are the same in the Y direction (the widths of the first channel 123 and the second channel 124 in the Y direction are the same as the widths of the first spacer layer 241 and the second spacer layer 242 in the Y direction). This solves the problem of different thicknesses of the channel 021 of the first transistor and the channel 021 of the second transistor obtained by non-self-aligned photolithography, avoiding the first channel 123 or the second channel 124 being too thick, which would cause the first channel 123 or the second channel 124 to not be fully depleted; and avoiding the second channel 124 or the first channel 123 being too thin, which would cause the second channel 124 or the first channel 123 to lose its semiconductor properties.

[0135] In some possible implementations, during the partial removal of the stacked structure under the protection of the first spacer layer 241 and the second spacer layer 242, the sidewalls of the first spacer layer 241 facing the second spacer layer 242 and the sidewalls of the second spacer layer 242 facing the first spacer layer 241 are also damaged by the etching material. Since the first spacer layer 241 and the second spacer layer 242 are located on the side of the stacked structure away from the first substrate 101, the portions of the first spacer layer 241 and the second spacer layer 242 that are further away from the stacked structure are more severely damaged. This results in the sidewall of the first spacer layer 241 facing the second spacer layer 242 gradually moving away from the second transistor from being flush with the second electrode 133 along the Z direction; and the sidewall of the second spacer layer 242 facing the first spacer layer 241 gradually moving away from the first transistor from being flush with the fourth electrode 134.

[0136] Alternatively, the width of the portion of the first spacer layer 241 closer to the substrate 10 in the Y direction is greater than or equal to the width of the portion of the first spacer layer 241 farther from the substrate 10 in the Y direction. Furthermore, the width of the surface of the first spacer layer 241 facing the substrate 10 in the Y direction is greater than the width of the surface of the first spacer layer 241 facing away from the substrate 10 in the Y direction.

[0137] The width of the portion of the second spacer layer 242 closer to the substrate 10 in the Y direction is greater than or equal to the width of the portion of the second spacer layer 242 farther from the substrate 10 in the Y direction. Furthermore, the width of the surface of the second spacer layer 242 facing the substrate 10 in the Y direction is greater than the width of the surface of the second spacer layer 242 away from the substrate 10 in the Y direction.

[0138] Based on the above, this application embodiment does not limit the specific shape of the sidewall of the first spacer layer 241 facing the second spacer layer 242, or the sidewall of the second spacer layer 242 facing the first spacer layer 241. The shape is related to the etching material, etching conditions, etc. For example, the shape of the sidewall of the first spacer layer 241 facing the second spacer layer 242, or the sidewall of the second spacer layer 242 facing the first spacer layer 241, can be a slope, an arc surface, a step, etc.

[0139] S160, such as Figure 7a As shown, a dielectric layer 25 is filled between the first electrode 113 and the third electrode 114, between the first channel 123 and the second channel 124, and between the second electrode 133 and the fourth electrode 134 in each stacked structure. The surface of the dielectric layer 25 facing away from the first substrate 1021 can be flush with the surfaces of the first spacer layer 241 and the second spacer layer 242 facing away from the first substrate 1021.

[0140] In some possible implementations, the material of the dielectric layer 25 is not limited in this application embodiment, as long as the material of the dielectric layer 25 includes a dielectric material. Optionally, the material of the dielectric layer 25 includes at least one of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon boron nitride (SiBN), silicon oxycarbonoxide (SiOC), silicon oxygen carbonitride (SiOCN), and silicon boron carbon nitride (SiCBN).

[0141] like Figure 7a As shown, in some possible implementations, the dielectric layer 25 can completely fill the space between the first electrode 113 and the third electrode 114, the first channel 123 and the second channel 124, and the second electrode 133 and the fourth electrode 134 in the stacked structure; or, as Figure 7b As shown, in some other possible implementations, due to the large size of the stacked structure in the Z direction, due to process reasons, there may be a situation where the middle position of the dielectric layer 25 is not filled, but the top is sealed, thus forming a hollow structure for the dielectric layer 25.

[0142] Compared to the scheme where the dielectric layer 25 is completely filled between the first electrode 113 and the third electrode 114, between the first channel 123 and the second channel 124, and between the second electrode 133 and the fourth electrode 134, in the scheme where the dielectric layer 25 has a hollow structure, the hollow part of the dielectric layer 25 is air. The dielectric constant of air is less than the dielectric constant of the dielectric material, and the overall dielectric constant of the dielectric layer 25 is even smaller. The electric field coupling between the first channel 123 of the first transistor and the second channel 124 of the second transistor is smaller.

[0143] S170, such as Figure 7c As shown, the first dummy gate 231 and the second dummy gate 232 are removed.

[0144] Optionally, if the materials of the first dummy gate 231 and the second dummy gate 232 include polysilicon, wet etching can be used to remove the first dummy gate 231 and the second dummy gate 232.

[0145] S180, such as Figure 7d As shown, a first bottom spacer layer 261 is formed covering the first electrode 113 and a second bottom spacer layer 262 is formed covering the third electrode 114. The first bottom spacer layer 261 can be used to isolate the first gate structure to be formed from the first electrode 113, and the second bottom spacer layer 262 can be used to isolate the second gate structure to be formed from the third electrode 114.

[0146] S190, such as Figure 7e As shown, a gate structure 14 is formed on the side of the first bottom spacer layer 261 and the second bottom spacer layer 262 opposite to the first substrate 101. At this time, the surface of the filled gate structure 14 on the side opposite to the first substrate 101 can be flush with the surfaces of the first spacer layer 241 and the second spacer layer 242 on the side opposite to the first substrate 101. Next, as... Figure 7f As shown, the gate structure 14 is partially removed. The gate structure 14 after partial removal still coincides at least partially with the orthogonal projection of the first channel 123 and the second channel 124 on the dielectric layer 25. However, along the Z direction, the first spacer layer 241 and the second spacer layer 242 protrude from the partially removed first gate structure 14.

[0147] S200, such as Figure 7g As shown, a third spacer layer 271 and a fourth spacer layer 272 are formed at intervals on the side of the gate structure 14 opposite to the first substrate 101. The third spacer layer 271 covers the sidewalls of the first spacer layer 241 and the second electrode 133, and the fourth spacer layer 272 covers the sidewalls of the second spacer layer 242 and the fourth electrode 134. Furthermore, the third spacer layer 271 and the fourth spacer layer 272 have the same width in the Y direction.

[0148] S210, such as Figure 7hAs shown, under the protection of the third spacer layer 271 and the fourth spacer layer 272, the gate structure 14 is partially removed (the removed part of the gate structure 14 is the part not covered by the third spacer layer 271 and the fourth spacer layer 272) to obtain the first gate structure 141 of the first transistor and the second gate structure 142 of the second transistor. The first gate structure 141 includes a first gate and a first gate dielectric for isolating the first gate from the first channel 123. The second gate structure 142 includes a second gate and a second gate dielectric for isolating the second gate from the second channel 124.

[0149] It should be understood that the first spacer layer 241 and the second spacer layer 242 protrude from the partially removed gate structure 14. During the formation of the third spacer layer 271, the first spacer layer 241 (or the first spacer layer 241 and the second pole 133) can be used to mark the setting position and height of the third spacer layer 271. During the formation of the fourth spacer layer 272, the second spacer layer 242 (or the second spacer layer 242 and the fourth pole 134) can be used to mark the setting position and height of the fourth spacer layer 272.

[0150] Alternatively, the first spacer layer 241 (or the first spacer layer 241 and the second electrode 133) is used to align the third spacer layer 271, and the second spacer layer 242 (or the second spacer layer 242 and the fourth electrode 134) is used to align the fourth spacer layer 272. In this way, in a transistor array, the third spacer layer 271 and the sidewalls of the first gate structure 141 to be formed facing the second transistor are flush, and the fourth spacer layer 272 and the sidewalls of the second gate structure 142 to be formed facing the first transistor are flush.

[0151] Furthermore, by making the widths of the third spacer layer 271 and the fourth spacer layer 272 the same in the Y direction, after partially removing the gate structure 14 using the first spacer layer 241 and the second spacer layer 242 as masks, the thickness of the first gate structure 141 in the Y direction is the same as the thickness of the second gate structure 142 in the Y direction (the thicknesses of the first gate structure 141, the second gate structure 142, the third spacer layer 271, and the fourth spacer layer 272 in the Y direction are all the same).

[0152] like Figure 8a and Figure 8bAs shown, the prior art uses a non-self-aligned photolithography process to obtain the first gate structure 141 of the first transistor and the second gate structure 142 of the second transistor. During the etching process of the gate structure 14, misalignment occurs, resulting in different thicknesses of the first gate structure 141 and the second gate structure 142 after etching. This leads to different thicknesses of the first gate of the first transistor and the second gate of the second transistor. The first gate or the second gate is too thick, and the second gate or the first gate is too thin, resulting in the problem of threshold voltage Vth drift of the first transistor or the second transistor.

[0153] In this application, since the total thickness of the first gate structure 141 in the Y direction is the same as the total thickness of the second gate structure 142 in the Y direction, it is only necessary to control the width of the first gate dielectric and the second gate dielectric to be the same in the Y direction, so that the width of the first gate and the second gate in the Y direction can be the same, thus avoiding the problem of threshold voltage Vth drift in the first transistor and the second transistor.

[0154] In some possible implementations, during the partial removal of the gate structure 14 under the protection of the third spacer layer 271 and the fourth spacer layer 272, the sidewalls of the third spacer layer 271 facing the fourth spacer layer 272 and the sidewalls of the second spacer layer 242 facing the third spacer layer 271 are also damaged by the etching material. Since the third spacer layer 271 and the fourth spacer layer 272 are located on the side of the gate structure 14 away from the first substrate 101, the portions of the third spacer layer 271 and the fourth spacer layer 272 further away from the gate structure 14 are more severely damaged. This results in the sidewall of the third spacer layer 271 facing away from the fourth spacer layer 272 gradually moving closer to the fourth spacer layer 272 along the Z direction, from being flush with the first gate structure 141; and the sidewall of the fourth spacer layer 272 facing away from the third spacer layer 271 gradually moving closer to the third spacer layer 271 from being flush with the second gate structure 142.

[0155] Alternatively, the width of the portion of the third spacer layer 271 closer to the substrate 10 in the Y direction is greater than or equal to the width of the portion of the third spacer layer 271 farther from the substrate 10 in the Y direction. Furthermore, the width of the surface of the third spacer layer 271 facing the substrate 10 in the Y direction is greater than the width of the surface of the third spacer layer 271 facing away from the substrate 10 in the Y direction.

[0156] The width of the portion of the fourth spacer layer 272 closer to the substrate 10 in the Y direction is greater than or equal to the width of the portion of the fourth spacer layer 272 farther from the substrate 10 in the Y direction. Furthermore, the width of the surface of the fourth spacer layer 272 facing the substrate 10 in the Y direction is greater than the width of the surface of the fourth spacer layer 272 away from the substrate 10 in the Y direction.

[0157] Based on the above, this application does not limit the specific shape of the sidewall of the third spacer layer 271 away from the fourth spacer layer 272, or the sidewall of the fourth spacer layer 272 away from the third spacer layer 271. The shape is related to the etching material, etching conditions, etc. For example, the shape of the sidewall of the third spacer layer 271 away from the fourth spacer layer 272, and the sidewall of the fourth spacer layer 272 away from the third spacer layer 271, can be a slope, an arc, a step, etc.

[0158] In some possible implementations, the materials of the first gate, the first gate dielectric, the second gate, and the second gate dielectric are not limited, as long as the materials of the first gate and the second gate are conductive, and the materials of the first gate dielectric and the second gate dielectric include dielectric materials.

[0159] Optionally, the materials of the first and second gate dielectrics include at least one of the following: hafnium dioxide (HfO2), aluminum oxide (Al2O3), zirconium dioxide (ZrO2), hafnium zirconium oxide (HfZrO), Ta2O5, tantalum pentoxide (La2O5), scandium oxide (ScO), silicon dioxide (SiO2), silicon oxynitride (SiON), hafnium oxide (HfSiO), aluminum oxide (Al2O3), and titanium dioxide (TiO2). Taking the first and second gate dielectrics being made of silicon oxynitride (SiON) as an example, silicon dioxide (SiO2) is first deposited, or silicon (Si) is first formed and then oxidized to obtain silicon dioxide (SiO2), followed by surface nitriding of the silicon dioxide (SiO2).

[0160] Optionally, the materials of the first gate and the second gate may include conductive metals or metal compounds. For example, the materials of the first gate and the second gate include at least one of titanium nitride (TiN), tungsten (W), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), titanium aluminum (TiAl), titanium (Ti), aluminum (Al), titanium aluminum carbide (TiAlC), and cobalt (Co).

[0161] In addition, such as Figure 9a As shown, after step S210 and before step S220, the chip fabrication method may further include filling a dielectric material 31 between the first gate structure 141 and the second gate structure 142. Furthermore, if the chip is a memory chip, and in addition to the first transistor and the second transistor, a capacitor 32 for a memory cell is also provided on the chip, then after forming the dielectric material 31, multiple capacitors 32 may be formed. The capacitors 32 are electrically connected to the first transistor through the first spacer layer 241 and through-holes in the dielectric material 31, and are electrically connected to the second transistor through the second spacer layer 242 and through-holes in the dielectric material 31.

[0162] In some possible implementations, the embodiments of this application do not limit the specific material of the dielectric material 31. Optionally, the dielectric material 31 may include at least one of silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon boron nitride (SiBN), silicon oxycarbonide (SiOC), silicon oxygen carbonitride (SiOCN), silicon boron carbon nitride (SiCBN), etc.

[0163] like Figure 9a As shown, in some possible implementations, the dielectric material 31 can completely fill the space between the first gate 141 and the second gate 142, and between the third spacer layer 271 and the fourth spacer layer 272; or, as... Figure 9b As shown, in some other possible implementations, due to the large size of the stacked structure in the Z direction, due to process reasons, there may be a situation where the middle position of the dielectric material 31 is not filled, but the top is sealed, thus forming a hollow structure for the dielectric material 31.

[0164] Compared to the scheme where the dielectric material 31 is completely filled between the first gate 141 and the second gate 142, and between the third spacer layer 271 and the fourth spacer layer 272, in the scheme where the dielectric material 31 has a hollow structure, the hollow part of the dielectric material 31 is air. The dielectric constant of air is less than that of the dielectric material 31, and the overall dielectric constant of the dielectric material 31 is even smaller. The electric field coupling between the first gate 141 of the first transistor and the second gate 142 of the second transistor is smaller.

[0165] S220, such as Figure 10a As shown, the first substrate 101 is removed using multiple intermediate patterns 1021 on the substrate as etching stop layers. Since the intermediate patterns 1021 on the substrate are made of different materials than the first substrate 101, the etching material will not damage the first electrode 113 and the third electrode 114 during the removal of the first substrate 101 using multiple intermediate patterns 1021 on the substrate as etching stop layers.

[0166] After step S210 and before step S220, the chip fabrication method may further include forming a wiring layer on the side of capacitor 32 facing away from substrate 10, so as to use the wiring of the wiring layer to transmit signals to capacitor 32, first transistor, and second transistor on the chip. Next, a wafer may be formed on the side of the wiring layer facing away from the first substrate 101 to support the chip; the wafer may be formed on the chip using a bonding method. Then, the chip and wafer are flipped, with the wafer below and the chip above, and step S220 is executed.

[0167] S230, such as Figure 10b As shown, multiple base intermediate patterns 1021 are removed.

[0168] S240, such as Figure 10c As shown, a bit line BL is formed on the side of the first electrode 113 and the third electrode 114 opposite to the first channel 123 and the second channel 124, and the bit line BL is in direct contact with the first electrode 113 and the third electrode 114. Then, as... Figure 10d As shown, a substrate can also be formed on the side of bit line BL that is away from the first electrode 113 and the third electrode 114.

[0169] As mentioned in step S120 above, a mask is used to partially etch the second conductive layer 13, the semiconductor layer 12, the first conductive layer 11, and the second substrate 102. Then, a shallow trench isolation layer 21 is filled between adjacent intermediate patterns 131 of the second conductive layer, between adjacent intermediate patterns 121 of the semiconductor layer, between adjacent intermediate patterns 111 of the first conductive layer, and between adjacent substrate patterns 1021. After removing the multiple substrate intermediate patterns 1021, the shallow trench isolation layer 21 includes multiple grooves, which are filled with multiple substrate intermediate patterns 1021 before step S220.

[0170] After removing the intermediate patterns 1021 of multiple substrates, the bit lines BL can be directly filled in the grooves, eliminating the need for the bit line BL patterning process, thereby saving fabrication costs and improving yield. Optionally, a single mask can be used to partially etch the second conductive layer 13, the semiconductor layer 12, the first conductive layer 11, and the second substrate 102 in one go, avoiding the misalignment problem caused by multiple etching steps, which would otherwise result in the intermediate patterns 131 of the second conductive layer, the multiple intermediate patterns 121 of the semiconductor layer, the multiple intermediate patterns 131 of the first conductive layer, and the multiple intermediate patterns 1021 of the substrate.

[0171] Meanwhile, by placing the bit line BL on the same side of the substrate as the first electrode 113 of the first transistor and the third electrode 114 of the second transistor, i.e., in a buried bitline (BBL) configuration, the area occupied by the bit line BL can be saved, effectively promoting chip miniaturization. Furthermore, the bit line BL can directly contact the first electrode 113 of the first transistor and the third electrode 114 of the second transistor to achieve electrical connection, eliminating the need for leads and thus avoiding the increased impedance caused by leads, which leads to RC delay.

[0172] In another embodiment, this application also provides a chip that can be fabricated using the chip fabrication method provided in the previous embodiment. For example... Figure 7h As shown, the chip includes a substrate 40 and a transistor group disposed on the substrate 40. The transistor group includes a first transistor, a dielectric layer 25, and a second transistor that are sequentially connected.

[0173] The first transistor includes a first electrode 113, a first channel 123, a second electrode 133, and a first spacer layer 241, which are sequentially stacked along the Z direction. The sidewalls of the first spacer layer 241, the second electrode 133, and the first channel 123 that are away from the dielectric layer 25 are all flush. The first transistor also includes a first gate structure 141 located on the side of the first channel 123 away from the second transistor. The first gate structure 141 includes a first gate and a first gate dielectric for isolating the first gate from the first channel 123.

[0174] The second transistor includes a third electrode 114, a second channel 124, a fourth electrode 134, and a second spacer layer 242, which are sequentially stacked along a first direction. The sidewalls of the second spacer layer 242, the fourth electrode 134, and the second channel 124 that are away from the dielectric layer 25 are all flush. The second transistor also includes a second gate structure 142 located on the side of the second channel 124 away from the first transistor. The second gate structure 142 includes a second gate and a second gate dielectric for isolating the second gate from the second channel 124.

[0175] The first spacer layer 241 and the second spacer layer 242, as well as the first channel 123 and the second channel 124, are symmetrical about the dielectric layer 25. Along the Z direction, the sidewall of the first spacer layer 241 facing the dielectric layer 25 is flush with the sidewall of the second electrode 133 and the first channel 123, and gradually moves away from the second transistor.

[0176] For ease of description, the sidewall of the first spacer layer 241 facing the dielectric layer 25 is called the first sidewall, the sidewall of the first spacer layer 241 away from the dielectric layer 25 is called the second sidewall, the sidewall of the second spacer layer 242 facing the dielectric layer 25 is called the third sidewall, and the sidewall of the second spacer layer 242 away from the dielectric layer 25 is called the fourth sidewall.

[0177] Since the first channel 123 and the second channel 124 are symmetrical about the dielectric layer 25, the first channel 123 and the second channel 124 have the same shape and size. Along the Y direction, the thickness of the first channel 123 is the same as the thickness of the second channel 124.

[0178] Since the first spacer layer 241 and the second spacer layer 242 are symmetrical about the dielectric layer 25, they have the same shape and size. Alternatively, along the first direction, the first sidewall of the first spacer layer 241 gradually moves away from the second transistor, starting flush with the sidewalls of the second electrode 133 and the first channel 123. Similarly, along the Z-direction, the third sidewall of the second spacer layer 242 gradually moves away from the first transistor, starting flush with the sidewalls of the fourth electrode 134 and the second channel 124. This can also be understood as the portion of the first sidewall of the first spacer layer 241 near the substrate 40 being flush with the sidewalls of the second electrode 133 and the first channel 123, while gradually moving away from the second transistor along the Z-direction. Likewise, the portion of the third sidewall of the second spacer layer 242 near the substrate 40 being flush with the sidewalls of the fourth electrode 134 and the second channel 124, while gradually moving away from the first transistor along the Z-direction. Furthermore, along the Y direction, the thickness of the first spacer layer 241 is the same as the thickness of the second spacer layer 242.

[0179] In this application, a first conductive layer 11, a semiconductor layer 12, and a second conductive layer 13 are first formed in sequence. Then, a first spacer layer 241 and a second spacer layer 242 are formed on the second conductive layer 13. Under the protection of the first spacer layer 241 and the second spacer layer 242, the first conductive layer 11, the semiconductor layer 12, and the second conductive layer 13 are partially removed. After the second conductive layer 13 is partially removed, a second electrode 133 and a fourth electrode 134 are formed. After the semiconductor layer 12 is partially removed, a first channel 123 and a second channel 124 are formed. After the first conductive layer 11 is partially removed, a first electrode 113 and a third electrode 114 are formed.

[0180] Since the sidewalls of the first spacer layer 241, the second electrode 133, and the first channel 123 that are away from the dielectric layer 25 are all flush, and the portion of the first sidewall of the first spacer layer 241 that is close to the substrate 40 is flush with the sidewalls of the second electrode 133 and the first channel 123, the first spacer layer 241 can serve as a protective layer for the second electrode 133, the first channel 123, and the first electrode 113 during the partial removal of the first conductive layer 11, the semiconductor layer 12, and the second conductive layer 13. Since the sidewalls of the second spacer layer 242, the fourth electrode 134, and the second channel 124 that are away from the dielectric layer 25 are all flush, and the portion of the third sidewall of the second spacer layer 242 near the substrate 40 is flush with the sidewalls of the fourth electrode 134 and the second channel 124, the second spacer layer 242 can serve as a protective layer for the fourth electrode 134, the second channel 124, and the third electrode 114 during the partial removal of the first conductive layer 11, the semiconductor layer 12, and the second conductive layer 13. During the partial removal of the first conductive layer 11, the semiconductor layer 12, and the second conductive layer 13, the etching material will affect the first spacer layer 241 and the second spacer layer 242. The portion of the first spacer layer 241 and the second spacer layer 242 further away from the substrate 40 is more affected by the etching material. Therefore, along the Z-direction, the first sidewall of the first spacer layer 241 gradually moves away from the second transistor, and the sidewall of the second spacer layer 242 gradually moves away from the first transistor.

[0181] In this case, because the first spacer layer 241 and the second spacer layer 242 are symmetrical about the dielectric layer, their widths in the Y direction are the same. Thus, under the protection of the first and second spacer layers 241 and 242, the widths of the first channel 123 and the second channel 124 obtained through the partial removal process are also the same in the Y direction. This solves the problem of different widths and thicknesses of the channel 021 of the first transistor and the channel 021 of the second transistor obtained by non-self-aligned photolithography, preventing the first channel 123 or the second channel 124 from being too thick, which would prevent the first channel 123 or the second channel 124 from being fully depleted; and preventing the second channel 124 or the first channel 123 from being too thin, which would cause the second channel 124 or the first channel 123 to lose its semiconductor properties.

[0182] In some possible implementations, the embodiments of this application do not limit the specific shape of the sidewall of the first spacer layer 241 facing the second spacer layer 242, and the sidewall of the second spacer layer 242 facing the first spacer layer 241, but the shape is related to the etching material, etching conditions, etc. For example, the shape of the sidewall of the first spacer layer 241 facing the second spacer layer 242, and the sidewall of the second spacer layer 242 facing the first spacer layer 241, can be a slope, a curved surface, a step, etc.

[0183] In some embodiments, such as Figure 7gAs shown, the chip includes multiple transistor groups. The first transistor further includes a third spacer layer 271, and the second transistor further includes a fourth spacer layer 272. The third spacer layer 271 covers the sidewall of the second electrode 133 away from the fourth electrode 134 and the surface of the first gate structure 141 away from the substrate 40. The fourth spacer layer 272 covers the sidewall of the fourth electrode 134 away from the second electrode 133 and the surface of the second gate structure 142 away from the substrate 40. The first gate structure 141 is flush with the sidewall of the third spacer layer 271 away from the dielectric layer 25, and the second gate structure 142 is flush with the sidewall of the fourth spacer layer 272 away from the dielectric layer 25. The first gate structure 141 and the second gate structure 142 are symmetrical about the dielectric layer 25.

[0184] Since the third spacer layer 271 covers the surface of the first gate structure 141 away from the substrate 40, and the fourth spacer layer 272 covers the surface of the second gate structure 142 away from the substrate 40, and the first gate structure 141 and the third spacer layer 271 are flush with the sidewalls of the dielectric layer 25 away from the dielectric layer 25, and the second gate structure 142 and the fourth spacer layer 272 are flush with the sidewalls of the dielectric layer 25 away from the dielectric layer 25, the third spacer layer 271 can serve as a protective layer for the first gate structure 141 and the fourth spacer layer 272 can serve as a protective layer for the second gate structure 142 during the formation of the first gate structure 141 and the second gate structure 142. During the process of forming the first gate structure 141 and the second gate structure 142 using photolithography, the etching material will affect the third spacer layer 271 and the fourth spacer layer 272. The portion of the third spacer layer 271 and the fourth spacer layer 272 that is further away from the substrate 40 is more affected by the etching material. Therefore, along the Z direction, the sidewall of the third spacer layer 271 facing the dielectric layer 25 gradually moves away from the second transistor, and the sidewall of the fourth spacer layer 272 facing the dielectric layer 25 gradually moves away from the first transistor.

[0185] In this case, by making the widths of the third spacer layer 271 and the fourth spacer layer 272 the same in the Y direction, the first gate structure 141 and the second gate structure 142 can be made symmetrical about the dielectric layer 25. That is, under the protection of the third spacer layer 271 and the fourth spacer layer 272, the widths of the first gate structure 141 and the second gate structure 142 obtained by the partial removal process are also the same in the Y direction. By simply controlling the widths of the first gate dielectric and the second gate dielectric to be the same in the Y direction, the widths of the first gate and the second gate can be made the same in the Y direction, thus avoiding the problem of threshold voltage Vth drift in the first transistor and the second transistor.

[0186] In some embodiments, such as Figure 10dAs shown, the chip also includes a bit line BL, which is disposed between the substrate 40 and the first electrode 113 and the third electrode 114, and the bit line BL is in direct contact with the first electrode 113 and the third electrode 114. By placing the bit line BL on the same side of the substrate as the first electrode 113 of the first transistor and the third electrode 114 of the second transistor, electrical connection is achieved through contact between the bit line BL and the first electrode 113 of the first transistor and the third electrode 114 of the second transistor. This eliminates the need for leads to achieve electrical connection, thereby avoiding the increased impedance caused by leads and the resulting RC delay.

[0187] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A chip, characterized in that, The device includes a substrate and at least one transistor group disposed on the substrate, the transistor group including a first transistor, a dielectric layer and a second transistor sequentially adjacent to each other along a second direction, the first direction intersecting the second direction; The first transistor includes: a first electrode, a first channel, a second electrode, and a first spacer layer, which are sequentially stacked along a first direction from the substrate toward the transistor group, wherein the sidewalls of the first spacer layer, the second electrode, and the first channel away from the dielectric layer are flush; and a first gate structure located on the side of the first channel away from the second transistor. The second transistor includes: a third electrode, a second channel, a fourth electrode, and a second spacer layer stacked sequentially along the first direction, wherein the sidewalls of the second spacer layer, the fourth electrode, and the second channel facing away from the dielectric layer are all flush; and a second gate structure located on the side of the second channel facing away from the first transistor. The first spacer layer and the second spacer layer, as well as the first channel and the second channel, are symmetrical about the dielectric layer. Along the first direction, the sidewall of the first spacer layer facing the dielectric layer is flush with the sidewall of the second electrode and the first channel, and gradually moves away from the second transistor.

2. The chip according to claim 1, characterized in that, The surface of the first spacer layer that contacts the dielectric layer is an arc surface, and the surface of the second spacer layer that contacts the dielectric layer is an arc surface.

3. The chip according to claim 1 or 2, characterized in that, The chip includes multiple groups of transistors; the first transistor further includes a third spacer layer, and the second transistor further includes a fourth spacer layer. The third spacer layer covers the sidewall of the second electrode opposite to the fourth electrode and the surface of the first gate structure opposite to the substrate, and the fourth spacer layer covers the sidewall of the fourth electrode opposite to the second electrode and the surface of the second gate structure opposite to the substrate. The first gate structure is flush with the sidewall of the third spacer layer away from the dielectric layer, and the second gate structure is flush with the sidewall of the fourth spacer layer away from the dielectric layer. The first gate structure and the second gate structure are symmetrical about the dielectric layer.

4. The chip according to any one of claims 1-3, characterized in that, The chip further includes a bit line disposed between the substrate and the first electrode and the third electrode, and the bit line is in direct contact with the first electrode and the third electrode.

5. A memory, characterized in that, It includes a controller and the chip according to any one of claims 1-4, wherein the controller is used to control the chip to read and write data.

6. An electronic device, characterized in that, It includes a circuit board and the memory of claim 5, the memory being disposed on the circuit board.

7. A method for fabricating a chip, characterized in that, include: Multiple stacked structures are formed on a substrate at intervals; the stacked structures include a first conductive pattern, a semiconductor pattern, and a second conductive pattern stacked sequentially along a first direction Z, and the multiple stacked structures are arranged along a second direction Y. A first dummy gate and a second dummy gate are formed on opposite sides of the stacked structure, respectively. A first spacer layer and a second spacer layer are formed on the side of the second conductive layer away from the substrate. The sidewall of the first spacer layer contacts the sidewall of the first dummy gate, and the sidewall of the second spacer layer contacts the sidewall of the second dummy gate. The width of the first spacer layer and the second spacer layer is the same in the second direction. Under the protection of the first spacer layer and the second spacer layer, the stacked structure is partially removed to obtain the second electrode, the first channel, and the first terminal of the first transistor, and the fourth electrode, the second channel, and the third electrode of the second transistor. Along the first direction, the first electrode, the first channel, and the second electrode are stacked in sequence, and the third electrode, the second channel, and the fourth electrode are stacked in sequence. The sidewalls of the first spacer layer, the second electrode, and the first channel that are away from the second transistor are all flush, and the sidewalls of the second spacer layer, the fourth electrode, and the second channel that are away from the dielectric layer are all flush.

8. The method for fabricating a chip according to claim 7, characterized in that, Along the first direction, the substrate includes a first substrate and a second substrate stacked together; Before forming the stacked structure on the substrate, the chip fabrication method further includes: A first conductive layer, a semiconductor layer, and a second conductive layer are sequentially formed on the second substrate; The second conductive layer, the semiconductor layer, the first conductive layer, and the second substrate are partially removed to obtain multiple intermediate patterns of the second conductive layer, multiple intermediate patterns of the semiconductor layer, multiple intermediate patterns of the first conductive layer, and multiple intermediate patterns of the substrate; the multiple intermediate patterns of the second conductive layer, the multiple intermediate patterns of the semiconductor layer, the multiple intermediate patterns of the first conductive layer, and the multiple intermediate patterns of the substrate are all arranged along a third direction X. Shallow trench isolation layers are filled between adjacent intermediate patterns of the second conductive layer, between adjacent intermediate patterns of the semiconductor layer, between adjacent intermediate patterns of the first conductive layer, and between adjacent substrate patterns. The plurality of stacked structures formed at intervals on the substrate include: A protective layer is formed on the side of the plurality of second conductive layers opposite to the first substrate, between the pattern in the middle of the second conductive layers and the shallow trench isolation layer; Under the protection of the protective layer, the intermediate patterns of the plurality of second conductive layers, the intermediate patterns of the plurality of semiconductor layers, and the intermediate patterns of the plurality of first conductive layers are partially etched to obtain the plurality of stacked structures arranged along the second direction.

9. The method for fabricating a chip according to claim 8, characterized in that, The substrate further includes a third substrate disposed on the side of the second substrate opposite to the first substrate, and the material of the third substrate includes a semiconductor material; The formation of the first conductive layer on the second substrate includes: The third substrate is doped to obtain the first conductive layer.

10. The method for fabricating a chip according to claim 8 or 9, characterized in that, After partially removing the stacked structure under the protection of the first and second spacer layers, the chip fabrication method further includes: A dielectric layer is filled between the first electrode and the third electrode, between the first channel and the second channel, and between the second electrode and the fourth electrode in each of the stacked structures. Remove the first dummy gate and the second dummy gate; A first bottom spacer layer covering the first pole and a second bottom spacer layer covering the third pole are formed; A gate structure is formed on the side of the first bottom spacer layer and the second bottom spacer layer opposite to the substrate; the gate structure at least partially coincides with the orthographic projection of the first channel and the second channel onto the dielectric layer; A third spacer layer and a fourth spacer layer are formed at intervals on the side of the gate structure opposite to the substrate; the third spacer layer covers the sidewalls of the first spacer layer and the second pole; the fourth spacer layer covers the sidewalls of the second spacer layer and the fourth pole; and the third spacer layer and the fourth spacer layer have the same width in the second direction. Under the protection of the third spacer layer and the fourth spacer layer, the gate structure is partially removed to obtain the first gate structure of the first transistor and the second gate structure of the second transistor. The first gate structure includes a first gate and a first gate dielectric for isolating the first gate from the first channel. The second gate structure includes a second gate and a second gate dielectric for isolating the second gate from the second channel.

11. The method for fabricating a chip according to claim 10, characterized in that, The first substrate and the second substrate are made of different materials; after obtaining the first gate and the second gate, the chip fabrication method further includes: The first substrate is removed using the second substrate as the etching stop layer.

12. The method for fabricating a chip according to claim 11, characterized in that, The material of the first substrate includes silicon, and the material of the second substrate includes silicon oxide.

13. The method for fabricating a chip according to claim 11 or 12, characterized in that, After removing the first substrate, the chip fabrication method further includes: Remove the second substrate; Bit lines are formed on the side of the first electrode and the third electrode that are away from the first channel and the second channel, and the bit lines are in direct contact with the first electrode and the third electrode.

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