Memory device

Abstract

The memory device of the present embodiment suppresses defects of the memory device. A memory device (1) according to an embodiment includes a second chip (10) to which a first chip (20) is bonded, the second chip including: a stacked body (900) including a plurality of conductive layers (103) arranged in a first direction perpendicular to a chip surface; a semiconductor layer (101a) above the laminate; a first contact (CC1) that penetrates at least a first conductive layer of the plurality of conductive layers, is connected to the first conductive layer, and includes a portion within the semiconductor layer; a second contact (CC1) that passes through at least a second conductive layer of the plurality of conductive layers, is connected to the second conductive layer, includes a portion within the semiconductor layer, and is arranged in a second direction parallel to the chip surface with the first contact; and a separation member (BB1) provided in the semiconductor layer between the first and second contacts. The size of the separation member on the opposite side of the first chip in the second direction is larger than the size of the first chip side in the second direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to storage devices. Background Technology

[0002] NAND flash memory is known as a storage device capable of storing data non-volatilely. Summary of the Invention

[0003] The storage device in the implementation method suppresses malfunctions of the storage device.

[0004] The memory device of the embodiment includes: a first chip including a substrate and circuitry on the substrate; and a second chip attached to the first chip, the second chip including: a stack including a plurality of conductive layers arranged separately from each other in a first direction perpendicular to the surface of the second chip and a memory pillar penetrating the plurality of conductive layers; a first semiconductor layer disposed above the stack in the first direction and connected to a source line; and a first contact penetrating at least a first conductive layer of the plurality of conductive layers and connected to the first conductive layer. The first semiconductor layer comprises: a portion of the first conductive layer located opposite to the first chip; a second contact penetrating and connected to at least the second conductive layer of the plurality of conductive layers, the portion of the second contact located opposite to the first chip of the first conductive layer located within the first semiconductor layer; the second contact and the first contact being arranged in a second direction parallel to the surface of the second chip; and a first separating member separating the first semiconductor layer between the first contact and the second contact in the second direction. The first separating member comprises: a first portion located along a face of the first semiconductor layer on the side of the first chip; and a second portion located along a face of the first semiconductor layer opposite to the first chip, wherein a first dimension of the second portion along the second direction is larger than a second dimension of the first portion along the second direction. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating an example of the overall configuration of the storage device according to the first embodiment.

[0006] Figure 2 This is a circuit diagram of the memory cell array of the memory device according to the first embodiment.

[0007] Figure 3 This is a schematic diagram of the bonding structure of the storage device according to the first embodiment.

[0008] Figure 4This is a cross-sectional view showing a construction example of the storage device according to the first embodiment.

[0009] Figure 5 This is a plan view showing the layout of the storage device according to the first embodiment.

[0010] Figure 6 This is a cross-sectional view showing a construction example of the memory cell array of the memory device according to the first embodiment.

[0011] Figure 7 This is a cross-sectional view showing a construction example of the storage column of the storage device according to the first embodiment.

[0012] Figure 8 This is a cross-sectional view showing the structure of the bonding pads of the storage device according to the first embodiment.

[0013] Figure 9 This is a cross-sectional view showing a construction example of the detachable component of the storage device according to the first embodiment.

[0014] Figure 10 This is a plan view showing an example of the construction of the contact member and the separation member of the storage device according to the first embodiment.

[0015] Figure 11A This is a cross-sectional view showing an example of the construction of the contact member and the separation member of the storage device according to the first embodiment.

[0016] Figure 11B This is a cross-sectional view showing an example of the construction of the contact member and the separation member of the storage device according to the first embodiment.

[0017] Figure 12 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0018] Figure 13 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0019] Figure 14 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0020] Figure 15 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0021] Figure 16 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0022] Figure 17 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0023] Figure 18 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0024] Figure 19 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0025] Figure 20 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0026] Figure 21 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0027] Figure 22 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0028] Figure 23 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0029] Figure 24 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0030] Figure 25 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0031] Figure 26 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0032] Figure 27 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0033] Figure 28 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0034] Figure 29 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0035] Figure 30 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0036] Figure 31 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the first embodiment.

[0037] Figure 32 This is a plan view showing a construction example of the storage device according to the second embodiment.

[0038] Figure 33 This is a cross-sectional view showing a construction example of the storage device according to the second embodiment.

[0039] Figure 34 This is a cross-sectional view showing a construction example of the storage device according to the third embodiment.

[0040] Figure 35 This is a cross-sectional view showing an example of the construction of the contact member and the separation member of the storage device according to the fourth embodiment.

[0041] Figure 36 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the fourth embodiment.

[0042] Figure 37 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the fourth embodiment.

[0043] Figure 38 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the fourth embodiment.

[0044] Figure 39 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the fourth embodiment.

[0045] Figure 40 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the fourth embodiment.

[0046] Figure 41 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the fourth embodiment.

[0047] Figure 42 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the fourth embodiment.

[0048] Figure 43 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the fourth embodiment.

[0049] Figure 44 This is a cross-sectional process diagram showing one step of the manufacturing method of the storage device according to the fourth embodiment.

[0050] Figure 45 This is a cross-sectional view showing a construction example of the storage device according to the fifth embodiment.

[0051] Explanation of reference numerals in the attached figures

[0052] 1: Memory device; 10: Array chip; PLN: Plane; 11: Memory cell array; 101a, 101c: Semiconductor layer; 103: Conductive layer; CC1, CC2, CC3: Contact; BB1, BB2: Separation component; HR: Support component; MA: Memory cell array area; CA: Contact area; DA: Plane separation area. Detailed Implementation

[0053] Reference Figures 1 to 45 The storage device and its manufacturing method according to the embodiments will be described. In the following description, elements having the same function and structure will be labeled with the same reference numerals. In addition, in each of the following embodiments, the constituent elements (e.g., circuits, wiring, various voltages, and signals, etc.) that are labeled with reference numerals / letters at the end for differentiation will be used with reference numerals (without the numerals / letters at the end) when they can be used without distinguishing them from each other.

[0054] <Implementation Method>

[0055] Implementation Method 1

[0056] Reference Figures 1 to 31 The storage device of the first embodiment and the method for manufacturing the storage device will be described.

[0057] (a) Example of composition

[0058] (a-1) Overall structure of the storage device

[0059] Reference Figure 1 An example of the overall configuration of the storage device 1 in this embodiment will be described. Figure 1 This is a block diagram showing the overall configuration of the storage device 1 according to this embodiment. Furthermore, in Figure 1 In the diagram, arrows are used to indicate a portion of the connections between the constituent elements, but the connections between the constituent elements are not limited to these.

[0060] The memory device 1 is, for example, a three-dimensional stacked NAND flash memory. The three-dimensional stacked NAND flash memory includes a plurality of memory cells (hereinafter also referred to as memory cell transistors) arranged in three dimensions on a substrate.

[0061] like Figure 1 As shown, the storage device 1 in this embodiment includes multiple planar PLNs, a voltage generation circuit 23, and a sequencer 24.

[0062] Each of the multiple planar PLNs is an independent circuit group capable of operating in parallel (simultaneously). Each of the multiple planar PLNs includes a memory cell array 11, a row decoder 21, and a sense amplifier 22.

[0063] Each storage cell array 11 includes multiple block BLKs. A block BLK is, for example, a collection of multiple storage cells whose data is erased together. The storage cells are arranged in three dimensions within the storage cell array 11. The multiple storage cells within a block BLK are associated with rows and columns. Details regarding the internal structure of the storage cell array 11 and the block BLKs will be described later.

[0064] The row decoder 21 is a circuit that decodes the row address. The row address is an address signal that specifies the routing in the row direction of the memory cell array 11. Based on the decoding result of the row address, the row decoder 21 supplies the voltage for the operation of the memory cell array 11 to the memory cell array 11.

[0065] The sensing amplifier 22 is a circuit for writing and reading data. During the read operation, the sensing amplifier 22 senses the data read from the memory cell array 11. During the write operation, the sensing amplifier 22 supplies a voltage corresponding to the data being written to the memory cell array 11.

[0066] The voltage generation circuit 23 generates various voltages for write operations, read operations, and erase operations. For example, the voltage generation circuit 23 is connected to the row decoder 21 and sense amplifier 22 of each plane PLN. The voltage generation circuit 23 supplies the generated voltage to each row decoder 21 and each sense amplifier 22.

[0067] The sequencer 24 is the control circuit for the memory device 1. The sequencer 24 controls the overall operation of the memory device 1. For example, the sequencer 24 is connected to the row decoder 21, the sense amplifier 22, and the voltage generation circuit 23. The sequencer 24 controls the row decoder 21, the sense amplifier 22, and the voltage generation circuit 23. Based on the control of an external controller (not shown), the sequencer 24 performs write operations, read operations, and erase operations on the memory cell array 11.

[0068] Hereinafter, the circuit group used to control the operation of the memory cell array 11, such as the row decoder 21, the sensing amplifier 22, the voltage generation circuit 23, and the sequencer 24, is also referred to as CMOS circuit (or peripheral circuit).

[0069] (a-2) Circuit configuration of memory cell array

[0070] Reference Figure 2 An example of the circuit configuration of the memory cell array 11 will be described. Figure 2 This is a circuit diagram of the memory cell array 11. Figure 2 The example shows the circuit configuration of a single block BLK.

[0071] like Figure 2As shown, a block BLK comprises multiple string units SU. A string unit SU is, for example, a set of multiple NAND strings NS selected together in a write or read operation. NAND strings NS comprise a set of multiple memory cells MC connected in series. For example, one block BLK comprises four string units SU0, SU1, SU2, and SU3.

[0072] Furthermore, the number of blocks BLK within the storage cell array 11 and the number of string units SU within the blocks BLK are arbitrary.

[0073] Each NAND string NS includes multiple memory cells MC, select transistor ST1, and select transistor ST2. Figure 2 In the example, the NAND string NS includes eight storage cells MC0, MC1, ..., MC6, MC7. Furthermore, the number of storage cells MC included in the NAND string NS is arbitrary.

[0074] A memory cell (MC) is a storage element that non-volatilely stores data. The memory cell (MC) is a transistor that includes a control gate and a charge accumulation layer. The memory cell (MC) can be either a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type transistor or an FG (Floating Gate) type transistor. In a MONOS type memory cell transistor, an insulating layer such as a silicon nitride layer is used in the charge accumulation layer. In an FG type memory cell transistor, a conductive layer such as a polysilicon layer is used in the charge accumulation layer. The following explanation focuses on the case where the memory cell (MC) is a MONOS type transistor.

[0075] Selector transistors ST1 and ST2 are switching elements. Each selector transistor ST1 and ST2 is used to select the string unit SU during various operations of storage device 1. The number of selector transistors ST1 and ST2 included in the NAND string NS is arbitrary. At least one selector transistor ST1 and one ST2 are required in the NAND string NS.

[0076] The current paths of select transistor ST2, memory cells MC0, ..., MC7, and select transistor ST1 within the NAND string NS are connected in series. The drain of select transistor ST1 is connected to bit line BL. The source of select transistor ST2 is connected to source line SL.

[0077] Within the same BLK, the control gates of memory cells MC0, ..., MC7 are connected to one of the corresponding word lines WL0, ..., WL7. Each of the four string units SU includes a memory cell MC0. The control gates of multiple memory cells MC0 within the BLK are shared by one word line WL0. Similarly, memory cells MC1, ..., MC7 are connected to their corresponding word lines WL1, ..., WL7, just as memory cells MC0 are connected.

[0078] The gates of multiple selection transistors ST1 within a series unit SU are connected to a single selection gate line SGD. More specifically, the gates of multiple selection transistors ST1 within a series unit SU0 are connected to a single selection gate line SGD0. The gates of multiple selection transistors ST1 within a series unit SU1 are connected to a single selection gate line SGD1. The gates of multiple selection transistors ST1 within a series unit SU2 are connected to a single selection gate line SGD2. The gates of multiple selection transistors ST1 within a series unit SU3 are connected to a single selection gate line SGD3.

[0079] The gates of multiple select transistors ST2 within block BLK are connected to a single select gate line SGS. Alternatively, similar to select gate line SGD, multiple different select gate lines SGS can be set within block BLK per string unit SU.

[0080] Word lines WL0, ..., WL7, select gate lines SGD0, ..., SGD3, and select gate line SGS are respectively connected to row decoder 21.

[0081] Bit lines BL are connected to one NAND string NS within each string unit SU of each BLK block. The same column address is assigned to multiple NAND strings NS connected to one bit line BL. Each bit line BL is connected to the sense amplifier 22.

[0082] Source lines SL are shared, for example, among multiple blocks BLK within a single plane PLN. Source lines SL are independent for each plane PLN.

[0083] A collection of multiple memory cells MC connected to a common word line WL within a single string unit SU is, for example, denoted as a cell unit CU. For instance, write and read operations are performed on a unit basis CU.

[0084] (a-3) Overview of the bonding structure of storage devices

[0085] Reference Figure 3 The general structure of the storage device 1 in this embodiment will be described below. Figure 3 This is a top view showing the outline of the bonding structure of the storage device 1.

[0086] like Figure 3 As shown, the storage device 1 in this embodiment includes two semiconductor chips 10 and 20.

[0087] One of the two semiconductor chips 10 and 20 is an array chip (also known as a memory cell array chip) 10. The array chip 10 is a chip with multiple memory cell arrays 11.

[0088] The other of the two semiconductor chips 10 and 20 is a CMOS circuit chip (also known as a CMOS chip) 20. The CMOS circuit chip 20 is a chip that has CMOS circuitry configured to control the array chip 10.

[0089] The memory device 1 of this embodiment is formed by bonding an array chip 10 and a CMOS circuit chip 20. The memory device 1 has a structure obtained by bonding the array chip 10 and the CMOS circuit chip 20 (hereinafter referred to as "bonding structure"). Hereinafter, without distinguishing between the array chip 10 and the CMOS circuit chip 20, the array chip 10 and the CMOS circuit chip 20 are each simply referred to as "chip".

[0090] Furthermore, multiple array chips 10 can be disposed within the storage device 1. In this case, multiple array chips 10 can be laminated on top of the CMOS circuit chip 20. Multiple CMOS circuit chips 20 can be disposed within the storage device 1.

[0091] like Figure 3 As shown, the array chip 10 includes multiple pads (electrodes, conductive layers, conductors) 111 in surface F1. The CMOS circuit chip 20 includes multiple pads 211 in surface F2. Pads 111 and 211 are used for bonding the two chips 10 and 20.

[0092] In the memory device 1 with the bonding structure, surface F1 of the array chip 10 is bonded to surface F2 of the CMOS circuit chip 20. In this way, surface F1 of the array chip 10, where pads 111 are provided, faces surface F2 of the CMOS circuit chip 20, where pads 211 are provided. Hereinafter, the surfaces F1 and F2 of the array chip 10 and the CMOS circuit chip 20 that are bonded are also referred to as bonding surface BF.

[0093] In the bonding structure, the pads 111 of the array chip 10 are bonded to the pads 211 of the CMOS circuit chip 20. Thus, one bonding pad BP is formed within the memory device 1. In other words, the electrodes constituting the pads 111 of the array chip 10 are bonded to the electrodes constituting the pads 211 of the CMOS circuit chip 20. This forms the bonding pad BP of the memory device 1 with the bonding structure.

[0094] The bonding pads (BP) include active pads and dummy pads. Active pads function as signal or power paths when the storage device 1 is operational. Active pads are electrically connected to either the signal or power path. Dummy pads do not function as signal or power paths when the storage device 1 is operational. Dummy pads are not electrically connected to either the signal or power path.

[0095] Hereinafter, the surface where the array chip 10 and the CMOS circuit chip 20 are bonded (bonding surface BF) is designated as the XY plane. Directions orthogonal to each other within the XY plane are designated as the X direction and the Y direction. The X and Y directions are parallel to the XY plane. A direction approximately perpendicular to the XY plane and extending from the array chip 10 toward the CMOS circuit chip 20 is designated as the Z1 direction. A direction approximately perpendicular to the XY plane and extending from the CMOS circuit chip 20 toward the array chip 10 is designated as the Z2 direction. Without distinguishing between the Z1 and Z2 directions, the direction approximately perpendicular to the XY plane is denoted as the Z direction.

[0096] (a-4) Construction of storage devices

[0097] Reference Figure 4 An example of the construction of the storage device 1 in this embodiment will be described. Figure 4 This is a cross-sectional view showing an example of the cross-sectional structure of storage device 1. Figure 4 The main components of the storage device 1 of this embodiment are extracted and shown.

[0098] As mentioned above, Figure 4 The storage device 1 of this embodiment shown has a bonding structure of array chip 10 and CMOS circuit chip 20.

[0099] The array chip 10 includes memory pillars MP, semiconductor layers 101a and 101c, insulating layers 102, 102A, 109, 121, 125, 126, 128, 129, 150 (150a, 150b), 160, 162, 165, 169, insulator 151, insulating film 155, conductive layer (word line and select gate line) 103, wiring 106, 127, 163, conductors 104, 161, 164, contacts CX, CZ, CC1, CC2, metal layer 120, and electrodes (pads) 111.

[0100] The CMOS circuit chip 20 includes a semiconductor substrate 200, a transistor TR, conductors (plugs) 204, 208, and 210, wiring 205 and 209, electrodes (pads) 211, and insulating layers 260 and 269. The transistor TR includes a gate insulating layer 202, a gate electrode 203, and a source / drain layer (not shown).

[0101] Electrodes 111 and 211 are used to bond pads BP. The contact surfaces of insulating layers 169 and 269 are the bonding surfaces BF of the two chips 10 and 20.

[0102] (a-5) Construction of the array chip

[0103] Reference Figure 4 and Figure 5 The structure of the array chip 10 in the storage device 1 of this embodiment will be described.

[0104] Reference Figure 5 The layout of the array chip 10 of the storage device 1 in this embodiment will be described.

[0105] Figure 5 This is a plan view showing the layout of the core region of the array chip 10 in the storage device 1 of this embodiment.

[0106] In the array chip 10 of the memory device 1, the core region includes multiple memory cell array regions MA, contact regions CA, pad regions PA, and planar separation regions DA.

[0107] In the case where the memory device 1 includes multiple planar PLNs, the array chip 10 includes multiple memory cell array regions MA. For example, the multiple memory cell array regions MA are arranged in the X direction within the core region. Each of the multiple memory cell array regions MA includes a memory cell array 11. Each memory cell array region MA is configured for each planar PLN.

[0108] The planar separation region DA divides the memory cell array region MA (memory cell array 11) into planes PLN. The planar separation region DA surrounds each memory cell array region MA. The planar separation region DA separates multiple memory cell arrays 11 along each plane PLN. The planar separation region DA has a grid-like layout when viewed from the Z direction. The planar separation region DA is positioned between two memory cell array regions MA, between a memory cell array region MA and a contact region CA, and between a memory cell array region MA and a pad region PA.

[0109] The planar separation region DA, viewed from the Z direction, includes a grid-like pattern of slits (openings). The separation member BB2, described later, is disposed within these slits. The separation member BB2 has a grid-like structure corresponding to the shape of the slits. Both the slits and the separation member BB2 have portions extending in the X direction and portions extending in the Y direction.

[0110] The contact region CA is configured within the core region to surround multiple memory cell array regions MA. Multiple contacts CC2, described later, are disposed within the contact region CA.

[0111] The pad area PA is configured in the region between the contact area CA and the memory cell array area MA. The pad area PA includes multiple pads 99. For example, the pads 99 in the pad area PA are external connection terminals. The pads 99 in the pad area PA are electrically connected to the contacts CC2 in the contact area CA, the wiring in the memory cell array area MA, and / or the wiring in the CMOS circuit chip 20.

[0112] In addition, the array chip 10 also includes a notched area (not shown) at the end of the array chip 10 and a peripheral area (not shown) between the notched area and the core area. The notched area includes a dicing area, alignment marks, and feature inspection patterns, etc. The peripheral area includes edge seals, etc.

[0113] exist Figure 4 In the middle, the array chip 10 is extracted and shown to be related to Figure 5 The corresponding parts are the AA line of the storage cell array region MA, the BB line of the contact region CA, and the CC line of the planar separation region DA.

[0114] like Figure 4 As shown, in the memory cell array region MA, the semiconductor layer 101a extends in the X and Y directions. The semiconductor layer 101a disposed within the memory cell array region MA functions as part of the source line SL. For example, the semiconductor layer 101a contains silicon.

[0115] In the memory cell array region MA, multiple insulating layers 102, 102A and multiple conductive layers 103 are alternately stacked layer by layer on the Z1-oriented surface of the semiconductor layer 101a. A stack 900 including multiple insulating layers 102, 102A and multiple conductive layers 103 is disposed within the memory cell array region MA. Multiple conductive layers 103, separated in the Z-direction by the insulating layers 102, are disposed between the CMOS circuit chip 20 and the semiconductor layer 101a. Figure 4 In this example, 10 insulating layers 102 and 10 conductive layers 103 are stacked alternately. The number of insulating layers 102 and conductive layers 103 stacked in the Z direction is set accordingly to the configuration of the memory cell array 11 (e.g., storage capacity).

[0116] Multiple conductive layers 103 each extend in the X direction and function as any one of the word line WL, select gate line SGD, and select gate line SGS. The conductive layers 103 may contain conductive materials such as tungsten (W).

[0117] Insulating layer 102 separates two adjacent conductive layers 103 in the Z direction. Insulating layer 102 contains an insulating material such as silicon oxide. Among the plurality of insulating layers 102, 102A, the insulating layer 102A located closest to the CMOS circuit chip 20 has a film thickness greater than the other insulating layers 102.

[0118] Multiple memory pillars MP are arranged within the memory cell array region MA. One memory pillar MP corresponds to one NAND string NS. The memory pillar MP has, for example, a cylindrical shape extending in the Z direction. The memory pillar MP passes through multiple insulating layers 102, 102A and multiple conductive layers 103.

[0119] The side surface of the memory pillar MP (the surface intersecting the XY plane) faces the conductive layer 103. The Z2 end of the memory pillar MP penetrates the semiconductor layer 101a. The memory pillar MP includes a memory layer 142, a semiconductor layer 143, and a core layer 144. The semiconductor layer 143 extends in the Z direction. A portion of the semiconductor layer 143 is in contact with the metal layer 120 on the semiconductor layer 101a. Details regarding the structure of the memory pillar MP will be described later.

[0120] For example, an insulating layer 109, such as aluminum oxide, can be provided between the conductive layer 103 and the insulating layers 102 and 102A, and between the conductive layer 103 and the storage column MP.

[0121] Hereinafter, the ends of each component in the Z direction, the ends of the components in the Z2 direction are also referred to as the upper part, and the ends of the components in the Z1 direction are also referred to as the bottom part.

[0122] A metal layer 120 is disposed on the semiconductor layer 101a. The metal layer 120 is electrically connected to the semiconductor layer 101a and the semiconductor layer 143 of the memory pillar MP. The metal layer 120 functions as a source line SL. In this way, the source line SL includes the portions of the metal layer 120 and the semiconductor layer 101a that are in contact with the memory pillar MP.

[0123] Furthermore, the construction of the source line SL is not limited to the example using metal layer 120. For example, the source line SL may also have a construction in which the source line SL, which is made of a semiconductor layer, is connected to the semiconductor layer 143 of the memory pillar MP via an opening formed in the memory layer 142 of the memory pillar MP. In this case, the semiconductor layer of the source line SL covers the end of the memory pillar MP.

[0124] For example, a slit (not shown) extending in the X direction is provided within the laminate 900, which includes insulating layers 102, 102A, and conductive layer 103. An insulator (not shown) fills the interior of the slit. This insulator penetrates multiple insulating layers 102, 102A, and multiple conductive layers 103. For example, the area defined by the insulator (and the slit) corresponds to one block BLK. Furthermore, the slit is also used in the formation process of conductive layer 103 to supply etchant and raw materials for conductive layer 103 into the laminate 900.

[0125] Conductor 104 is disposed within insulating layer 162 on the Z1-oriented surface of memory cell MP. Conductor 104 has, for example, a cylindrical shape extending in the Z direction. Wiring 106 is disposed within insulating layer 165 on the Z1-oriented surface of conductor 104. Multiple wirings 106 are arranged in the X direction within memory cell array region MA. Each of the multiple wirings 106 extends in the Y direction. Each of the multiple memory cell MP is electrically connected to any one of the multiple wirings 106 via conductor 104. Wiring 106 functions as bit lines BL. Wiring 106 contains, for example, copper (Cu).

[0126] The X-direction ends of the laminate 900, which includes multiple insulating layers 102, 102A and multiple conductive layers 103, are processed into a stepped shape. Hereinafter, the stepped portion of the laminate 900 is referred to as the stepped structure. The stepped structure is covered by the insulating layer 160. Furthermore, the region within the memory cell array region MA in which the stepped structure is configured is referred to as the lead-out region.

[0127] In the stepped structure, the conductive layer 103 includes a portion (hereinafter referred to as the Terrace) on the Z1 direction side that is not covered by the stacked insulating layer 102 and other conductive layers 103 (not overlapping with other conductive layers 103). The conductive layer 103 contacts the contact (contact plug) CC1 on the Terrace. Thus, the conductive layer 103 is electrically connected to the contact CC1.

[0128] Multiple contacts CC1 are disposed within the lead-out area of ​​the memory cell array region MA. The multiple contacts CC1 are arranged in the X and / or Y directions. Contacts CC1 penetrate the stepped insulating layer 102 and conductive layer 103. Contacts CC1 are conductors. Contacts CC1 have a cylindrical shape extending in the Z direction. Contacts CC1 include a portion 90 that contacts the platform of conductive layer 103. Contacts CC1 include a portion 91 that reaches semiconductor layers 101a, 101c and insulating layer 121. Details regarding the construction of contacts CC1 will be described later.

[0129] A conductor (via plug) 161 is disposed within an insulating layer 162. A wiring 163 is disposed within an insulating layer 165. The wiring 163 is connected to the contact CC1 via the conductor 161. The wiring 163 is electrically connected to the electrode 111, for example, via a conductor 164 within the insulating layer 165.

[0130] Multiple support members HR are provided in the lead-out area. The support members HR penetrate the stepped insulating layer 102 and conductive layer 103. The support members HR have a cylindrical shape extending in the Z direction. In the formation process of the conductive layer 103 (described later), the support members HR function as components to prevent the collapse of the laminate 900. The material of the support members HR is an insulator such as silicon oxide. Details regarding the structure of the support members HR will be described later.

[0131] An insulating layer 150b is disposed within the insulating layer 160 on the side surface of portion 90 of the contact CC1. An insulating layer 150a is disposed between the insulating layer 150b and the insulating layer 109. For example, an insulator 151 is disposed between the contact CC1 and the side surface of the conductive layer 103. For example, an insulating film 155 is disposed between portion 91 of the contact CC1 and the semiconductor layers 101a and 101c.

[0132] An insulating layer 169 is disposed on the Z1-oriented surface of the insulating layer 165. Multiple electrodes 111 are disposed within the same layer as the insulating layer 169. The electrodes 111 are arranged within the insulating layer 169. The electrodes 111 have a quadrilateral shape when viewed from the Z direction. In the memory cell array region MA, the electrodes 111 are disposed on the Z1-oriented surface of the conductor 164. The electrodes 111 are electrically connected to a corresponding wire 163 among a plurality of wires 163. The electrodes 111 are connected to a corresponding electrode 211 of the CMOS circuit chip 20. The electrodes 111 and 211 function as bonding pads BP. The electrodes 111 contain copper. Furthermore, the number of layers of conductors 161 and 164 and wires 163 disposed between the electrodes 111 and the contact CC1 is arbitrary.

[0133] In addition, the bonding pads (BP) include active pads that are connected to the circuit and dummy pads that are not connected to the circuit.

[0134] exist Figure 4 Although the illustration is omitted, electrodes 111 that electrically connect the wiring (bit line) 106 to the CMOS circuit chip 20 are provided in the memory cell array region MA.

[0135] Insulating layers 125 and 126 are stacked on the Z2-oriented surface of semiconductor layer 101c and on metal layer 120. Insulating layer 126 extends along the X and Y directions on the Z2-oriented surface of insulating layer 125. Insulating layer 125 is silicon oxide made of SiH4. Insulating layer 126 is silicon oxide.

[0136] Wiring 127 is disposed on the surface of insulating layer 126 facing the Z2 direction. For example, within the memory cell array region MA, wiring 127 is electrically connected to the metal layer (source line) 120 via a contact (conductor) CX disposed within insulating layers 125 and 126. The contact CX is a component continuous with wiring 127. The contact CX is formed by embedding a component of wiring 127 within an opening formed in insulating layers 125 and 126.

[0137] Insulating layers 128 and 129 are stacked on the Z2-oriented surface of wiring 127. Insulating layer 128 is disposed between insulating layer 129 and wiring 127. The material of insulating layer 128 is silicon oxide made from TEOS. The material of insulating layer 129 is silicon nitride.

[0138] For example, in a certain region (e.g., a lead-out region), a contact region CA, and a planar separation region BA of the memory cell array region MA, a semiconductor layer 101c and an insulating layer 121 are disposed between the semiconductor layer 101a and the insulating layer 125. The insulating layer 121 is disposed between the semiconductor layer 101a and the semiconductor layer 101c. The material of the semiconductor layer 101c is, for example, silicon. The material of the insulating layer 121 is, for example, silicon oxide.

[0139] Hereinafter, the laminate including semiconductor layer 101a, insulating layer 121, and semiconductor layer 101c is referred to as dummy layer DM. In addition, the configuration including insulating layer 125 on semiconductor layer 101c can also be referred to as dummy layer DM.

[0140] In this embodiment, a separation member BB1 is provided within the dummy layer DM of the lead-out region. The separation member BB1 separates the dummy layer DM into multiple parts. The separation member BB1 electrically separates multiple contacts CC1 arranged in the X direction and multiple contacts CC1 arranged in the Y direction. The separation member BB1 is positioned between two adjacent contacts CC1. The separation member BB1 electrically separates two contacts CC1 within the dummy layer DM. The separation member BB1 has a tapered cross-sectional shape. A tapered shape is a conical shape in which the dimensions of the member along a direction parallel to the chip surface (X or Y direction) decrease from the Z2 direction side towards the Z1 direction side. Details regarding the construction of the separation member BB1 will be described later.

[0141] For example, a separation member BB1 is also provided at the boundary between the lead-out area and the area including multiple storage columns MP (the terminal part of the lead-out area).

[0142] The contact area CA of the array chip 10 is described.

[0143] The contact region CA includes semiconductor layers 101a and 101c and an insulating layer 121. The insulating layer 121 is disposed between the two semiconductor layers 101a and 101c. Semiconductor layer 101a is disposed on the Z2-oriented surface of the insulating layer 160. The insulating layer 121 is disposed on semiconductor layer 101a. Semiconductor layer 101c is disposed on insulating layer 121. For example, the semiconductor layers 101a and 101c of the contact region CA are separated from the semiconductor layers 101a and 101c within the memory cell array region MA by a planar separation region DA.

[0144] Multiple contacts (contact plugs) CC2 are provided within the contact area CA. The contacts CC2 are positioned corresponding to the openings provided within the dummy layer DM and the insulating layers 125 and 126. The contacts CC2 have a cylindrical shape extending primarily in the Z-direction within the insulating layer 160. The Z2-direction end of the contacts CC2 protrudes from the insulating layer 160. The Z2-direction end of the contacts CC2 is located within the dummy layer DM. The contacts CC2 are used for electrical connections between the wiring 127 and components (e.g., transistors TR) within the CMOS circuit chip 20. The contacts CC2 may contain, for example, tungsten.

[0145] Wiring 127 is electrically connected to contact CC2 via contact (conductor) CZ. Contact CZ is disposed within an opening provided in insulating layers 125 and 126 and dummy layer DM. Contact CZ is a continuous component with wiring 127. The side of contact CZ is covered by insulating layer 126. Insulating layer 126 is provided between the side of contact CZ and dummy layer DM, and between the side of contact CZ and insulating layer 125. Contact CZ is electrically separated from dummy layer DM through insulating layer 126.

[0146] In the contact area CA, insulating layers 128 and 129 are stacked on wiring 127 and insulating layer 126.

[0147] Within the contact area CA, multiple electrodes (pads) 111 are disposed within the insulating layer 169. Within the contact area CA, each electrode 111 has a quadrilateral shape when viewed from the Z direction.

[0148] Electrode 111 is electrically connected to contact CC2 via multiple conductors 161 and 164 and wiring 163. Conductors 161 are provided on the Z1-oriented surface of the multiple contacts CC2. Wiring 163 is provided on the Z1-oriented surface of conductors 161. Conductors 164 are provided on the Z1-oriented surface of wiring 163.

[0149] Furthermore, the configuration of the plurality of conductors 161, 164 and the plurality of wirings 163 used to connect the contact CC2 to the electrode 111 is not limited to Figure 5 For example, the number of conductors 161, 164 between contact CC2 and electrode 111, and the number of wiring 163 between contact CC2 and electrode 111, can be appropriately changed.

[0150] Electrode 111 electrically connects the array chip 10 and the CMOS circuit chip 20. Electrode 111 is connected to the corresponding electrode 211 of the CMOS circuit chip 20. As a result, a bonding pad BP is formed in the contact area CA.

[0151] The planar separation region DA of the array chip 10 is described.

[0152] A layer (dummy layer DM) including semiconductor layers 101a and 101c and insulating layer 121 is disposed on the surface of insulating layer 160 facing the Z2 direction within the planar separation region DA.

[0153] The semiconductor layers 101a and 101c and the insulating layer 121 within the planar separation region DA are not used as paths for electrically connecting the memory cell array 11 to other components. However, the semiconductor layers 101a and 101c of the planar separation region DA may include portions that are continuous with the semiconductor layers 101a and 101c of the memory cell array region MA.

[0154] Insulating layers 125 and 126 are stacked on the Z2-oriented surface of semiconductor layer 101c. Wiring 127 can be disposed on insulating layer 126 within the planar separation region DA.

[0155] In the planar separation region DA, insulating layers 128 and 129 are stacked on top of insulating layer 126, separated by wiring 127.

[0156] A separation member (insulator) BB2 is provided within the planar separation region DA. For example, the separation member BB2 is provided within a gap (opening) formed within the planar separation region DA. The gap is provided within the semiconductor layer 101a, insulating layer 121, semiconductor layer 101c, and insulating layer 125. The insulator, serving as the separation member BB2, fills the gap. The separation member BB2 is adjacent to the semiconductor layers 101a, 101c, and insulating layer 121 in the X direction (or Y direction).

[0157] Furthermore, the following situation also exists: In a region between two memory cell array regions MA, a separating member BB2 is provided between semiconductor layers 101a and 101c belonging to their respective memory cell array regions MA. As an insulator, the separating member BB2 separates the semiconductor layers 101a (and 101c) of one memory cell array 11 from those of the other adjacent memory cell array 11. Between the memory cell array region MA and the contact region CA, the separating member BB2 is provided between the semiconductor layer 101a (and 101c) and the dummy layer DM. As an insulator, the separating member BB2 separates the semiconductor layer 101a (and 101c) from the dummy layer DM.

[0158] Separator BB2 has a tapered cross-sectional shape. The tapered shape of separator BB2 is a normal tapered shape. Details regarding the construction of separator BB2 will be described later.

[0159] The insulator used for the separating member BB2 is a member continuous with the insulating layer 126. The insulator of the separating member BB2 is a portion (protrusion) that protrudes from the insulating layer 126 in the Z1 direction. The Z1-direction end of the insulator of the separating member BB2 contacts the insulating layer 160. The material of the separating member BB2 is the same as the material of the insulating layer 126 (e.g., silicon oxide).

[0160] Furthermore, the separating member BB2 may also be a member that is not continuous with the insulating layer 126. The separating member BB2 may also contain an insulating material that is different from the material of the insulating layer 126. There may also be cases where a void is provided inside the separating member BB2.

[0161] In this way, the separating member BB2 separates the semiconductor layer 101a (and semiconductor layer 101c) included in the source line SL of the memory cell array region MA into multiple portions (multiple memory cell arrays 11) of each plane PLN. The semiconductor layer 101a (and semiconductor layer 101c) included in the source line SL is independent in each portion of the memory cell array 11. Thus, multiple memory cell arrays 11 corresponding to each of the multiple planes PLN are disposed within the array chip 10.

[0162] (a-6) Construction of CMOS Circuit Chips

[0163] The cross-sectional structure of the CMOS circuit chip 20 in the storage device 1 of this embodiment will be described.

[0164] like Figure 4As shown, the CMOS circuit chip 20 includes a semiconductor substrate 200. In the CMOS circuit chip 20, a plurality of transistors TR are disposed on the Z2-oriented surface of the semiconductor substrate 200. The transistors TR are used as components of a row decoder 21, a sense amplifier 22, a voltage generation circuit 23, and a sequencer 24. Each transistor TR includes a gate insulating layer 202, a gate electrode 203, and a source / drain layer (not shown). The gate insulating layer 202 is disposed on the Z2-oriented surface of the semiconductor substrate 200. The gate electrode 203 is disposed on the gate insulating layer 202. The source / drain layer is disposed within the semiconductor substrate 200.

[0165] An insulating layer 260 is disposed on the Z2-oriented surface of the semiconductor substrate 200. The insulating layer 260 covers the transistor TR, conductors 204, 208, and 210, and wirings 205 and 209. For example, the insulating layer 260 has a stacked structure including multiple insulating films (multilayer wiring structure). Furthermore, the number of wiring layers disposed within the CMOS circuit chip 20 is arbitrary.

[0166] An insulating layer 269 is disposed on the Z2-oriented surface of the insulating layer 260. The Z2-oriented surface of the insulating layer 269 is, for example, in contact with the Z1-oriented surface of the insulating layer 169. The surfaces of the insulating layers 269 and 169 that are in contact with each other correspond to the bonding surfaces BF of the two semiconductor chips 10 and 20.

[0167] Multiple electrodes (pads) 211 are disposed within the insulating layer 269. Electrodes 211 are connected to electrodes 111 and conductors 210. For example, electrodes 211 have a quadrilateral shape when viewed from the Z direction.

[0168] Thus, the transistor TR on the semiconductor substrate 200 is electrically connected to the memory cell array 11 of the array chip 10 or the contacts CC1 and CC2 of the array chip 10.

[0169] The gate electrode 203, conductors 204, 208, 210, wiring 205, 209, and electrode 211 may contain conductive materials such as metals or semiconductors. Electrode 211 may contain copper, for example. The gate insulating layer 202, and insulating layers 260, 269 may contain insulating materials such as silicon oxide.

[0170] (a-7) Construction of a memory cell array

[0171] Reference Figure 6 The details of the cross-sectional structure of the storage cell array 11 are explained below. Figure 6 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array 11. Figure 6 The image shows two memory columns MP included in the memory cell array 11.

[0172] like Figure 6 As shown, semiconductor layer 101a functions as part of source line SL. Semiconductor layer 101a may contain silicon, for example. Semiconductor layer 101a may also contain phosphorus (P) as an impurity for semiconductors, for example.

[0173] On the Z1-oriented surface of semiconductor layer 101a, multiple layers (e.g., 10 layers) of insulating layer 102 and multiple layers (e.g., 10 layers) of conductive layer 103 are alternately stacked.

[0174] exist Figure 6 In this example, the 10 conductive layers 103, starting from the side closest to the semiconductor layer 101a, function as the select gate line SGS, word lines WL0, WL1, ..., WL6, WL7, and select gate line SGD, respectively. Furthermore, the select gate lines SGS and SGD can each be composed of multiple conductive layers 103.

[0175] For example, a titanium nitride (TiN) / tungsten (W) laminate can be used in the conductive material of conductive layer 103. In this case, titanium nitride is formed to cover tungsten. Titanium nitride, for example, functions as a barrier layer to inhibit the oxidation of tungsten and / or a tight adhesion layer to improve the tight adhesion of tungsten when tungsten is formed, based on chemical vapor deposition (CVD).

[0176] For example, an insulating layer 109 made of a high dielectric constant material such as alumina (AlO) is formed such that a conductive layer 103 is covered between two stacked insulating layers 102. The insulating layer 109 is disposed between the conductive layer 103 and the insulating layer 102, and between the conductive layer 103 and the storage pillar MP.

[0177] Multiple memory pillars (MPs) are disposed within the memory cell array 11. Each memory pillar (MP) extending in the Z-direction penetrates a 10-layer conductive layer 103. One end of the memory pillar (MP) in the Z-direction (the end in the Z2 direction) penetrates a semiconductor layer 101a. Alternatively, the memory pillars (MPs) can be constructed by connecting multiple pillars in the Z-direction.

[0178] The internal structure of the memory column MP is described below. The memory column MP includes a memory layer 142, a semiconductor layer 143, a core layer 144, and a cover layer 145.

[0179] The storage layer 142 includes a block insulating layer 40, a charge storage layer 41, and a tunnel insulating layer 42. The sides of the core layer 144, starting from the outside of the storage pillar MP, are sequentially covered by the block insulating layer 40, the charge storage layer 41, the tunnel insulating layer 42, and the semiconductor layer 143.

[0180] Semiconductor layer 143 is configured to be in contact with the side of tunnel insulating layer 42. Semiconductor layer 143 is the region where the current path (channel) of memory cell MC and selection transistors ST1 and ST2 is formed. Semiconductor layer 143 covers the side and bottom surfaces of core layer 144. Block insulating layer 40, charge storage layer 41, and tunnel insulating layer 42 are removed at one end of memory pillar MP in the Z direction (end in the Z2 direction). As a result, semiconductor layer 143 is partially exposed. The impurity concentration of the exposed portion 143a of semiconductor layer 143 (hereinafter referred to as the exposed portion) is higher than the impurity concentration of the portion of semiconductor layer 143 covered by memory layer 142 (hereinafter referred to as the covered portion). For example, the crystallinity of the exposed portion 143a of semiconductor layer 143 is higher than the crystallinity of the covered portion of semiconductor layer 143. Semiconductor layer 143 contains silicon.

[0181] A metal layer (source line) 120 is disposed on the Z2 direction side end (exposed portion) 143a of the semiconductor layer 143 and on the semiconductor layer 101a. The metal layer 120 is in direct contact with the semiconductor layers 101a and 143 (143a).

[0182] The capping layer 145 is configured to cover the Z1-direction ends of the semiconductor layer 143 and the core layer 144 at the Z-direction end (Z1-direction end) of the storage pillar MP. For example, the side of the capping layer 145 is in contact with the tunnel insulating layer 42. The capping layer 145 may contain silicon, for example.

[0183] A conductor 104 is disposed on the Z1-oriented surface of the cover layer 145. Wiring (bit lines) 106 are disposed on the Z1-oriented surface of the conductor 104.

[0184] Reference Figure 7 This illustrates an example of the cross-sectional structure of the storage column MP along the XY plane (planar structure viewed from the Z direction). More specifically, Figure 7 A cross-sectional structure of the storage pillar MP in the layer including the conductive layer 103 is shown.

[0185] In a cross-section including the conductive layer 103, a core layer 144 is disposed, for example, at the center of the storage pillar MP. A semiconductor layer 143 covers the sides of the core layer 144. A tunnel insulating layer 42 covers the sides of the semiconductor layer 143. A charge storage layer 41 covers the sides of the tunnel insulating layer 42. A bulk insulating layer 40 covers the sides of the charge storage layer 41. The conductive layer 103 covers the sides of the bulk insulating layer 40. The core layer 144, the tunnel insulating layer 42, and the bulk insulating layer 40 each, for example, comprise silicon oxide. The charge storage layer 41 has the function (property) of storing charge. The charge storage layer 41, for example, comprises silicon nitride.

[0186] For example, an insulating layer 109 containing a metal oxide such as aluminum oxide (AlO) is disposed between the conductive layer 103 and the block insulating layer 40.

[0187] The memory cell MC is formed by combining the memory pillar MP with the conductive layer 103, which serves as the word line WL. The selection transistor ST1 is formed by combining the memory pillar MP with the conductive layer 103, which serves as the select gate line SGD. The selection transistor ST2 is formed by combining the memory pillar MP with the conductive layer 103, which serves as the select gate line SGS. Thus, each memory pillar MP can function as a NAND string NS.

[0188] (a-8) Cross-sectional structure of the bonding pad

[0189] Reference Figure 8 The cross-sectional structure of the bonding pad BP is explained. Figure 8 This is a cross-sectional view showing an example of the cross-sectional structure of the bonding pad BP. Furthermore, in Figure 8 For the sake of simplicity, the construction of a BP without a bonding pad (dummy pad) connected to the circuit is illustrated.

[0190] like Figure 8 As shown, electrode 111 includes a copper layer 70 and a barrier metal layer 71. Electrode 211 includes a copper layer 72 and a barrier metal layer 73.

[0191] In the bonding process between the array chip 10 and the CMOS circuit chip 20, electrode 111 and electrode 211 are connected. Figure 8 In the example, the area of ​​electrode 111 in the bonding surface BF is approximately equal to the area of ​​electrode 211. In this case, if copper is used for both electrodes 111 and 211, the copper layer 70 of electrode 111 will be integrated with the copper layer 72 of electrode 211. As a result, it may become difficult to confirm the copper boundaries between the two electrodes 111 and 211. However, the bonding of the two semiconductor chips 10 and 20 can be confirmed by the deformation of the shape formed by the bonding of electrodes 111 and 211 due to the positional offset of the bonding and / or the positional offset of the blocking metal layers 71 and 73 (the generation of discontinuities in the side).

[0192] When electrodes 111 and 211 are formed separately using the damascene process, the sides of electrodes 111 and 211 have a tapered shape. Therefore, in the cross-sectional shape of the bonding pad BP along the Z direction in the portion obtained by bonding electrodes 111 and 211, the sidewall (side) of the bonding pad BP is not straight, and the cross-sectional shape of the bonding pad BP is non-quadrilateral.

[0193] When electrode 111 and electrode 211 are bonded together, the barrier metal layers 71 and 73 cover the bottom surface, sides, and top surface of copper layers 70 and 72 that form the bonding pad BP. In contrast, in conventional wiring using copper, an insulating layer (SiN or SiCN, etc.) to prevent copper oxidation is provided on the top surface of the copper, and the barrier metal is not provided on the top surface of the copper. Therefore, even without any offset in the bonding position, it is possible to distinguish between the bonding pad BP and the conventional wiring layer.

[0194] (a-9) Construction of planar separated regions

[0195] Figure 9 This is a cross-sectional view showing the construction of the separation member BB2 within the planar separation region DA.

[0196] like Figure 9 As shown, the separation member BB2 is disposed within the planar separation region DA in the opening OX formed in the laminate including the insulating layer 125 and the dummy layer DM. The separation member BB2 separates the semiconductor layers 101a and 101c of the dummy layer DM and the insulating layer 121 into multiple portions 101a-3, 101a-4, 101c-3, 101c-4, 121-3, and 121-4.

[0197] Separating member BB2 has a conical cross-sectional shape. The conical shape of separating member BB2 is a positive conical shape. Separating member BB2 includes multiple parts b21, b22, b23, b24, and b25 arranged in the Z direction.

[0198] Part b21 is located on the surface (lower surface) along the Z1 direction of semiconductor layer 101a. Part b22 is located on the surface (upper surface) along the Z2 direction of semiconductor layer 101a. Part b23 is located on the surface (lower surface) along the Z1 direction of semiconductor layer 101c. Part b24 is located on the surface (upper surface) along the Z2 direction of semiconductor layer 101c (the surface of insulating layer 125 along the Z1 direction). Part b25 is located on the surface (upper surface) along the Z2 direction of insulating layer 125.

[0199] Regarding the linewidth dimensions of portions b21 and b22 of the discrete member BB2 within semiconductor layer 101a, the dimension D2b of portion b22 along the X direction (or Y direction) is larger than the dimension D2a of portion b21 along the X direction (or Y direction).

[0200] Regarding the linewidth dimensions of portions b23 and b24 of the discrete member BB2 within semiconductor layer 101c, the dimension D2d of portion b24 along the X direction (or Y direction) is larger than the dimension D2c of portion b23 along the X direction (or Y direction).

[0201] Regarding the linewidth dimensions of portions b24 and b25 of the separation member BB2 within the insulation layer 125, the dimension D2e of portion b25 along the X direction (or Y direction) is larger than the dimension D2d of portion b24 along the X direction (or Y direction).

[0202] In this way, the dimension (line width) of the separation member BB2 along the X direction (or Y direction) increases as it moves from the Z1 direction side toward the Z2 direction side.

[0203] Therefore, regarding the separation member BB2 embedded in the laminate including the dummy layer DM and the insulating layer 125, the dimension D2e of the separation member BB2 in the direction along the surface of the chip in the Z2 direction is larger than the dimension D2a of the separation member BB2 in the direction along the surface of the chip in the Z1 direction.

[0204] (a-10) Draw out the structure within the region

[0205] Reference Figure 10 , Figure 11A as well as Figure 11B The structure of the constituent elements in the lead-out region of the memory cell array region MA in the memory device 1 of this embodiment will be described.

[0206] Figure 10 This is a plan view showing the structure of the contact CC1 and the separation member BB1 in the lead-out area of ​​the memory cell array 11 in the memory device 1 of this embodiment. Figure 11A and Figure 11B This is a cross-sectional view showing the structure of the contact CC1 and the separation member BB1 in the lead-out area of ​​the memory cell array 11 in the memory device 1 of this embodiment. Figure 11A The construction of contact CC1 and its nearby components within the lead-out area along the X direction is shown. Figure 11B The construction of the contact CC1 and its adjacent components in the lead-out area along the Y direction is shown.

[0207] like Figure 10 , Figure 11A as well as Figure 11BAs shown, in the lead-out region, contact CC1 penetrates one or more conductive layers 103 within the stepped structure. Contact CC1 penetrates the conductive layer 103 of the connected object. Contact CC1 penetrates other conductive layers 103 and insulating layers 102 between the conductive layer 103 of the connected object and the semiconductor layer 101a. For example, multiple contacts CC1 are arranged along the X direction (and Y direction).

[0208] The contact CC1 includes a portion (hereinafter also referred to as the protrusion) 90 extending in a direction parallel to the surface of the chip (X and Y directions). The contact CC1 contacts the platform of the corresponding conductive layer 103 through the protrusion 90. In the contact portion between the conductive layer 103 and the protrusion 90, the insulating layer 109 is removed from the conductive layer 103. As a result, the Z2 direction surface of the protrusion 90 is in direct contact with the Z1 direction surface of the conductive layer 103.

[0209] The side of the protrusion 90 is covered by an insulating layer 150b. An insulating layer 150a is disposed in the Z direction between the insulating layer 150b and the conductive layer 103 (insulating layer 109). The insulating layer 109 is sandwiched between the insulating layer 150a and the conductive layer 103. The insulating layers 150a and 150b extend in the Y direction. The insulating layers 150a and 150b are components used in forming the protrusion 90 or products arising from such components. The material of the insulating layers 150a and 150b is silicon oxide.

[0210] Contact CC1 is electrically separated from other conductive layers 103 except for the corresponding conductive layer (the conductive layer of the connected object) 103 by insulator 151. Insulator 151 is disposed between the side of contact CC1 and the side of one or more conductive layers 103 through which contact CC1 penetrates. The material of insulator 151 is silicon oxide.

[0211] The contact CC1 includes a portion (hereinafter also referred to as a protrusion) 91 that protrudes into the dummy layer DM. For example, the protrusion 91 of the contact CC1 penetrates the semiconductor layer 101a. The Z2 direction side end (upper end) of the contact CC1 is located within the semiconductor layer 101c. There is a situation where, corresponding to the manufacturing process, the diameter of the upper end of the contact CC1 and the cross-sectional area in the direction parallel to the chip surface decrease from the Z1 direction side towards the Z2 direction side. Therefore, the contact CC1 tends to have an inverted conical shape.

[0212] In the lead-out region, the dummy layer DM is configured to overlap with the stepped structure (laminated structure 900) in the Z direction. As described above, the dummy layer DM includes a semiconductor layer (e.g., a silicon layer) 101a, an insulating layer (e.g., a silicon oxide layer) 121, and a semiconductor layer (e.g., a silicon layer) 101c. The protrusion 91 penetrates the semiconductor layer 101a and the insulating layer 121 of the dummy layer DM. The Z2 direction end of the protrusion 91 reaches the semiconductor layer 101c of the dummy layer DM.

[0213] An insulating film 155 is disposed between the dummy layer DM and the protrusion 91 of the contact CC1. Within the dummy layer DM, the insulating film 155 covers the protrusion 91. Through the insulating film 155, the dummy layer DM and the contact CC1 are electrically separated. The insulating film 155 is made of silicon oxide.

[0214] As described above, multiple support members (e.g., silicon oxide pillars) HR are disposed within the lead-out area. For example, each contact CC1 is disposed within the area between two support members HR arranged along the X (or Y) direction. The multiple contacts CC1 and the multiple support members HR are arranged alternately in the X (or Y) direction.

[0215] The support member HR penetrates one or more insulating layers 102 and one or more conductive layers 103 within the stepped structure. The end of the support member HR in the Z2 direction reaches the level where the dummy layer DM is provided. The end of the support member HR in the Z2 direction is located within the level where the semiconductor layer 101c is provided in the Z direction. The support member HR adjacent to the contact CC1 in the X direction penetrates the insulating layer 150a. The support member HR adjacent to the contact CC1 in the Y direction penetrates the insulating layers 150a and 150b.

[0216] The storage device 1 of this embodiment includes a separation member BB1 in the lead-out region. The separation member BB1 protrudes in the Z direction from the insulating layer 126 toward the stepped structure of the laminate 900. The separation member BB1 is continuous with the insulating layer 126. The separation member BB1 is an insulator. The material of the separation member BB1 is silicon oxide, the same material as the insulating layer 126.

[0217] Furthermore, the separating member BB1 may also be a member that is not continuous with the insulating layer 126. The separating member BB1 may also contain an insulating material that is different from the material of the insulating layer 126. There may also be cases where a void is provided inside the separating member BB1.

[0218] For example, the separating member BB1 has a lattice-like layout when viewed from the Z direction. The separating member BB1 includes a portion b1 extending in the X direction and a portion b2 extending in the Y direction. The separating member BB1 is arranged in the lead-out area in a manner that overlaps with the support member HR in the Z direction. The portion of the dummy layer DM surrounded by the lattice-like separating member BB1 has a quadrilateral planar shape when viewed from the Z direction.

[0219] Separating member BB1 penetrates the insulating layer 125 and the dummy layer DM. Separating member BB1 is disposed within a gap (opening) OP formed within the dummy layer DM and the insulating layer 125. Separating member BB1 is disposed between adjacent dummy layers DM in the X and Y directions. Separating member BB1 is positioned in the region between two contacts CC1 arranged in the X (or Y) direction. Separating member BB1 contacts the support member HR. For example, separating member BB1 covers the side of the support member HR within the layer of the dummy layer DM.

[0220] Separating member BB1 has a tapered cross-sectional shape. The tapered shape of separating member BB1 is the same as that of separating member BB2, which is a positive tapered shape. Separating member BB1 is disposed within an opening OP formed in a laminate including insulating layer 125 and dummy layer DM. Separating member BB1 includes multiple portions b11, b12, b13, b14, and b15 arranged in the Z direction.

[0221] Part b11 is located on the surface (lower surface) along the Z1 direction of semiconductor layer 101a. Part b12 is located on the surface (upper surface) along the Z2 direction of semiconductor layer 101a. Part b13 is located on the surface (lower surface) along the Z1 direction of semiconductor layer 101c. Part b14 is located on the surface (upper surface) along the Z2 direction of semiconductor layer 101c (the surface of insulating layer 125 along the Z1 direction). Part b15 is located on the surface (upper surface) along the Z2 direction of insulating layer 125.

[0222] Regarding the linewidth dimensions of portions b11 and b12 of the discrete member BB1 within semiconductor layer 101a, the dimension D1b of portion b12 along the X direction (or Y direction) is larger than the dimension D1a of portion b11 along the X direction (or Y direction).

[0223] Regarding the linewidth dimensions of portions b13 and b14 of the discrete member BB1 within semiconductor layer 101c, the dimension D1d of portion b14 along the X direction (or Y direction) is larger than the dimension D1c of portion b13 along the X direction (or Y direction).

[0224] Regarding the linewidth dimensions of portions b14 and b15 of the separation member BB1 within the insulation layer 125, the dimension D1e of portion b15 along the X direction (or Y direction) is larger than the dimension D1d of portion b14 along the X direction (or Y direction).

[0225] In this way, the dimension (line width) of the separating member BB1 along the X direction (or Y direction) increases as it moves from the Z1 direction side toward the Z2 direction side.

[0226] Therefore, regarding the separation member BB1 embedded in the laminate including the dummy layer DM and the insulating layer 125, the dimension D1e of the separation member BB1 along the X direction (or Y direction) on the Z2 direction side is larger than the dimension D1a of the separation member BB1 along the X direction (or Y direction) on the Z1 direction side.

[0227] Corresponding to the positive conical shape of the separating member BB1, the semiconductor layers 101a and 101c and the insulating layers 121 and 125 within the region surrounded by the separating member BB1 have an inverted conical cross-sectional shape. The dimension of the semiconductor layer 101a along the X direction (or Y direction) is larger than the dimension of the insulating layer 125 along the X direction (or Y direction). For example, the dimension of the separating member BB1 in the Z direction is equal to the sum of the dimension of the dummy layer DM in the Z direction and the dimension of the insulating layer 125 in the Z direction.

[0228] For example, the dimension D1e of the separating member BB1 is larger than the dimension D2e of the separating member BB2. For example, the dimension D1a of the separating member BB1 is larger than the dimension D2a of the separating member BB2.

[0229] Furthermore, at each part (position) b11, b12, b13, b14, and b15 in the Z direction of the separating member BB1, there are cases where the dimension of a certain part in the Z direction along the X direction is substantially the same as the dimension of that part in the Y direction, and there are also cases where they are different.

[0230] In this embodiment, the separating member BB1 divides the semiconductor layers 101a and 101c and the insulating layer 121 of the dummy layer DM into multiple portions 101a-1, 101a-2, ..., 101c-1, 101c-2, ..., 121-1, 121-2, ... according to each contact CC1 reaching the dummy layer DM. Thus, the multiple portions of the semiconductor layers 101a and 101c are electrically isolated from each other. The semiconductor layers 101a and 101c surrounded by the separating member BB1 are not electrically connected to other components (e.g., wiring or pads) on the Z2 direction side.

[0231] In the storage device 1 of this embodiment, multiple contacts CC1 are electrically separated from each other without being connected via the dummy layer DM by means of the separation member BB1.

[0232] (b) Manufacturing method

[0233] Reference Figures 12 to 31 The manufacturing method of the storage device 1 according to the first embodiment will be described. Figures 12 to 23 Each of these is a cross-sectional process diagram showing the manufacturing process of the array chip 10 in the memory device 1 of this embodiment.

[0234] like Figure 12 As shown, on the first surface of the array chip 10 facing the Z1 direction, a semiconductor layer 101c, such as a silicon layer, is formed on a semiconductor substrate (e.g., a silicon substrate) 100 by, for example, CVD. An insulating layer 121, such as a silicon oxide layer, is formed on the semiconductor layer 101c. A semiconductor layer 101a, such as a silicon layer, is formed on the insulating layer 121.

[0235] A stack 900 comprising multiple insulating layers 102, 102A and multiple sacrificial layers 999 is formed on semiconductor layer 101a by CVD. In the stack 900, insulating layers 102 and sacrificial layers 999 are deposited alternately in the Z1 direction. The sacrificial layer 999 is replaced by a conductive layer (word line and select gate line) 103 in a subsequent process. Insulating layers 102, 102A are, for example, silicon oxide layers. Sacrificial layer 999 is, for example, a silicon nitride layer.

[0236] In the laminate 900, the thickness of the uppermost insulating layer 102A in the Z direction is greater than the thickness of the other insulating layers 102 in the Z direction.

[0237] Insulating layer 999A is formed on insulating layer 102A. The material of insulating layer 999A is the same as that of sacrificial layer 999 (e.g., silicon nitride).

[0238] In the lead-out region of the array chip 10, the end of the stack 900 in the X direction is processed into a stepped shape by photolithography and etching.

[0239] Thus, a stepped structure is formed in the lead-out region. In the stepped structure, each sacrificial layer 999 exposes its surface (facing the Z1 direction) at the portion that becomes the platform of the conductive layer 103.

[0240] In the contact area CA and the planar separation area DA, the insulating layers 102, 102A, 999A and the sacrificial layer 999 are removed.

[0241] like Figure 13As shown, insulating layer 150a is formed on insulating layers 102, 102A, 999A, and sacrificial layer 999 by CVD in a stepped configuration. Insulating layer 150a covers the sidewalls (steps) of insulating layers 102, 102A, and sacrificial layer 999 in the lead-out region. Hereinafter, insulating layer 150a is also referred to as a sidewall spacer. The material of sidewall spacer 150a is, for example, silicon oxide. For example, the thickness of sidewall spacer 150a in the Z direction is substantially equal to the thickness of insulating layer 102 in the Z direction.

[0242] Multiple insulating layers 150x are formed on the sidewall spacer film 150a by CVD and etching. Each of the multiple insulating layers 150x has a step (platform) constructed according to a step-by-step pattern, forming an independent pattern. For example, the insulating layer 150x is disposed in the region corresponding to the contact portion of the contact element CC1 of the subsequently formed conductive layer 103 platform. The insulating layer 150x extends in the Y direction. Hereinafter, the insulating layer 150x is referred to as the spacer film. The material of the spacer film 150x is, for example, the same as the material of the sacrificial layer 999 (e.g., silicon nitride). For example, the thickness T1 of the spacer film 150x in the Z direction is substantially equal to the sum of the thickness T2 of one insulating layer 102 and the thickness T3 of one sacrificial layer 999.

[0243] like Figure 14 As shown, in the memory cell array region MA, an insulating layer 160, such as a silicon oxide layer, is formed on the sidewall spacer film 150a and spacer film 150x using the TEOS CVD method. The insulating layer 160 uses the uppermost insulating layer 102A of the laminate 900 as a barrier and is planarized by chemical mechanical polishing (CMP).

[0244] In the contact region CA and the planar separation region DA, an insulating layer 160 is formed on the semiconductor layer 101a.

[0245] like Figure 15 As shown, within the lead-out region of the memory cell array region MA, multiple openings are formed in a predetermined area of ​​the insulating layer 160 by photolithography and etching. The lower ends of the openings reach the semiconductor layer 101c. After forming the openings, multiple support members HR are formed within the openings. The support members HR penetrate the stepped structure of the sidewall spacer film 150a and the laminate 900. The support members HR are formed, for example, by an insulator such as silicon oxide.

[0246] The support member HR located at the formation coordinate of the contact CC1 is selectively removed from among the multiple support members HR. As a result, an opening OP1 is formed at the formation coordinate of the contact CC1 in the lead-out region, from the insulating layer 160 to the semiconductor layer 101c. For example, a portion of the support member HR (not shown) may remain at the bottom of the opening OP1.

[0247] Within the contact region CA, the opening OP1, which reaches the semiconductor layer 101c at the bottom, is similarly formed within the insulating layer 160 at the formation coordinate of the contact CC2.

[0248] like Figure 16 As shown, etching is performed via the opening OP1 to selectively remove the spacer film 150x.

[0249] As a result, the spacer film 150x recedes in a direction parallel to the surface of the semiconductor substrate 100. Consequently, in a direction parallel to the surface of the semiconductor substrate 100, the recess (groove) R1a is formed in the opening OP1 at a position corresponding to the platform portion of the conductive layer 103. The recess R1a and the spacer film 150x between the insulating layer 160 and the insulating layer 150a are formed accordingly.

[0250] Simultaneously etch (remove) the sacrificial layer 999, which is made of the same material as the spacer 150x.

[0251] At the location of the sacrificial layer 999, the recess R1b is formed between the sidewall spacer 150a and the insulating layer 102, or between two adjacent insulating layers 102 in the Z direction.

[0252] Based on the thickness of the spacer membrane 150x, the dimension of the recess R1a in the Z direction is larger than the dimension of the recess R1b in the Z direction.

[0253] like Figure 17 As shown, insulator 151 is formed within opening OP1, which includes recesses R1a and R1b. Insulator 151 is selectively etched by isotropic etching, such as wet etching.

[0254] The insulator 151 is removed from the recess R1a, which has a large space. Within the recess R1a, the spacer 150x is exposed relative to the opening OP1.

[0255] On the other hand, the insulator 151 remains in the recess R1b, which has a smaller space than the recess R1a. The sacrificial layer 999 is sealed by the insulator 151 remaining in the recess R1b and is not exposed relative to the opening OP1.

[0256] For example, the insulator 151 is removed at the bottom of the opening OP1. The semiconductor layers 101a, 101c and the insulating layer 121 are exposed relative to the opening OP1.

[0257] like Figure 18 As shown, an insulating film 155 is formed on the surface of the semiconductor layers 101a and 101c and the insulating layer 121 exposed through the opening OP1 by the WVG (Water vapor generation) method.

[0258] For example, in the contact area CA, an insulating film 155 is formed on the surface of the exposed semiconductor layers 101a, 101c and the insulating layer 121.

[0259] like Figure 19 As shown, the spacer film 150x is selectively etched (removed). The spacer film 150x is further recessed in a direction parallel to the surface of the semiconductor substrate 100. As a result, the dimension of the recess R2 of the spacer film 150x in the direction parallel to the surface of the semiconductor substrate 100 is larger than the dimension of the insulator 151 in the direction parallel to the surface of the semiconductor substrate 100.

[0260] like Figure 20 As shown, in the lead-out region and contact region CA, the sacrificial member 180 fills the opening OP1, including the recess R2. The sacrificial member 180 is selectively removed from the upper surface of the insulating layers 160 and 102A by etching. The upper end of the sacrificial member 180 is aligned with the upper surface of the insulating layer 160. The material of the sacrificial member 180 is, for example, a semiconductor such as amorphous silicon.

[0261] like Figure 21 As shown, a replacement process for forming the word line WL is performed. The sacrificial layer 999 is selectively removed via a slit (not shown) formed within the laminate 900. The spacer membrane 150x is divided into multiple sections in the Y direction through this slit. The spacer membrane 150x is in contact with the slit. Collapse of the laminate 900 in the state where the sacrificial layer 999 has been removed is suppressed by the support member HR.

[0262] After the sacrificial layer 999 is removed, an insulating layer 109, such as an alumina film, is formed in the space of the laminate 900 in such a way that it does not fill the space where the sacrificial layer 999 has been removed. A conductive layer 103 is formed on the insulating layer 109 in the space of the laminate 900 where the sacrificial layer 999 has been removed.

[0263] In this embodiment, the spacer membrane 150x is removed simultaneously with the removal of the sacrificial layer 999 in the lead-out region. The space created by the removal of the spacer membrane 150x is connected to the gap. The insulating layer 109 and the conductive layer 103 are formed within the space created by the removal of the spacer membrane 150x. However, the space created at the location of the spacer membrane 150x is larger than the space between the insulating layers 102. Therefore, the space created at the location of the spacer membrane 150x is not blocked by the insulating layer 109 and the conductive layer 103.

[0264] Next, the insulating layer 109 and conductive layer 103 in the gap (not shown) used for replacement processing are removed. At this time, in the lead-out area, the insulating layer 109 and conductive layer 103 in the space created at the position of the spacer 150x are removed simultaneously with the insulating layer 109 and conductive layer 103 in the gap.

[0265] An insulator such as silicon oxide fills the gaps. At the same time, an insulating layer 150b fills the space created at the position of the spacer film 150x.

[0266] like Figure 22 As shown, sacrificial member 180 is removed from the lead-out region and contact region CA of the memory cell array region MA. The removal of sacrificial member 180 creates an opening OP2. At the bottom of the recess R2, a portion of insulating layer 150a and insulating layer 109 is removed via the opening OP2. Thus, in the lead-out region, the platform of conductive layer 103 is exposed within the recess R2.

[0267] like Figure 23 As shown, the conductor fills the opening OP2, which includes the recess R2. Thus, the contact CC1 is formed within the opening OP2 of the lead-out region.

[0268] Each of the formed contacts CC1 penetrates one or more insulating layers 102 and one or more conductive layers 103. The Z2-direction end (protrusion 91) of the contact CC1 reaches the insulating film 155 within the semiconductor layers 101a and 101c. The contact CC1 contacts the platform of the corresponding conductive layer 103 via a portion extending in the X (and Y) directions (protrusion 90). Thus, the contact CC1 is electrically connected to the corresponding conductive layer 103.

[0269] An insulator 151 is disposed between the side of the contact CC1 and the side of the conductive layer 103. Thus, the contact CC1 is electrically isolated from other conductive layers 103 besides the corresponding conductive layer 103.

[0270] In the contact region CA, contact CC2 and contact CC1 are formed substantially simultaneously within the insulating layer 160. The end of contact CC2 extends into the insulating film 155 within the semiconductor layers 101a and 101c.

[0271] Subsequently, various conductors 104, 161, 164, wiring 106, 163, electrodes 111, and insulating layers 162, 165, 169 are sequentially formed to connect to the storage column MP and contacts CC1, CC2 using known techniques.

[0272] The array chip 10 is formed through the above processes.

[0273] The CMOS circuit chip 20 is manufactured separately from the array chip 10.

[0274] Figures 24 to 31 These are cross-sectional process diagrams showing the manufacturing process after the array chip 10 and the CMOS circuit chip 20 in the memory device 1 of this embodiment are bonded together.

[0275] like Figure 24 As shown, the array chip 10 is bonded to the CMOS circuit chip 20 with the Z1-oriented surface of the array chip 10 facing the Z2-oriented surface of the CMOS circuit chip 20. After the two chips are bonded, the semiconductor substrate 100 of the array chip 10 is removed by grinding, wet etching, and CMP. As a result, the semiconductor layer 101c is exposed in the Z2 direction.

[0276] like Figure 25 As shown, the resist mask 182 is formed on the semiconductor layer 101c by photolithography and etching. An opening OP3 is formed within the resist mask 182. The opening OP3 is disposed within the resist mask 182 in such a way that the semiconductor layer 101c in the region where the memory pillar MP is formed in the memory cell array region MA is exposed.

[0277] In the lead-out region, contact region CA, and planar separation region DA, the semiconductor layer 101c is covered by a resist mask 182.

[0278] like Figure 26 As shown, based on the pattern of the resist mask 182, the semiconductor layer 101c is partially removed (etched) by reactive ion etching (RIE). This exposes the Z2-direction end of the memory pillar MP. Through etching, a step is formed between the semiconductor layers 101a and 101c within the memory cell array region MA.

[0279] The exposed memory layer 142 of the memory pillar MP is removed by etching. As a result, the semiconductor layer 143 of the memory pillar MP is exposed.

[0280] By ion implantation into the semiconductor layer 143, impurities (dopants) are added to the exposed portion (exposed portion) 143a of the semiconductor layer 143.

[0281] Subsequently, laser annealing is performed on the exposed portion 143a containing the added impurities. As a result, the exposed portion 143a of the semiconductor layer 143 crystallizes.

[0282] like Figure 27 As shown, after removing the resist mask 182, the metal layer 120 is formed on the semiconductor layers 101a and 101c by physical vapor deposition (PVD), photolithography, and etching. The metal layer 120 extends from the Z2-oriented surface of the semiconductor layer 101a to the Z2-oriented surface of the semiconductor layer 101c via the side surface of the semiconductor layer 101c.

[0283] An insulating layer 125 is formed on the array chip 10 by CVD in such a way that it covers the semiconductor layer 101c and the metal layer 120.

[0284] like Figure 28 As shown, in the planar separation region DA, a gap (opening) OP4a for separating the planes PLN is formed within the insulating layer 125, the semiconductor layer 101c, the insulating layer 121, and the semiconductor layer 101a. Thus, in the planar separation region DA, the semiconductor layers 101a and 101c are separated according to each plane PLN. The gap OP4a has a lattice-like structure when viewed from the Z direction. The gap OP4a has a conical cross-sectional shape.

[0285] In a process performed simultaneously with the formation of the opening OP4a in the planar separation region DA, the opening OP4b in the contact region CA is formed within the insulating layer 125, semiconductor layer 101c, insulating layer 121, and semiconductor layer 101a, such that the end (insulating film 155) of the contact CC2 in the Z2 direction is exposed. For example, the opening OP4b has a quadrilateral or circular structure when viewed from the Z direction. The opening OP4b has a conical cross-sectional shape.

[0286] In the process of separating the semiconductor layers 101a and 101c in the planar separation region DA, the gap OP4c is formed in the lead-out region of the array chip 10 in such a way that it penetrates the insulating layer 125, the semiconductor layer 101c, the insulating layer 121, and the semiconductor layer 101a in the Z direction. The gap OP4c is formed with a lattice-like layout when viewed from the Z direction. The gap OP4c has a positive conical cross-sectional shape.

[0287] The gap OP4c is provided in the area between two adjacent contact members CC1. For example, the gap OP4c is formed at a position that overlaps with the support member HR in the Z direction.

[0288] The insulating layer 102 closest to the source line side of the stack 900 (the uppermost insulating layer in the Z2 direction) is exposed via the slot OP4c. At the location of the slot OP4c, a step (groove) can be formed at the exposed portion of the insulating layer 102, corresponding to the etching used to form the slot OP4c.

[0289] like Figure 29 As shown, insulating layer 126 is formed on insulating layer 125, semiconductor layer 101c, insulating layer 121, and semiconductor layer 101a by CVD. The interior of the gap OP4a in the planar separation region DA, the interior of the opening OP4b in the contact region CA, and the interior of the gap OP4c in the lead-out region (memory cell array region MA) are filled by insulating layer 126.

[0290] In this manner, through the same process, the separation member BB1 in the lead-out area and the separation member BB2 in the planar separation area DA are formed within the gaps OP4a and OP4c formed in the insulating layers 121 and 125 and the semiconductor layers 101a and 101c. The separation members BB1 and BB2 are insulators that are continuous with the insulating layer 126.

[0291] Furthermore, the separation components BB1 and BB2 can also be formed through a different process than the formation of the insulating layer 126. For example, the components (insulators) used to form the separation components BB1 and BB2 can be embedded in the gaps OP4a and OP4c. Then, the insulating layer 126 is formed on the insulating layer 125 and the separation components BB1 and BB2.

[0292] There are also cases where voids are generated within the separation components BB1 and BB2 during their formation.

[0293] The formed separation components BB1 and BB2 have a lattice-like structure when viewed from the Z direction. The shapes of the formed separation components BB1 and BB2, and the gaps OP4a and OP4c, respectively, have a conical cross-sectional structure. That is, in the separation components BB1 and BB2, the dimension along the X direction (or Y direction) of the portion on the Z2 direction side (array chip 10 side) is larger than the dimension along the X direction (or Y direction) of the portion on the Z1 direction side (CMOS circuit chip 20 side).

[0294] like Figure 30 As shown, at the location where the memory cell array region MA overlaps with the metal layer 120 in the Z direction, the opening is formed in the insulating layers 125 and 126 by photolithography and etching.

[0295] After the opening is formed, metal wiring 127 is formed on the insulating layer 126. The wiring 127 is processed into a predetermined shape by photolithography and etching.

[0296] The components of wiring 127 are embedded in the openings of insulating layers 125 and 126. Thus, the contact CX is formed in the opening in a manner that connects to the metal layer 120.

[0297] In the contact region CA, an opening is formed within the insulating layer 126 in the area overlapping with the contact CC2 in the Z direction, through a process performed simultaneously with the formation of the opening in the memory cell array region MA. During the formation of this opening, the insulating film 155 covering the Z2 direction side end of the contact CC2 is removed. Wiring 127 is formed on the insulating layer 126 in a manner that fills the opening. Thus, in the contact region CA, the contact CZ is formed to connect the wiring 127 to the contact CC2. The contact CZ is in direct contact with the contact CC2. Furthermore, during the formation of the opening OP4b (see...), Figure 28 Remove the insulating film 155 from the end of the contact CC2 on the Z2 direction side.

[0298] For example, in the planar separation region DA, wiring 127 is formed on the insulating layer 126.

[0299] like Figure 31 As shown, an oxide insulating layer 128 is formed on the wiring 127 and the insulating layer 126. An oxide insulating layer 129 is formed on the insulating layer 128.

[0300] The storage device 1 of this embodiment is completed through the above procedures.

[0301] (c) Summary

[0302] In the connection between multiple conductive layers and wiring in a stepped structure of a storage device, a contact that penetrates multiple conductive layers is used. In this case, the contact is electrically isolated from other components besides the corresponding conductive layer.

[0303] For example, when the contact reaches a semiconductor layer that overlaps with the stepped structure in the Z direction, the contact is electrically separated from the semiconductor layer by an insulating film formed between the semiconductor layer and the contact.

[0304] When the insulating film formed between the contact and the semiconductor layer is thin, the contact may be electrically connected to the semiconductor layer. In this case, multiple contacts may be electrically connected via the semiconductor layer.

[0305] Assuming that the insulating film between the contacts and the semiconductor layer is thick to ensure sufficient insulation, volume expansion of the component due to the formation of this insulating film may occur within the stepped structure near the contacts. This insulating film is formed prior to the replacement of the sacrificial layer-conductive layer in the stepped structure (laminate).

[0306] In this case, after the sacrificial layer is removed from the interior of the stepped structure during the replacement process, the expanded insulating film will compress the space where the sacrificial layer was removed. That is, the space where the sacrificial layer was removed will become smaller. As a result, there is a possibility of poor embedding of the conductive layer in the space where the sacrificial layer was removed.

[0307] Therefore, it is difficult to increase the thickness of the insulating film between the contact and the semiconductor layer.

[0308] like Figure 4 , Figures 10 to 11B As shown, in the storage device 1 of this embodiment, an insulator separation member BB1 is provided in the lead-out region of the stepped structure. The separation member BB1 divides the semiconductor layers 101a and 101c that overlap with the stepped structure in the Z direction into multiple portions 101a-1, 101a-2, ..., 101c-1, 101c-2, ... The separation member BB1 is provided between multiple contacts CC1 that each penetrate the stepped structure.

[0309] In this way, the separating member BB1 electrically separates the multiple contacts CC1 from each other. Thus, in this embodiment, electrical conduction between the multiple contacts CC1 is prevented without increasing the thickness of the insulating film 155.

[0310] The contact CC1, formed in a manner that penetrates the step structure and the semiconductor layer 101a, tends to have a smaller diameter and cross-sectional area from the Z1 direction side toward the Z2 direction side. Therefore, the separation member BB1, which has a tapered cross-sectional shape with a linewidth dimension that expands from the Z1 direction side toward the Z2 direction side, can separate the semiconductor layer 101a with high positional accuracy while suppressing interference with the contact CC1 among multiple contact CC1s.

[0311] On the other hand, there is a case where the upper end of the contact CC1 is located in the region between the Z2 direction side (upper surface) and the Z1 direction side (lower surface) of the upper semiconductor layer 101c of the two stacked semiconductor layers 101a and 101c. That is, the contact CC1 exists at the lower surface of the semiconductor layer 101c, but not at the upper surface. Therefore, even when the upper end of the contact CC1 is located within the semiconductor layer 101c, the separation member BB1 with the above-described positive conical shape can separate the semiconductor layer 101c with high positional accuracy among the multiple contacts CC1 while suppressing interference with the contact CC1.

[0312] Furthermore, the separation member BB1 for separating the contacts CC1 and the separation member BB2 for separating the planar PLNs (source lines) are formed substantially simultaneously. Therefore, in the memory device 1 of this embodiment, even if the separation member BB1 is formed within the memory cell array region MA, the increase in manufacturing steps and excessive increase in cost can be avoided.

[0313] As described above, the storage device 1 of this embodiment can suppress defects such as short circuits between components.

[0314] (2) Second implementation method

[0315] Reference Figure 32 and Figure 33 The storage device of the second embodiment will be described.

[0316] Figure 32 This is a plan view showing a construction example of the storage device 1 in this embodiment. Figure 33 This is a cross-sectional view showing a construction example of the storage device 1 in this embodiment.

[0317] like Figure 32 and Figure 33 As shown, the support member HR can also be formed in the region between the contact member CC1 and the separation member BB1. The Z2 direction end of the support member HR is located within the semiconductor layer 101c of the dummy layer DM.

[0318] The separating member BB1 does not overlap with the supporting member HR in the Z direction. The separating member BB1 surrounds the area of ​​the dummy layer DM where the supporting member HR and the contact member CC1 are located.

[0319] For example, one of the two support members HR that sandwich a contact CC1 in the X direction has a support member HR that penetrates the insulation layer 150b.

[0320] In this embodiment, similar to the first embodiment, in the lead-out region of the memory cell array region MA, the semiconductor layers 101a and 101c are independent for each corresponding contact CC1. As a result, the multiple contacts CC1 are separated from each other.

[0321] As described above, the storage device of the second embodiment can suppress the malfunction of the storage device in substantially the same way as the first embodiment.

[0322] (3) Third implementation

[0323] Reference Figure 34 The storage device of the third embodiment will be described.

[0324] Figure 34 This is a cross-sectional view showing a construction example of the storage device 1 in this embodiment.

[0325] like Figure 34 As shown, in this embodiment, an insulating film covering the protrusion 91 of the contact CC1 is not provided within the dummy layer DM. The protrusion 91 is in direct contact with the semiconductor layers 101a and 101c.

[0326] As described above, within the lead-out region, semiconductor layers 101a and 101c are electrically separated by a lattice-shaped separation member (insulator) BB1, according to each corresponding contact CC1.

[0327] Therefore, even if the contact CC1 is in direct contact with the semiconductor layers 101a and 101c, the current does not flow between the semiconductor layer 101a, which functions as part of the source line SL, and the contact CC1, or between the two contacts CC1, due to the isolation provided by the separating member BB1.

[0328] Therefore, there are also cases where the insulating film 155 of the above-described embodiment may not be provided between the contact CC1 and the semiconductor layers 101a and 101c.

[0329] For example, in the manufacturing process of the memory device 1 of this embodiment, the process of forming the insulating film (WVG process) between the semiconductor layers 101a, 101c and the protrusion 91 of the contact CC1 can be eliminated. As a result, the manufacturing cost of the memory device 1 of this embodiment can be reduced.

[0330] As described above, the storage device of the third embodiment can suppress the malfunction of the storage device in the same way as the embodiments described above.

[0331] (4) Fourth implementation method

[0332] Reference Figures 35 to 44 The storage device of the fourth embodiment and its manufacturing method will be described.

[0333] (a) Construction example

[0334] Figure 35 This is a cross-sectional view showing the structure of the contact CC3 and the separation member BB1 in the lead-out area of ​​the memory cell array 11 in the memory device 1 of this embodiment.

[0335] like Figure 35 As shown, in the storage device 1 of this embodiment, a plurality of contacts (contact plugs) CC3 are provided in the lead-out area within the storage cell array region MA. Similar to the embodiment described above, the contacts CC3 penetrate one or more insulating layers 102 and one or more conductive layers 103 within the stepped structure of the lead-out area.

[0336] In this embodiment, the structure of contact CC3 differs from that of contact CC1 in other embodiments of the memory device 1. The protruding portion 90 on the side of contact CC3 contacts the side of conductive layer 103 (word line WL and select gate lines SGD, SGS). Conductive layer 103 has a portion protruding in the Z1 direction at the contact portion with contact CC3.

[0337] Therefore, in the storage device 1 of this embodiment, the electrical connection between the contact CC3 and the conductive layer 103 can be ensured.

[0338] In addition, the support member HR can also be with Figure 32 Similarly, it is configured in the area between the separating member BB1 and the contact member CC3.

[0339] (b) Manufacturing method

[0340] Reference Figures 36 to 44 The manufacturing method of the storage device 1 in this embodiment will be described. Figures 36 to 44 These are cross-sectional process diagrams showing the manufacturing process of the storage device 1 according to this embodiment.

[0341] like Figure 36 As shown, similarly to the manufacturing method of the memory device 1 in the first embodiment, semiconductor layers 101a and 101c and insulating layer 121 are formed on the semiconductor substrate 100. A laminate 900 including multiple insulating layers 102 and 102A and multiple sacrificial layers 999 is formed on the semiconductor layer 101a. A stepped structure is formed at the end of the laminate 900 in the X direction.

[0342] The spacer 150y is formed in a manner that covers the laminate 900. The material of the spacer 150y is, for example, the same as the material of the sacrificial layer 999 (e.g., silicon nitride).

[0343] The spacer film 150y is processed into a predetermined shape using photolithography and RIE. Thus, as... Figure 37 As shown, multiple spacer membranes 150z are formed individually at each stage of a stepped structure. For example, the thickness T4 of the spacer membrane 150z is substantially the same as the thickness T2 of the insulating layer 102.

[0344] An insulating layer 160 is formed on the laminate 900 and the spacer film 150z. The insulating layer 160 is planarized by etching back and CMP methods to align the upper surface of the insulating layer 160 with the upper surface of the laminate 900. The material of the insulating layer 160 is, for example, silicon oxide formed using TEOS.

[0345] In the contact region CA and the planar separation region DA, an insulating layer 160 is formed on the semiconductor layer 101a.

[0346] like Figure 38 As shown, in the lead-out area of ​​the memory cell array region MA, multiple support members HR are formed in a through-step structure. The lower end of the support member HR reaches the semiconductor layer 101c.

[0347] The support member HR at the location where the contact CC3 is to be formed is removed from the plurality of support members HR. As a result, an opening OP1 is formed in the area where the contact CC3 is to be formed. For example, at the bottom of the opening OP1, semiconductor layers 101a and 101c are exposed.

[0348] In the contact area CA, at the location where the contact CC2 is to be formed, an opening OP1 is formed simultaneously with the opening OP1 in the lead-out area, exposing the semiconductor layers 101a and 101c at the bottom.

[0349] The spacer film 150z is selectively etched through the opening OP1. As a result, the spacer film 150z recedes in a direction parallel to the surface of the semiconductor substrate 100. The sacrificial layer 999, which is made of the same material as the spacer film 150z, also recedes in the same direction parallel to the surface of the semiconductor substrate 100.

[0350] Therefore, a groove R5a is formed within the opening OP1, corresponding to the position of the platform portion of the conductive layer 103. A groove R5b is formed between two adjacent insulating layers 102 in the Z direction.

[0351] For example, in the Z direction, the size of slot R5a is larger than the size of slot R5b.

[0352] like Figure 39 As shown, insulator 151 is formed in opening OP1, which includes recesses R5a and R5b.

[0353] Wet etching is selectively performed on insulator 151. Insulator 151 remains in the groove R5b of the opening OP1. Insulator 151 is removed from the groove R5a, which has a larger size.

[0354] Next, an oxidation process based on the WVG method is performed. The exposed portions of the semiconductor layers 101a, 101c and the insulating layer 121 are oxidized. As a result, an insulating film 155 is formed on the semiconductor layers 101a, 101c and the insulating layer 121 at the bottom of the opening OP1.

[0355] like Figure 40 As shown, the sacrificial member 180 fills the opening OP1, which includes the trench R5a. The sacrificial member 180 is, for example, amorphous silicon. The trench R5a is sealed by the sacrificial member 180.

[0356] like Figure 41 As shown, a replacement process for forming conductive layer 103 is performed. As a result, insulating layer 109 and conductive layer (word line and select gate line) 103 are formed in the space within the stack 900 where sacrificial layer 999 has been removed.

[0357] As described above, the material of the spacer 150z is the same as that of the sacrificial layer 999. Therefore, the spacer 150z is also removed along with the sacrificial layer 999. In the lead-out region, the conductive layer 103 and the insulating layer 109 are also formed in the space where the spacer 150z has been removed.

[0358] like Figure 42 As shown, in the lead-out region, the sacrificial member 180 is selectively removed. This forms the opening OP2. The insulating layer 109 covering the sides of the conductive layer 103 is exposed relative to the opening OP2. In the opening OP2, the exposed insulating layer 109 is selectively removed. This exposes the sides of the conductive layer 103 within the opening OP2.

[0359] like Figure 43 As shown, contact CC3 fills the opening OP2. As described above, in the lead-out area (stepped structure), the insulating layer 109 is removed from the side of the conductive layer 103. Therefore, contact CC3, filled in the opening OP2, is in direct contact with the conductive layer 103. This ensures electrical connection between contact CC3 and the conductive layer 103.

[0360] As a result, each contact CC3 is formed to be connected to the corresponding conductive layer 103. The side of each contact CC3 is in direct contact with the side of the corresponding conductive layer 103.

[0361] In the contact area CA, the contact CC2 and the contact CC3 are formed substantially simultaneously within the insulating layer 160.

[0362] The ends of contacts CC2 and CC3 reach the insulating film 155 within semiconductor layers 101a and 101c.

[0363] Subsequently, bit lines BL and other wiring 163 are formed in the array chip 10 in the same manner as in the embodiment described above. After the array chip 10 is formed through the above processes, it is attached to the CMOS circuit chip 20 in the same manner as in the embodiment described above.

[0364] After that, as Figure 44 As shown, the source line, which includes a portion of the metal layer 120 and the semiconductor layer 101a, passes through the aforementioned... Figures 24 to 27 The manufacturing process is essentially the same as that described above. After the source wire is formed, it is processed through the same process as described above. Figure 28 and Figure 29 The manufacturing process is essentially the same as that of the separation member BB1 and the separation member BB2 within the planar separation region DA, which are formed substantially simultaneously within the lead-out region of the memory cell array region MA. Thus, within the lead-out region, the semiconductor layers 101a and 101c are divided into multiple portions. As a result, adjacent contacts CC3 are electrically separated by the separation member BB1.

[0365] Subsequently, through the above Figure 30 and Figure 31 The manufacturing process is essentially the same as that of the storage device 1 in this embodiment.

[0366] Furthermore, in this embodiment, the following can also be omitted. Figure 39 The oxidation process of semiconductor layers 101a and 101c based on the WVG method.

[0367] The storage device 1 of this embodiment can achieve substantially the same effects as the embodiment described above.

[0368] (5) Fifth Embodiment

[0369] Reference Figure 45 The storage device of the fifth embodiment will be described.

[0370] Figure 45 This is a cross-sectional view showing a construction example of the storage device 1 in this embodiment.

[0371] like Figure 45As shown, the support member HR, arranged in the X direction relative to the contact CC1, can also be configured in the lead-out area of ​​the memory cell array region MA in a manner that penetrates the insulating layers 150a and 150b. In the layer where the support member HR penetrates the platform of the conductive layer 103, the side of the support member HR is in contact with the insulating layers 150a and 150b. The end of the support member HR in the Z2 direction contacts the separation member BB1.

[0372] In addition, within the lead-out area, the contact CC1 can also be arranged in a manner that makes the contact CC1 inclined relative to the XY plane.

[0373] The storage device 1 in this embodiment can achieve the same effect as the embodiment described above.

[0374] (6) Other

[0375] In the above embodiment, a memory device 1 is shown as an example having a configuration in which one CMOS circuit chip 20 is provided relative to one array chip 10. However, the memory device 1 of the embodiment may have a configuration in which multiple CMOS circuit chips 20 are provided relative to one array chip 10, or it may have a configuration in which multiple array chips 10 are provided relative to one CMOS circuit chip 20.

[0376] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A storage device comprising: The first chip includes a substrate and circuitry on the substrate; and The second chip is attached to the first chip. The second chip includes: A stack comprising a plurality of conductive layers arranged separately from each other in a first direction perpendicular to the surface of the second chip and a memory pillar penetrating the plurality of conductive layers; A first semiconductor layer is disposed above the stack in the first direction and is arranged with a portion of the source line in a second direction parallel to the surface of the second chip; A first contact, wherein the first contact penetrates at least one of the plurality of conductive layers and is connected to the first conductive layer, wherein a portion of the first contact located on the opposite side of the first chip than the first conductive layer is located within the first semiconductor layer; The second contact penetrates at least the second conductive layer of the plurality of conductive layers and is connected to the second conductive layer. A portion of the second contact that is on the opposite side of the first chip than the second conductive layer is located within the first semiconductor layer. The second contact and the first contact are arranged in the second direction. as well as The first separating member separates the first semiconductor layer in the second direction between the first contact and the second contact. The first separation member includes: a first portion located along the surface of the first chip side in the first semiconductor layer; The second part is located on the opposite side of the first chip along the first semiconductor layer. The first dimension of the second part along the second direction is larger than the second dimension of the first part along the second direction.

2. The storage device according to claim 1, The second chip also includes: The second semiconductor layer is disposed at the same level as the first semiconductor layer; and A second separation member is disposed between the first semiconductor layer and the second semiconductor layer, thereby separating the first semiconductor layer from the second semiconductor layer. The first semiconductor layer belongs to the first memory cell array. The second semiconductor layer belongs to a second memory cell array that is different from the first memory cell array.

3. The storage device according to claim 2, The second separation component includes: Part 3 is located on the surface along the first chip side of the first semiconductor layer and the second semiconductor layer; The fourth part is located on the opposite side of the first chip along the first semiconductor layer and the second semiconductor layer. The third dimension of the fourth part along the second direction is larger than the fourth dimension of the third part along the second direction.

4. The storage device according to claim 2, The material of the second separating component is the same as that of the first separating component.

5. The storage device according to claim 1, The first separation component includes: Part 5 extends in the second direction; and The sixth part extends in the third direction, which is parallel to and intersects the surface of the second chip.

6. The storage device according to claim 1, The second chip further includes a third semiconductor layer, which is disposed above and separately from the first semiconductor layer. The first contact and the second contact each penetrate the first semiconductor layer. The upper ends of the first contact and the second contact are located within the third semiconductor layer. The first separating member further separates the third semiconductor layer into multiple parts in the second direction between the first contact and the second contact.

7. The storage device according to claim 6, The second chip further includes a metal layer disposed on the portion of the source line and aligned with the third semiconductor layer in the second direction. The metal layer functions as another part of the source line, and overlaps with the memory column in the first direction across the source line.

8. The storage device according to claim 1, The second chip also includes a first insulating layer disposed above the first semiconductor layer. The first separating member is continuous with the first insulating layer.

9. The storage device according to claim 8, The second chip further includes a third contact that penetrates and connects to at least a third conductive layer of the plurality of conductive layers. A portion of the third contact located on the opposite side of the third conductive layer from the first chip is situated within the first semiconductor layer. The third contact is arranged in the second direction, separated from the first contact by the second contact. The first insulating layer extends above the second contact in the second direction. The first separating member, which is continuous with the first insulating layer, also separates the first semiconductor layer in the second direction between the second contact and the third contact.

10. The storage device according to claim 8, The material of the first separating component is the same as the material of the first insulating layer.

11. The storage device according to claim 1, The first semiconductor layer includes: The 7th part where the first contact is located; and The 8th part where the second contact is located The first separating member electrically separates the 7th part from the 8th part.

12. The storage device according to claim 11, Viewed from the first direction, the first separating member has a lattice-like structure. The 7th part and the 8th part are each surrounded by the 1st separating member. Viewed from the first direction, the 7th part and the 8th part each have a quadrilateral structure.

13. The storage device according to claim 1, The second chip also includes: The first insulating film portion is disposed between the first contact and the first semiconductor layer; and The second insulating film portion is disposed between the second contact and the first semiconductor layer.

14. The storage device according to claim 1, The first contact and the second contact are in contact with the first semiconductor layer.

15. The storage device according to claim 1, The second chip also includes a support member through which at least one of the plurality of conductive layers is penetrated. The supporting member overlaps with the first separating member in the first direction.

16. The storage device according to claim 1, The second chip further includes a first support member through which at least one of the plurality of conductive layers is penetrated. The first support member is disposed between the first contact member and the first separation member in the second direction. The portion of the first support member located on the opposite side of the first chip from the plurality of conductive layers is within the first semiconductor layer.

17. The storage device according to claim 1, The first contact element includes a protrusion extending in the second direction. The first conductive layer includes a platform on the first chip side that does not overlap with the plurality of conductive layers other than the first conductive layer. The protrusion contacts the surface of the platform on the side of the first chip. The second conductive layer is disposed between the first semiconductor layer and the first conductive layer. The first contact element penetrates the second conductive layer. A first insulator is provided between the first contact and the side of the second conductive layer.

18. The storage device according to claim 1, The second conductive layer is disposed between the first semiconductor layer and the first conductive layer. The first contact element is in contact with the side surface of the first conductive layer. The first contact element penetrates the second conductive layer. A first insulator is provided between the first contact and the side of the second conductive layer.

19. A storage device comprising: The first chip includes a substrate and circuitry on the substrate; and The second chip is attached to the first chip. The second chip includes: A stack comprising a plurality of conductive layers arranged separately from each other in a first direction perpendicular to the surface of the second chip and a memory pillar penetrating the plurality of conductive layers; A semiconductor layer is disposed above the laminate in the first direction; The first contact penetrates at least one of the plurality of conductive layers and is connected to the first conductive layer, wherein the upper end of the first contact is located within the semiconductor layer; The second contact penetrates and is connected to at least the second conductive layer of the plurality of conductive layers, the upper end of the second contact is located within the semiconductor layer, and the second contact and the first contact are arranged in a second direction parallel to the surface of the second chip; as well as A separating member separates the semiconductor layer in the second direction between the first contact and the second contact. The separation component includes: a first portion located along the surface of the first chip side in the semiconductor layer; The second part is located on the opposite side of the first chip in the semiconductor layer. The first dimension of the second part along the second direction is larger than the second dimension of the first part along the second direction.

20. The storage device according to claim 19, The portions of the semiconductor layer contained therein and separated from each other by the separating members, and the portions of the upper ends of the first contact and the second contact respectively, are not electrically connected to any member on the opposite side of the first chip.

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