Method for preparing polycrystalline silicon resistor and prepared polycrystalline silicon resistor

Abstract

The invention relates to a method for preparing a polycrystalline silicon resistor and the prepared polycrystalline silicon resistor. The method comprises the following steps: S1, forming a polycrystalline silicon layer on a substrate; s2, first ion implantation is carried out on the polycrystalline silicon layer, the implanted ions are boron, and the polycrystalline silicon layer with the first ion implantation is obtained; s3, performing second ion implantation on the polycrystalline silicon layer subjected to the first ion implantation, wherein the implanted ions are nitrogen; and S4, carrying out annealing treatment on the polycrystalline silicon layer subjected to the first ion implantation and the second ion implantation. The polycrystalline silicon resistor prepared by adopting the method disclosed by the invention is relatively low in mismatch degree.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor fabrication, and more specifically, to a method for fabricating polycrystalline silicon resistors and the fabricated polycrystalline silicon resistors. Background Technology

[0002] In today's era, microelectronics technology has become the foundation of the entire information industry and an important indicator of a nation's comprehensive strength and economic development. With the development of integrated circuit technology, chips with high speed, high device density, low power consumption, and low cost are increasingly becoming the main products in the manufacture of very large-scale integrated circuits.

[0003] In integrated circuit manufacturing, especially when it comes to the manufacture of polysilicon resistors, the behavior of hydrogen ions during the annealing process is an important consideration. Hydrogen ions readily penetrate the polysilicon interior during annealing and tend to move along grain boundaries. This phenomenon significantly affects the resistance value of polysilicon resistors, leading to resistor mismatch. Summary of the Invention

[0004] The purpose of this disclosure is to provide a method for preparing polycrystalline silicon resistors and the prepared polycrystalline silicon resistors, wherein the polycrystalline silicon resistors prepared by the method of this disclosure have a low degree of mismatch.

[0005] To achieve the above objectives, the first aspect of this disclosure provides a method for preparing polycrystalline silicon resistors, the method comprising the following steps: S1. A polycrystalline silicon layer is formed on the substrate; S2. Perform a first ion implantation on the polycrystalline silicon layer, wherein the implanted ion is boron, to obtain a first ion implanted polycrystalline silicon layer. S3. Perform a second ion implantation on the polycrystalline silicon layer implanted by the first ion implantation, wherein the implanted ion is nitrogen; S4. Anneal the polycrystalline silicon layer that has undergone the first ion implantation and the second ion implantation.

[0006] Optionally, the substrate includes one or more of silicon substrate, silicon oxide, and silicon oxynitride.

[0007] Optionally, in step S1, the method for forming a polycrystalline silicon layer on the substrate includes one or more of chemical vapor deposition, physical vapor deposition, and thermal growth.

[0008] Optionally, the thickness of the polycrystalline silicon layer is 800~1000 Å.

[0009] Optionally, in step S2, the ion implantation material is boron difluoride, and the conditions for the first ion implantation include: an implantation dose of (3~7) × 10⁻⁶. 15 pcs / cm 2 The injected energy is 2~7 keV.

[0010] Optionally, in step S3, the ion implantation material includes N2, and the conditions for the second ion implantation include: an implantation dose of (3~6) × 10⁻⁶. 15 pcs / cm 2 The injected energy is 5~10 keV.

[0011] Optionally, in step S4, the annealing conditions include: a time of 10-50 seconds and a temperature of 1000-1100°C. The atmosphere used for the annealing process includes one or more of N2, H2 and O2.

[0012] Optionally, the method further includes: S5. An isolation layer is formed on the polysilicon layer after annealing. The isolation layer comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride; Methods for forming the isolation layer include chemical vapor deposition and / or physical vapor deposition.

[0013] Alternatively, this method can be used for 40nm or 55nm processes.

[0014] The second aspect of this disclosure provides a polycrystalline silicon resistor prepared using the method described in the first aspect of this disclosure.

[0015] Optionally, the polysilicon resistor comprises a substrate layer, a polysilicon layer, and a silicon nitride layer stacked sequentially. The thickness of the silicon nitride layer is 1~10 Å.

[0016] Through the above technical solution, the method disclosed herein sequentially implants boron and nitrogen into a polycrystalline silicon layer. During the annealing process, the nitrogen-containing ion implantation material can form a silicon nitride protective layer on the surface of the polycrystalline silicon layer. Then, the annealing process is performed to prevent hydrogen ions from entering the interior of the polycrystalline silicon, thereby reducing the degree of mismatch in the polycrystalline silicon resistance.

[0017] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0018] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the structure of a polycrystalline silicon resistor according to one embodiment of the present disclosure. Detailed Implementation

[0019] The first aspect of this disclosure provides a method for preparing polycrystalline silicon resistors, the method comprising the following steps: S1. A polycrystalline silicon layer is formed on the substrate; S2. Perform a first ion implantation on the polycrystalline silicon layer, wherein the implanted ion is boron, to obtain a first ion implanted polycrystalline silicon layer. S3. Perform a second ion implantation on the polycrystalline silicon layer implanted by the first ion implantation, wherein the implanted ion is nitrogen; S4. Anneal the polycrystalline silicon layer that has undergone the first ion implantation and the second ion implantation.

[0020] During the fabrication of polycrystalline silicon resistors, processes such as hydride decomposition, ionization, and dissociation in a plasma environment generate hydrogen ions. During the annealing step, these hydrogen ions easily penetrate the interior of the polycrystalline silicon, significantly affecting the resistance value of the polycrystalline silicon resistor and leading to mismatch. To reduce the degree of mismatch in polycrystalline silicon resistors, this disclosure further implants nitrogen-containing ion implantation material after boron implantation. During the annealing process, N atoms can break the Si-O bonds on the surface of the polycrystalline silicon layer and combine with silicon atoms to form Si-N bonds, passivating the surface of the polycrystalline silicon layer to form silicon nitride, preventing hydrogen ions from entering the polycrystalline silicon, thereby reducing the mismatch in polycrystalline silicon resistors.

[0021] According to one embodiment of this disclosure, the substrate includes one or more of silicon substrate, silicon oxide, and silicon oxynitride, and the thickness of the substrate is conventional in the art.

[0022] According to one embodiment of the present disclosure, in step S1, the method for forming a polycrystalline silicon layer on the substrate includes one or more of chemical vapor deposition, physical vapor deposition, and thermal growth.

[0023] According to a specific embodiment of this disclosure, a polycrystalline silicon layer is formed on a substrate by chemical vapor deposition. The conditions for chemical vapor deposition include a pressure of 10,000 to 13,000 Pa and a temperature of 500 to 700 °C. The silicon-containing raw material may include SiH4.

[0024] According to one embodiment of this disclosure, the thickness of the polycrystalline silicon layer is 800~1000 Å, and the thickness can be controlled by the deposition time according to production needs.

[0025] To avoid lattice structure damage and ensure stable and uniform resistivity of the prepared polycrystalline silicon resistor, according to one embodiment of this disclosure, in step S2, the ion implantation material is boron difluoride, and the conditions for the first ion implantation include: an implantation dose of (3~7) × 10⁻⁶. 15 pcs / cm 2 including but not limited to 3×10 15 pcs / cm 24×10 15 pcs / cm 2 5×10 15 pcs / cm 2 6×10 15 pcs / cm 2 7×10 15 pcs / cm 2 The injection energy is 2~7 keV, including but not limited to 2 keV, 2.5 keV, 3 keV, 3.7 keV, 4 keV, 5 keV, 6 keV, 6.2 keV, and 7 keV.

[0026] According to one embodiment of this disclosure, the first ion implantation includes implanting boron difluoride onto the surface of a polycrystalline silicon layer, wherein the boron can further diffuse into the interior of the polycrystalline silicon layer during subsequent processing.

[0027] To ensure that the nitrogen-containing ion implantation material has a suitable implantation depth, promotes its conversion into silicon nitride, and prevents hydrogen ions from entering the polycrystalline silicon, according to one embodiment of this disclosure, in step S3, the ion implantation material includes N2, and the conditions for the second ion implantation include: an implantation dose of (3~6) × 10⁻⁶. 15 pcs / cm 2 The preferred value is (4~5)×10 15 pcs / cm 2 including but not limited to 3×10 15 pcs / cm 2 4×10 15 pcs / cm 2 5×10 15 pcs / cm 2 6×10 15 pcs / cm 2 The injection energy is 5~10 keV, preferably 6~7 keV, including but not limited to 5 keV, 6 keV, 6.2 keV, 7 keV, 8 keV, 9 keV, and 10 keV.

[0028] In order to make the prepared polycrystalline silicon resistor have a suitable resistance value, according to one embodiment of the present disclosure, in step S4, the annealing conditions include: time of 10~50s; temperature of 1000~1100℃, preferably 1030~1060℃; and the atmosphere used for the annealing includes one or more of N2, H2 and O2.

[0029] According to one embodiment of this disclosure, the method further includes: S5. An isolation layer is formed on the polysilicon layer after annealing. The isolation layer comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride; Methods for forming the isolation layer include chemical vapor deposition and / or physical vapor deposition.

[0030] According to one embodiment of this disclosure, the method is used for a 40nm process or a 55nm process.

[0031] According to a specific embodiment of this disclosure, a method for preparing a polycrystalline silicon resistor may include the following steps: S1. Form a polycrystalline silicon layer with a thickness of 800~1000Å on the substrate; The substrate includes one or more of silicon substrates, silicon oxide, and silicon oxynitride; Methods for forming a polycrystalline silicon layer on a substrate include one or more of chemical vapor deposition, physical vapor deposition, and thermal growth. S2. Perform a first ion implantation on the polycrystalline silicon layer, with boron as the implanted ion, to obtain a polycrystalline silicon layer with the first ion implantation. The ion implantation material is boron difluoride, and the conditions for the first ion implantation include: an implantation dose of (3~7)×10⁻⁶. 15 pcs / cm 2 The injected energy is 2~7 keV; S3. Perform a second ion implantation on the polycrystalline silicon layer implanted with the first ion, using nitrogen as the implanted ion; The ion implantation material includes N2, and the conditions for the second ion implantation include: an implantation dose of (4~5) × 10⁻⁶. 15 pcs / cm 2 The injected energy is 6~7 keV; S4. Anneal the polysilicon layer that has undergone the first and second ion implantation. The annealing conditions include: a time of 10~50s and a temperature of 1030~1060℃; the atmosphere used for annealing includes one or more of N2, H2 and O2. S5. An isolation layer is formed on the polysilicon layer after annealing. The isolation layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride; Methods for forming an isolation layer include chemical vapor deposition and / or physical vapor deposition.

[0032] By adopting the above specific implementation method, hydrogen ions can be prevented from entering the interior of polycrystalline silicon, thereby reducing the degree of mismatch in polycrystalline silicon resistance.

[0033] The second aspect of this disclosure provides a polycrystalline silicon resistor prepared using the method described in the first aspect of this disclosure.

[0034] According to one embodiment of this disclosure, the polycrystalline silicon resistor includes a substrate layer, a polycrystalline silicon layer, and a silicon nitride layer stacked sequentially; the thickness of the silicon nitride layer is 1~10 Å.

[0035] According to one embodiment of this disclosure, such as Figure 1 As shown, the polycrystalline silicon resistor further includes an isolation layer disposed on the side of the silicon nitride layer away from the polycrystalline silicon layer.

[0036] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0037] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0038] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A method for preparing polycrystalline silicon resistors, characterized in that, The method includes the following steps: S1. A polycrystalline silicon layer is formed on the substrate; S2. Perform a first ion implantation on the polycrystalline silicon layer, wherein the implanted ion is boron, to obtain a first ion implanted polycrystalline silicon layer; S3. Perform a second ion implantation on the polycrystalline silicon layer implanted by the first ion implantation, wherein the implanted ion is nitrogen; S4. Anneal the polycrystalline silicon layer that has undergone the first ion implantation and the second ion implantation.

2. The method according to claim 1, wherein, The substrate includes one or more of silicon substrate, silicon oxide, and silicon oxynitride.

3. The method according to claim 1, wherein, In step S1, the method for forming a polycrystalline silicon layer on the substrate includes one or more of chemical vapor deposition, physical vapor deposition, and thermal growth.

4. The method according to claim 1, wherein, The thickness of the polycrystalline silicon layer is 800~1000 Å.

5. The method according to claim 1, wherein, In step S2, the ion implantation material is boron difluoride, and the conditions for the first ion implantation include: an implantation dose of (3~7)×10⁻⁶. 15 pcs / cm 2 The injected energy is 2~7 keV.

6. The method according to claim 1, wherein, In step S3, the ion implantation material includes N2, and the conditions for the second ion implantation include: an implantation dose of (3~6) × 10⁻⁶. 15 pcs / cm 2 The injected energy is 5~10 keV.

7. The method according to claim 1, wherein, In step S4, the annealing conditions include: a time of 10-50 seconds and a temperature of 1000-1100°C. The atmosphere used for the annealing process includes one or more of N2, H2 and O2.

8. The method according to claim 1, wherein, The method further includes: S5. An isolation layer is formed on the polysilicon layer after annealing. The isolation layer comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride; Methods for forming the isolation layer include chemical vapor deposition and / or physical vapor deposition.

9. The method according to any one of claims 1 to 8, wherein, This method can be used for 40nm or 55nm processes.

10. A polycrystalline silicon resistor prepared by the method according to any one of claims 1 to 9.

11. The polycrystalline silicon resistor according to claim 10, wherein, The polysilicon resistor comprises a substrate layer, a polysilicon layer, and a silicon nitride layer stacked sequentially. The thickness of the silicon nitride layer is 1~10 Å.

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