A transistor comprising a vertical structure, a manufacturing method and applications

Abstract

The present application relates to a kind of transistor comprising vertical structure, preparation method and application.Transistor comprising vertical structure, gate is vertical structure;The part of the gate, cover the first pattern formed by high hole concentration structure layer processing above;Another part, vertically to the device surface extends to potential barrier layer downwards.The present application, directly through the design of special gate electrode structure, without increasing more processing technology, compared with prior art processing technology, revolutionary proposes a new set of processing logic, changes the structure of gate electrode only needs to reserve processing space when designing transistor structure, without increasing more internal structure of device, also without introducing additional electrode or electrode auxiliary structure, and by simulation analysis can obtain unexpected technical effect, effectively solve the technical problems of transistor anti single particle effect field processing precision, high cost, low yield, it is conducive to large-scale popularization and application.

Description

Technical Field

[0001] This invention relates to components of semiconductors or other solid-state devices, and also to processes specifically applicable to the manufacture or handling of semiconductors or solid-state devices or their components. In particular, it relates to a transistor comprising a vertical structure, a method for its fabrication, and its application. Background Technology

[0002] Gallium nitride (GaN) transistors, also known as high electron mobility transistors (HEMTs), are third-generation wide-bandgap semiconductor devices based on gallium nitride (GaN) material. As a typical wide-bandgap semiconductor material, gallium nitride has been widely used in civilian fields such as automotive electronics, power electronics, and 5G communication base stations. Furthermore, its high switching frequency and high power density characteristics make it irreplaceable in high-end fields such as aerospace and satellite exploration, making it a key candidate material for core electronic devices in these fields. Among them, p-GaN (p-type gallium nitride) is a group III nitride semiconductor material doped with acceptor impurities (such as magnesium). Its main characteristic is hole conductivity, and it is widely used in power electronics and high-frequency devices. The doping concentration is a key parameter for the performance of gallium nitride-based semiconductor devices, usually achieved through Mg doping. The doping concentration directly affects the p-type contact quality and device efficiency.

[0003] However, aerospace and satellite exploration equipment needs to operate in the complex space environment for extended periods, which contains a large number of high-energy particles (such as protons, electrons, and heavy ions). These high-energy particles severely affect the reliability of gallium nitride (GaN) devices, greatly limiting their large-scale application in space. Research has confirmed that high-energy particle incident radiation can cause significant degradation in key electrical parameters of GaN devices, such as output characteristics, transfer characteristics, and transconductance. In more severe cases, it can directly damage the internal structure of the device. Among these factors, the single-event effect is the main cause of these problems and a core technological bottleneck restricting the space application of GaN devices.

[0004] Specifically, the mechanism of the single-event effect is as follows: when high-energy particles from space enter the gallium nitride device, they will generate a large number of electron-hole pairs. Under the influence of the electric field inside the device, these charge carriers will undergo collisional ionization, further generating more electron-hole pairs. These electron-hole pairs are collected by the device electrodes through recombination, diffusion, and drift, forming a transient large current. In severe cases, this can cause permanent damage between the drain and source electrodes, or even cause gate breakdown, leading to complete device failure.

[0005] CN116913959A discloses a single-particle P-resistant material with a Schottky island structure. GaN transistors and their fabrication methods are described. The transistor includes: a substrate layer, a nucleation layer, a buffer layer, a channel layer, and a barrier layer; a source electrode, a drain electrode, a nitride layer, and a passivation layer; at least one Schottky island located above the barrier layer; and a gate electrode located on the nitride layer. The source and drain electrodes form ohmic contacts with the barrier layer. The nitride layer is located between the source and drain electrodes, and the passivation layer is located between the source and the nitride layer, and between the nitride layer and the drain electrode. The Schottky island is located on one or both sides of the nitride layer, and forms a Schottky contact with the barrier layer. The bottom of the gate electrode forms an ohmic or Schottky contact with the nitride layer. This method solves the problem of conventional HEMT devices easily burning out at low operating voltages and improves the single-event burn-out voltage of P-type nitride gate HEMT devices. The burn-out voltage of the device is increased from 380V to 450V.

[0006] CN115548090A discloses an ion-implanted single-event p-GaN transistor and its fabrication method. The transistor, from bottom to top, comprises a substrate layer, a nucleation layer, a buffer layer, a channel layer, and a barrier layer. A source and a drain are respectively disposed at both ends of the upper surface of the barrier layer, with a p-GaN layer between the source and drain. A gate is disposed on the p-GaN layer. Passivation layers are disposed between the p-GaN layer and both the source and drain. Ion-implanted regions are located at the two edges of the upper end of the p-GaN layer, and the implanted ions are any one of fluoride ions, nitrogen ions, and argon ions. This invention can significantly alleviate the peak electric field at the edge and reduce the reverse leakage current at the edge, thereby increasing the breakdown voltage and enhancing the resistance to single-event effects. This avoids the risk of breakdown by high-energy particles in space and improves the service life and reliability of aerospace power systems. By employing ion implantation, the peak electric field at the edge of the p-GaN is significantly reduced from 4.3 MV / cm to 2.66 MV / cm.

[0007] To address these issues, scholars both domestically and internationally have observed a strong correlation between single-event effects (SEE) and the degradation of electrical properties in gallium nitride (GaN) devices. These SEE are closely related to factors such as the type and energy of the incident particles, the incident time, and the incident position. Although various techniques are being employed to reduce the impact of SEE on device electrical properties, research in this field remains relatively scarce.

[0008] In conclusion, developing more efficient and radiation-resistant gallium nitride (GaN) device structures is key to promoting the widespread application of GaN devices in aerospace and satellite exploration, and has significant research value and application prospects. Summary of the Invention

[0009] To address the aforementioned technical problems, this invention proposes a transistor comprising a vertical structure, a fabrication method, and an application. In the transistor comprising a vertical structure, the gate is a vertical structure.

[0010] A portion of the gate covers the first pattern formed by processing a high hole concentration structure layer; wherein the high hole concentration structure layer is a first high hole concentration structure layer covering the barrier layer and a second high hole concentration structure layer located above the first high hole concentration structure layer.

[0011] Another portion of the gate extends downward perpendicularly to the device surface to the barrier layer, and one side of the vertical surface of the gate covers the side of the first high hole concentration structure layer, the second high hole concentration structure layer and the vertical surface of the gate that are in contact, and the first high hole concentration structure layer, the second high hole concentration structure layer and the gate form a Schottky contact; wherein the doping concentration of the first high hole concentration structure layer is less than the doping concentration of the second high hole concentration structure layer.

[0012] The source electrode and drain electrode are located on the two sides of the upper surface of the barrier layer that are not covered by the high hole concentration structure.

[0013] Furthermore, the transistor also includes a channel layer covered by the barrier layer.

[0014] Furthermore, the transistor also includes a buffer layer covered by the channel layer.

[0015] Furthermore, the transistor also includes a substrate layer covered by the buffer layer.

[0016] Furthermore, the transistor further includes a passivation protection layer covering the barrier layer, wherein the passivation protection layer covers the area on the upper surface of the barrier layer that is not covered by the first pattern, the source electrode, the drain electrode, and the gate, and covers the end face of the barrier layer and part of the end face of the channel layer that is not covered by other layers and should not be exposed.

[0017] Furthermore, the source electrode and the drain electrode sequentially penetrate the passivation protection layer and the barrier layer until they contact the channel layer, and the source electrode and the drain electrode form an ohmic contact with the contacting barrier layer and the channel layer.

[0018] Furthermore, the substrate material is GaN, sapphire, Si, diamond, or SiC substrate material.

[0019] Furthermore, the buffer layer is made of one or more materials such as GaN, AlGaN, InGaN, and InAlN, with a thickness ranging from 50nm to 10μm.

[0020] Furthermore, the channel layer is made of GaN and has a thickness ranging from 5 nm to 1 μm.

[0021] Furthermore, the barrier layer is made of AlN, InN, AlGaN, InGaN, or InAlN, and its thickness ranges from 5nm to 1μm.

[0022] Furthermore, the first high hole concentration structure layer and the second high hole concentration structure layer are fabricated using p-GaN, wherein the thickness of the first high hole concentration structure layer or the second high hole concentration structure layer is 5-200 nm, and the doping concentration of the thickness of the first high hole concentration structure layer or the second high hole concentration structure layer is 10. 5 -10 22 / cm -3 And it satisfies that the doping concentration of the first high hole concentration structural layer is less than the doping concentration of the second high hole concentration structural layer.

[0023] Furthermore, the thickness of the passivation protective layer is 20 nm-1 μm.

[0024] Furthermore, the passivation protective layer is made of SiO2, Si3N4, AlN, Al2O3, MgO, Sc2O3, TiO2, HfO2, BCB, ZrO2, Ta2O5 or La2O3.

[0025] Furthermore, the source electrode, the drain electrode, and the gate are made of Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN, or any combination thereof; the combination includes combining and / or forming an alloy.

[0026] The present invention also provides a method for fabricating the aforementioned transistor comprising a vertical structure, comprising:

[0027] The high hole concentration structure layer is patterned according to the design scheme to form the first pattern, and then passivation is performed to fully cover the surface of the processed structure to form a passivation protective layer.

[0028] The vertical structure is fabricated by patterning the passivation protective layer according to the design scheme after the passivation protective layer is formed. After patterning, a first pattern is exposed, and a fourth pattern is exposed on the side surface of the high hole concentration structure layer near the drain electrode, and sequentially penetrates the passivation protective layer to expose the barrier layer.

[0029] A gate is fabricated on the exposed first and fourth patterns, and a Schottky contact is formed between the gate and the high hole concentration structure layer and the barrier layer covered by the gate.

[0030] Furthermore, the method also includes:

[0031] According to the design scheme, the passivation protective layer is patterned to form a second pattern and a third pattern that sequentially penetrate the passivation protective layer and the barrier layer and expose the channel layer;

[0032] Source electrodes and drain electrodes are fabricated in the second and third patterns, respectively, and ohmic contacts are formed between the source electrodes, the drain electrodes, the barrier layer, and the channel layer by high-temperature alloy annealing.

[0033] Furthermore, the preparation method further includes:

[0034] A buffer layer, a channel layer, a barrier layer, and a high hole concentration structure layer are sequentially grown on a substrate layer; wherein the high hole concentration structure layer includes a first high hole concentration structure layer covering the barrier layer and a second high hole concentration structure layer located on the first high hole concentration structure layer, wherein the doping concentration of the first high hole concentration structure layer is less than the doping concentration of the second high hole concentration structure layer.

[0035] The present invention further provides the aforementioned uses of transistors with vertical structures, such as satellite power supplies containing transistors with vertical structures, and satellites containing satellite power supplies.

[0036] The beneficial effects of this invention are as follows:

[0037] This invention addresses the issue of electric field at the gate edge by designing a vertical gate structure. The gate extends through a portion above a high-hole-concentration structural layer and another portion into a barrier layer. Using this structure, the electric field strength near the gate is reduced from 5.3 MV / cm to 2.5 MV / cm, a reduction of 52.83%, significantly better than the reduction achieved by other existing solutions.

[0038] In existing technologies, to address the single-event effect (SEE) problem in transistors, domestic and international scholars have conducted research on SEE in gallium nitride (GaN) devices using simulation software and ground-based simulation test facilities in space environments. It has been clearly established that the degree of degradation of the device's electrical characteristics is closely related to factors such as the type, energy, and incident position of the incident particles. Based on this, related research has proposed two types of radiation hardening strategies: first, by introducing additional electrodes to achieve timely collection of electron-hole pairs and suppress the generation of instantaneous large currents; second, by optimizing the internal structure of the device to change the transmission path of leakage current and reduce the impact of SEE on device characteristics. These approaches all introduce new processing difficulties into the transistor fabrication process, increasing costs and reducing yield. Furthermore, the added structure can easily lead to shorter transistor lifespan and poor stability.

[0039] This invention, by directly designing a special gate electrode structure, eliminates the need for additional processing steps or auxiliary structures. Compared to existing technologies, it presents a revolutionary new processing logic. Changing the gate electrode structure only requires reserving processing space when designing the transistor structure, without adding more internal device structures or introducing additional electrodes or electrode auxiliary structures. Furthermore, simulation analysis confirms that it can achieve unexpected technical effects, effectively solving the technical problems of high processing precision, high cost, and low yield in the field of transistor anti-single-event effect, which is conducive to large-scale promotion and application. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of a transistor structure including a vertical structure provided in Embodiment 1 of the present invention;

[0041] Figures 2-8 This is a schematic diagram of the fabrication process of a transistor with a vertical structure provided in Embodiment 2 of the present invention;

[0042] Figure 9 This is a diagram showing the electric field distribution of a transistor structure including a vertical structure using the present invention.

[0043] Figure 10 The above is a comparison diagram of simulation test results for a transistor structure incorporating a vertical structure according to the present invention.

[0044] The attached figures are labeled as follows:

[0045] 100 - Substrate layer, 200 - Buffer layer, 300 - Channel layer, 400 - Barrier layer, 501 - First high hole concentration structure layer, 502 - Second high hole concentration structure layer, 503 - First pattern, 600 - Passivation protection layer, 601 - Second pattern, 602 - Third pattern, 603 - Fourth pattern, 611 - Source electrode, 612 - Drain electrode, 613 - Gate, 401 - Mesa pattern. Detailed Implementation

[0046] Figure 1 This is a schematic diagram of a transistor with a vertical structure according to the present invention, wherein the gate 613 has a vertical structure;

[0047] A portion of the gate 613 covers the first pattern 503 formed by processing a high hole concentration structure layer; wherein the high hole concentration structure layer is a first high hole concentration structure layer 501 covering the barrier layer 400 and a second high hole concentration structure layer 502 located on the first high hole concentration structure layer 501.

[0048] Another portion of the gate 613 extends downward perpendicularly to the device surface to the barrier layer 400, and one side of the vertical surface of the gate 613 covers the side of the first high hole concentration structure layer 501, the second high hole concentration structure layer 502 that are in contact with the vertical surface of the gate, and the first high hole concentration structure layer 501, the second high hole concentration structure layer 502 and the gate 613 form a Schottky contact; wherein the doping concentration of the first high hole concentration structure layer 501 is less than the doping concentration of the second high hole concentration structure layer 502;

[0049] The source electrode 611 and the drain electrode 612 are located on the two sides of the upper surface of the barrier layer 400 that are not covered by the high hole concentration structure layer.

[0050] Figure 2-8 This is a schematic diagram of the process flow for manufacturing the transistor containing the vertical structure described in this invention, as shown below. Figure 2 As shown, a buffer layer 200 is grown on a substrate layer 100; wherein, the material of the substrate layer 100 can be GaN, sapphire, Si, diamond or SiC substrate material; the thickness ranges from 50nm to 10μm, preferably, the thickness is 50nm, 60nm, ..., 9μm, 10μm.

[0051] A channel layer 300 is grown on the buffer layer 200. The material of the channel layer 300 is GaN, and the thickness ranges from 5nm to 1μm. Preferably, the thickness is 5nm, 6nm, ..., 1μm.

[0052] A barrier layer 400 is grown on the channel layer 300. The material of the barrier layer can be AlN, InN, AlGaN, InGaN or InAlN, and the thickness ranges from 5nm to 1μm. Preferably, the thickness can be the endpoint values ​​of 5nm, 6nm, ..., 1μm.

[0053] A high hole concentration structure layer is grown on the barrier layer 400. First, a first high hole concentration structure layer 501 is grown, followed by a second high hole concentration structure layer 502. Both high hole concentration structure layers are made of p-GaN. The thickness of the first high hole concentration structure layer 501 or the second high hole concentration structure layer 502 is 5-200 nm, and the doping concentration of the first high hole concentration structure layer 501 or the second high hole concentration structure layer 502 is 10⁻⁶. 5 -10 22 / cm -3 And the doping concentration of the first high hole concentration structural layer 501 is less than the doping concentration of the second high hole concentration structural layer 502.

[0054] After the aforementioned processing is completed, the matrix structure to be processed is obtained.

[0055] like Figure 3 As shown, Figure 2 The obtained substrate structure is processed according to the design scheme. The exposed cross-section of the upper part of the buffer layer 200, the channel layer 300, the barrier layer 400, the first high hole concentration structure layer 501, and the second high hole concentration structure layer 502 after processing is a mesa pattern 401. The mesa pattern 401 is used to isolate the transistor from other GaN high electron mobility transistors during use. The processing method for this step can be ion implantation, photolithography, and / or plasma dry etching. After processing, it can be seen from the vertical cross-section that the thickness of the mesa pattern 401 is greater than or equal to the sum of the thicknesses of the four layers: the channel layer 300, the barrier layer 400, the first high hole concentration structure layer 501, and the second high hole concentration structure layer 502.

[0056] like Figure 4 As shown, according to the design scheme, the above-processed structure is further patterned. The first high hole concentration structure layer 501 and the second high hole concentration structure layer 502, after processing, collectively constitute the first pattern 503. The barrier layer 400 is exposed in the remaining portions not covered by the first pattern. The patterning process employs photolithography, plasma dry etching, and / or wet etching techniques. The thickness of the first pattern 503 is equal to the sum of the thicknesses of the first high hole concentration structure layer 501 and the second high hole concentration structure layer 502.

[0057] like Figure 5As described above, according to the design scheme, a passivation protective layer 600 is formed on the platform pattern 401, the first pattern 503, and the exposed barrier layer 400. Common deposition processes are employed, such as sputtering or chemical vapor deposition. The thickness of the passivation protective layer 600 is 20 nm to 1 μm; the material used can be SiO2, Si3N4, AlN, Al2O3, MgO, Sc2O3, TiO2, HfO2, BCB, ZrO2, Ta2O5, or La2O3.

[0058] like Figure 6 As shown, according to the design scheme, the structure covered with the passivation protective layer 600 is further patterned. At a certain distance on both sides of the first pattern 503, the passivation protective layer 600 and the barrier layer 400 are removed until the channel layer 300 is exposed, resulting in two recessed regions: the second pattern 601 and the third pattern 602. At the first pattern 503, the passivation protective layer 600 covering the first pattern 503 is removed, as is the passivation protective layer 600 on the side of the first pattern 503 closest to the third pattern 602. This patterning process exposes the side surface of the first pattern 503 on the side closest to the third pattern 602, and sequentially penetrates the passivation protective layer 600 to expose the barrier layer 400, resulting in the fourth pattern 603. The processing utilizes photolithography, plasma dry etching, or wet etching techniques.

[0059] like Figure 7 As shown, a source electrode 611 is fabricated in the second pattern 601, and a drain electrode 612 is fabricated in the third pattern 602. A high-temperature alloy annealing process is used to form ohmic contacts between the source electrode 611 and the drain electrode 612 and the channel layer 300. The source electrode 611 and the drain electrode 612 are fabricated using photolithography, electron beam evaporation, or sputtering techniques.

[0060] like Figure 8 As shown, a gate 613 is processed in the fourth pattern 603, and a portion of the gate 613 covers the first pattern 503 formed by processing a high hole concentration structure layer; wherein, the high hole concentration structure layer is a first high hole concentration structure layer 501 covering the barrier layer and a second high hole concentration structure layer 502 located on the first high hole concentration structure layer 501.

[0061] Another portion of the gate 613 extends downward perpendicularly to the device surface to the barrier layer 400, and one side of the vertical surface of the gate 613 covers the side of the first high hole concentration structure layer 501, the second high hole concentration structure layer 502 that are in contact with the vertical surface of the gate 613. The first high hole concentration structure layer 501, the second high hole concentration structure layer 502 and the gate 613 form a Schottky contact; the gate 613 and the barrier layer 400 form a Schottky contact.

[0062] The source electrode 611, the drain electrode 612 and the gate electrode 613 can be made of Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN or any combination thereof; the combination includes combining and / or forming an alloy.

[0063] Figure 9 This is a comparison of simulation test results for the transistor with the vertical structure of this invention. The X-axis represents the sensitive region located at the gate. The red curve in the figure represents the transistor without the vertical structure of this invention, whose maximum gate electric field strength is 5.3 MV / cm. The black curve represents the transistor with the vertical structure of this invention, whose maximum gate electric field strength is 2.5 MV / cm. It can be seen that the vertical structure of this invention, through the design of a special gate electrode, extends the gate metal structure vertically, with one part covering the high hole concentration structure layer and the other part extending vertically downwards to the barrier layer 400. This design can effectively alleviate the electric field at the gate edge. As shown in the figure, the transistor with the vertical structure of this invention can reduce the electric field strength from 5.3 MV / cm to 2.5 MV / cm, a reduction of 52.83%.

[0064] like Figure 10 As shown, black, red, and blue represent the drain voltages in the simulation test, with black representing 400V, red 450V, and blue 500V. The figure shows that when the simulation test voltages are 400V and 450V, there is no sudden increase in the electric field strength, indicating that the vertical structure of this invention does not pose a risk of burnout at 400V and 450V. When the test voltage continues to rise to 500V, a significant and sudden increase in the electric field strength occurs at the gate, proving that the device gate is broken down at this voltage level, resulting in device failure. Therefore, the structure of this invention can withstand a breakdown voltage of 500V, demonstrating high reliability, good repeatability, and greater suitability for applications in space environments.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A transistor comprising a vertical structure, characterized in that, The transistor comprising a vertical structure, wherein the gate (613) is a vertical structure; A portion of the gate (613) covers the first pattern (503) formed by processing a high hole concentration structure layer; wherein the high hole concentration structure layer is a first high hole concentration structure layer (501) covering the barrier layer (400) and a second high hole concentration structure layer (502) located on the first high hole concentration structure layer (501). Another portion of the gate (613) extends downward perpendicularly from the device surface to the barrier layer (400), and one side of the vertical surface of the gate (613) covers the side of the first high hole concentration structure layer (501), the second high hole concentration structure layer (502) in contact with the vertical surface of the gate, and the first high hole concentration structure layer (501), the second high hole concentration structure layer (502) and the gate (613) form a Schottky contact; wherein the doping concentration of the first high hole concentration structure layer (501) is less than the doping concentration of the second high hole concentration structure layer (502); The transistor further includes a channel layer (300) covered by the barrier layer (400), a buffer layer (200) covered by the channel layer (300), and a substrate layer (100) covered by the buffer layer (200); it also includes a passivation protection layer (600) covering the barrier layer (400), wherein the passivation protection layer (600) covers the area on the upper surface of the barrier layer (400) that is not covered by the first pattern (503), the source electrode (611), the drain electrode (612), and the gate (613), and covers the end face of the barrier layer (400) and a portion of the end face of the channel layer (300) that is not covered by other layers and should not be exposed; The source electrode (611) and the drain electrode (612) are located on the two sides of the upper surface of the barrier layer (400) that are not covered by the high hole concentration structure layer, respectively; the source electrode (611) and the drain electrode (612) pass through the passivation protection layer (600) and the barrier layer (400) in sequence until they contact the channel layer (300), and the source electrode (611) and the drain electrode (612) form an ohmic contact with the barrier layer (400) and the channel layer (300) that are in contact with each other; The vertical surface of the gate (613) faces the drain electrode (612).

2. The transistor comprising a vertical structure according to claim 1, characterized in that, The substrate material is GaN, sapphire, Si, diamond, or SiC.

3. The transistor comprising a vertical structure according to claim 1, characterized in that, The buffer layer is made of one or more materials such as GaN, AlGaN, InGaN, and InAlN, with a thickness ranging from 50nm to 10μm.

4. The transistor comprising a vertical structure according to claim 1, characterized in that, The channel layer is made of GaN and has a thickness ranging from 5 nm to 1 μm.

5. The transistor comprising a vertical structure according to claim 1, characterized in that, The barrier layer is made of AlN, InN, AlGaN, InGaN, or InAlN, and its thickness ranges from 5nm to 1μm.

6. The transistor comprising a vertical structure according to claim 1, characterized in that, The first and second high hole concentration structural layers are fabricated using p-GaN. The thickness of either the first or second high hole concentration structural layer is 5-200 nm, and the doping concentration of either layer is 10⁻⁶. 5 -10 22 / cm -3 And it satisfies that the doping concentration of the first high hole concentration structural layer is less than the doping concentration of the second high hole concentration structural layer.

7. The transistor comprising a vertical structure according to claim 1, characterized in that, The thickness of the passivation protective layer is 20 nm-1 μm.

8. The transistor comprising a vertical structure according to claim 1, characterized in that, The passivation protective layer is made of SiO2, Si3N4, AlN, Al2O3, MgO, Sc2O3, TiO2, HfO2, BCB, ZrO2, Ta2O5 or La2O3.

9. The transistor comprising a vertical structure according to claim 1, characterized in that, The source electrode, the drain electrode, and the gate are made of Ti, Al, Ni, Mo, Pt, Pd, Au, W, TiW, TiN, or any combination thereof; the combination includes combining and / or forming an alloy.

10. A method for fabricating a transistor comprising a vertical structure according to any one of claims 1-9, characterized in that, The method includes: The high hole concentration structure layer is processed into a pattern according to the design scheme to form the first pattern (503), and passivation is performed to fully cover the surface of the processed structure to form a passivation protective layer (600). The vertical structure is fabricated by patterning the passivation protection layer (600) according to the design scheme after the passivation protection layer (600) is formed. After patterning, the first pattern (503) is exposed, and the fourth pattern (603) is exposed on the side surface of the high hole concentration structure layer near the drain electrode (612) and penetrates the passivation protection layer (600) to expose the barrier layer (400). A gate (613) is fabricated on the exposed first pattern (503) and fourth pattern (603), and a Schottky contact is formed between the gate (613) and the high hole concentration structure layer and the barrier layer (400) covered by the gate (613). The preparation method further includes: According to the design scheme, the passivation protection layer (600) is patterned to form a second pattern (601) and a third pattern (602) that sequentially penetrate the passivation protection layer (600), the barrier layer (400) and expose the channel layer (300); wherein, the fourth pattern (603) faces closer to the third pattern (602). In the second pattern (601) and the third pattern (602), the source electrode (611) and the drain electrode (612) are prepared by deposition, respectively, and high-temperature alloy annealing is performed after deposition so that the source electrode (611) and the drain electrode (612) form ohmic contacts with the barrier layer (400) and the channel layer (300).

11. A satellite power supply, characterized in that, Includes the transistor with a vertical structure as described in any one of claims 1-9.

12. A satellite, characterized in that, Includes the satellite power supply as described in claim 11.

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