Stacked semiconductor die architecture with dies orthogonal to base die or substrate stack

Abstract

The invention discloses a microelectronic assembly having a stack of dies disposed such that a face of each die in the stack is orthogonal to a face of a substrate. Each die has a first face and a second face opposite the first face. The die stack includes a plurality of dies, wherein a face of each die is parallel to faces of other dies in the die stack. The die stack is disposed on the substrate such that a face of each die is substantially orthogonal to a face of the substrate. Each die in the die stack may have a corresponding conductive contact, and the conductive contact on each die in the die stack may be coupled to the conductive contact on the substrate via an interconnect. The interconnect may be a solder joint, such as a solder bump or a solder ball.

Description

Background Technology

[0001] Electronic circuits typically fabricated on wafers of semiconductor materials such as silicon are called integrated circuits (ICs). Wafers containing such ICs are usually diced into many individual dies. These dies can be packaged into an IC package that includes one or more dies and other electronic components. IC dies are conventionally coupled to a package substrate for mechanical stability and to facilitate connection to other components, such as circuit boards. Attached Figure Description

[0002] The embodiments will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. For ease of description, the same reference numerals denote the same structural elements. In the accompanying figures, embodiments are shown by way of example rather than limitation.

[0003] Figures 1A to 1B This is a flowchart of a method for manufacturing a stacked semiconductor die architecture having dies orthogonally stacked with a base die or substrate, according to some embodiments.

[0004] Figures 2A to 2N Cross-sectional views are provided at various stages in the fabrication of an example stacked semiconductor die architecture having dies orthogonally stacked with a substrate die or substrate, according to some embodiments.

[0005] Figures 3A to 3C Cross-sectional views are provided at various stages in the fabrication of an example stacked semiconductor die architecture having dies orthogonally stacked with a substrate die or substrate, according to some embodiments.

[0006] Figures 4A to 4B An isometric view of a die stack coupled to a substrate die or substrate according to some embodiments is provided, wherein the die is orthogonal to the substrate die or substrate stack.

[0007] Figures 5A to 5B A schematic cross-sectional view of an example die stack coupled to a substrate die or substrate according to some embodiments is provided.

[0008] Figures 6A to 6B Schematic cross-sectional views are provided for other examples of die stacks coupled to a substrate die or substrate according to some embodiments.

[0009] Figures 7A to 7B A schematic cross-sectional view is provided as an example of a conductive contact between a die and a base die or substrate in a die stack according to some embodiments.

[0010] Figure 8 This is a top view of wafers and dies that may be included in a microelectronic assembly having a die stack according to any embodiment of this disclosure.

[0011] Figure 9 This is a side cross-sectional view of an IC device that may be included in a microelectronic assembly having a die stack according to any embodiment of the present disclosure.

[0012] Figure 10 This is a side cross-sectional view of an IC device assembly that may include a die stack according to any embodiment of the present disclosure, based on some embodiments of the present disclosure.

[0013] Figure 11 This is a block diagram of an example communication device that may include a microelectronic assembly having a die stack according to any embodiment of the present disclosure, based on some embodiments of the present disclosure. Detailed Implementation

[0014] This document discloses microelectronic components and related apparatus and methods. For example, in some embodiments, the microelectronic component may include a substrate and a die stack. The substrate may be a base die or a substrate, and the substrate has a top surface. The die stack includes: a first die having a first surface; a first conductive contact on the first surface of the first die; a second die having a first surface and a second surface opposite to the first surface; a second conductive contact on the first surface of the second die; and a spacer layer between the first surface of the first die and the second surface of the second die, wherein the first surface of the first die is parallel to the second surface of the second die. The first surface of the first die and the second surface of the second die are substantially orthogonal to the top surface of the substrate. The die stack is coupled to the top surface of the base die, and the component includes a first base die conductive contact coupled to the first conductive contact and a second base die conductive contact coupled to the second conductive contact.

[0015] To illustrate the IC package described herein, it is important to understand the phenomena that may occur during the assembly and packaging of the IC. The following basic information can be considered as the basis for properly interpreting the contents of this disclosure. Such information is provided for illustrative purposes only and should not be construed in any way as limiting the broad scope of this disclosure and its potential applications.

[0016] A trend in the computer industry is to improve device performance and increase memory size while reducing power consumption and footprint. IC packaging can include stacked IC dies to improve performance and save space. A die stack in an IC package refers to multiple dies that are stacked and interconnected to serve as a single unit. For example, current solutions for increasing memory size include increasing the size of memory dies and increasing the number of memory dies in a die stack. Note that the dies in a die stack can be any type of die, including, for example, memory dies, logic dies, analog dies, power management dies, interface dies, mixed-signal dies, and sensor dies. Typically, each die in a die stack is parallel to a base die, and the dies are interconnected using conductive interconnects (e.g., conductive traces and conductive vias) extending through the dies. The base die is used for power delivery to and from the dies in the die stack. Stacked dies save space, allowing for more compact IC designs. Furthermore, stacking dies reduces the distance between interconnect components, resulting in faster data transfer rates and lower power consumption. However, as the stack becomes taller, delivering power to the topmost die within the stack can become difficult. Additionally, removing heat from the stack can become problematic as the stack increases in height. Therefore, die stack size is limited by power and heat dissipation constraints.

[0017] In a general sense, any typical IC die includes a substrate, active regions within the substrate containing transistors and other active circuitry, and a metallization stack above the substrate that shares contact areas with the active regions. The metallization stack is the region of the IC die in which the various devices in the active regions (e.g., transistors, capacitors, resistors, etc.) are interconnected via conductive traces and conductive vias.

[0018] Conventionally, IC dies can be stacked within a package such that the dies are parallel to each other, with active circuitry positioned in a plane parallel to the contact areas of adjacent dies. This architecture is subject to certain inherent limitations. For example, computing IC dies that include high-performance computing circuitry that generates significant heat must be placed on top of any such stack to ensure proper heat dissipation. Typically, as mentioned above, the size of the die stack is limited by power and thermal constraints. This placement limits the number of high-power computing IC dies that can be placed in a package with a limited (or constrained) footprint.

[0019] Embodiments of the present invention aim to improve die stacking constraints by arranging die stacks such that the dies in the stack are laterally stacked above the surface of the substrate (e.g., arranged such that the die faces of the dies in the stack are in a plane perpendicular to the substrate rather than parallel to the substrate). That is, in a "sliced ​​bread" configuration, the die stack is orthogonal to the substrate. When the dies in the die stack are laterally (e.g., orthogonal or perpendicular) to the substrate, each die can be directly connected to the substrate without wiring connections from or through other dies in the die stack. Therefore, compared to other arrangements where the die stack is parallel to the substrate and wiring connections are made through or along the entire die stack to reach the top die, when the dies in the die stack are orthogonal to the substrate, each substrate-to-die connection is direct and there is no top die. When the dies in the die stack are perpendicular to the substrate, the substrate can deliver power individually to each die in the die stack. Similarly, input / output communication can occur directly between each die and the substrate in a die stack. The substrate can be a base die or a substrate (e.g., a packaging substrate).

[0020] Therefore, embodiments of the microelectronic components discussed herein include arranging a die stack such that the face of each die in the stack is orthogonal to the face of a substrate (e.g., a base die or substrate), and each die in the die stack can be directly coupled to the substrate. Specifically, each die includes a thin silicon layer and has a first face, a second face opposite the first face, and an edge extending between the first and second faces. The die stack includes a plurality of dies, wherein the face of each die is parallel to the faces of the other dies in the die stack. The die stack is disposed on the substrate such that the face of each die is substantially orthogonal to the face of the substrate, and the bottom edge of each die is substantially parallel to the face of the substrate. Each die in the die stack may have a corresponding conductive contact, and the conductive contact on each die in the die stack may be coupled to a conductive contact on the substrate via an interconnect. The interconnect may be a solder joint, such as a solder bump or solder ball. The number of dies in the die stack may be modular and may be adjusted depending on the application. In some examples, multiple die stacks can be coupled to a substrate, with space between each die stack to allow for efficient thermal removal.

[0021] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein illustrative embodiments that can be practiced are shown. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0022] The description uses the phrases "in embodiments" or "in multiple embodiments," each of which can refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., as used with respect to embodiments of this disclosure are synonymous. As used herein, "package" and "IC package" are synonymous, as are "die" and "IC die." The terms "top" and "bottom" may be used herein to interpret various features of the accompanying drawings; however, these terms are merely for ease of discussion and do not imply a desired or required orientation. As used herein, the term "insulating" means "electrically insulating" unless otherwise stated.

[0023] Although some elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, "dielectric material" may include one or more dielectric materials, or "insulating material" may include one or more insulating materials. The terms "oxide," "carbide," "nitride," etc., refer to compounds containing oxygen, carbon, nitrogen, etc., respectively. The term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide. Unless otherwise stated, the term "insulating" and its variations (e.g., "insulating" or "insulator") mean "electrically insulating," and the term "conductive" and its variations (e.g., "conductive" or "conductor") mean "electrically conducting." Regarding optical signals and / or devices, components, and elements that operate on or use optical signals, the term "conduction" may also mean "optical conduction." When two materials or layers are described as "contacting," this may mean that the two materials or layers may be in physical contact with an interface layer formed due to said contact, such as direct physical contact. The term "insulating material" refers to a solid material that is substantially non-conductive (and / or a liquid material that solidifies after the treatments described herein). By way of example and not limitation, they may include organic polymers and plastics, as well as inorganic materials such as ionic crystals, ceramics, glasses, silicon, and alumina, or combinations thereof. They may include dielectric materials, highly polarizable materials, and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of this disclosure. Other examples of insulating materials are underfills and mold or mold-like materials used in encapsulation applications, including materials used, for example, in organic interlayers, encapsulation supports, and other such components.

[0024] In some embodiments, the IC die disclosed herein may include a substantially single-crystal semiconductor, such as silicon or germanium, as a substrate material (e.g., a substrate, a body), on which integrated circuits are fabricated using conventional semiconductor processing methods. The semiconductor substrate material may include, for example, N-type or P-type materials. The die may include, for example, a crystalline substrate material formed using a bulk silicon (or other bulk semiconductor material) or a semiconductor-on-insulator (SOI, e.g., silicon-on-insulator) structure. In some other embodiments, the substrate material of one or more of the IC dies may include alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-N, III-V, II-VI, or IV group materials. In other embodiments, the substrate material may include a compound semiconductor, for example, having a first sublattice of at least one element from group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from group V of the periodic table (e.g., P, As, Sb). In other embodiments, the substrate material may include an intrinsic IV or III-V semiconductor material or alloy that is not intentionally doped with any electroactive impurities; in alternative embodiments, a nominal level of impurity dopant may be present. In other embodiments, the die may include an amorphous material, such as a polymer; for example, the substrate material may include a silicon dioxide-filled epoxy resin. In other embodiments, the substrate material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Generally, substrate materials may include one or more of the following: tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium. Although several examples of materials for dies are described herein, any material or structure that can be used as a basis (e.g., substrate material) on which IC circuits and structures as described herein can be built falls within the spirit and scope of this disclosure.

[0025] In various embodiments, components associated with the IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, components associated with the IC may include components monolithically integrated within the IC, mounted on the IC, or connected to the IC. The IC described herein can be analog or digital and can be used in many applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC described herein may be employed in a single IC die or as part of a chipset for performing one or more related functions in a computer.

[0026] In a general sense, "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components, facilitating communication of electrical signals between them; an optical interconnect provides an optical connection between two optical components, facilitating communication of optical signals between them. As used herein, both electrical interconnects and optical interconnects are included in the term "interconnect." The nature of the described interconnects will be understood with reference to the signal medium associated with them. Thus, when used with reference to electronic devices (such as ICs that operate using electrical signals), the term "interconnect" describes any element formed of a conductive material used to provide electrical connections to one or more elements associated with the IC and / or electrical connections between various such elements. In this context, the term "interconnect" can refer to electrical traces (sometimes also called "lines," "wires," "metallic wires," or "trenches") and conductive vias (sometimes also called "vias" or "metallic vias"). Sometimes, conductive traces and vias may be referred to as "conductive traces" and "conductive vias," respectively, to highlight the fact that these elements comprise conductive materials such as metals. Similarly, when used in devices that also operate on optical signals (such as photonic ICs (PICs)), "interconnect" can also describe any element formed of optically conductive material used to provide optical connections to one or more elements associated with the PCI. In this context, the term "interconnect" can refer to optical waveguides (e.g., structures that guide and confine light waves), including optical fibers, beam splitters, optical combiners, optical couplers, and optical vias.

[0027] The term "conductive trace" can be used to describe conductive elements isolated by insulating material. Within an IC die, this insulating material includes interlayer low-k dielectrics disposed within the IC die. Within a package substrate and a printed circuit board (PCB), this insulating material includes organic materials such as ajinomoto fiber composite (ABF), polyimide, or epoxy resin. Such conductive lines are typically arranged across several levels or layers of a metallized stack.

[0028] The term "conductive via" can be used to describe a conductive element that interconnects two or more conductive lines at different levels of an interconnected metallization stack. For this purpose, vias can be provided that are substantially perpendicular to the plane of the IC die / chip or the support structure on which the IC structure is provided, and vias can interconnect two conductors in adjacent levels or two conductors in non-adjacent levels.

[0029] The term "packaging substrate" can be used to describe any substrate material that facilitates the packaging of any assembly of semiconductor dies and / or other electrical components, such as passive electrical components. As used herein, packaging substrates can be formed of any material, including but not limited to insulating materials such as resin-impregnated glass fibers (e.g., PCBs or printed circuit boards (PWB)), glass, ceramics, silicon, silicon carbide, etc. Furthermore, as used herein, packaging substrate can refer to a substrate comprising stacked layers (e.g., ABF layers).

[0030] The term “metallized stack” can be used to refer to one or more interconnect stacks used to provide connections to different circuit components to IC dies / chips and / or package substrates.

[0031] As used herein, the term “spacing” for interconnect refers to the center-to-center distance between adjacent interconnects.

[0032] In the context of a stack of dies coupled to each other or in the context of dies coupled to a package substrate or a base die, the term “interconnect” may also refer to a die-to-die (DTD) interconnect and a die-to-package substrate (DTPS) interconnect, respectively. In some embodiments, a DTPS interconnect may also refer to a die-to-base die interconnect.

[0033] Although not specifically shown in all of these figures to avoid confusion, when describing a DTD or DTPS interconnect, the surface of the first die may include a first set of conductive contacts, and the surface of the second die, package substrate, or base die may include a second set of conductive contacts. One or more conductive contacts of the first set can then be electrically and mechanically coupled to some conductive contacts of the second set via the DTD or DTPS interconnect.

[0034] The DTPS interconnects disclosed herein can take any suitable form. In some embodiments, a set of DTPS interconnects may include solder (e.g., solder bumps or solder balls subjected to thermal reflow to form the DTPS interconnect). DTPS interconnects including solder may include any suitable solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, a set of DTPS interconnects may include anisotropic conductive materials, such as anisotropic conductive films or anisotropic conductive pastes. Anisotropic conductive materials may include conductive materials dispersed in non-conductive materials. In some embodiments, anisotropic conductive materials may include microscopic conductive particles embedded in an adhesive or thermosetting adhesive film (e.g., thermosetting biphenyl-type epoxy resin or acrylic-based material). In some embodiments, conductive particles may include polymers and / or one or more metals (e.g., nickel or gold). For example, conductive particles may include nickel-coated gold or silver-coated copper, which is in turn coated with a polymer. In another example, the conductive particles may include nickel. When the anisotropic conductive material is not compressed, there may be no conductive path from one side of the material to the other. However, when the anisotropic conductive material is sufficiently compressed (e.g., through conductive contacts on either side of the anisotropic conductive material), the conductive material near the compressed region can come into contact with each other to form a conductive path from one side of the film to the other in the compressed region.

[0035] DTD interconnects can take any suitable form. In some embodiments, some or all of the DTD interconnects in a microelectronic component or IC package as described herein can be metal-to-metal interconnects (e.g., copper-to-copper interconnects or plated interconnects). In such embodiments, conductive contacts on either side of the DTD interconnect can be joined together (e.g., under elevated pressure and / or temperature) without the use of intermediate solder or anisotropic conductive material. In some metal-to-metal interconnects, a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide) can be present between the bonded metals (e.g., between copper pads or pillars providing associated conductive contacts). In some embodiments, one side of the DTD interconnect may include metal pillars (e.g., copper pillars), and the other side of the DTD interconnect may include metal contacts recessed in a dielectric (e.g., copper contacts). In some embodiments, metal-to-metal interconnects (e.g., copper-to-copper interconnects) may include noble metals (e.g., gold) or their oxides that are conductive (e.g., silver). In some embodiments, metal-to-metal interconnects may include metal nanostructures (e.g., nanorods) that may have a reduced melting point. Metal-to-metal interconnects may be able to reliably conduct higher currents than other types of interconnects; for example, some solder interconnects can form brittle intermetallic compounds when current flows through them, and the maximum current delivered through such interconnects can be constrained to mitigate mechanical failure.

[0036] In some embodiments, the die on either side of a set of DTD interconnects may be a bare (e.g., unencapsulated) die.

[0037] In some embodiments, DTD interconnects may include solder. For example, a DTD interconnect may include conductive bumps or pillars (e.g., copper bumps or pillars) attached to corresponding conductive contacts by solder. In some embodiments, a thin solder capping layer may be used in metal-to-metal interconnects to accommodate planarity, and the solder may become an intermetallic compound during processing. In some embodiments, the solder used in some or all DTD interconnects may have a higher melting point than the solder included in some or all DTPS interconnects. For example, when forming DTD interconnects in an IC package prior to forming DTPS interconnects, solder-based DTD interconnects may use higher-temperature solders (e.g., melting points above 200°C), while DTPS interconnects may use lower-temperature solders (e.g., melting points below 200°C). In some embodiments, higher-temperature solders may include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, lower-temperature solders may include tin and bismuth (e.g., eutectic tin-bismuth), tin, silver, bismuth, indium, indium and tin, or gallium.

[0038] In some embodiments, a set of DTD interconnects may include anisotropic conductive materials, such as any of the materials discussed above for DTPS interconnects. In some embodiments, DTD interconnects may be used as data transmission channels, while DTPS interconnects may be used as power lines and ground lines, etc.

[0039] It will be appreciated that one or more levels of underfill (e.g., organic polymer materials such as benzotriazole, imidazole, polyimide, or epoxy resin) may be provided in the IC package described herein, and may not be labeled to avoid confusing the figures. In various embodiments, the levels of underfill may include the same or different insulating materials. In some embodiments, the levels of underfill may include a thermosetting epoxy resin with silica particles; in some embodiments, the levels of underfill may include any suitable material capable of performing underfill functions such as supporting the die and reducing thermal stress on interconnects. In some embodiments, the selection of the underfill material may be based on design considerations such as shape factor, size, stress, operating conditions, etc.; in other embodiments, the selection of the underfill material may be based on material properties and processing conditions such as curing temperature, glass transition temperature, viscosity, and chemical resistance, among other factors; in some embodiments, the selection of the underfill material may be based on both design and processing considerations.

[0040] In some embodiments, one or more layers of solder resist (e.g., liquid epoxy, liquid photoimageable polymer, dry film photoimageable polymer, acrylic resin, solvent) may be provided in the IC package described herein, and may not be labeled or shown to avoid obscuring the figures. The solder resist may be a liquid or dry film material comprising a photoimageable polymer. In some embodiments, the solder resist may be non-photoimageable.

[0041] The terms “substantially,” “close to,” “approximately,” “near,” and “about” generally refer to a target value within + / -20% (e.g., within + / -5% or 10% of the target value) based on the context of a specific value as described herein or known in the art.

[0042] Terms indicating the orientation of various elements, such as “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between elements, are generally referred to within + / - 5% to 20% of the target value based on the context of a particular value as described herein or known in the art.

[0043] The term “connection” refers to a direct connection between connected things (which may be one or more of mechanical, electrical and / or thermal connections) without any intermediate means, while the term “coupled” refers to a direct connection between connected things, or an indirect connection through one or more passive or active intermediate means.

[0044] The description uses the phrases "in one embodiment" or "in an embodiment," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., as used with respect to embodiments of this disclosure are synonymous.

[0045] This disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments.

[0046] As used herein, the terms “above,” “below,” “between,” and “on” refer to the relative position of a material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with that other layer, or may have one or more intermediate layers. Furthermore, a layer disposed between two layers may be in direct contact with one or both of the two layers, or may have one or more intermediate layers. Conversely, a first layer described as being “on” a second layer refers to a layer in direct contact with that second layer. Similarly, unless otherwise explicitly stated, a feature disposed between two features may be in direct contact with the adjacent feature, or may have one or more intermediate layers.

[0047] As used herein, the term “setup” refers to location, positioning, placement and / or arrangement, rather than any particular method of formation.

[0048] When a reference measurement range is used, the term "between" includes the ends of the measurement range.

[0049] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0050] Although some elements may be referred to in the singular form herein, such elements may include multiple sub-elements. For example, "conductive material" may include one or more conductive materials. In another example, "dielectric material" may include one or more dielectric materials.

[0051] Unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” and “third” to describe common objects merely indicates different examples of similar objects being referenced and is not intended to imply that the objects described in this way must be in a given order in time, space, ranking, or any other way.

[0052] In the following detailed description, reference is made to the accompanying drawings, which form a part of the description, and practical embodiments are illustrated in the drawings by way of example. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0053] The accompanying drawings are not necessarily drawn to scale. Although many of the drawings show straight structures with flat walls and right-angled corners, this is merely for illustrative purposes, and actual devices manufactured using these techniques will exhibit rounded corners, surface roughness, and other characteristics.

[0054] In the accompanying drawings, the same reference numerals refer to the same or similar elements / materials shown, such that, unless otherwise stated, the interpretation of an element / material with a given reference numeral provided in the context of one of the drawings applies to other drawings that may illustrate elements / materials with the same reference numerals. Furthermore, singular and plural forms of labels may be used with reference numerals to indicate single and multiple elements of the same or similar type, kind, or category, respectively.

[0055] Furthermore, some schematic diagrams of example structures of the various devices and components described herein, shown in the accompanying drawings, may be rendered with precise right angles and straight lines. However, it should be understood that such schematic diagrams may not reflect real-world process constraints, which may result in features appearing less “ideal” when examined using images from suitable characterization tools, such as scanning electron microscopy (SEM) images, transmission electron microscopy (TEM) images, or non-contact profilometers. Possible processing and / or surface defects may also be visible in such images of real structures, such as surface roughness, curvature or profile deviations, pits or scratches, imperfectly straight edges of the material, tapered vias or other openings, unintentional rounding of corners or variations in the thickness of different material layers, accidental spirals within crystal regions, edge or combined dislocations, and / or accidental dislocation defects of individual atoms or clusters of atoms. Other defects not listed herein but common in the fields of device fabrication and / or packaging may also be present.

[0056] Note that in the accompanying drawings, various components (e.g., interconnects, conductive contacts, etc.) are shown aligned (e.g., at corresponding interfaces) for illustrative purposes only; in reality, some or all of them may be misaligned. Furthermore, other components, such as bonding pads, landing pads, metallization, etc., may be present in the assembly and are not shown in the figures to avoid confusion. Additionally, the figures are intended to illustrate the relative arrangement of components within the assembly, and typically, such assemblies may include other components not shown (e.g., various interface layers or various other components related to optical functions, electrical connections, or thermal mitigation). For example, in some other embodiments, the assembly shown may include more dies and other electrical components. Furthermore, although some components of the assembly are shown in the figures as planar rectangles or formed of rectangular solids, this is merely for illustrative purposes, and embodiments of these assemblies may be curved, rounded, or other irregularly shaped, as determined by and sometimes unavoidable by the manufacturing processes used to produce the various components.

[0057] The accompanying drawings show a specific number and arrangement of structures and components for illustrative purposes, and any desired number or arrangement of such structures and components may be present in various embodiments.

[0058] Furthermore, unless otherwise stated, the structures shown in the figures may take any suitable form or shape depending on the material properties, manufacturing process, and operating conditions.

[0059] Various operations can be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. In particular, these operations may not be performed in the order presented. The described operations may be performed in a different order than the described embodiments. Various additional operations may be performed, and / or the described operations may be omitted in additional embodiments.

[0060] When used to describe a size range, the phrase "between X and Y" indicates a range including both X and Y. For convenience, the phrase "Figure 2" can be used to refer to... Figures 2A to 2N The collection of attached figures; the phrase "Figure 3" can be used to refer to... Figures 3A to 3B The accompanying drawings, etc. Although some elements may be referred to in the singular form herein, such elements may include multiple sub-elements. For example, "insulating material" may include one or more insulating materials. As used herein, "conductive contact" may refer to a portion of a conductive material (e.g., metal) that serves as an electrical interface between different components; the conductive contact may be recessed into the surface of the component, flush with the surface of the component, or extend away from the surface of the component, and may take any suitable form (e.g., a conductive pad or socket, or a portion of a conductive wire or via).

[0061] Figures 1A to 1B A flowchart is shown of a method 100 for manufacturing a stacked semiconductor die architecture having dies orthogonally stacked with a substrate die or a base die, according to some embodiments. Figures 2A to 2N Provided according to some embodiments Figures 1A to 1B Cross-sectional views of various stages in the fabrication of an example stacked semiconductor die architecture according to Method 100. Similarly, Figures 3A to 3C Provided according to some embodiments in having according to Figures 1A to 1B The method is orthogonal to cross-sectional views of various stages in the fabrication of an example stacked semiconductor die architecture, which is an example of a die or substrate stack.

[0062] Although each operation of method 100 is shown once and in a specific order, the operations can be performed in any suitable order and repeated as needed. For example, one or more operations can be performed in parallel to fabricate multiple stacked semiconductor dies, wherein the dies are simultaneously orthogonal to a substrate die or substrate. In another example, one or more operations can be performed in parallel to fabricate multiple stacked wafers simultaneously. Furthermore, the exemplary fabrication method 100 may include other operations not specifically shown in FIG1.

[0063] Method 100 may begin with process 102, which includes adding sacrificial material to one side of a first wafer. Figure 2A An assembly 200, which may be an example result of process 102, is shown, illustrating a wafer 215 having a sacrificial material 225 on a first surface 217-1 of wafer 215. The sacrificial material 225 may be deposited onto wafer 215. Wafer 215 may include a semiconductor material, such as silicon. Wafer 215 may be constructed from a semiconductor material system including, for example, an N-type or P-type material system. In some embodiments, the sacrificial material 225 may include one or more of silicon dioxide, polyimide, amorphous silicon, and aluminum. The sacrificial material 225 may be a resist layer, such as a photoresist, and may include polymers, resins, or other materials. Although several examples of materials that can form the sacrificial material 225 are described herein, any materials and / or structures that can be formed as described herein and used as sacrificial material 225 fall within the spirit and scope of this disclosure.

[0064] Next, method 100 includes process 104 of creating a cavity in the sacrificial material. Figure 2B An example result of process 104 is shown, illustrating an assembly 202 comprising a wafer 215, a sacrificial material 225, and multiple cavities 230 within the sacrificial material 225. In some examples, etching, patterning, or any suitable fabrication technique may be used to form the cavities 230.

[0065] Next, method 100 includes process 106 of filling the cavity with a conductive material to form a conductive contact. Figure 2C An example result of process 106 is shown, illustrating an assembly 204 including a wafer 215, sacrificial material 225, and conductive contacts 235. The conductive contacts 235 are on a first surface 217-1 of the wafer 215, where cavities 230 are fabricated in process 104. In some embodiments, the conductive contacts 235 are uniformly spaced on the first surface 217-1 of the wafer 215. The conductive contacts 235 may comprise one or more conductive materials, such as copper, silver, nickel, gold, platinum, lead, indium, bismuth, or other metals or alloys. The conductive contacts 235 may have a width 237 and a height 239. The height 239 may range from about 10 micrometers to 1.4 millimeters, and in some examples, the height ranges from about 25 micrometers to 55 micrometers. The width 237 may have any suitable value to provide conductive contacts with target electrical characteristics.

[0066] Method 100 includes a process 108 for removing sacrificial material from a first side of a wafer. Figure 2D An example result of process 108 is shown, illustrating an assembly 206 including wafer 215 and conductive contacts 235. Removal from the first surface 217-1 of wafer 215... Figure 2C The sacrificial material 225 shown.

[0067] Next, method 100 includes a process 110 of providing a spacer layer to the surface of the wafer around the conductive contact portion. Figure 2E An example result of process 110 is shown, illustrating an assembly 208 including a wafer 215, conductive contacts 235, and a spacer layer 240. The spacer layer 240 is disposed on a first surface 217-1 of the wafer 215. The spacer layer 240 is an insulating material, and the spacer layer 240 may be a dielectric material. In some embodiments, the spacer layer 240 provides stress relief for the wafer. In some embodiments, the spacer layer 240 provides strain relief for the wafer. The spacer layer 240 material may be selected to have a coefficient of thermal expansion (CTE) that can alleviate or minimize any stress between the die and the substrate (e.g., a substrate die or substrate) in a stacked semiconductor die architecture manufactured via method 100. The stress between the die and the substrate may be caused by non-uniform thermal expansion in the microelectronic assembly. In some embodiments, the CTE of the spacer layer material may have a value between the CTE of the substrate and the CTE of the die. In some embodiments, the spacer layer 240 may include polyimide, a suitable epoxy resin material, such as epoxy resin, Ajinomoto stacked film (ABF), or any other suitable organic material. In some embodiments, spacer layer 240 may include inorganic materials, and in some embodiments, spacer layer 240 may include oxides.

[0068] Method 100 also includes a process 112 of creating cavities in a spacer layer next to each conductive contact. Figure 2F An example result of process 112 is shown, illustrating an assembly 210 including wafer 215, conductive contacts 235, spacer layer 240, and cavity 245. Cavity 245 can be formed using etching, patterning, or any suitable fabrication technique.

[0069] Processes 102-112 of method 100 can be performed on a first wafer, and similar processes 122-132 of method 100 can be performed on a second wafer. In some embodiments, processes 122-132 are performed in parallel with processes 102-112 to produce a second wafer cell including a spacer layer and conductive contacts. Processes 114-118 can be performed on the first wafer to prepare for stacking the second wafer on the first wafer. In other examples, processes 114-118 can be performed on the second wafer to prepare for stacking the first wafer on the second wafer.

[0070] Next, method 100 includes process 114 of providing a carrier on top of the spacer layer. Figure 2G An example result of process 114 is shown, illustrating component 212, which includes wafer 215, conductive contacts 235, spacer layer 240, cavity 245, and carrier 250 on the top surface 241 of spacer layer 240. In many embodiments, carrier 250 comprises a layer of any solid material capable of withstanding the temperatures, pressures, and chemicals used in semiconductor processes; examples of carrier 250 include semiconductor wafers, glass wafers, ceramic wafers, etc. In some embodiments, the carrier may comprise glass or silicon carbide material.

[0071] Method 100 also includes a process 116 of grinding the wafer to a selected thickness. Figure 2H An example result of process 116 is shown, illustrating assembly 214, which includes a thinned wafer 215, conductive contacts 235, a spacer layer 240, a cavity 245, and a carrier 250 on the top surface 241 of the spacer layer 240. The wafer 215 is ground by removing material from its second surface 217-2 until a selected height 219 is reached. Any selected method can be used to remove material from the second surface 217-2 of the wafer 215, such as mechanical grinding (e.g., using a diamond and resin-bonded grinding wheel), chemical mechanical planarization (i.e., chemical etching and mechanical polishing), wet etching (i.e., etching away wafer material using a chemical solution), etc. In various embodiments, the height 219 of the thinned wafer 215 can range from about 35 micrometers to 800 micrometers.

[0072] Next, method 100 includes process 118 of adding an adhesive layer to the ground surface of the wafer. Figure 2I An example result of process 118 is shown, illustrating an assembly 216 comprising an adhesive layer 255 on the second surface 217-2 of wafer 215. Note that, for illustrative purposes, assembly 216 includes an inverted assembly 214 such that the carrier 250 is shown at the bottom of assembly 216. In some embodiments, adhesive layer 255 may be non-conductive. In some embodiments, adhesive layer 255 may be epoxy resin. In some embodiments, adhesive layer 255 may be an insulating material.

[0073] Next, method 100 includes a process 140 of attaching a spacer layer (from step 132) of the second wafer to an adhesive layer on the first wafer to produce a wafer stack. Figure 2J An exemplary result of process 140 is shown, illustrating an assembly 218 including a carrier 250, a first spacer layer 240, a first wafer 215, an adhesive layer 255, a second spacer layer 260, and a second wafer 265. Method 100 also includes a process 142 of grinding the second wafer to a selected height. Figure 2K Example results of process 142 are shown, illustrating the following: Figure 2J The component 220 is a wafer stack of component 218, wherein a second wafer 265 is thinned to a selected height 269. In some examples, the thinning height 269 of the second wafer (i.e., after grinding) is approximately the same as the height 219 of the first wafer.

[0074] Method 100 continues with process 144, which repeats steps 122-132 with a third wafer, adds an adhesive layer to the grinding surface of the second wafer, attaches a spacer layer of the third wafer to the adhesive layer on the second wafer, and grinds the third wafer to a selected height. Figure 2L An example intermediate result of process 144 is shown, illustrating component 222, which includes component 220 having an adhesive layer 270 on a second wafer 265. Figure 2M An exemplary result of process 144 is shown, illustrating the following: Figure 2L Component 224 of component 222, wherein the third spacer layer 280 is attached to the adhesive layer 270 on the second wafer 265, and the third wafer 275 is on top of the third spacer layer 280. Therefore, component 220 is a wafer stack comprising three wafers.

[0075] In various embodiments, process 144 of method 100 may be repeated to add additional wafers to assembly 224. In some embodiments, the number of wafers corresponds to the number of dies in a die stack manufactured using method 100.

[0076] Method 100 includes process 150: individualizing a wafer stack at a cavity in a spacer layer to produce a die stack, wherein each die is coupled to one of the conductive contacts; and rotating each die stack by 90 degrees. Figure 2N An example result of process 150 is shown, illustrating assembly 226 comprising three die stacks 285-1, 285-2, and 285-3. Specifically, Figure 2M The wafer stack shown in component 224 is individualized at cavity 245, thereby producing Figure 2N The three die stacks 285-1, 285-2, and 285-3 are shown. Each die stack 285 includes three dies (wherein, the three dies are portions of wafers 215, 265, and 275), three spacer layers (wherein, the three spacer layers are portions of spacer layers 240, 260, and 280), and three conductive contacts 235. Specifically, the first die stack 285-1 includes dies 215-1, 265-1, and 275-1. A first spacer layer 240-1 and conductive contacts 235 are located on a first surface of the first die 215-1. An adhesive layer 255-1 is located on a second surface of the first die 215-1. A second spacer layer 260-1 and conductive contacts 235 are located between the adhesive layer 255-1 and the first surface of the second die 265-1. An adhesive layer 270-1 is located on a second surface of the second die 265-1. The third spacer layer 280-1 and the conductive contact 235 are located between the adhesive layer 270-1 and the first surface of the third die 275-1. The second die stack 285-2 and the third die stack 285-3 are substantially similar to the first die stack 285-1. Figure 2N As shown, the die stack 285 is rotated 90 degrees, such that the dies in die stack 285-1 are parallel to the dies in die stack 285-2 and parallel to the dies in die stack 285-3. Similarly, the dies in die stack 285 are perpendicular to... Figure 2M The orientation of the wafer stack shown in component 224, which is individualized to manufacture die stack 285.

[0077] Next, method 100 includes a process 152 of disposing each die stack on a substrate such that the faces of the dies in each die stack are substantially orthogonal to the top surface of the substrate. The substrate may be a base die, a substrate (such as a packaging substrate), or any other suitable substrate. Figure 3AAn example result of process 152 is shown, illustrating an assembly 300 including a substrate 310 having a top surface 311, conductive contacts 315, and a die stack 285. In some embodiments, the conductive contacts 315 are on the top surface 311 of the substrate 310. In some embodiments, the conductive contacts 315 are at least partially embedded in the substrate 310, wherein the top surface of each conductive contact 315 is aligned with or protrudes above the top surface 311 of the substrate 310. Figure 3A As shown, the substrate 310 includes a plurality of conductive contacts 315, each corresponding to a conductive contact 235 on the die stack 285. For example, the conductive contacts 315 include conductive materials such as copper, silver, nickel, gold, platinum, lead, indium, bismuth, or other metals or alloys.

[0078] Method 100 then includes a process 154 of coupling the conductive contact of a die in each of the die stacks to a corresponding conductive contact on the top surface of the substrate. Figure 3B An example result of process 154 is shown, illustrating an assembly 302 including a die stack 285 coupled to a substrate 310. Specifically, conductive contacts 315 on the top surface of the substrate 310 are coupled to corresponding conductive contacts 235 on the die stack. In some embodiments, the dies in the die stack 285 can be electrically and mechanically coupled to the substrate 310 via DTPS or DTD interconnects 320. In particular, conductive contacts 235 can be electrically and mechanically coupled to corresponding conductive contacts 315 on the top surface of the substrate 310 via interconnects 320. In some examples, the substrate 310 is a package substrate. In some examples, the substrate 310 is a base die. In various examples, the interconnects 320 include solder (e.g., solder bumps or balls). In some embodiments, the interconnects 320 may be adjacent to the dies and / or base dies 310 in the die stack 285, as shown, for example, regarding Figures 5A to 5B and Figures 6A to 6B The discussion.

[0079] Next, method 100 includes a process 156 of adding an insulating filler material on top of the top surface of the substrate and around the bottom portion of the die stack. Figure 3CAn example result of process 156 is shown, illustrating an assembly 304 including a die stack 285 coupled to a substrate 310, wherein an insulating material 325 surrounds a portion of the die stack 285 on the top surface 311 of the substrate 310. The insulating material 325 may be a molded underfill. In some embodiments, the insulating material 325 may extend over the conductive contacts 235 to the spacer layers 240, 260, 280, and the insulating material 325 may extend partially around the spacer layers 240, 260, 280. In some embodiments, the insulating material 325 may extend upward from the top surface 311 of the substrate 310 to the die stack 285 around the interconnect 320; in such embodiments, the insulating material 325 may act as an underfill material. In some embodiments, the insulating material 325 may extend upward between the top surfaces 311 of the substrate 310 between the die stacks 285 surrounding the associated interconnects 320 and further upward beyond the conductive contacts 235; in such embodiments, the insulating material 325 may act as an underfill material. The insulating material 325 may include a variety of different insulating materials (e.g., underfill materials and different overmolding materials). The insulating material 325 may be an insulating material, such as a suitable epoxy resin material. In some embodiments, the insulating material 325 may include an underfill material, which is an epoxy flux that facilitates attaching the die stacks 285 to the substrate 310 and polymerizing and encapsulating the interconnects 320. The insulating material 325 may be selected to have a coefficient of thermal expansion (CTE) that can mitigate or minimize stress between the die and the substrate 310 in the die stacks 285 caused by uneven thermal expansion in the microelectronic component 304. In some embodiments, the CTE of the insulating material 325 may have a value between the CTE of the substrate 310 (e.g., the CTE of the dielectric material of the substrate 310) and the CTE of the dies 215, 265, 275 in the die stack 285.

[0080] In some embodiments, Figure 3C The microelectronic component 304 may also include a heat sink. The heat sink can be used to remove heat from the die stack 285 (e.g., to allow heat to be more easily dissipated by a heat sink or other thermal management device). The heat sink may include any suitable thermally conductive material (e.g., metal, suitable ceramic, etc.) and may include any suitable features (e.g., fins). In some embodiments, the heat sink may be an integrated heat sink.

[0081] The components of the microelectronic assemblies shown in the accompanying drawings can have any suitable dimensions. Only a subset of the drawings are labeled with reference numerals indicating dimensions, but this is merely for clarity, and any microelectronic assembly disclosed herein may have components with the dimensions discussed herein. For example, in some embodiments, the thickness of the substrate may be between 0.1 mm and 1.4 mm (e.g., between 0.1 mm and 0.35 mm, between 0.25 mm and 0.8 mm, or approximately 1 mm).

[0082] Figures 4A-4B An isometric view of an assembly 400, according to some embodiments, including a die stack 450 coupled to a substrate 310 (e.g., a substrate die or substrate), wherein dies 415-1, 415-2, 415-3 are orthogonal to the substrate 310 stack. Figure 4A As shown, the die stack 450 includes a plurality of dies 415, with spacer layers 420 between the dies 415. For example, in Figure 4A In this configuration, a first spacer layer 420-1 is located between a first die 415-1 and a second die 415-2, and a second spacer layer 420-2 is located between a second die 415-2 and a third die 415-3. An example die stack 450 includes four dies 415. In other embodiments, the die stack 450 includes more than four dies 415. The die stack 415 may be substantially similar to the die stack 285 of FIG. 2. In some embodiments, according to... Figures 1A to 1B Method 100 manufactures component 400.

[0083] Figure 4B An isometric view of an assembly 402 including a die stack 450 coupled to a substrate 310 is provided, showing conductive contacts 315 on the top surface of the substrate 310 and interconnects 320 coupling the die stack 450 to the substrate 310. The interconnects 320 are coupled to the die stack 450 at spacer layers 420. In some embodiments, conductive contacts coupling to corresponding dies 415 in the die stack 450 are present at the bottom edge of the spacer layers 420. In various examples, assembly 402 may be... Figure 3B The isometric view of component 302.

[0084] Figures 5A to 5B Schematic cross-sectional views of components 500, 502 according to some embodiments are provided, each cross-sectional view showing a die stack 450 coupled to a substrate 310 (e.g., a substrate die or substrate). Figure 5AAn assembly 500 is shown, wherein a conductive contact 235 on a die 415 has a width 535 smaller than that of the spacer layer 420. In some embodiments, the width 535 of the conductive contact 235 is less than half the width 520 of the spacer layer 420, and in some embodiments, the width 535 of the conductive contact 235 is less than one-third the width 520 of the spacer layer 420. In some embodiments, a gap 540 exists between the conductive contact 235 and the corresponding spacer layer 420 above the corresponding conductive contact 235. In some embodiments, the interconnect 320 may fill the gap 540. Thus, the gap 540 may be filled with solder to the corresponding face of the adjacent die 415.

[0085] Figure 5B Component 502 is shown, wherein conductive contacts 315 on substrate 310 have a width smaller than that of spacer layer 420. Furthermore, conductive contacts 235 have a width smaller than that of spacer layer 420. In component 502, the corresponding conductive contacts 235 extend into the corresponding spacer layer 420, and there is no gap 540. In some embodiments, the width 515 of the conductive contacts 315 on substrate 310 is approximately half the width 520 of spacer layer 420, and in some embodiments, the width 515 of the conductive contacts 315 is approximately 10% to approximately 40% smaller than the width 520 of spacer layer 420. In some embodiments, interconnects 320 extend downward into substrate 310 in the region below the spacer layer excluding conductive contacts 315. Therefore, interconnects 320 can be directly coupled to the top surface of substrate 310 adjacent to conductive contacts 315. Insulating material 325 extends upward around the interconnects on the top surface of substrate 310, representing a portion of the path between die stacks.

[0086] Figures 6A to 6B Schematic cross-sectional views are provided for other examples of die stacks coupled to a substrate die or substrate according to some embodiments. Figure 6A A cross-sectional view of an assembly 600 including a die stack 650 on a substrate 310 is provided. The die stack 650 includes a die 415 and a spacer layer 420. In the die stack 650, conductive contacts 235 have a width smaller than the top of the corresponding spacer layer 420, similar to... Figures 5A to 5B The width of the conductive contact 235 is shown. The spacer layer 420 includes a bottom portion 625 extending immediately adjacent to the conductive contact 235 between the conductive contact 235 and the adhesive layer 555. The bottom portion 625 of the corresponding spacer layer 420 extends to the corresponding interconnect 320. (As shown) Figure 6AAs shown, in some embodiments, the conductive contact 235 in the die stack 650 does not directly physically contact the corresponding conductive contact 315 on the substrate 310, and the corresponding interconnect 320 couples the conductive contact 235 in the die stack 650 to the corresponding conductive contact 315 on the substrate 310.

[0087] Figure 6B A cross-sectional view of an assembly 602 including a die stack 655 on a substrate 310 is provided. The die stack 655 includes dies 415 and spacer layers 420, and is disposed substantially perpendicular to the substrate 310. The dies 415 in the die stack 655 extend downwards into the substrate 310 such that the bottom edge of the dies 415 is on the substrate 310. In some embodiments, an adhesive layer 555 also extends into the substrate 310. Similar to... Figure 6A In component 600, the conductive contact 235 in the die stack 655 does not directly physically contact the corresponding conductive contact 315 on the substrate 310, and the corresponding interconnect 320 couples the conductive contact 235 in the die stack 650 to the corresponding conductive contact 315 on the substrate 310. Insulating material 325 surrounds the die 415 and extends around the interconnect 320 and the conductive contacts 235 and 315 in the space between the dies 415.

[0088] Figures 7A to 7B Schematic isometric views and cross-sectional views of examples of conductive contacts between a die and a substrate die or substrate in a die stack according to some embodiments are provided. Specifically, Figure 7A and Figure 7B It includes a substrate 310, a die 715, and conductive contacts 720 and 725 between the substrate 310 and the die 715. The die 715 is disposed on the substrate 310 and is substantially orthogonal to the substrate 310, similar to... Figures 4A to 4B , Figures 5A to 5B and Figures 6A to 6B die 415 in the die stack. For example... Figure 7A As shown in the isometric view, in some embodiments, conductive contacts 720 and 725 are conductive posts. The conductive contact 720 extends vertically upward away from the substrate 310, and the conductive contact 725 extends vertically outward away from the die 715. In various embodiments, each of the conductive contacts 720 on the substrate 310 has a corresponding conductive contact 725 on the die 715, and the die 715 is orthogonally disposed on the substrate 310 such that the conductive contact 725 on the die 715 contacts the corresponding conductive contact 720 on the substrate 310. Figure 7B The cross-sectional view shows an example of the interface between the conductive contact 720 on the substrate 310 and the conductive contact 725 on the die 715.

[0089] Various embodiments of microelectronic components having dies orthogonally stacked to the substrate, as described above, can advantageously and readily be manufactured in parallel with conventional manufacturing techniques for packaging substrates. The various arrangements of microelectronic components and die stacks shown in Figures 1 through 7 do not represent an exhaustive set of microelectronic components having dies orthogonally stacked to the substrate or substrate as described herein, but are merely illustrative examples. In particular, the number and location of the various elements shown in Figures 1 through 7 are purely illustrative, and in various other embodiments, other numbers of these elements may be used relative to each other, in accordance with the general architectural considerations described herein. For example, although not specifically shown in these figures, in some embodiments, the microelectronic component may include a redistribution layer (RDL) between any pair of layers in the die stack 285, the RDL including multiple interconnect structures (e.g., conductive lines and conductive vias) to facilitate signal and / or power wiring connections between components. In another example, although not specifically shown in these figures, in some embodiments, the packaging substrate of the microelectronic component may include one or more recesses. In such embodiments, the bottom surface of the recess in the packaging substrate may be provided by a solid material of the packaging substrate. Recesses can be formed in the packaging substrate in any suitable manner (e.g., via 3D printing, laser cutting, or drilling recesses in an existing packaging substrate). At least a portion of the substrate or base die can be disposed over or at least partially disposed within such a recess. In yet another example, a feature of any of Figures 1 to 7 can be combined with a feature of any other one of Figures 1 to 7. For example, in some embodiments, the die stack can include more than three layers, and the coupling between the die stack and the substrate can have, for instance, the following characteristics. Figures 5A to 5B , Figures 6A to 6B and Figures 7A to 7B The different arrangements shown are illustrated.

[0090] The microelectronic components disclosed herein, particularly stacked semiconductor die architectures having dies orthogonally stacked with a substrate die or substrate, can be included in any suitable electronic component. Figure 8-11 Various examples of devices that may be included or incorporated in any microelectronic components and / or stacked semiconductor architectures disclosed herein are shown.

[0091] Figure 8This is a top view of wafer 1500 and die 1502, which can be included in any microelectronic component as described herein. For example, die 1502 can be any die described herein. Wafer 1500 may be made of semiconductor material and may include one or more dies 1502 having an IC structure formed on the surface of wafer 1500. Each die 1502 can be a repeating unit of a semiconductor product including any suitable IC. After the semiconductor product is manufactured, wafer 1500 may undergo a individualization process in which dies 1502 are separated from each other to provide discrete “chips” of the semiconductor product. Die 1502 may include one or more transistors (e.g., discussed below). Figure 9 Some of the transistors 1640) and / or supporting circuitry to transmit electrical signals to the transistors and any other IC components. In some embodiments, the die 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridged RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple devices of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be combined with a processing device (e.g., Figure 11 The processing device 1802 or other logic configured to store information in a memory device or execute instructions stored in a memory array is formed on the same die 1502.

[0092] Figure 9 This is a side cross-sectional view of an IC device 1600 that can be included in any microelectronic component as described herein. For example, the IC device 1600 may be disposed on / in any die and / or die stack described herein. The IC device 1600 may be formed on a substrate 1602 (e.g., Figure 8 On the 1500 chip, and may be included in the die (e.g., Figure 8The substrate 1602 may be a semiconductor substrate composed of a semiconductor material system including, for example, an N-type or P-type material system (or a combination of both). The substrate 1602 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator substructure. In some embodiments, the substrate 1602 may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as group III-V materials (i.e., materials from groups III and V of the periodic table), group II-VI materials (i.e., materials from groups II and IV of the periodic table), or group IV materials (i.e., materials from group IV of the periodic table) may also be used to form the substrate 1602. Although several examples of materials that can form the substrate 1602 are described herein, any material that can be used as the substrate of the IC device 1600 may be used. The substrate 1602 may be a singlet die (e.g., Figure 8 The die 1502) or the chip (e.g., Figure 8 The portion of the chip 1500.

[0093] IC device 1600 may include one or more device layers 1604 disposed on substrate 1602. Device layer 1604 may include features of one or more transistors 1640 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on substrate 1602. Device layer 1604 may include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 for controlling current flow in the transistors 1640 between S / D regions 1620, and one or more S / D contacts 1624 for transmitting electrical signals to / from the S / D regions 1620. Transistor 1640 may include additional features not depicted for clarity, such as device isolation regions, gate contacts, etc. Transistor 1640 is not limited to... Figure 9 The types and configurations described herein can include a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or combinations thereof. Planar transistors may include bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), or high electron mobility transistors (HEMTs). Non-planar transistors may include FinFET transistors, such as dual-gate or tri-gate transistors, and all-around or fully all-around gate transistors, such as nanoribbon and nanowire transistors.

[0094] Each transistor 1640 may include a gate 1622 formed of at least two layers (gate dielectric and gate electrode). The gate dielectric may include one or more layers stacked together. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when using a high-k material, an annealing process may be performed on the gate dielectric to improve its quality.

[0095] The gate electrode may be formed on the gate dielectric and may include at least one P-type work function metal or an N-type work function metal, depending on whether the transistor 1640 is a P-type metal-oxide-semiconductor (PMOS) or an N-type metal-oxide-semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, may be included for other purposes. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metals discussed below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any metals discussed above with reference to PMOS transistors (e.g., for work function tuning).

[0096] In some embodiments, when a cross-section of transistor 1640 is viewed along the source-channel-drain direction, the gate electrode may be formed of a U-shaped structure, the U-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and does not include the sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may be formed of a combination of U-shaped structures and planar non-U-shaped structures. For example, the gate electrode may be formed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0097] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming the sidewall spacers are well known in the art and typically include deposition and etching steps. In some embodiments, multiple pairs of spacers may be used; for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0098] The S / D region 1620 can be formed within a substrate 1602 adjacent to the gate 1622 of each transistor 1640. For example, the S / D region 1620 can be formed using an implantation / diffusion process or an etching / deposition process. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic can be implanted into the substrate 1602 to form the S / D region 1620. An annealing process to activate the dopant and further diffuse them into the substrate 1602 can be performed after the ion implantation process. In the latter process, the substrate 1602 can be etched first to form a recess at the location of the S / D region 1620. An epitaxial deposition process can then be performed to fill the recess with the material used to fabricate the S / D region 1620. In some embodiments, a silicon alloy such as silicon germanium or silicon carbide can be used to fabricate the S / D region 1620. In some embodiments, the epitaxially deposited silicon alloy can be in-situ doped with dopant such as boron, arsenic, or phosphorus. In some embodiments, one or more alternative semiconductor materials, such as germanium or group III-V materials or alloys, may be used to form the S / D region 1620. In further embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D region 1620.

[0099] Electrical signals such as power and / or input / output (I / O) signals can be transmitted through one or more interconnect layers disposed on device layer 1604. Figure 9 The interconnect layers 1606, 1608, and 1610 are shown as interconnect layers 1606, 1608, and 1610, which transfer data to and / or from the device. For example, conductive features of the device layer 1604 (e.g., gate 1622 and S / D contact 1624) may be electrically coupled to the interconnect structure 1628 of the interconnect layers 1606, 1608, and 1610. One or more interconnect layers 1606, 1608, and 1610 may form a metallized stack (also referred to as an “ILD stack”) 1619 of the IC device 1600.

[0100] Interconnect structure 1628 can be arranged within interconnect layers 1606-1610 to transmit electrical signals according to a variety of designs (in particular, the arrangement is not limited to...). Figure 9 The specific configuration of the interconnect structure 1628 depicted in the diagram). Although in Figure 9The disclosure depicts a specific number of interconnect layers 1606, 1608, and 1610, but embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0101] In some embodiments, the interconnect structure 1628 may include lines 1628a and / or vias 1628b filled with a conductive material such as a metal. Lines 1628a may be arranged to transmit electrical signals in a direction substantially parallel to a plane parallel to the surface of the substrate 1602 on which the device layer 1604 is formed. For example, from Figure 9 From the perspective of the angle, line 1628a can transmit electrical signals in the direction of entering and exiting the page. Via 1628b can be arranged to transmit electrical signals in a direction substantially perpendicular to the plane of the surface of the substrate 1602 on which the device layer 1604 is formed. In some embodiments, via 1628b can electrically couple lines 1628a of different interconnect layers 1606, 1608 and 1610 together.

[0102] Interconnect layers 1606, 1608, and 1610 may include a dielectric material 1626 disposed between interconnect structures 1628, such as... Figure 9 As shown. In some embodiments, the dielectric material 1626 disposed between interconnect structures 1628 in different interconnect layers 1606, 1608 and 1610 may have different compositions; in other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606, 1608 and 1610 may be the same.

[0103] A first interconnect layer 1606 may be formed over a device layer 1604. In some embodiments, the first interconnect layer 1606 may include a line 1628a and / or a via 1628b, as shown. The line 1628a of the first interconnect layer 1606 may be coupled to a contact portion (e.g., an S / D contact portion 1624) of the device layer 1604.

[0104] A second interconnect layer 1608 may be formed over a first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include a via 1628b to couple a line 1628a of the second interconnect layer 1608 to a line 1628a of the first interconnect layer 1606. Although for clarity, lines 1628a and vias 1628b are structurally depicted as lines within each interconnect layer (e.g., within the second interconnect layer 1608), in some embodiments, lines 1628a and vias 1628b may be structurally and / or materially continuous (e.g., simultaneously filled during a dual damascene process).

[0105] Based on similar techniques and configurations described in conjunction with the second interconnect layer 1608 or the first interconnect layer 1606, a third interconnect layer 1610 (and additional interconnect layers, as needed) may be continuously formed on the second interconnect layer 1608. In some embodiments, the interconnect layers that are “higher” (i.e., further away from the device layer 1604) in the metallization stack 1619 of the IC device 1600 may be thicker.

[0106] IC device 1600 may include solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on interconnect layers 1606, 1608, and 1610. Figure 9 In the diagram, conductive contact 1636 is shown in the form of a bonding pad. Conductive contact 1636 may be electrically coupled to interconnect structure 1628 and is configured to transmit electrical signals from transistor 1640 to other external devices. For example, solder joints may be formed on one or more conductive contacts 1636 to mechanically and / or electrically couple a chip including IC device 1600 to another component (e.g., a circuit board). IC device 1600 may include additional or alternative structures to transmit electrical signals from interconnect layers 1606, 1608, and 1610; for example, conductive contact 1636 may include other similar features (e.g., posts) for transmitting electrical signals to external components.

[0107] Figure 10 This is a side cross-sectional view of an IC device assembly 1700 according to any embodiment disclosed herein. The IC device assembly 1700 may include a stacked semiconductor die architecture, wherein dies are stacked orthogonally to a substrate die or base. The IC device assembly 1700 includes a plurality of components disposed on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes components disposed on a first surface 1740 and an opposing second surface 1742 of the circuit board 1702; typically, components may be disposed on one or both of surfaces 1740 and 1742. Any IC package discussed below with reference to the IC device assembly 1700 may take the form of any embodiment of the microelectronic assembly discussed above, and / or may include one or more die stacks orthogonal to the substrate die or base discussed with reference to Figures 2-7.

[0108] In some embodiments, circuit board 1702 may be a PCB comprising multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to transmit electrical signals between components coupled to circuit board 1702 (optionally combined with other metal layers). In other embodiments, circuit board 1702 may be a non-PCB substrate.

[0109] Figure 10The illustrated IC device assembly 1700 includes an on-intermediate package structure 1736 coupled to a first side 1740 of a circuit board 1702 via a coupling member 1716. The coupling member 1716 electrically and mechanically couples the on-intermediate package structure 1736 to the circuit board 1702 and may include solder balls (e.g.,...). Figure 10 (as shown), the male and female parts of the socket, adhesive, bottom filler material and / or any other suitable electrical and / or mechanical coupling structure.

[0110] The on-intermediate package structure 1736 may include an IC package 1720 coupled to the package intermediary 1704 via a coupling member 1718. The coupling member 1718 may take any suitable form for the application, such as the form discussed above with reference to coupling member 1716. Although Figure 10 A single IC package 1720 is shown, but multiple IC packages can be coupled to a package interposer 1704; in fact, additional interposers can be coupled to the package interposer 1704. The package interposer 1704 can provide an intermediate substrate for bridging the circuit board 1702 and the IC package 1720. The IC package 1720 can be or include, for example, a die (die 1502 of FIG. 5), an IC device (e.g., any IC device described herein, or any combination of such IC devices), or any other suitable component. Typically, the package interposer 1704 can extend the connections to a wider pitch or rewire the connections to different connections. For example, the package interposer 1704 can couple the IC package 1720 (e.g., a die) to a set of ball grid array (BGA) conductive contacts of the coupling member 1716 to couple to the circuit board 1702. Figure 10 In the illustrated embodiment, the IC package 1720 and the circuit board 1702 are attached to opposite sides of the package interposer 1704; in other embodiments, the IC package 1720 and the circuit board 1702 may be attached to the same side of the package interposer 1704. In some embodiments, three or more components may be interconnected through the package interposer 1704.

[0111] In some embodiments, the encapsulation interposer 1704 may be formed as a stacked semiconductor die architecture, wherein the die is orthogonally stacked with a substrate die or substrate as described herein. In some embodiments, the encapsulation interposer 1704 may be formed as a PCB. In some embodiments, the encapsulation interposer 1704 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some embodiments, the encapsulation interposer 1704 may be formed of alternating rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials. In any of these embodiments, the encapsulation interposer 1704 may include a plurality of metal layers separated from each other by dielectric material layers and interconnected by conductive vias. The encapsulation interposer 1704 may include metal lines 1710 and vias 1708, including but not limited to conductive vias 1706. The encapsulation interposer 1704 may also include embedded devices 1714, including passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package interposer 1704. The on-interposer package structure 1736 may take the form of any on-interposer package structure known in the art.

[0112] IC device assembly 1700 may include IC package 1724 coupled to a first side 1740 of circuit board 1702 via coupling member 1722. Coupling member 1722 may take the form of any embodiment discussed above with reference to coupling member 1716, and IC package 1724 may take the form of any embodiment discussed above with reference to IC package 1720.

[0113] Figure 10 The illustrated IC device assembly 1700 includes a package-on-package structure 1734 coupled to a second side 1742 of a circuit board 1702 via a coupling member 1728. The package-on-package structure 1734 may include IC packages 1726 and 1732 coupled together via a coupling member 1730, such that IC package 1726 is disposed between the circuit board 1702 and IC package 1732. The coupling members 1728 and 1730 may take the form of any embodiment of the coupling member 1716 discussed above, and the IC packages 1726 and 1732 may take the form of any embodiment of the IC package 1720 discussed above. The package-on-package structure 1734 can be configured according to any package-on-package structure known in the art.

[0114] Figure 11 This is a block diagram of an example communication device 1800 according to any embodiment disclosed herein. The example communication device 1800 may include one or more microelectronic components and / or stacked semiconductor die architectures, wherein the dies are stacked orthogonally to a substrate die or substrate. A handheld or laptop communication device may be an example of the communication device 1800. Any suitable component of the communication device 1800 may include one or more of the microelectronic components discussed herein, IC packages 1720, 1724, IC device assembly 1700, IC device 1600, or the die 1502 disclosed herein. In particular, any suitable component of the communication device 1800 may include one or more semiconductor die architectures, wherein the dies are stacked orthogonally to a substrate as described herein, for example, as part of a microelectronic component as described herein. Multiple components in Figure 11 The components are shown as included in the communication device 1800, but any one or more of these components may be omitted or copied to suit the application. In some embodiments, some or all of the components included in the communication device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured onto a single system-on-a-chip (SoC) die.

[0115] Additionally, in various embodiments, the communication device 1800 may not include... Figure 11 The communication device 1800 may include one or more components, but may also include interface circuitry for coupling to one or more components. For example, the communication device 1800 may not include the display device 1806, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 1806 may be coupled. In another set of examples, the communication device 1800 may not include the audio input device 1824 or the audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 1824 or the audio output device 1808 may be coupled.

[0116] Communication device 1800 may include processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. Processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing device. Communication device 1800 may include memory 1804, which itself may include one or more memory devices such as volatile memory (e.g., dynamic RAM (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drives. In some embodiments, memory 1804 may include memory that shares a die with processing device 1802. This memory may be used as cache memory and may include embedded DRAM (eDRAM) or spin-transfer torque magnetic RAM (STT-MRAM).

[0117] In some embodiments, communication device 1800 may include communication module 1812 (e.g., one or more communication modules). For example, communication module 1812 may be configured to manage wireless communication for transmitting data to and from communication device 1800. The term "wireless" and its derivatives can be used to describe circuits, apparatus, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation through a non-solid medium. This term does not imply that the associated apparatus does not include any wiring, although they may not in some embodiments. Communication module 1812 may be or may include any microelectronic component disclosed herein.

[0118] The Communication Module 1812 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), Long Term Evolution (LTE) projects, and any amendments, updates, and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as "3GPP2"), etc.). Broadband Wireless Access (BWA) networks compliant with IEEE 802.16 are often referred to as WiMAX networks. WiMAX is an acronym for Global Microwave Access Interoperability, a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. The Communication Module 1812 can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. Communication module 1812 may operate according to Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication module 1812 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, and any other wireless protocol designated as 3G, 4G, 5G, and above. In other embodiments, communication module 1812 may operate according to other wireless protocols. Communication device 1800 may include antenna 1822 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions). Antenna 1822 may include one or more semiconductor die architectures, wherein the dies are orthogonal to a substrate stack as described herein, for example, as part of a microelectronic component as described herein.

[0119] In some embodiments, communication module 1812 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, communication module 1812 may include multiple communication modules. For example, a first communication module 1812 may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and a second communication module 1812 may be dedicated to longer-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication module 1812 may be dedicated to wireless communications, and the second communication module 1812 may be dedicated to wired communications. In some embodiments, communication module 1812 may support millimeter-wave communications.

[0120] The communication device 1800 may include a battery / power circuit 1814. The battery / power circuit 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the communication device 1800 to an energy source (e.g., AC line power) that is separate from the communication device 1800.

[0121] The communication device 1800 may include a display device 1806 (or a corresponding interface circuit, as described above). The display device 1806 may include any visual indicator, such as a head-up display, computer monitor, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0122] The communication device 1800 may include an audio output device 1808 (or a corresponding interface circuit, as described above). The audio output device 1808 may include any device that generates audible indicators, such as a speaker, headphones, or earphones.

[0123] The communication device 1800 may include an audio input device 1824 (or a corresponding interface circuit, as described above). The audio input device 1824 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0124] The communication device 1800 may include a GPS device 1818 (or a corresponding interface circuit, as described above). The GPS device 1818 can communicate with a satellite-based system and can receive the location of the communication device 1800, as is known in the art.

[0125] The communication device 1800 may include other output devices 1810 (or corresponding interface circuitry, as described above). Examples of other output devices 1810 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0126] The communication device 1800 may include other input devices 1820 (or corresponding interface circuitry, as described above). Examples of other input devices 1820 may include accelerometers, gyroscopes, compasses, image capture devices, keyboards, cursor control devices (such as mice, styluses, touchpads), barcode readers, quick-response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0127] The communication device 1800 can have any desired form factor, such as a handheld or mobile communication device (e.g., a cellular phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), desktop communication device, server or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable communication device. In some embodiments, the communication device 1800 can be any other electronic device that processes data.

[0128] The following paragraphs provide examples of the various embodiments disclosed herein.

[0129] Example 1 provides a microelectronic component including: a substrate having a top surface, wherein the substrate is one of a substrate and a substrate die; a die stack including: a first die having a first surface, a first conductive contact on the first surface of the first die, a second die having a first surface and a second surface opposite to the first surface, a second conductive contact on the first surface of the second die, and a spacer layer between the first surface of the first die and the second surface of the second die, wherein the first surface of the first die is parallel to the second surface of the second die; wherein the first surface of the first die and the second surface of the second die are substantially orthogonal to the top surface of the substrate, and wherein the die stack is coupled to the top surface of the substrate; a first substrate conductive contact coupled to the first conductive contact; and a second substrate conductive contact coupled to the second conductive contact.

[0130] Example 2 provides a microelectronic component according to Example 1, wherein the first die is a memory die.

[0131] Example 3 provides a microelectronic component of any of Examples 1-2, further comprising an adhesive between the spacer layer and the second side of the second die.

[0132] Example 4 provides a microelectronic component of any of Examples 1-3, further comprising an insulating material between the first conductive contact and the second surface of the second die.

[0133] Example 5 provides a microelectronic component of any of Examples 1-4, wherein the spacer layer is an insulating material.

[0134] Example 6 provides a microelectronic component of any of Examples 1-5, wherein the spacer layer is a polyimide material.

[0135] Example 7 provides a microelectronic component of any of Examples 1-6, further comprising solder for coupling the conductive contacts of the substrate die and the first conductive contact.

[0136] Example 8 provides a microelectronic component of Example 7, wherein solder is coupled to at least one of a substrate die and a first die.

[0137] Example 9 provides a microelectronic component of any of Examples 1-8, wherein solder is between the spacer layer and the top surface of the substrate die.

[0138] Example 10 provides a microelectronic component of Examples 1-9, wherein a first conductive contact is located between the spacer layer and the top surface of the substrate die.

[0139] Example 11 provides a microelectronic component of Examples 1-10, wherein the first conductive contact comprises copper.

[0140] Example 12 provides a microelectronic component according to any one of Examples 1-11, wherein the spacer layer is between approximately half and three times the thickness of the first die.

[0141] Example 13 provides a microelectronic component according to any one of Examples 1-12, further comprising an insulating material on the top surface of a substrate die, the insulating material surrounding a portion of the die stack.

[0142] Example 14 provides a microelectronic component comprising: a die stack including: a first die having a first surface, a second surface opposite to the first surface, and a bottom edge extending between the first surface and the second surface of the first die; a first conductive contact on the first surface of the first die; a second die having a first surface, a second surface opposite to the first surface, and a bottom edge extending between the first surface and the second surface of the second die, wherein the second surface of the second die is parallel to the first surface of the first die, and the bottom edge of the second die is aligned in the same plane as the bottom edge of the first die; and a spacer layer between the first surface of the first die and the second surface of the second die; and a substrate having a top surface, wherein the bottom edge of the first die is substantially parallel to the top surface of the substrate, and the bottom edge of the second die is substantially parallel to the top surface of the substrate; a substrate conductive contact on the top surface of the substrate; and solder between the substrate conductive contact and the first conductive contact.

[0143] Example 15 provides a microelectronic component of Example 14, wherein the spacer layer is an insulating material.

[0144] Example 16 provides a microelectronic component of Example 14, wherein the area of ​​the first face of the first die is between approximately 10 and 100 times larger than the bottom edge of the first die.

[0145] Example 17 provides a microelectronic component of any of Examples 14-16, further comprising an adhesive between the spacer layer and the second side of the second die.

[0146] Example 18 provides a microelectronic component of any of Examples 14-17, further comprising an insulating material between a first conductive contact and a second surface of a second die.

[0147] Example 19 provides a microelectronic component of Example 18, wherein an insulating material is part of a spacer layer.

[0148] Example 20 provides a microelectronic component of any of Examples 14-19, wherein the substrate die conductive contact is a substrate conductive post, and the first conductive contact is a first conductive post, wherein the substrate conductive post is in contact with the first conductive post.

[0149] Example 21 provides a microelectronic component of any of Examples 14-20, further comprising a first gap between the bottom edge of a first die and the top surface of a substrate die, and a second gap between the bottom edge of a spacer layer and the top surface of the substrate die, wherein the second gap is larger than the first gap.

[0150] Example 22 provides a microelectronic component of Example 21, wherein solder is in a second gap.

[0151] Example 23 provides a microelectronic component of any of Examples 14-22, further comprising an insulating material on the top surface of a substrate die and surrounding the bottom edge of a first die and surrounding the bottom edge of a second die.

[0152] Example 23 provides a method of manufacturing a microelectronic component, the method comprising: providing a die stack comprising: a first die having a first surface and a second surface opposite to the first surface, a first conductive contact on the first surface of the first die, a second die having a first surface and a second surface opposite to the first surface, a second conductive contact on the first surface of the second die, and a spacer layer between the first surface of the first die and the second surface of the second die, wherein the first surface of the first die is parallel to the second surface of the second die; providing a substrate having a top surface, a first substrate conductive contact on the top surface and a second substrate conductive contact on the top surface; disposing the die stack on the top surface of the substrate, wherein the first surface of the first die and the first surface of the second die are substantially perpendicular to the top surface of the substrate; coupling the first conductive contact on the first surface of the first die to the first substrate conductive contact; and coupling the second conductive contact on the first surface of the second die to the second substrate conductive contact.

[0153] Example 24 provides the method of Example 23, and further includes providing solder material between a first conductive contact on a first surface of the first die and a first substrate conductive contact.

[0154] Example 25 provides a method according to any one of Examples 23-24, further comprising providing an insulating material around the top surface of the substrate die and around the bottom portion of the die stack, wherein the bottom portion of the die stack includes a first conductive contact and a second conductive contact.

[0155] Example 26 provides a method according to any one of Examples 23-25, further comprising providing an adhesive between the spacer layer and the second surface of the second die.

[0156] Example 27 provides a method according to any one of Examples 23-26, further comprising providing an insulating material between the first conductive contact and the second surface of the second die.

[0157] Example 28 provides a method according to any one of Examples 23-27, further comprising providing a material that reduces stress between the first conductive contact and the second surface of the second die.

[0158] Example 29 provides a process for manufacturing a semiconductor packaging substrate, the process comprising: providing a die stack including: a first die having a first side and a second side opposite to the first side, a first conductive contact on the first side of the first die, a second die having a first side and a second side opposite to the first side, a second conductive contact on the first side of the second die, and a spacer layer between the first side of the first die and the second side of the second die, wherein the first side of the first die is parallel to the second side of the second die; providing a substrate having a top surface, a first substrate conductive contact on the top surface and a second substrate conductive contact on the top surface; disposing the die stack on the top surface of the substrate, wherein the first side of the first die and the first side of the second die are substantially perpendicular to the top surface of the substrate; coupling the first conductive contact on the first side of the first die to the first substrate conductive contact; and coupling the second conductive contact on the first side of the second die to the second substrate conductive contact.

[0159] Example 30 provides the process of Example 29, and further includes providing solder material between a first conductive contact on a first surface of the first die and a first substrate conductive contact.

[0160] Example 31 provides a process according to any one of Examples 29-30, further comprising providing an insulating material around the top surface of the substrate die and around the bottom portion of the die stack, wherein the bottom portion of the die stack includes a first conductive contact and a second conductive contact.

[0161] Example 32 provides a process according to any one of Examples 29-31, further comprising providing an adhesive between the spacer layer and the second surface of the second die.

[0162] Example 33 provides a process according to any one of Examples 29-32, further comprising providing an insulating material between the first conductive contact and the second surface of the second die.

[0163] Example 34 provides a process according to any one of Examples 29-33, and further includes a material for reducing stress between the first conductive contact and the second surface of the second die.

[0164] The above description of the embodiments shown in this disclosure, including the content described in the specification summary, is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed. While specific embodiments and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of this disclosure, as will be recognized by those skilled in the art. These modifications can be made to this disclosure based on the detailed description above.

Claims

1. A microelectronic component, comprising: A substrate having a top surface, wherein the substrate is one of a substrate and a substrate die; die stack, the die stack comprising: A first die, the first die having a first surface. The first conductive contact portion is located on the first surface of the first die. The second die has a first surface and a second surface opposite to the first surface. The second conductive contact portion is located on the first surface of the second die, and A spacer layer is located between the first surface of the first die and the second surface of the second die, wherein the first surface of the first die is parallel to the second surface of the second die. Wherein, the first surface of the first die and the second surface of the second die are substantially orthogonal to the top surface of the substrate, and The die stack is coupled to the top surface of the substrate; A first substrate conductive contact portion, the first substrate conductive contact portion coupled to the first conductive contact portion; and The second substrate conductive contact portion is coupled to the second conductive contact portion.

2. The microelectronic component according to claim 1, wherein, The first die is a memory die.

3. The microelectronic assembly of claim 1, further comprising an adhesive between the spacer layer and the second surface of the second die.

4. The microelectronic component according to claim 1 further includes an insulating material between the first conductive contact and the second surface of the second die.

5. The microelectronic component according to claim 1, wherein, The spacer layer is an insulating material.

6. The microelectronic component according to claim 1, wherein, The spacer layer is made of polyimide.

7. The microelectronic component according to any one of claims 1-6, further comprising solder coupling the conductive contact portion of the substrate die and the first conductive contact portion.

8. The microelectronic component according to claim 7, wherein, The solder is coupled to at least one of the substrate and the first die.

9. The microelectronic component according to claim 7, wherein, The solder is between the spacer layer and the top surface of the substrate.

10. The microelectronic component according to any one of claims 1-6, wherein, The first conductive contact portion is between the spacer layer and the top surface of the substrate.

11. The microelectronic component according to any one of claims 1-6, wherein, The first conductive contact portion comprises copper.

12. The microelectronic component according to any one of claims 1-6, wherein, The spacer layer is between approximately half and three times the thickness of the first die.

13. The microelectronic assembly according to any one of claims 1-6, further comprising an insulating material on the top surface of the substrate, the insulating material surrounding a portion of the die stack.

14. A microelectronic component, comprising: die stack, the die stack comprising: A first die, the first die having a first surface, a second surface opposite to the first surface, and a bottom edge extending between the first surface and the second surface of the first die. The first conductive contact portion is located on the first surface of the first die. A second die has a first surface, a second surface opposite to the first surface, and a bottom edge extending between the first and second surfaces, wherein the second surface of the second die is parallel to the first surface of the first die, and the bottom edge of the second die is aligned with the bottom edge of the first die in the same plane. A spacer layer, the spacer layer being located between the first surface of the first die and the second surface of the second die; and A substrate having a top surface, wherein the bottom edge of the first die is substantially parallel to the top surface of the substrate, and the bottom edge of the second die is substantially parallel to the top surface of the substrate; A substrate conductive contact portion, the substrate conductive contact portion being located on the top surface of the substrate; and Solder, the solder being located between the conductive contact portion of the substrate and the first conductive contact portion.

15. The microelectronic component according to claim 14, wherein, The area of ​​the first surface of the first die is approximately 10 to 100 times larger than the bottom edge of the first die.

16. The microelectronic component according to claim 14, wherein, The substrate conductive contact portion is a substrate conductive post, and the first conductive contact portion is a first conductive post, wherein the substrate conductive post is in contact with the first conductive post.

17. The microelectronic assembly of claim 14, further comprising a first gap between the bottom edge of the first die and the top surface of the substrate, and a second gap between the bottom edge of the spacer layer and the top surface of the substrate, wherein, The second gap is larger than the first gap.

18. A process for manufacturing a semiconductor packaging substrate, the process comprising: A die stack is provided, the die stack comprising: A first die, the first die having a first surface and a second surface opposite to the first surface. The first conductive contact portion is located on the first surface of the first die. The second die has a first surface and a second surface opposite to the first surface. The second conductive contact portion is located on the first surface of the second die, and A spacer layer is located between the first surface of the first die and the second surface of the second die, wherein the first surface of the first die is parallel to the second surface of the second die. A substrate having a top surface, a first substrate conductive contact portion on the top surface, and a second substrate conductive contact portion on the top surface are provided; The die stack is disposed on the top surface of the substrate, wherein the first surface of the first die and the first surface of the second die are substantially perpendicular to the top surface of the substrate; Couple the first conductive contact portion on the first surface of the first die to the first conductive contact portion of the substrate; and The second conductive contact portion on the first surface of the second die is coupled to the second substrate conductive contact portion.

19. The process of claim 18, further comprising providing solder material between the first conductive contact portion and the first substrate conductive contact portion on the first surface of the first die.

20. The process of claim 18, further comprising providing an insulating material on the top surface of the substrate die and surrounding the bottom portion of the die stack, wherein, The bottom portion of the die stack includes the first conductive contact and the second conductive contact.

Images