High-voltage device and manufacturing method thereof

Abstract

The invention provides a high-voltage device and a manufacturing method thereof. The manufacturing method of the high-voltage device comprises the following steps: providing a substrate of which the top surface is provided with a pad oxide layer; a plurality of isolation structures, an isolation wall and a plurality of active regions are formed in the substrate, the isolation wall and the active regions are defined by the isolation structures, the active regions comprise a first active region and a second active region which are adjacent, and the isolation wall is located between the first active region and the second active region; a patterned second hard mask layer is formed on the substrate, the patterned second hard mask layer covers the second active region, the isolation wall and the isolation structure between the second active region and the isolation wall, and the first active region is exposed; and under the masking of the patterned second hard mask layer and the isolation wall, a thermal oxidation process is adopted to consume the substrate of the first active region to form a high-voltage gate oxide layer. When the high-voltage gate oxide layer is grown on the first active region in an oxidation mode, the isolation wall can block transverse diffusion of oxygen atoms, and beaks formed by oxidation of the second active region are reduced. The high-voltage device is manufactured by using the manufacturing method.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a high-voltage device and its manufacturing method. Background Technology

[0002] High voltage (HV) devices are products capable of withstanding high voltages while ensuring that the gate is not broken down under high voltage operation. Typically, to achieve the purpose of withstanding high voltage, the thickness of the high voltage gate oxide layer is two orders of magnitude greater than that of the low voltage gate oxide layer.

[0003] Figure 1 This is a schematic cross-sectional view of a process in the fabrication of a high-voltage device. (Example) Figure 1 As shown, the top of the substrate 100 has a gate active region 101 and a source / drain active region 102 separated by a shallow trench isolation structure 103. In the step of forming a high-voltage gate oxide layer 104 on the gate active region 101, a patterned hard mask layer 105 needs to be formed on the substrate 100. The patterned hard mask layer 105 covers the source / drain active region 102 and part of the top surface of the shallow trench isolation structure 103 on the side of the source / drain active region 102. The patterned hard mask layer 105 exposes the gate active region 101. Then, the substrate surface of the gate active region 101 is oxidized by a furnace tube process to form the high-voltage gate oxide layer 104.

[0004] refer to Figure 1 As shown, due to the relatively thick thickness of the high-voltage gate oxide layer 104, the growth time required is long. Furthermore, in addition to the vertical thickness growth during the growth process, there is also lateral diffusion of O2. This lateral diffusion of O2 causes the silicon on the substrate surface of the source / drain active regions 102 to be oxidized, forming a bird's beak-like structure made of SiO2 material. Figure 1 As shown in the dashed box, the bird's beak can easily prevent the formation of metal silicide in a part of the top surface of the subsequent source-drain active region 102, resulting in high contact resistance of the contact plugs (CT) on the source-drain active region, which in turn leads to increased power consumption of the high voltage device or even failure to work properly.

[0005] To reduce the birdbeak effect on the active regions of the source and drain, the industry often adjusts the growth rate of the furnace tube process, such as increasing the temperature to increase the growth rate of the high-voltage gate oxide layer, or by implanting other ions into the substrate surface to change the Si surface structure and thus adjust the growth rate of the high-voltage gate oxide layer and the birdbeak effect. However, these methods firstly challenge the furnace tube process limits and alter the thickness of the high-voltage gate oxide layer, and secondly, increasing ion implantation can have negative effects on the equipment. Therefore, methods for reducing the birdbeak effect of adjacent active regions when oxidizing and growing a high-voltage gate oxide layer on an active region still need improvement. Summary of the Invention

[0006] One of the objectives of this invention is to reduce the beak effect of adjacent active regions when growing a high-voltage gate oxide layer on an active region.

[0007] To achieve the above objectives, the present invention provides a method for fabricating a high-voltage device. The method includes: providing a substrate, on which a pad oxide layer covering the top surface of the substrate is formed; forming a plurality of isolation structures and isolation walls and a plurality of active regions defined by the plurality of isolation structures in the substrate, wherein the plurality of active regions include adjacent first active regions and second active regions, and the isolation walls are located between the first active regions and the second active regions; forming a patterned second hard mask layer on the substrate, the patterned second hard mask layer covering the second active regions, the isolation walls, and the isolation structures between the second active regions and the isolation walls, and exposing the first active regions; and, under the masking of the patterned second hard mask layer and the isolation walls, using a thermal oxidation process to consume the substrate of the first active regions to form a high-voltage gate oxide layer.

[0008] Optionally, a method for forming a plurality of isolation structures and isolation walls and a plurality of active regions defined by the plurality of isolation structures in the substrate includes: forming a patterned first hard mask layer on the substrate; etching the substrate to form a plurality of trenches under the masking of the patterned first hard mask layer; and filling the plurality of trenches with an isolation material to form a plurality of isolation structures.

[0009] Optionally, after etching the substrate to form multiple trenches and before filling the multiple trenches with an insulating material to form multiple insulating structures, a line oxide layer is formed in the multiple trenches, the line oxide layer covering the inner surface of the trenches.

[0010] Optionally, the linear oxide layer is an oxide layer including a dopant, wherein the dopant includes nitrogen.

[0011] Optionally, the method of forming a patterned second hard mask layer on the substrate includes: forming a second hard mask material layer covering the substrate on the substrate; forming a patterned second photoresist layer on the second hard mask material layer; using the patterned second photoresist layer as a mask, etching away a portion of the second hard mask material layer to form a patterned second hard mask layer, the patterned second hard mask layer exposing the first active region and a portion of the surface of the isolation structure between the first active region and the isolation wall near the first active region; and, under the mask of the patterned second hard mask layer, etching away the pad oxide layer on the first active region and removing the top end of the isolation structure near the first active region.

[0012] Optionally, the method for fabricating the high-voltage device further includes: removing the patterned second hard mask layer; forming a gate electrode on the first active region, the gate electrode covering the high-voltage gate oxide layer; forming a patterned third photoresist layer on the substrate, the patterned third photoresist layer covering the isolation wall and exposing the second active region and the gate electrode; and performing ion implantation under the masking of the patterned third photoresist layer and the gate electrode to form a source / drain region on top of the second active region.

[0013] Optionally, the gate electrode extends to cover the unetched surface of the isolation structure on the side of the first active region.

[0014] Optionally, the method for fabricating the high-voltage device further includes: forming a source / drain region on the top of the second active region, then forming a metal silicide on the top surface of the second active region and the top surface of the gate electrode; and forming a first contact plug on the metal silicide of the gate electrode, the first contact plug being electrically connected to the gate electrode, and forming a second contact plug on the metal silicide of the second active region, the second contact plug being electrically connected to the second active region.

[0015] Optionally, the distance between the first active area and the second active area is A, and the distance between the isolation wall and the second active area is B, where B is greater than or equal to 1 / 4 of A and less than or equal to 1 / 2 of A.

[0016] In another aspect, the present invention provides a high-voltage device. The high-voltage device includes a substrate, a pad oxide layer, and a high-voltage gate oxide layer. The substrate has a plurality of isolation structures formed therein, as well as isolation walls and a plurality of active regions defined by the plurality of isolation structures. The plurality of active regions include adjacent first and second active regions. The isolation walls are located between the first and second active regions. The pad oxide layer covers the top surface of the isolation walls and a portion of the top surface of the substrate of the second active region. The high-voltage gate oxide layer is located on the substrate surface of the first active region. When the high-voltage gate oxide layer is formed by consuming the substrate of the first active region using a thermal oxidation process, the isolation walls prevent the second active region from being oxidized.

[0017] In the high-voltage device and its fabrication method provided by this invention, an isolation wall is formed simultaneously with the etching of the substrate to form multiple active regions. The multiple active regions include adjacent first and second active regions. The isolation wall is located between the first and second active regions. Under the cover of a patterned second hard mask layer, when the high-voltage gate oxide layer is formed by consuming the substrate surface layer of the first active region using a thermal oxidation process, the isolation wall can prevent oxygen atoms from diffusing laterally to the second active region. This can prevent the top of the substrate of the second active region from being oxidized to form a "bird's beak," thereby avoiding the problem of high contact plug resistance caused by the inability to form metal silicide in the contact plug formation area on the top surface of the second active region. This is beneficial to improving the high power consumption problem of high-voltage devices, and it does not challenge the limits of the thermal oxidation process or implant other unnecessary ions, making the process safe and reliable. In addition, the isolation wall and multiple active regions can be defined using the same mask, without the need for additional masks and process steps, and can be compatible with current process flows, simply and effectively improving the "bird's beak" problem. Attached Figure Description

[0018] Figure 1 This is a schematic cross-sectional view of a process in the fabrication of a high-voltage device.

[0019] Figure 2 This is a schematic flowchart illustrating a method for manufacturing a high-voltage device according to an embodiment of the present invention.

[0020] Figures 3 to 17 This is a step-by-step structural diagram of a method for manufacturing a high-voltage device according to an embodiment of the present invention.

[0021] Explanation of reference numerals in the attached figures:

[0022] ( Figure 1 100 - Substrate; 101 - Under-gate active region; 102 - Source / drain active region; 103 - Isolation structure; 104 - High-voltage gate oxide layer; 105 - Patterned hard mask layer;

[0023] ( Figures 3 to 17 200 - Substrate; 201 - Pad oxide layer; 202 - First active region; 203 - Second active region; 204 - Isolation wall; 205 - High voltage gate oxide layer; 206 - Source / drain region; 301 - First hard mask material layer; 301a - Patterned first hard mask layer; 302 - ODL layer; 303 - Silicon anti-reflection layer; 304 - Patterned first photoresist layer; 305 - Trench; 306 - Line oxide layer; 307 - Isolation structure; 308 - Second hard mask material layer; 308a - Patterned second hard mask layer; 309 - Second photoresist layer; 309a - Patterned second photoresist layer; 310 - Gate electrode; 311 - Patterned third photoresist layer; 312 - Metal silicide; 313 - First contact plug; 314 - Second contact plug. Detailed Implementation

[0024] To reduce the birdbeak effect of adjacent active regions when growing a high-voltage gate oxide layer on an active region, this invention provides a high-voltage device and its fabrication method.

[0025] The high-voltage device and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0026] It should be understood that when an element is referred to as being "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intermediary elements. Conversely, when an element is referred to as being "directly connected to" other elements, there are no intermediary elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0027] Figure 2 This is a schematic flowchart illustrating a method for manufacturing a high-voltage device according to an embodiment of the present invention. (See reference) Figure 2 As shown, the method for manufacturing the high-voltage device provided in this embodiment includes:

[0028] Step S1, providing a substrate on which a pad oxide layer covering the top surface of the substrate is formed;

[0029] Step S2: A plurality of isolation structures, an isolation wall defined by the plurality of isolation structures, and a plurality of active regions are formed in the substrate. The plurality of active regions include an adjacent first active region and a second active region. The isolation wall is located between the first active region and the second active region.

[0030] Step S3: A patterned second hard mask layer is formed on the substrate, the patterned second hard mask layer covering the second active region, the isolation wall, and the isolation structure between the second active region and the isolation wall, and the patterned mask layer exposes the first active region; and,

[0031] Step S4: Under the cover of the patterned second hard mask layer and the isolation wall, a high-voltage gate oxide layer is formed by consuming the substrate of the first active region using a thermal oxidation process.

[0032] It should be noted that, although Figure 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 2 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0033] Figures 3 to 17 This is a step-by-step structural diagram illustrating a method for manufacturing a high-voltage device according to an embodiment of the present invention. The following is in conjunction with... Figure 2 , Figures 3 to 17 The manufacturing method of the high-voltage device in this embodiment will be described.

[0034] refer to Figure 3 As shown, the substrate 200 provided in step S1 can be any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC), or silicon-on-insulator (SOI).

[0035] A pad oxide layer 201 covering the top surface of the substrate 200 is formed on the substrate 200. Exemplarily, the pad oxide layer 201 may be a silicon oxide layer, but is not limited thereto. The pad oxide layer 201 provides a buffer for the subsequent formation of a patterned first hard mask layer, and may also serve as a stop layer in the subsequent step of removing the patterned first hard mask layer.

[0036] Execute step S2, refer to Figure 8 As shown, a plurality of isolation structures 307 are formed in the substrate 200, as well as an isolation wall 204 and a plurality of active regions separated and defined by the plurality of isolation structures 307. The plurality of active regions include an adjacent first active region 202 and a second active region 203, and the isolation wall 204 is located between the first active region 202 and the second active region 203.

[0037] In this embodiment, the isolation structure 307 is a shallow trench isolation structure (STI), but it is not limited to this.

[0038] Specifically, step S2 may include the following sub-steps.

[0039] refer to Figure 3 and Figure 4As shown, a patterned first hard mask layer 301a is formed on the substrate 200. Using the patterned first hard mask layer 301a as a mask, the etch pad oxide layer 201 and the substrate 200 form a plurality of trenches 305. The plurality of trenches 305 separate and define an isolation wall 204 and a plurality of active regions in the substrate 200. The plurality of active regions include an adjacent first active region 202 and a second active region 203. The isolation wall 204 is located between the first active region 202 and the second active region 203.

[0040] The method for forming a patterned first hard mask layer 301a on the substrate 200 may include: such as Figure 3 As shown, a first hard mask material layer 301, an ODL (organic dielectric layer) layer 302, a silicon anti-reflective layer 303, and a first photoresist layer are formed in sequence from bottom to top on the pad oxide layer 201 of the substrate 200. The first photoresist layer is exposed and developed to form a patterned first photoresist layer 304. Using the patterned first photoresist layer 304 as a mask, the silicon anti-reflective layer 303, the ODL layer 302, and the first hard mask material layer 301 are etched to form a patterned first hard mask layer 301a. The silicon anti-reflective layer 303 formed under the first photoresist layer can reduce the reflection of light on the lower surface of the photoresist layer during exposure, so that most of the exposure energy is absorbed by the photoresist layer. Moreover, the ODL layer 302 is also formed under the silicon anti-reflective layer 303. The combination of the ODL layer 302 and the silicon anti-reflective layer 303 can better achieve the ideal photolithography process.

[0041] For example, the material of the first hard mask material layer 301 includes, but is not limited to, silicon nitride (SiN).

[0042] After forming multiple trenches 305, the remaining patterned first photoresist layer 304, silicon anti-reflective layer 303, and ODL layer 302 are removed.

[0043] refer to Figure 5 As shown, a line oxide layer 306 is formed within multiple trenches 305, covering the inner surface of the trenches 305. In this embodiment, the line oxide layer 306 can be formed on the inner surface of the trenches 305 by thermal oxidation, atomic layer deposition, or plasma-enhanced chemical vapor deposition. It should be noted that the line oxide layer 306 is relatively thin; even when formed using a thermal oxidation process, it will only consume silicon on the sidewalls of the active region and will not oxidize the silicon in the central region of the top surface of the active region.

[0044] For example, when a linear oxide layer 306 is formed in multiple trenches 305 using a thermal oxidation process, the sharp corners at the top of the active region can also be rounded.

[0045] refer to Figure 6As shown, ion implantation can be performed on the line oxide layer 306 to increase its density and enhance the isolation capability of the isolation wall 204 and the subsequently formed isolation structure, thus helping to suppress the bird's beak effect. That is, the line oxide layer 306 can be an oxide layer including doped materials, such as silicon oxide, and the doped materials include, but are not limited to, nitrogen (N). It should be noted that in this embodiment, the line oxide layer 306 is doped after its formation; in other embodiments, ion implantation can be performed simultaneously during the formation of the line oxide layer 306.

[0046] refer to Figure 6 and Figure 7 As shown, multiple isolation structures 307 are formed by filling multiple trenches 305 with isolation material. Specifically, an isolation material layer is formed on the substrate 200, which fills the multiple trenches 305 and covers a patterned first hard mask layer 301a. The isolation material layer on the patterned first hard mask layer 301a is removed by chemical mechanical polishing (CMP) and / or etching processes, while retaining the isolation material layer within the trenches 305, thus forming the isolation structures 307. The patterned first hard mask layer 301a serves as an etching stop layer or polishing stop layer for the isolation material layer.

[0047] The isolation material layer can be a silicon oxide layer, but is not limited to this. The isolation material layer can be formed by high-density plasma (HDP) or high aspect ratio deposition (HARP) processes.

[0048] refer to Figure 7 and Figure 8 As shown, the patterned first hard mask layer 301a can be removed using wet etching processes or similar methods.

[0049] For example, after removing the patterned first hard mask layer 301a, the spacing between the top surface of the isolation structure 307 and the top surface of the substrate 200 is greater than or equal to... and less than or equal to The thickness of the pad oxide layer 201 on the surface of the substrate 200 is greater than or equal to and less than or equal to

[0050] In this embodiment, reference Figure 8 As shown, the distance between the first active region 202 and the second active region 203 is A, and the distance between the isolation wall 204 and the second active region 203 is B. B is greater than or equal to 1 / 4 of A and less than or equal to 1 / 2 of A. For example, B is 1 / 3 of A. This way, it will not affect the subsequent setting of the gate electrode above the first active region 202 or the setting of the contact plug on the gate electrode.

[0051] For example, the spacing A between the first active region 202 and the second active region 203 is greater than or equal to 0.8 μm and less than or equal to 1.2 μm, for example, A is 1 μm. The width of the isolation wall 204 can be greater than or equal to 60 nm and less than or equal to 100 nm.

[0052] Execute step S3, refer to Figures 9 to 12 As shown, a patterned second hard mask layer 308a is formed on the substrate 200. The patterned second hard mask layer 308a covers the second active region 203, the isolation wall 204, and the isolation structure 307 between the second active region 203 and the isolation wall 204, and the patterned second hard mask layer 308a exposes the first active region 202.

[0053] Specifically, the method for forming a patterned second hard mask layer 308a on the substrate 200 may include: referring to Figure 9 As shown, a second hard mask material layer 308 covering the substrate 200 is formed on the substrate 200. The second hard mask material layer 308 includes, but is not limited to, a silicon nitride layer; as shown... Figure 10 As shown, a second photoresist layer 309 is formed on the second hard mask material layer 308; as Figure 11 As shown, the second photoresist layer 309 is exposed and developed to form a patterned second photoresist layer 309a; as Figure 11 and Figure 12 As shown, using a patterned second photoresist layer 309a as a mask, a portion of the second hard mask material layer 308 is etched away to form a patterned second hard mask layer 308a. The patterned second hard mask layer 308a exposes the first active region 202 and a portion of the surface of the isolation structure 307 between the first active region 202 and the isolation wall 204 near the first active region 202. Under the mask of the patterned second hard mask layer 308a, the pad oxide layer 201 on the first active region 202 and the top edge of the isolation structure 307 near the first active region 202 are etched away.

[0054] It should be noted that in this embodiment, under the masking of the patterned second hard mask layer 308a, the etching removes one end of the isolation structure 307 between the first active region 202 and the second active region 203. This can meet the minimum spacing requirements of high-voltage devices and contact plugs, and take into account issues such as windows in the process. However, the top of the isolation structure 307 on the side of the first active region 202 is etched open, which causes the top of the isolation structure 307 to become thinner in the horizontal direction. This makes it easier for oxygen atoms to diffuse laterally along the thinned top of the isolation structure 307 into the adjacent active region to form a beak. Therefore, this application forms an isolation wall 204 between the first active region 202 and the second active region 203, which can effectively prevent oxygen atoms from diffusing into the second active region 203 and effectively prevent the second active region 203 from oxidizing and forming a beak.

[0055] Execute step S4, refer to Figure 12 As shown, under the cover of the patterned second hard mask layer 308a and the isolation wall 204, a high-voltage gate oxide layer 205 is formed by consuming the substrate of the first active region 202 using a thermal oxidation process. The high-voltage gate oxide layer 205 covers the top surface of the substrate of the first active region 202.

[0056] For example, the thermal oxidation process can be carried out in a furnace tube. The thermal oxidation process involves placing a substrate at a high temperature and, through an oxygen atmosphere, converting a thin layer of silicon on the substrate surface, such as a silicon surface, into silicon dioxide. Thermal oxidation processes include, but are not limited to, dry oxygen oxidation, water vapor oxidation, and / or wet oxygen oxidation. Dry oxygen oxidation uses a dry, pure oxygen atmosphere, resulting in a good oxide film quality, but the oxidation rate is slow. Water vapor oxidation uses a pure water vapor atmosphere, resulting in the fastest oxidation rate, but the oxide film quality is relatively poor. Wet oxygen oxidation uses both pure oxygen and pure water vapor, resulting in an oxide film quality and oxidation rate that fall between those of dry oxygen oxidation and water vapor oxidation. Those skilled in the art can choose the specific implementation method of the thermal oxidation process according to actual needs.

[0057] In this embodiment, the thickness of the high-voltage gate oxide layer 205 is greater than or equal to...

[0058] refer to Figure 12 As shown, during the thermal oxidation process to form the high-voltage gate oxide layer 205, oxygen atoms in the oxidizing atmosphere can diffuse into the isolation wall 204 and also oxidize part of the isolation wall, thereby enabling the top of the isolation wall 204 to have an oxide layer, such as... Figure 12 As shown in the dashed box.

[0059] like Figure 13 As shown, after forming the high-voltage gate oxide layer 205, the patterned second hard mask layer 308a is removed.

[0060] like Figure 14 As shown, a gate electrode 310 is formed on the first active region 202, and the gate electrode 310 covers a high-voltage gate oxide layer 205. An exemplary method for forming the gate electrode 310 on the first active region 202 includes: forming a gate material layer on a substrate 200, the gate material layer covering the substrate 200; etching away a portion of the gate material layer on the substrate to form the gate electrode 310. (Reference) Figure 14 As shown, the gate electrode 310 can extend to cover the unetched surface of the isolation structure 307 on the side of the first active region 202, that is, the end of the gate electrode 310 rests on the flat surface of the isolation structure 307. This facilitates the subsequent connection between the contact plug on the gate electrode 310 and the gate electrode 310, and helps to avoid the contact plug on the gate electrode 310 and the isolation wall 204 from being shot. For example, the material of the gate electrode 310 includes, but is not limited to, polysilicon.

[0061] like Figure 15 As shown, a patterned third photoresist layer 311 is formed on the substrate 200. The patterned third photoresist layer 311 covers the isolation wall 204 and exposes the second active region 203 and the gate electrode 310. Under the shielding of the patterned third photoresist layer 311 and the gate electrode 310, source / drain ion implantation is performed to form a source / drain region 206 on top of the second active region 203. It should be noted that under the shielding of the patterned third photoresist layer 311, the doped ions from the source / drain ion implantation will not be implanted into the isolation wall 204 to form an active region, thus avoiding the influence of the isolation wall 204 on the electrical performance of the high-voltage device. The isolation wall 204, extending upwards from the bottom of the active region, is placed between the first active region 202 and the second active region 203, which can also extend the electric field path of the high-voltage device, improve electric field concentration, and facilitate the realization of smaller devices.

[0062] like Figure 16 As shown, the patterned third photoresist layer 311 can be removed using processes such as ashing.

[0063] like Figure 17 As shown, a metal silicide 312 is formed on the top surface of the second active region 203 and the top surface of the gate electrode 310; a first contact plug 313 is formed on the metal silicide of the gate electrode 310, the first contact plug 313 is electrically connected to the gate electrode 310, and a second contact plug 314 is formed on the metal silicide of the second active region 203, the second contact plug 314 is electrically connected to the source / drain region 206 of the second active region 203.

[0064] Specifically, a dielectric layer (not shown) can be formed on the substrate, covering the substrate 200 and the gate electrode 310; part of the dielectric layer and part of the pad oxide layer 201 are etched away, and multiple contact holes are formed in the dielectric layer. A number of contact holes correspond to the positions of the gate electrode 310 and are exposed on the surface of the gate electrode 310, and a number of contact holes correspond to the positions of the second active region 203 (specifically the source / drain region 206) and are exposed on the substrate surface of the second active region 203; metal material is filled into the multiple contact holes, and heat treatment is performed. The metal in the metal material and the silicon in the substrate diffuse into each other to form metal silicide 312. The unreacted metal material that forms metal silicide 312 is removed; conductive material is filled into the contact holes, and a first contact plug 313 is formed in the contact hole on the gate electrode 310, and a second contact plug 314 is formed in the contact hole on the second active region 203.

[0065] For example, the metallic material can be molybdenum (Mo), chromium (Cr), titanium (Ti), zirconium (Zr), or copper (Cu), etc. Conductive materials include, but are not limited to, tungsten (W).

[0066] It should be noted that the reference Figure 17 As shown, due to the presence of the isolation wall 204, when the high-voltage gate oxide layer 205 is formed, it can not only block oxygen from passing through the isolation structure 307 from the first active region 202 to the second active region 203, but also provide oxygen consumption. Because the isolation wall 204 is made of silicon, even if oxygen passes through the isolation structure 307 to the isolation wall 204, it will be consumed by the reaction of the isolation wall 204. Therefore, the isolation wall 204 has a good effect of isolating oxygen from passing through, making it less likely for the substrate of the second active region 203 to be oxidized to form a beak, thus preventing the oxide layer near the isolation structure 307 on the second active region 203 from being too thick. When etching to form the contact hole, a larger area of ​​the substrate surface of the second active region 203 can be effectively exposed, and a relatively uniform metal silicide 312 can be formed at the bottom of the contact hole of the second active region 203, thereby avoiding the problem of high contact plug resistance due to the lack of metal silicide.

[0067] This application also provides a high-voltage device. The high-voltage device can be manufactured using the above-described method for manufacturing high-voltage devices.

[0068] refer to Figure 17As shown, the high-voltage device includes a substrate 200, a pad oxide layer 201, and a high-voltage gate oxide layer 205. The substrate 200 has multiple isolation structures 307, isolation walls 204 defined by the multiple isolation structures 307, and multiple active regions. The multiple active regions include adjacent first active regions 202 and second active regions 203. The isolation walls 204 are located between the first active regions 202 and the second active regions 203. The pad oxide layer 201 covers the top surface of the isolation walls 204 and a portion of the top surface of the second active region 203. The high-voltage gate oxide layer 205 is located on and covers the substrate surface of the first active region 202. When the high-voltage gate oxide layer 205 is formed by consuming the substrate of the first active region 202 using a thermal oxidation process, the isolation walls 204 prevent the second active region 203 from being oxidized.

[0069] In this embodiment, since the high-voltage gate oxide layer 205 is formed by consuming part of the substrate through a thermal oxidation process, the bottom surface of the high-voltage gate oxide layer 205 is lower than the top surface of the substrate of the second active region 203.

[0070] In the high-voltage device and its fabrication method provided by this invention, an isolation wall 204 is formed simultaneously with etching the substrate 200 to form multiple active regions. The multiple active regions include adjacent first active regions 202 and second active regions 203. The isolation wall 204 is located between the first active regions 202 and the second active regions 203. Under the masking of a patterned second hard mask layer 308a, when a thermal oxidation process is used to consume the substrate surface layer of the first active region 202 to form a high-voltage gate oxide layer 205, the isolation wall 204 can prevent oxygen atoms from laterally diffusing into the second active region 203, thus avoiding the... The top of the substrate of the second active region 203 is oxidized to form a bird's beak, which avoids the problem of high contact plug resistance caused by the inability to form metal silicide in the contact plug formation area on the top surface of the second active region 203. This helps to improve the high power consumption of high voltage devices, and does not challenge the limits of thermal oxidation process or implant other unnecessary ions, making the process safe and reliable. In addition, the isolation wall 204 and multiple active regions can use the same mask definition, without the need for additional masks and process steps, which can be compatible with the current process flow and simply and effectively improve the bird's beak problem.

[0071] It should be noted that this instruction manual uses a progressive approach, with later descriptions focusing on the differences from earlier descriptions. Similarities and similarities between different sections can be found by referring to each other.

[0072] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for manufacturing a high-voltage device, characterized in that, include: A substrate is provided on which a pad oxide layer is formed covering the top surface of the substrate; A plurality of isolation structures, an isolation wall defined by the plurality of isolation structures, and a plurality of active regions are formed in the substrate, wherein the plurality of active regions include adjacent first active regions and second active regions, and the isolation wall is located between the first active regions and the second active regions; A patterned second hard mask layer is formed on the substrate, the patterned second hard mask layer covering the second active region, the isolation wall, and the isolation structure between the second active region and the isolation wall, and the patterned second hard mask layer exposes the first active region; as well as, Under the cover of the patterned second hard mask layer and the isolation wall, a high-voltage gate oxide layer is formed by consuming the substrate of the first active region using a thermal oxidation process.

2. The method for manufacturing a high-voltage device as described in claim 1, characterized in that, A method for forming a plurality of isolation structures, an isolation wall, and a plurality of active regions defined by the plurality of isolation structures in the substrate includes: A patterned first hard mask layer is formed on the substrate, and under the masking of the patterned first hard mask layer, the substrate is etched to form a plurality of trenches; and Multiple isolation structures are formed by filling the multiple trenches with isolation material.

3. The method for manufacturing a high-voltage device as described in claim 2, characterized in that, After etching the substrate to form multiple trenches and before filling the multiple trenches with isolation material to form multiple isolation structures, a line oxide layer is formed in the multiple trenches, the line oxide layer covering the inner surface of the trenches.

4. The method for manufacturing a high-voltage device as described in claim 3, characterized in that, The line oxide layer is an oxide layer including a dopant, the dopant including nitrogen.

5. The method for manufacturing a high-voltage device as described in claim 1, characterized in that, The method for forming a patterned second hard mask layer on the substrate includes: A second hard mask material layer covering the substrate is formed on the substrate; A patterned second photoresist layer is formed on the second hard mask material layer. Using the patterned second photoresist layer as a mask, a portion of the second hard mask material layer is etched away to form a patterned second hard mask layer. The patterned second hard mask layer exposes the first active region and a portion of the surface of the isolation structure between the first active region and the isolation wall near the first active region. Under the cover of the patterned second hard mask layer, the pad oxide layer on the first active region is etched away, and the top of the isolation structure near the first active region is removed.

6. The method for manufacturing a high-voltage device as described in claim 5, characterized in that, The method for manufacturing the high-voltage device further includes: Remove the graphical second hard mask layer; A gate electrode is formed on the first active region, and the gate electrode covers the high-voltage gate oxide layer; A patterned third photoresist layer is formed on the substrate, the patterned third photoresist layer covering the isolation wall and exposing the second active region and the gate electrode; and, Ion implantation is performed under the cover of the patterned third photoresist layer and the gate electrode to form a source / drain region on top of the second active region.

7. The method for manufacturing a high-voltage device as described in claim 6, characterized in that, The gate electrode extends to cover the unetched surface of the isolation structure on the side of the first active region.

8. The method for manufacturing a high-voltage device as described in claim 6, characterized in that, Also includes: After forming source and drain regions at the top of the second active region, metal silicide is formed on the top surface of the second active region and the top surface of the gate electrode; as well as, A first contact plug is formed on the metal silicide of the gate electrode, and the first contact plug is electrically connected to the gate electrode. A second contact plug is formed on the metal silicide of the second active region, and the second contact plug is electrically connected to the second active region.

9. The method for manufacturing a high-voltage device as described in claim 1, characterized in that, The distance between the first active area and the second active area is A, and the distance between the isolation wall and the second active area is B, where B is greater than or equal to 1 / 4 of A and less than or equal to 1 / 2 of A.

10. A high-voltage device, characterized in that, include: A substrate in which a plurality of isolation structures are formed, as well as an isolation wall and a plurality of active regions defined by the plurality of isolation structures, wherein the plurality of active regions include adjacent first active regions and second active regions, and the isolation wall is located between the first active regions and the second active regions; A pad oxide layer, the pad oxide layer covering the top surface of the isolation wall and part of the top surface of the substrate of the second active region; as well as, A high-voltage gate oxide layer is located on the substrate surface of the first active region; Specifically, when the high-voltage gate oxide layer is formed by consuming the substrate of the first active region using a thermal oxidation process, the isolation wall is used to prevent the second active region from being oxidized.

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