Monolithic integrated p-GaN HEMT-Si SBD device and preparation method thereof

Abstract

According to the monolithic integrated p-GaN HEMT-Si SBD device and the preparation method thereof provided by the invention, the p-GaN HEMT and the Si SBD are integrated in a monolithic manner, and the reverse conduction loss is remarkably reduced by utilizing the low turn-on voltage of the Si SBD. Through monolithic integration of the p-GaN HEMT and the Si SBD, parasitic inductance and resistance of external connection between devices are reduced. The monolithic integration technology is utilized, the packaging number and external connecting lines are reduced, the size of the power conversion unit is reduced, and the miniaturization requirement of electronic equipment is met; the cost of links such as packaging, testing and assembling is reduced, the overall cost of the product is reduced, and the market competitiveness is improved. According to the invention, connection points between devices are reduced, fault risks caused by connection point problems are avoided, the internal design of a chip is optimized, signal transmission delay and interference are reduced, the stability and reliability of a system are improved, and the circuit adapts to a complex working environment.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, specifically relating to a monolithically integrated p-GaN HEMT-Si SBD device and its fabrication method. Background Technology

[0002] Power electronic systems such as synchronous buck or boost converters have seen significant improvements through the adoption of gallium nitride (GaN)-based power devices. However, these devices inevitably enter a reverse conduction state during operation. For gallium nitride high electron mobility transistors (HEMTs), the presence of the body diode leads to substantial power losses during reverse conduction in circuit applications. Therefore, improving the reverse conduction capability of gallium nitride HEMTs is crucial for further reducing power losses in gallium nitride-based power electronic systems.

[0003] The relevant technologies offer two solutions: one is to set a Schottky source and connect a Schottky barrier diode (SBD) in parallel as a freewheeling diode.

[0004] In the Schottky source configuration, a discrete Schottky contact is used as the integrated freewheeling diode to achieve reverse operation. In the off state, the gate depletes the channel, the Schottky contact is reverse biased, and the channel current is blocked. The electric field is mainly concentrated below the bottom of the Schottky contact on the drain side and below the edges of the two field plates. In the on state, electrons can flow from the source to the drain through the channel, and current can bypass the discrete Schottky contact. A small amount of current can also flow through the channel region below the Schottky contact. In the reverse state, electrons can flow from the drain to the source through the Schottky contact. This reverse current flow is independent of the gate state and can occur even if the channel below the gate is pinched off. If the gate-source voltage is higher than the threshold voltage, additional current can flow from the drain to the source through the channel below the gate. This solution has a reverse conduction voltage of 1.4V, and the reverse conduction loss is still relatively high. Therefore, a new solution to reduce reverse conduction loss needs to be developed.

[0005] In a solution where a Schottky barrier diode (SBD) is connected in parallel as a freewheeling diode, the SBD primarily acts as a freewheeling diode, providing a reverse current path when the HEMT is turned off. Its operation can be divided into the following stages: When the HEMT is on, the SBD is not on; at this time, the HEMT directly carries the drain-to-source current, and the conduction loss in the system is mainly caused by the HEMT's on-resistance. When the HEMT is off, the current between the source and drain cannot stop immediately because the load current is maintained for a period of time due to the inductive effect. At this time, the Schottky diode conducts rapidly due to its low forward voltage drop, providing a low-impedance path that allows the load current to flow. A significant drawback of this solution is the large parasitic inductance and resistance of the discrete cascaded circuit, resulting in a large size, which is unfavorable for high power density applications. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this application provides a monolithically integrated p-GaN HEMT-Si SBD device and its fabrication method. The technical problem to be solved by this application is achieved through the following technical solution: In a first aspect, this application provides a monolithically integrated p-GaN HEMT-Si SBD device, comprising a p-GaN HEMT device and a Si SBD disposed on the right side of the p-GaN HEMT device; the p-GaN HEMT device, from bottom to top, includes a substrate 1, an AlN nucleation layer 4, a GaN buffer layer 5, an AlGaN barrier layer 6, a p-GaN layer 7, and a gate 11; wherein, drain 8 and source 9 are disposed on the left and right sides of the p-GaN layer 7; the Si SBD, from top to bottom, includes a substrate 1 and a Si drift layer 2; an N+ doped region 3 is disposed in the upper left position of the Si drift layer 2, a Si SBD cathode 10 is disposed above the N+ doped region 3, and a Si SBD anode 12 is disposed in the upper right position of the Si drift layer 2; the drain 8 and the Si SBD cathode 10 are interconnected through a first metal layer, and the source 9 is interconnected with the Si SBD anode 12 through a second metal layer; a second passivation layer is disposed between the first metal layer and the second metal layer; and the p-GaN HEMT device and the Si SBD ... A first passivation layer is disposed between the substrate 1 and the first metal layer between the SBDs. Optionally, the N+ doped region 3 is formed by implanting n+ type ions into the Si drift layer 2 at the left position on the Si drift layer 2, with a doping concentration of 5 × 10⁻⁶. 18 -5×10 19 cm -3 .

[0007] Optionally, the source 9 may be made of one or more metals selected from Ni, Pt, Au, or Ti; the drain 8 may be made of Ni, Pt, Au, or Ti, or a combination of multiple metals; and the gate 11 may be made of a combination of Ni and Au.

[0008] Optionally, the Si SBD cathode 10 may be made of Al or a combination of Ti, Al, Ni and Au, and the Si SBD anode 12 may be made of Ni or a combination of Ni and Au.

[0009] Optionally, substrate 1 is a Si substrate, GaN substrate, SiC substrate or sapphire substrate with a thickness of 200nm-800μm.

[0010] Optionally, the material of the AlN nucleation layer 4 is AlN or AlGaN, with a thickness of 10nm-200μm.

[0011] Optionally, the materials of both the GaN buffer layer 5 and the AlGaN barrier layer 6 include GaN, AlN, or AlGaN; the thickness of the GaN buffer layer 5 is 1μm-5μm, and the thickness of the AlGaN barrier layer 6 is 100nm-500nm.

[0012] Optionally, the thickness of the Si drift layer 2 is 3-15 μm, and the doping concentration is 1×10⁻⁶. 16 cm -3 .

[0013] Secondly, this application provides a method for fabricating a monolithically integrated p-GaN HEMT / Si SBD device, wherein the method for fabricating the monolithically integrated p-GaN HEMT / Si SBD device as described in the first aspect includes: S100, select substrate 1 and prepare an n-Si epitaxial layer on it; S200, etch away the n-Si epitaxial layer in the p-GaN HEMT region, and retain the n-Si epitaxial layer in the Si SBD region as Si drift layer 2; S300, n+ type ions are injected into the Si drift layer 2 at the upper left position to form an N+ doped region 3; S400, an AlN nucleation layer 4, a GaN buffer layer 5, an AlGaN barrier layer 6 and a p-GaN are sequentially generated on one side where the n-Si epitaxial layer is etched away, and the p-GaN on both sides is etched away to obtain a p-GaN layer 7. S500, a Si SBD cathode 10 is fabricated on the N+ doped region 3, and a drain 8 and a source 9 are fabricated on both sides of the p-GaN layer 7; S600, a gate 11 is fabricated on the p-GaN layer 7 and a Si SBD anode 12 is fabricated on the upper right side of the Si drift layer 2; S700, deposit a first passivation layer on the device after the gate 11 and Si SBD anode 12 have been fabricated to cover the device surface; S800, photolithography and etching are performed on the first passivation layer to form a contact hole between the drain 8 and the cathode 10, and the drain 8 and the cathode 10 are connected through the first metal layer; In S900, a second passivation layer is deposited on the first metal layer, and photolithography and etching are performed on the second passivation layer to form contact holes for the source 9 and the Si SBD anode 12; the source 9 and the Si SBD anode 12 are connected through the second metal layer to obtain a monolithically integrated p-GaN HEMT / Si SBD device.

[0014] Optional, the S300 includes: An N+ doped region 3 was formed by implanting n+ ions into the upper left position of the Si drift layer 2 using ion implantation technology. The N+ doped region 3 was then annealed to repair lattice damage and activate the doped ions. The doping concentration of the n+ ions was 5 × 10⁻⁶. 18 -5×10 19 cm -3 .

[0015] Beneficial effects: 1. This application integrates a p-GaN HEMT and a Si SBD onto a single chip without external circuit connections, optimizing the parasitic inductance and resistance present in external circuits and reducing parasitic parameters. Compared to the cascading of discrete devices, this better leverages the switching speed and power conversion efficiency of GaN devices.

[0016] 2. This application integrates p-GaN HEMT and Si SBD on the same chip through monolithic integration, eliminating the need for multiple packages of discrete devices and a large number of external interconnect lines, thereby reducing size and cost.

[0017] 3. The electrical connections within the integrated chip, such as the interconnect metal layer, ensure stable connections, reducing the number of connection points between discrete components, lowering the risk of system failure due to poor connections, solder joint failures, and other factors, and increasing reliability.

[0018] 4. When applied in a circuit, this application results in lower reverse conduction losses, leading to lower circuit losses and less heat generation, thus optimizing thermal management. Under the same losses, this application offers greater current capability.

[0019] 5. This application uses Si SBD as the reverse conduction path. Since the turn-on voltage of Si SBD is only 0.7V, which is significantly lower than the reverse conduction voltage drop of the prior art, the power loss during reverse conduction can be greatly reduced.

[0020] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of a monolithically integrated p-GaN HEMT-Si SBD device provided in this application; Figure 2 This is a schematic flowchart of a method for fabricating a monolithically integrated p-GaN HEMT-Si SBD device provided in this application; Figure 3 This is a schematic diagram illustrating the fabrication process of a monolithically integrated p-GaN HEMT-Si SBD device provided in this application; Figure 4 This is a buck circuit diagram of the analog parallel diode device provided in this application; Figure 5 This is a diagram of the buck circuit structure of the device simulating non-parallel diodes provided in this application; Figure 6 This application provides the corresponding Figure 4 and Figure 5 A schematic diagram of the simulation waveform. Detailed Implementation

[0022] The present application will be described in further detail below with reference to specific embodiments, but the implementation of the present application is not limited thereto.

[0023] Firstly, such as Figure 1 As shown, this application provides a monolithically integrated p-GaN HEMT-Si SBD device, including a p-GaN HEMT device and a Si SBD disposed on the right side of the p-GaN HEMT device. The p-GaN HEMT device, from bottom to top, includes a substrate 1, an AlN nucleation layer 4, a GaN buffer layer 5, an AlGaN barrier layer 6, a p-GaN layer 7, and a gate 11. Drain 8 and source 9 are disposed on the left and right sides of the p-GaN layer 7. The Si SBD, from top to bottom, includes a substrate 1 and a Si drift layer 2. An N+ doped region 3 is disposed in the upper left position of the Si drift layer 2, a Si SBD cathode 10 is disposed above the N+ doped region 3, and a Si SBD anode 12 is disposed in the upper right position of the Si drift layer 2. The drain 8 and the Si SBD cathode 10 are interconnected through a first metal layer, and the source 9 is interconnected with the Si SBD anode 12 through a second metal layer. A second passivation layer is disposed between the first and second metal layers. A first passivation layer is disposed between the HEMT device and the SiSBD, from the substrate 1 to the first metal layer.

[0024] In bridge topologies such as Buck and LLC, reverse conduction of GaN HEMTs typically occurs during the dead time, i.e., the gap between the turn-off of one device and the turn-off of the next. During this time, the reverse voltage has not yet fully decreased, while the reverse current has already begun to rise. Energy dissipation during this period is a significant component of reverse conduction losses. Generally, there is a voltage drop of approximately 2V during reverse conduction, resulting in substantial reverse conduction losses. This application employs a Si SBD as the reverse conduction path. Due to the low on-resistance of the Si SBD, current preferentially flows through it. Furthermore, since the turn-on voltage of the Si SBD is only 0.7V, it significantly reduces power losses during reverse conduction.

[0025] In addition, the same structure can be used in this application, but the materials can be monolithically integrated using SiC MOS and SiC SBD or using GaN HEMT and GaN SBD.

[0026] In one embodiment of this application, the N+ doped region 3 is formed by implanting n+ type ions into the Si drift layer 2 at the left position on the Si drift layer 2, with a doping concentration of 5 × 10⁻⁶. 18 -5×10 19 cm -3 .

[0027] In one embodiment of this application, the source electrode 9 is made of one or more metals selected from Ni, Pt, Au, or Ti; the drain electrode 8 is made of Ni, Pt, Au, or Ti, or a combination of multiple metals; and the gate electrode 11 is made of a combination of Ni and Au.

[0028] In one embodiment of this application, the Si SBD cathode 10 is made of Al or a combination of Ti, Al, Ni and Au, and the Si SBD anode 12 is made of Ni or a combination of Ni and Au.

[0029] In one embodiment of this application, substrate 1 is a Si substrate, GaN substrate, SiC substrate or sapphire substrate, with a thickness of 200nm-800μm.

[0030] In one embodiment of this application, the material of the AlN nucleation layer 4 is AlN or AlGaN, and the thickness is 10nm-200μm.

[0031] In one embodiment of this application, the materials of both the GaN buffer layer 5 and the AlGaN barrier layer 6 include GaN, AlN, or AlGaN; the thickness of the GaN buffer layer 5 is 1μm-5μm, and the thickness of the AlGaN barrier layer 6 is 100nm-500nm.

[0032] All thicknesses mentioned in this application refer to the thickness in the direction perpendicular to the plane of the epitaxial structure.

[0033] In one embodiment of this application, the thickness of the Si drift layer 2 is 3-15 μm, and the doping concentration is 1×10⁻⁶. 16 cm -3 .

[0034] Secondly, combining Figure 2 and Figure 3 This application provides a method for fabricating a monolithically integrated p-GaN HEMT / Si SBD device, the method comprising: S100, select substrate 1 and prepare an n-Si epitaxial layer on it; The substrate thickness in this application is 200nm-800μm.

[0035] S200, etch away the n-Si epitaxial layer in the p-GaN HEMT region, and retain the n-Si epitaxial layer in the Si SBD region as Si drift layer 2; This application utilizes RIE or ICP technology to etch the n-Si epitaxial layer region, retaining the Si SBD region as the Si drift layer 2.

[0036] S300, n+ type ions are injected into the Si drift layer 2 at the upper left position to form an N+ doped region 3; In this application, n+ type ions are implanted into the upper left position of the Si drift layer 2 using ion implantation technology to form an N+ doped region 3. The N+ doped region 3 is then annealed to repair lattice damage and activate the doped ions. The doping concentration of the n+ type ions is 5 × 10⁻⁶. 18 -5×10 19 cm -3 .

[0037] S400, an AlN nucleation layer 4, a GaN buffer layer 5, an AlGaN barrier layer 6 and a p-GaN are sequentially generated on one side where the n-Si epitaxial layer is etched away, and the p-GaN on both sides is etched away to obtain a p-GaN layer 7. On the side where the n-Si epitaxial layer has been etched away, an AlN nucleation layer, a GaN buffer layer, a barrier layer, and a p-GaN layer are grown sequentially. The AlN nucleation layer can be made of GaN, AlN, or AlGaN, with a thickness of 30 nm to 5 μm; the buffer layer has a thickness of 1 μm to 5 μm; the AlGaN barrier layer can be made of AlGaN or AlN, with a thickness of 100 to 500 nm; and the p-GaN layer has a thickness of 60 nm.

[0038] The specific method involves depositing a mask layer on the side where the n-Si epitaxial layer has been etched away, using photolithography to expose the growth region, removing the mask layer in the growth region, and then sequentially growing an AlN nucleation layer, a GaN buffer layer, a barrier layer, and a p-GaN layer using MOCVD.

[0039] Cleaning the epitaxial wafer involves removing impurities, dust, oxides, and organic matter. The wafer is first ultrasonically cleaned in acetone for 2 minutes, then heated in a 60°C stripping solution water bath for approximately 10 minutes, followed by cleaning in acetone for 3 minutes. It is then sequentially cleaned in ethanol and ultrapure water for 2 minutes each, and finally dried with nitrogen (N2). Photoresist is coated onto the p-GaN layer. Using photolithography, the p-GaN regions to be etched are exposed on the photoresist. An ICP etching machine is then used to etch the p-GaN, removing the photoresist and cleaning the wafer.

[0040] S500, a Si SBD cathode 10 is fabricated on the N+ doped region 3, and a drain 8 and a source 9 are fabricated on both sides of the p-GaN layer 7; This application describes the fabrication of Si SBD cathodes and HEMT source / drain electrodes. First, the Si SBD cathode is fabricated, with the metal being an Al or Ti / Al / Ni / Au metal stack. Photolithography is performed, followed by exposure and development to leave ohmic contact windows. Then, electron beam evaporation is used to deposit ohmic contact metal on the resulting n+ doped region. After evaporation, the metal is stripped off. At this point, the cathode and semiconductor have Schottky contacts, requiring annealing to achieve ohmic contacts. Next, the HEMT source / drain electrodes are fabricated, with the metal being a combination of Ni, Pt, Au, or Ti metals or a Ni / Pt / Au / Ti metal stack. Photolithography is performed, followed by exposure and development to leave ohmic contact windows. Then, electron beam evaporation is used to deposit metal. After evaporation, the metal is stripped off. At this point, the source / drain electrodes and semiconductor have Schottky contacts, requiring annealing to achieve ohmic contacts.

[0041] S600, a gate 11 is fabricated on the p-GaN layer 7 and a Si SBD anode 12 is fabricated on the upper right side of the Si drift layer 2; This application describes the fabrication of the SBD anode and HEMT gate. The SBD anode metal is a combination of Ni or Ni / Au metal layers, and the HEMT gate metal is Ni / Au. First, photolithography is performed, followed by exposure and development to leave the Schottky contact window. Then, electron beam evaporation is used to deposit the metal, and after evaporation, the metal is stripped away.

[0042] S700, deposit a first passivation layer on the device after the gate 11 and Si SBD anode 12 have been fabricated to cover the device surface; This application employs plasma chemical vapor deposition (PECVD) to deposit a 50 nm SiNx, SiO2, Al2O3, or AlN passivation layer 2 on the surfaces of the barrier layer, source (S), drain (D), gate (G), cathode, and anode. The nitrogen (N) source can be provided by ammonia (NH3), and the silicon (Si) source can be provided by silane (SiH4), thereby effectively suppressing current collapse.

[0043] S800, photolithography and etching are performed on the first passivation layer to form a contact hole between the drain 8 and the Si SBD cathode 10, and the drain 8 and the Si SBD cathode 10 are connected through the first metal layer. In this application, photolithography and etching are performed on the passivation layers above the drain (D) and cathode respectively to form the drain and cathode contact holes leading electrodes, thus completing the metal interconnection between the drain and Si SBD of the GaN HEMT.

[0044] In S900, a second passivation layer is deposited on the first metal layer, and photolithography and etching are performed on the second passivation layer to form contact holes for the source 9 and the Si SBD anode 12; the source 9 and the Si SBD anode 12 are connected through the second metal layer to obtain a monolithically integrated p-GaN HEMT / Si SBD device.

[0045] In this application, the device after S800 is placed in a PECVD reaction chamber for passivation layer deposition. Then, photolithography and etching are performed on the passivation layers above the source (S) and anode respectively to form source and anode contact holes and lead-out electrodes, completing the metal interconnection between the source of GaNHEMT and the anode of Si SBD.

[0046] This application integrates a p-GaN HEMT and a Si SBD on a single chip, significantly reducing reverse conduction losses by leveraging the low turn-on voltage of the Si SBD. Monolithic integration of the p-GaN HEMT and Si SBD also reduces parasitic inductance and resistance of external connections between devices. Utilizing monolithic integration technology reduces the number of packages and external interconnects, shrinking the power conversion unit size to meet the miniaturization requirements of electronic devices; it also reduces costs in packaging, testing, and assembly, lowering overall product costs and enhancing market competitiveness. Furthermore, this application reduces the number of interconnections between devices, avoiding failure risks caused by interconnection issues; it optimizes the internal chip design, enabling better collaboration between the p-GaN HEMT and Si SBD, reducing signal transmission delay and interference, improving system stability and reliability, and adapting to complex operating environments.

[0047] During circuit operation, a short period of time must be allowed between the switching of the upper and lower transistors to ensure both transistors are simultaneously off during the switching process. A buck circuit built using LTspice is used to simulate the parallel diode device described in this application, such as... Figure 4The conventional device shown is the one without a parallel diode, such as Figure 5 As shown. Figure 6 for Figure 4 and Figure 5 The corresponding simulation waveform, from Figure 6 As can be seen, connecting diodes in parallel significantly reduces the reverse conduction voltage drop from 2V to 0.7V. According to the formula for calculating reverse conduction loss... Figure 6 The reverse conduction loss in the upper middle diagram is 0.16W. Figure 6 The reverse conduction loss in the lower figure is 0.45W. This application can significantly reduce the reverse conduction loss.

[0048] It is worth noting that the terms "first" and "second" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0049] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A monolithically integrated p-GaN HEMT-Si SBD device, characterized in that, The device includes a p-GaN HEMT device and a Si SBD disposed on the right side of the p-GaN HEMT device. The p-GaN HEMT device includes, from bottom to top, a substrate (1), an AlN nucleation layer (4), a GaN buffer layer (5), an AlGaN barrier layer (6), a p-GaN layer (7), and a gate (11). Drain (8) and source (9) are disposed on the left and right sides of the p-GaN layer (7). The Si SBD includes, from top to bottom, a substrate (1) and a Si drift layer (2). An N+ doped region (3) is disposed in the upper left position of the Si drift layer (2), a Si SBD cathode (10) is disposed above the N+ doped region (3), and a Si SBD anode (12) is disposed in the upper right position of the Si drift layer (2). The drain (8) and the Si SBD cathode (10) are interconnected through a first metal layer, and the source (9) is interconnected with the Si SBD cathode (10) through a second metal layer. The SBD anode (12) is interconnected, a second passivation layer is disposed between the first metal layer and the second metal layer, and a first passivation layer is disposed between the p-GaN HEMT device and the Si SBD from the substrate (1) to the first metal layer.

2. The monolithically integrated p-GaN HEMT-Si SBD device according to claim 1, characterized in that, The N+ doped region (3) is formed by implanting n+ type ions into the Si drift layer (2) from the left side of the Si drift layer (2), with a doping concentration of 5 × 10⁻⁶. 18 -5×10 19 cm -3 .

3. The monolithically integrated p-GaN HEMT-Si SBD device according to claim 1, characterized in that, The source electrode (9) is made of one or more metals selected from Ni, Pt, Au or Ti; the drain electrode (8) is made of Ni, Pt, Au or Ti or a combination of multiple metals; and the gate electrode (11) is made of a combination of Ni and Au.

4. The monolithically integrated p-GaN HEMT-Si SBD device according to claim 1, characterized in that, The Si SBD cathode (10) uses Al or a combination of Ti, Al, Ni and Au metals, and the Si SBD anode (12) uses Ni or a combination of Ni and Au metals.

5. The monolithically integrated p-GaN HEMT-Si SBD device according to claim 1, characterized in that, The substrate (1) is a Si substrate, GaN substrate, SiC substrate or sapphire substrate, with a thickness of 200nm-800μm.

6. The monolithically integrated p-GaN HEMT-Si SBD device according to claim 1, characterized in that, The material of the AlN nucleation layer (4) is AlN or AlGaN, and the thickness is 10nm-200μm.

7. The monolithically integrated p-GaN HEMT-Si SBD device according to claim 1, characterized in that, The materials of the GaN buffer layer (5) and the AlGaN barrier layer (6) both include GaN, AlN or AlGaN; the thickness of the GaN buffer layer (5) is 1μm-5μm, and the thickness of the AlGaN barrier layer (6) is 100nm-500nm.

8. The monolithically integrated p-GaN HEMT-Si SBD device according to claim 1, characterized in that, The Si drift layer (2) has a thickness of 3-15 μm and a doping concentration of 1×10⁻⁶. 16 cm -3 .

9. A method for fabricating a monolithically integrated p-GaN HEMT / Si SBD device, characterized in that, The method for fabricating a monolithically integrated p-GaN HEMT / Si SBD device as described in any one of claims 1 to 8 comprises: S100, select a substrate (1) and prepare an n-Si epitaxial layer on it; S200, etch away the n-Si epitaxial layer in the p-GaN HEMT region, and retain the n-Si epitaxial layer in the Si SBD region as the Si drift layer (2). S300, n+ type ions are injected into the Si drift layer (2) at the upper left position to form an N+ doped region (3). S400, an AlN nucleation layer (4), a GaN buffer layer (5), an AlGaN barrier layer (6) and p-GaN are sequentially generated on the side where the n-Si epitaxial layer is etched away, and the p-GaN on both sides is etched away to obtain a p-GaN layer (7). S500, a Si SBD cathode (10) is prepared on the N+ doped region (3), and a drain (8) and a source (9) are prepared on both sides of the p-GaN layer (7). S600, a gate (11) is fabricated on the p-GaN layer (7) and a Si SBD anode (12) is fabricated on the upper right side of the Si drift layer (2). S700, a first passivation layer is deposited on the device after the gate (11) and Si SBD anode (12) have been fabricated to cover the device surface; S800, photolithography and etching are performed on the first passivation layer to form a contact hole between the drain (8) and the cathode (10), and the drain (8) and the cathode (10) are connected through the first metal layer. S900, a second passivation layer is deposited on the first metal layer, and photolithography and etching are performed on the second passivation layer to form contact holes for the source (9) and the Si SBD anode (12); the source (9) and the Si SBD anode (12) are connected through the second metal layer to obtain a monolithically integrated p-GaN HEMT / Si SBD device.

10. The method for fabricating a monolithically integrated p-GaN HEMT / Si SBD device according to claim 9, characterized in that, The S300 includes: An N+ doped region (3) is formed by implanting n+ type ions into the upper left position of the Si drift layer (2) using ion implantation technology. The N+ doped region (3) is then annealed to repair lattice damage and activate the doped ions. The doping concentration of the n+ type ions is 5 × 10⁻⁶. 18 -5×10 19 cm -3 .

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