Semiconductor device and design method thereof

Abstract

The embodiment of the invention relates to a semiconductor device and a design method thereof. The purpose of the present invention is to suppress an increase in development cost and development cycle without causing a change in characteristics of paired elements. In a plan view, a plurality of MOS cells 3Q are arranged adjacent to each other on a main surface of a semiconductor substrate, each of the plurality of MOS cells being composed of at least one MOSFET and having the same structure. A multilayer wiring layer is formed over the plurality of MOS cells 3Q. A wiring M8 is formed in the uppermost wiring layer among the plurality of wiring layers. Each of the plurality of MOS cells (3Q) includes a MOS cell (1Q) and a MOS cell (2Q) constituting a part of a differential circuit as paired elements. In plan view, the coverage rate of the MOS cell 1Q covered by the wiring M8 is the same as the coverage rate of the MOS cell 2Q covered by the wiring M8.

Description

[0001] Cross-reference to related applications

[0002] The entire disclosure of Japanese Patent Application No. 2024-156819, filed on September 10, 2024, including the specification, drawings and abstract, is incorporated herein by reference. Technical Field

[0003] This invention relates to a semiconductor device and a design method thereof, and more particularly to a semiconductor device comprising a pair of elements forming part of a differential circuit and a design method thereof. Background Technology

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2014-138104

[0006] Semiconductor devices are equipped with terminals for external connection to connect to other semiconductor devices or wiring substrates. For example, Patent Document 1 discloses a technique for electrically connecting the pad electrodes of a semiconductor chip to a package substrate and connecting the solder balls of the package substrate to the wiring of a printed circuit board. Summary of the Invention

[0007] The topmost wiring layer of a semiconductor chip has multiple wirings, some of which are used as pad electrodes to connect bump electrodes or wiring. Typically, the topmost wiring layer is the thickest among the wirings formed on a semiconductor chip.

[0008] When MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are formed beneath such thick wiring, stress from these wirings is known to cause variations in MOSFET characteristics. For example, stress from the wiring in the topmost layer can cause a variation of approximately ±5% in the MOSFET's drain saturation current (IDsat).

[0009] Semiconductor chips are equipped with analog IP (intellectual property) as functional blocks of circuits with specific functions. The paired components used in a portion of the differential circuit of the analog IP consist of a pair of MOSFETs with identical structures to achieve the same characteristics. Therefore, if a characteristic change occurs in one MOSFET, the sensitivity of the differential circuit will change significantly. To avoid this characteristic change, it is effective to arrange the wiring of the topmost wiring layer so that it does not cover the paired components.

[0010] Typically, upper-level routing (such as the topmost routing layer) is placed later in the design process. Furthermore, the routing layout in the topmost routing layer may vary depending on the package specifications of each product. If a layout change results in paired components being covered by routing on the topmost layer, it becomes necessary to move the paired components, requiring a redesign of the floor plan around the analog IP. This leads to increased development costs and time. Additionally, as processes become smaller, analog IP standards are becoming more stringent, making it increasingly difficult to meet these standards.

[0011] Therefore, there is a need for technologies that can mitigate increases in development costs and time without causing changes in the characteristics of paired components. Furthermore, even with advancements in process miniaturization, there is a need for technologies that more easily meet the standards of analog IP. Other issues and novel features will become apparent from the description and accompanying drawings in this specification.

[0012] A brief overview of the typical embodiments disclosed in this application is as follows.

[0013] A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface; a plurality of MOS cells arranged adjacent to each other on the first surface of the semiconductor substrate, each of the plurality of MOS cells comprising at least one MOSFET and having the same structure; a multilayer wiring layer formed above the plurality of MOS cells; and a first wiring layer formed on the uppermost wiring layer of the multilayer wiring layer. Each of the plurality of MOS cells includes a first MOS cell and a second MOS cell as a pair of elements forming part of a differential circuit, and in a plan view, the coverage of the first MOS cell covered by the first wiring layer is the same as the coverage of the second MOS cell covered by the first wiring layer.

[0014] A design method for a semiconductor device according to one embodiment includes: (a) fabricating a plurality of MOS cells arranged adjacent to each other on a first surface of a semiconductor substrate, each of the plurality of MOS cells comprising at least one MOSFET and having the same structure; (b) fabricating a first wiring, the first wiring being formed on the uppermost wiring layer of a multilayer wiring layer formed above the plurality of MOS cells; and (c) selecting a first MOS cell and a second MOS cell from the plurality of MOS cells as a pair of elements forming part of a differential circuit, such that the coverage of the first MOS cell covered by the first wiring in a plan view is the same as the coverage of the second MOS cell covered by the first wiring in a plan view.

[0015] According to one embodiment, the increase in development costs and time can be suppressed without causing changes in the characteristics of paired components. Attached Figure Description

[0016] Figure 1 This is a plan view of a semiconductor device according to the first embodiment.

[0017] Figure 2 This shows an equivalent circuit diagram of an analog IP including differential circuitry according to the first embodiment.

[0018] Figure 3 This is a plan view showing the layout of the pad electrodes and paired components according to the first embodiment.

[0019] Figure 4 This is a plan view showing the state before and after the design change of the pad electrodes according to the first embodiment.

[0020] Figure 5 This is a plan view showing the layout of the pad electrodes and paired components in the inspection example.

[0021] Figure 6 This is a flowchart illustrating a design method for a semiconductor device according to a first embodiment.

[0022] Figure 7 This is a plan view showing the layout of the pad electrodes and paired components according to the first embodiment.

[0023] Figure 8 This is a plan view used to explain the number of MOS cells that can be arranged according to the first embodiment.

[0024] Figure 9 This is a cross-sectional view of a semiconductor device according to the first embodiment.

[0025] Figure 10 This is a cross-sectional view showing a plurality of MOS cells according to the first embodiment.

[0026] Figure 11 This is a cross-sectional view showing a plurality of MOS cells according to the first embodiment.

[0027] Figure 12 This is a perspective view showing an example of the structure of the MOSFET in the first modified example.

[0028] Figure 13 This is a plan view showing the state of the pad electrodes before and after the design change in the second modified example.

[0029] Figure 14 This shows an equivalent circuit diagram of an analog IP including differential circuitry according to the second embodiment.

[0030] Figure 15 This is a plan view showing the layout of the pad electrodes and paired components according to the second embodiment.

[0031] Figure 16 This is a plan view showing the layout of the pad electrodes and paired components according to the second embodiment.

[0032] Figure 17 This is a plan view showing a plurality of MOS cells according to the second embodiment.

[0033] Figure 18 This is a cross-sectional view of a semiconductor device according to the second embodiment.

[0034] Figure 19 This shows an equivalent circuit diagram of an analog IP including differential circuitry according to a third embodiment.

[0035] Figure 20 This is a plan view showing the layout of the pad electrodes and paired components according to the third embodiment.

[0036] Figure 21 This is a plan view showing the layout of the pad electrodes and paired components according to the third embodiment.

[0037] Figure 22 This is a plan view showing a MOS cell that is a pair of elements according to the third embodiment.

[0038] Figure 23 This is a plan view showing a MOS cell that is a pair of elements according to the third embodiment.

[0039] Figure 24 This is a plan view showing an unused MOS cell according to the third embodiment.

[0040] Figure 25 This is a cross-sectional view of a semiconductor device according to a third embodiment.

[0041] Figure 26 This is a plan view showing the layout of the pad electrodes and paired components according to the fourth embodiment. Detailed Implementation

[0042] In the following description, embodiments will be illustrated with reference to the accompanying drawings. Throughout the drawings used to explain the embodiments, components with the same function are represented by the same reference numerals, and repeated descriptions are omitted. In the following embodiments, descriptions of the same or similar parts are generally not repeated unless specifically necessary.

[0043] In this application, the described X, Y, and Z directions intersect and are orthogonal to each other. In this application, the Z direction is described as the vertical direction, depth direction, or thickness direction of the structure. The expression "plan view" or "plan view" as used in this application refers to a plane formed by the X and Y directions viewed from the Z direction. The expression "plan view" or "plan view" also refers to a view of the main surface of the semiconductor substrate SUB from above.

[0044] (First Embodiment)

[0045] <Planar Layout of Semiconductor Devices>

[0046] The following will refer to Figures 1 to 9 The semiconductor device 100 (semiconductor chip) according to the first embodiment is described.

[0047] Figure 1 This is a plan view of the semiconductor device 100 viewed from above. (As shown...) Figure 1 As shown, the semiconductor device 100 includes a plurality of pad electrodes (PADs) formed in the uppermost wiring layer. The plurality of pad electrodes (PADs) are arranged in an interleaved configuration. Figure 1 The number of pad electrodes (PADs) shown is an example and can be changed appropriately. By connecting external connection components such as bump electrodes to the pad electrodes (PADs), the semiconductor device 100 can be electrically connected to other semiconductor chips or wiring substrates.

[0048] like Figure 9 As shown, the semiconductor device 100 includes a multilayer wiring layer consisting of wiring layers WL1 to WL8, with wiring layer WL8 forming the uppermost wiring layer. A plurality of wirings M8 are formed in wiring layer WL8. Pad electrodes PAD are part of the plurality of wirings M8.

[0049] like Figure 1 As shown, the semiconductor device 100 includes an analog IP10 as a circuit functional block with a specific function.

[0050] Figure 2 A BGR (bandgap reference) circuit, as a differential circuit included in analog IP10 according to a first embodiment, is shown. MOS cells 1Q and 2Q form part of the differential circuit as paired elements.

[0051] In the first embodiment, MOS unit 1Q and MOS unit 2Q are each composed of a single n-type MOSFET.

[0052] Figure 3 Is as Figure 1The enlarged-scale simulation plan view within IP10 shows the positional relationship between multiple pad electrodes (PADs) and MOS cells 1Q and 2Q. To avoid characteristic variations as paired components, MOS cells 1Q and 2Q are arranged such that the coverage of MOS cell 1Q covered by the pad electrodes (PADs) is the same as the coverage of MOS cell 2Q covered by the pad electrodes (PADs).

[0053] Here, MOS cells 1Q and 2Q are not covered by the pad electrode PAD (wiring M8). However, if the coverage of MOS cell 1Q is the same as that of MOS cell 2Q, then wiring M8 can cover all MOS cells 1Q and all MOS cells 2Q, or wiring M8 can cover part of MOS cells 1Q and part of MOS cells 2Q.

[0054] like Figure 4 As shown, for example, due to specification variations within the package of each product, the pitch between each pad electrode (the distance between each wiring M8) may change. In this case, since the arrangement of MOS cells 1Q and 2Q remains unchanged, misalignment occurs in the positional relationship between the pad electrodes and MOS cells 1Q and 2Q. Figure 4 In this process, the pitch narrows uniformly relative to the reference pad electrode PADa, and the further away from the reference pad electrode PADa, the greater the movement of the pad electrode PAD. That is, the further away from the reference pad electrode PADa, the greater the misalignment between the pad electrode PAD and the positional relationship between the MOS cells 1Q and 2Q.

[0055] For example, when a pad electrode PAD that is one pitch away from the reference pad electrode PADa in the X or Y direction moves 5 μm toward the reference pad electrode PADa, a pad electrode PAD that is two pitches away from the reference pad electrode PADa in the X or Y direction moves 10 μm toward the reference pad electrode PADa.

[0056] As a result, the coverage of MOS cell 1Q and MOS cell 2Q may change, and for example, the coverage of MOS cell 1Q and MOS cell 2Q may become different values. As a countermeasure in this case, the design method of the inspection example and the design method of the first embodiment will be described.

[0057] <Examine the design methodology of the example>

[0058] In the inspection example, such as Figure 5 As shown in the “Initial Design”, the pitch between each wiring M8 is designed so that MOS cells 1Q and 2Q are not covered by the pad electrode PAD (wiring M8), and the layout of multiple wiring M8 is performed.

[0059] Next, as Figure 5As shown in the "Design Changes" section, the pitch between each wiring M8 can be changed. Therefore, portions of MOS cell 1Q and MOS cell 2Q may be unevenly covered by the pad electrodes (PADs). That is, the coverage of MOS cell 1Q may differ from that of MOS cell 2Q.

[0060] In this case, such as Figure 5 As shown in the "Moving Pairs of Components" section, the arrangement of MOS cells 1Q and 2Q is changed to avoid changes in characteristics as paired components. However, this requires a complete redesign of the floor plan around the simulation IP10, increasing development costs and time. For example, although only paired components (MOS cells 1Q and 2Q) are illustrated here, other components used in the simulation IP10 are also densely packed around them. Since the arrangement of these other components also needs to be changed, significant development costs and time are required.

[0061] <Design Method of the First Embodiment>

[0062] Will use Figure 6 and 7 A design method for the semiconductor device 100 in the first embodiment is described. The design method for the semiconductor device 100 includes... Figure 6 Steps S1 to S5 are shown.

[0063] First, in step S1, as Figure 7 As shown in the “Initial Design” diagram, a plurality of MOS cells 3Q are fabricated and arranged adjacent to each other on the main surface of a semiconductor substrate in a planar view. Each of the plurality of MOS cells 3Q consists of at least one MOSFET and has the same structure. In a first embodiment, each of the plurality of MOS cells 3Q consists of a single n-type MOSFET.

[0064] Next, in step S2, among the multilayer wiring layers formed above the multiple MOS cells 3Q, a plurality of wirings M8 are formed in the uppermost wiring layer (wiring layer WL8). Here, among the plurality of wirings M8, wirings M8 used as pad electrodes PADs are formed. Then, the pitch between each wiring M8 is designed, and the layout of the plurality of wirings M8 is performed.

[0065] Next, in step S3, MOS cells 1Q and 2Q are selected from the plurality of MOS cells 3Q to form a differential circuit as paired elements. Here, MOS cells 1Q and 2Q are selected such that the coverage of MOS cell 1Q covered by wiring M8 in the plan view is the same as the coverage of MOS cell 2Q covered by wiring M8 in the plan view.

[0066] Therefore, in the first embodiment, by pre-fabricating multiple MOS cells 3Q as candidates for paired elements (MOS cells 1Q, 2Q), MOS cells 1Q and 2Q with the same coverage can be selected regardless of the layout of the multiple wirings M8. Thus, the characteristic variation of the paired elements does not occur. Moreover, unlike the inspection example, it is not necessary to avoid MOS cells 1Q and 2Q when laying out the wirings M8, thereby increasing the layout freedom of the wirings M8.

[0067] Note that among the multiple MOS cells 3Q, excluding MOS cells 1Q and 2Q, the other MOS cells 3Q are not used for differential circuits or other circuits. For example, the gate, source, and drain regions of the n-type MOSFETs in the unselected MOS cells 3Q are connected to ground potential.

[0068] Then, as Figure 7 As shown in the "Design Change" section, the pitch between each wiring M8 can be changed. In step S4, if the pitch between each wiring M8 changes (yes), then MOS cells 1Q and 2Q are reselected in step S5. If the pitch between each wiring M8 does not change (no), then step S5 is unnecessary.

[0069] In step S5, as Figure 7 As shown in the “Reselect Pairs” section, MOS cells 1Q and 2Q are reselected from multiple MOS cells 3Q so that the coverage of MOS cells 1Q and 2Q is the same.

[0070] Therefore, in the first embodiment, even if the pitch between each wiring M8 changes, MOS cells 1Q and 2Q can be reselected, thus preventing changes in the characteristics of paired components. Furthermore, since it is not necessary to change the arrangement of other components used in the analog IP10, increases in development costs and time can be suppressed.

[0071] Note that even if the pitch between each wiring M8 changes in step S4, step S5 can be skipped if the coverage of MOS cell 1Q is the same as that of MOS cell 2Q. That is, if the coverage of MOS cell 1Q is different from that of MOS cell 2Q, then MOS cells 1Q and 2Q are reselected in step S5.

[0072] Moreover, in the first embodiment, in order to select MOS cells 1Q and 2Q from the plurality of MOS cells 3Q, a control circuit 20 and a register 21 electrically connected to the plurality of MOS cells 3Q are prepared in the stage of step S1.

[0073] Once the layout of the wiring M8 is determined, the coverage rate of each MOS unit 3Q among the plurality of MOS units 3Q is determined. The register 21 stores information regarding the coverage rate of each MOS unit 3Q among the plurality of MOS units 3Q covered by the wiring M8 in the planar view. In steps S3 and S5, the control circuit 20 automatically selects the MOS units 1Q and 2Q having the same coverage rate covered by the wiring M8 in the planar view based on the information in the register 21 from among the plurality of MOS units 3Q.

[0074] Using Figure 8 , the number of MOS units that can be arranged between each pad electrode PAD will be explained. The number of MOS units that can be arranged varies depending on the distance from the reference pad electrode PADa.

[0075] Let the size of one MOS unit 1Q, 2Q, 3Q be A1. Let N be the number of spare MOS units 3Q other than the MOS units 1Q and 2Q. The area B1 for arranging the plurality of spare MOS units 3Q can be expressed as "B1 = A1 × N". Further, let D1 be the offset between each pad electrode PAD when the pitch changes, and let P be the number of pad electrodes PAD from the reference pad electrode PADa to the farthest pad electrode PADb. Note that the pad electrodes PAD arranged in a staggered manner are counted as 0.5. Let the margin of the paired elements at the boundary of the pad electrode PAD be A1 / 2.

[0076] As seen from the reference pad electrode PADa, the maximum offset M of the pad electrode PAD is "M = D1 × P+(A1 / 2)".

[0077] When the pad electrode PAD moves, the area B1 where M < B1 is arranged in the direction in which the pad electrode PAD may cover the paired elements, thereby allowing adjustment of the coverage range between the pad electrode PAD and the paired elements. This relationship also applies to other embodiments described later.

[0078] <Cross-sectional structure of semiconductor device>

[0079] Next, reference will be made to Figures 9 to 11 to describe the cross-sectional structure of the semiconductor device 100. Figure 9 is a cross-sectional view along Figure 7 the line A-A shown.

[0080] As Figure 9 shown, the semiconductor device 100 includes a semiconductor substrate SUB, a plurality of MOS units 3Q formed on the main surface of the semiconductor substrate SUB, and a multilayer wiring layer formed above the plurality of MOS units 3Q. As described above, each MOS unit 3Q among the plurality of MOS units 3Q includes MOS units 1Q and 2Q, which form part of a differential circuit as paired elements.

[0081] The multi-layer routing layer includes routing layers WL1 to WL8. Routers M1 to M8 are formed on routing layers WL1 to WL8, respectively. The thickness of routing M8 is greater than the thickness of routing layers M1 to M7 formed in the multi-layer routing layer. Here, an example of an 8-layer multi-layer routing layer is illustrated, but the number of layers in a multi-layer routing layer can be appropriately changed.

[0082] Multiple MOS cells 1Q, 2Q, 3Q and wiring M1 are electrically connected via plug PG. Wirings M1 to M7 are electrically connected via vias V1 to V6 respectively. Wirings M7 and M8 are electrically connected via via V7.

[0083] The plug PG is primarily formed of, for example, tungsten film. Wiring M1 to M7 and vias V1 to V6 are damascene or dual-damascene structures and are primarily formed of, for example, copper film. Via V7 is primarily formed of, for example, tungsten film. Wiring M8 is primarily formed of patterned aluminum alloy film.

[0084] Figure 10 and Figure 11 The cross-sectional structures of the MOSFETs constituting MOS cells 1Q, 2Q, and 3Q are shown. Figure 10 The cross-section of the MOSFET along its gate length is shown, and Figure 11 The cross-section of the MOSFET in the gate width direction is shown.

[0085] like Figure 10 and Figure 11 As shown, a component isolation portion (STI) is formed in a semiconductor substrate (SUB). For example, the semiconductor substrate (SUB) is made of p-type silicon. The component isolation portion (STI) includes a groove formed in the semiconductor substrate (SUB) to a predetermined depth from the main surface of the semiconductor substrate (SUB) and an insulating film embedded within the groove. The insulating film is, for example, a silicon oxide film.

[0086] In the plan view of the semiconductor substrate SUB, each MOSFET is formed in an active region AR surrounded by a device isolation portion STI. A well region WR is formed within the semiconductor substrate SUB within the active region AR. A gate electrode GE is formed on the well region WR via a gate insulating film. The gate electrode GE is, for example, a polysilicon film. An impurity region SD is formed in the well region WR. The impurity region SD constitutes the source or drain region of the MOSFET. The well region WR, located between the two impurity regions SD and below the gate electrode GE, forms the channel region of the MOSFET. The gate electrode GE and the impurity regions SD are electrically connected to wiring M1 via a plug PG.

[0087] In the first embodiment, each MOSFET is an n-type MOSFET. In this case, the well region WR has p-type conductivity, and the gate electrode GE and the impurity region SD have n-type conductivity. In other embodiments described later, the MOSFETs constituting MOS cells 1Q, 2Q, and 3Q can be p-type MOSFETs. In a p-type MOSFET, the well region WR has n-type conductivity, and the gate electrode GE and the impurity region SD have p-type conductivity.

[0088] like Figure 9 As shown, the semiconductor device 100 also includes a control circuit 20 and a register 21, but as Figure 10 and Figure 11 As shown, the control circuit 20 and register 21 are configured using multiple MOSFETs.

[0089] Here, we will refer to Figure 10 and Figure 11 The definition describes the state in which MOS cells 1Q, 2Q, and 3Q are covered by wiring M8. In the first embodiment, it is assumed that MOS cells 1Q, 2Q, and 3Q located near the boundary with wiring M8 may be affected by stress from wiring M8, and in fact, even MOS cells 1Q, 2Q, and 3Q that are not covered by wiring M8 can be defined as being covered by wiring M8.

[0090] The distance of the active region AR in the gate length direction of the MOSFET is L1, and the distance of the active region AR in the gate width direction of the MOSFET is W1. In the first embodiment, if the MOSFETs included in the MOS cells 1Q, 2Q, and 3Q that are not covered by the wiring M8 are formed in the active region AR at a distance of L1 / 2 or less or W1 / 2 or less from the wiring M8 in the plan view, then these MOS cells 1Q, 2Q, and 3Q are considered to be covered by the wiring M8 in the plan view.

[0091] (First Modification Example)

[0092] The first modification example of the first embodiment will now be described. Figure 10 and Figure 11 The diagram illustrates a planar MOSFET, but MOSFETs can also have a FIN-FET structure. (Refer to...) Figure 12 Describe the FIN-FET structure of a MOSFET.

[0093] like Figure 12As shown, a plurality of protrusions 30 are provided on a semiconductor substrate SUB, and these protrusions 30 are part of the semiconductor substrate SUB. The plurality of protrusions 30 extend in the X direction and are separated from each other in the Y direction. Component isolation portions STI are formed on the semiconductor substrate SUB located between the plurality of protrusions 30. In other words, the space between the plurality of protrusions 30 corresponds to a groove formed in the semiconductor substrate SUB, and the component isolation portions STI are formed inside the groove. The upper surface of the component isolation portions STI is positioned lower than the upper surface of the protrusions 30.

[0094] The gate electrode GE extends in the Y direction and is formed to cover the upper surface and two side surfaces of at least one protrusion 30. A gate insulating film is formed between the gate electrode GE and the protrusion 30. A well region WR is formed in the semiconductor substrate SUB including the protrusion 30. An impurity region SD is formed in the protrusion 30 exposed from the gate electrode GE (within the well region WR).

[0095] In the case of a FIN-FET structure, the well region WR, which is covered by the gate electrode GE and located between two impurity regions SD that become the source region or the drain region, becomes the channel region of the MOSFET.

[0096] In a FIN-FET structure MOSFET, compared to a planar structure MOSFET, more MOSFETs can be arranged in the same planar area, and the gate width of each MOSFET can be widened within the same planar area. Therefore, compared to a planar structure MOSFET, a higher drive current can be ensured in a FIN-FET structure MOSFET, and miniaturization of the semiconductor device 100 can be facilitated.

[0097] (Second Modification Example)

[0098] A second modified example of the first embodiment will now be described. In the first embodiment, as... Figure 4 As shown, an example of a uniform narrowing of the pitch relative to the reference pad electrode PADa is illustrated when the pitch between each pad electrode PAD (the distance between each trace M8) changes.

[0099] However, as Figure 13 As shown, a situation may arise where the pitch between each pad electrode PAD does not change due to product specifications, but the position of each pad circuit PAD needs to be fine-tuned. In other words, there may be a situation where the entire pad electrode PAD is uniformly offset in the Y or X direction. In this case, by pre-fabricating multiple MOS cells 3Q as candidates for paired components (MOS cells 1Q, 2Q), characteristic variations of the paired components can be prevented.

[0100] (Second Embodiment)

[0101] The following will refer to Figures 14 to 18 The semiconductor device 100 in the second embodiment is described. In the following description, the differences from the first embodiment will be explained primarily, and points overlapping with the first embodiment will be omitted.

[0102] Figure 14 The first-stage switch of the differential input circuit, which is included in the differential circuit of the analog IP10 in the second embodiment, is shown. MOS cell groups 1QA and 2QA form part of the differential circuit as paired elements and are electrically connected to the ESD protection circuit 22.

[0103] like Figure 15 As shown, MOS cell group 1QA consists of multiple MOS cells 1Q, while MOS cell group 2QA consists of multiple MOS cells 2Q. The number of multiple MOS cells 1Q is equal to the number of multiple MOS cells 2Q. In the second embodiment, each MOS cell 1Q and MOS cell 2Q consists of a p-type MOSFET.

[0104] exist Figure 14 In the equivalent circuit diagram, MOS cell group 1QA shows a state in which multiple MOS cells 1Q are connected in parallel with each other, while MOS cell group 2QA shows a state in which multiple MOS cells 2Q are connected in parallel with each other.

[0105] Additionally, such as Figure 15 As shown, wiring M8, which is separate from the pad electrode PAD, is provided above MOS cell group 1QA and MOS cell group 2QA to establish an electrical connection with ESD protection circuit 22.

[0106] The following will use Figures 16 to 18 The design method of the semiconductor device 100 in the second embodiment is described. Figure 18 It is along Figure 16 The cross-sectional view of line BB is shown. In the second embodiment, Figure 6 Steps S1 to S5 shown are performed in the same manner as in the first embodiment.

[0107] First, in step S1, as Figure 16 As shown in the “initial design”, multiple MOS cells 3Q are fabricated and arranged adjacent to each other on the main surface of a semiconductor substrate in a planar view. Each of the multiple MOS cells 3Q consists of a p-type MOSFET.

[0108] Next, in step S2, among the multilayer wiring layers formed above the multiple MOS cells 3Q, multiple wirings M8 are formed in the topmost wiring layer (wiring layer WL8). Then, the pitch between each wiring M8 is designed, and the layout of the multiple wirings M8 is performed.

[0109] Next, in step S3, as Figure 18 As shown, multiple MOS cells 1Q and multiple MOS cells 2Q are selected from multiple MOS cells 3Q to form a differential circuit as paired elements. Here, the coverage of MOS cell group 1QA covered by wiring M8 in the plan view is the same as the coverage of MOS cell group 2QA covered by wiring M8 in the plan view. Therefore, in the second embodiment, as in the first embodiment, no change in the characteristics of the paired elements occurs.

[0110] Note that among the multiple MOS cells 3Q, the other MOS cells 3Q excluding MOS cell group 1QA and MOS cell group 2QA are not used for differential circuits and other circuits. In the second embodiment, control circuit 20 and register 21 are not used to select the multiple MOS cells 1Q and multiple MOS cells 2Q. Instead, multiple wirings formed in a wiring layer below wiring layer WL8 and used for connecting differential circuits are used.

[0111] For example, such as Figure 17 As shown, the gate electrode GE and the sludge region SD of the MOSFET are electrically connected to multiple wirings M1 via plug PG. The multiple wirings M1 are electrically connected to multiple wirings M2 via via V1.

[0112] By changing the arrangement of via V1 in connecting wiring M1 and wiring M2, multiple MOS cells 1Q and multiple MOS cells 2Q can be electrically connected to... Figure 14 The equivalent circuit wiring is as follows, and multiple unselected MOS cells 3Q may become unavailable. For example, the gate electrode GE and the sludge region SD of the p-type MOSFET of an unselected MOS cell 3Q are respectively connected to the power supply potential Vdd.

[0113] In the case of paired components carrying high currents, such as switches in differential input circuits, the use of control circuit 20 may cause resistive components to affect the characteristics of the paired components. Therefore, by changing the arrangement of via V1 to switch the wiring, the influence of resistive components on the current path of the differential input circuit can be avoided. Moreover, this configuration can minimize the wiring load connected to the paired components.

[0114] Subsequently, as Figure 16 As shown in the “Design Change” section, the pitch between each wiring M8 can be changed. In step S4, if the pitch between each wiring M8 changes (yes), then in step S5, multiple MOS cells 1Q and multiple MOS cells 2Q are reselected.

[0115] In step S5, as Figure 16As shown in "Reselecting Pairs", multiple MOS cells 1Q and multiple MOS cells 2Q are reselected from multiple MOS cells 3Q so that the coverage of MOS cell group 1QA is the same as the coverage of MOS cell group 2QA.

[0116] Therefore, in the second embodiment, as in the first embodiment, even if the pitch between each wiring M8 changes, multiple MOS cells 1Q and multiple MOS cells 2Q can be reselected, so that the characteristics of paired components do not change.

[0117] (Third Embodiment)

[0118] Below, we will use Figures 19 to 25 The semiconductor device 100 in the third embodiment is described. In the following description, the differences from the first and second embodiments will be mainly described, and points overlapping with the first and second embodiments will be omitted.

[0119] Figure 19 The differential output circuit included as a differential circuit in analog IP10 in the third embodiment is shown. MOS cell group 1QA and MOS cell group 2QA form part of the differential circuit as paired elements.

[0120] like Figure 20 As shown, MOS cell group 1QA consists of multiple MOS cells 1Q, while MOS cell group 2QA consists of multiple MOS cells 2Q. The number of multiple MOS cells 1Q is equal to the number of multiple MOS cells 2Q.

[0121] exist Figure 19 In the equivalent circuit diagram, MOS cell group 1QA shows the state in which multiple MOS cells 1Q are connected in parallel, while MOS cell group 2QA shows the state in which multiple MOS cells 2Q are connected in parallel.

[0122] In Figure 19 In the case of identical differential output circuits, because each MOS cell group in MOS cell group 1QA and MOS cell group 2QA is relatively large, each part of MOS cell group 1QA and MOS cell group 2QA is easily covered by the pad electrode PAD. Making the coverage of MOS cell group 1QA and MOS cell group 2QA the same prevents characteristic variations between paired components.

[0123] Below, we will use Figures 21 to 25 The design method of the semiconductor device 100 in the third embodiment is described. Figure 25 It is along Figure 21 The cross-sectional view of line CC is shown. In the third embodiment, as in the first embodiment, the following is performed: Figure 6 Steps S1 to S5 are shown.

[0124] First, in step S1, as Figure 21 As shown in the “Initial Design”, multiple MOS cells 3Q are fabricated on the main surface of a semiconductor substrate arranged adjacent to each other in a planar view.

[0125] Next, in step S2, among the multilayer wiring layers formed above the multiple MOS cells 3Q, multiple wirings M8 are formed in the topmost wiring layer (wiring layer WL8). Then, the pitch between each wiring M8 is designed, and the layout of the multiple wirings M8 is performed.

[0126] Next, in step S3, as Figure 25 As shown, multiple MOS cells 1Q and multiple MOS cells 2Q are selected from multiple MOS cells 3Q to form a differential circuit as paired elements. Here, the coverage of MOS cell group 1QA covered by wiring M8 in the plan view is the same as the coverage of MOS cell group 2QA covered by wiring M8 in the plan view. Therefore, in the third embodiment, as in the first embodiment, no change in the characteristics of the paired elements occurs.

[0127] like Figure 22 , Figure 23 and Figure 24 As shown, in the third embodiment, the multiple MOS cells 1Q, 2Q, and 3Q are each composed of one or more n-type MOSFETs and one or more p-type MOSFETs. The number of one or more n-type MOSFETs is equal to the number of one or more p-type MOSFETs.

[0128] An n-type MOSFET has a p-type well region WRp, an n-type gate electrode GEn, and two impurity regions SDn, which serve as either the source or drain region. A p-type MOSFET has an n-type well region WRn, a p-type gate electrode GEn, and two impurity regions SDp, which serve as either the source or drain region. For example... Figure 22 and Figure 23 As shown, in MOS cell 1Q and MOS cell 2Q, one or more n-type MOSFETs and one or more p-type MOSFETs are connected in an inverter configuration.

[0129] Note that among the multiple MOS cells 3Q, the other MOS cells 3Q excluding MOS cell group 1QA and MOS cell group 2QA are not used for differential circuits and other circuits. In the third embodiment, as in the second embodiment, multiple wirings formed in a wiring layer below the wiring layer WL8 and used for connecting differential circuits are used to select the multiple MOS cells 1Q and multiple MOS cells 2Q.

[0130] For example, such as Figure 22 , Figure 23 and Figure 24 As shown, the gate electrode GEn and sludge region SDn of the n-type MOSFET and the gate electrode GEp and sludge region SDp of the p-type MOSFET are electrically connected to multiple wirings M1 via plug PG. The multiple wirings M1 are electrically connected to multiple wirings M2 via via V1.

[0131] By changing the arrangement of via V1 in connecting wiring M1 and wiring M2, multiple MOS cells 1Q and multiple MOS cells 2Q can be electrically connected to... Figure 19 The equivalent circuit wiring is as follows, and multiple unselected MOS cells 3Q may become unavailable. For example, the gate electrode GEn and sludge region SDn of the n-type MOSFET of the unselected MOS cell 3Q are respectively connected to the ground potential Vss, and the gate electrode GEp and sludge region SDp of the p-type MOSFET of the unselected MOS cell 3Q are respectively connected to the power supply potential Vdd.

[0132] The differential output circuit of the third embodiment also carries a large current, similar to the differential input circuit of the second embodiment. Therefore, by changing the arrangement of via V1 to switch the wiring, the influence of resistive components on the current path of the differential output circuit can be avoided. Moreover, this configuration can minimize the wiring load connected to paired components.

[0133] Subsequently, as Figure 21 As shown in the “Design Change” section, the pitch between each wiring M8 can be changed. In step S4, if the pitch between each wiring M8 changes (yes), then in step S5, a reselection of multiple MOS cells 1Q and multiple MOS cells 2Q is performed.

[0134] In step S5, as Figure 21 As shown in "Reselecting Pairs", multiple MOS cells 1Q and multiple MOS cells 2Q are reselected from multiple MOS cells 3Q so that the coverage of MOS cell group 1QA is the same as the coverage of MOS cell group 2QA.

[0135] In this way, even in the third embodiment, as in the first and second embodiments, even if the pitch between each wiring M8 changes, multiple MOS cells 1Q and multiple MOS cells 2Q can be reselected, so that the characteristics of paired elements do not change.

[0136] (Fourth Embodiment)

[0137] The following will refer to Figure 26 The design method of the semiconductor device 100 in the fourth embodiment is described. In the following description, the differences from the first to third embodiments will be explained mainly, and points overlapping with the first to third embodiments will be omitted.

[0138] In the fourth embodiment, the unused MOS cell 3Q is used as an element to adjust the capability of the differential circuit. For example, even using the same analog IP10, there may be situations where the capability of the differential circuit needs to be fine-tuned due to individual customer requirements. In such cases, a technology that allows for flexible and rapid response is provided.

[0139] That is, as illustrated in the third embodiment, as Figure 26 As shown, in Figure 6 Following step S5, at least one or more MOS cells 1Q are added to MOS cell group 1QA from multiple MOS cells 3Q, and the same number of added MOS cells 1Q are added to MOS cell group 2QA from multiple MOS cells 3Q. In this way, the capability of the differential circuit can be fine-tuned by adding unused MOS cells 3Q as MOS cells 1Q and MOS cells 2Q to the differential circuit.

[0140] Although the present invention has been specifically described based on the above embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from its spirit.

Claims

1. A semiconductor device, comprising: A semiconductor substrate having a first surface; Multiple MOS cells are arranged adjacent to each other on the first surface of the semiconductor substrate; Each of the plurality of MOS units consists of at least one MOSFET and has the same structure. A multilayer wiring layer is formed above the plurality of MOS cells; as well as The first wiring is formed on the uppermost wiring layer in the multi-layer wiring layers. Each of the plurality of MOS cells includes a first MOS cell and a second MOS cell, which are paired elements forming part of a differential circuit, and In the plan view, the coverage of the first MOS cell covered by the first wiring is the same as the coverage of the second MOS cell covered by the first wiring.

2. The semiconductor device according to claim 1, The MOS cells other than the first MOS cell and the second MOS cell are not used in the differential circuit and other circuits.

3. The semiconductor device according to claim 1, The thickness of the first wiring is greater than the thickness of the other wirings formed in the multilayer wiring layer.

4. The semiconductor device according to claim 3, The first wiring includes pad electrodes for connecting external connection components.

5. The semiconductor device according to claim 1, Each of the plurality of MOS units consists of an n-type MOSFET or a p-type MOSFET.

6. The semiconductor device according to claim 1, Each of the plurality of MOS cells consists of one or more n-type MOSFETs and one or more p-type MOSFETs, the number of the one or more n-type MOSFETs being the same as the number of the one or more p-type MOSFETs, and in the first MOS cell and the second MOS cell, the one or more n-type MOSFETs and the one or more p-type MOSFETs are connected in an inverter configuration.

7. The semiconductor device according to claim 1, The first MOS unit and the second MOS unit included in the plurality of MOS units are each a plurality of MOS units. The number of the plurality of first MOS cells is equal to the number of the plurality of second MOS cells, and in, When the plurality of first MOS cells are configured as the first MOS cell group and the plurality of second MOS cells are configured as the second MOS cell group, the coverage of the first MOS cell group covered by the first wiring in the plan view is the same as the coverage of the second MOS cell group covered by the first wiring in the plan view.

8. A method for designing a semiconductor device, comprising: (a) Fabricating a plurality of MOS cells arranged adjacent to each other on a first surface of the semiconductor substrate; Each of the plurality of MOS units consists of at least one MOSFET and has the same structure. (b) A first wiring is formed on the uppermost wiring layer of the multilayer wiring layers formed above the plurality of MOS cells; as well as (c) Select a first MOS cell and a second MOS cell from the plurality of MOS cells as part of a differential circuit as paired elements, such that the coverage of the first MOS cell covered by the first wiring in the plan view is the same as the coverage of the second MOS cell covered by the first wiring in the plan view.

9. The method for designing semiconductor devices according to claim 8, The thickness of the first wiring is greater than the thickness of the other wirings formed in the multilayer wiring layer.

10. The method for designing semiconductor devices according to claim 9, The first wiring is used as a pad electrode for connecting external connection components.

11. The method for designing semiconductor devices according to claim 8, Each of the plurality of MOS units consists of an n-type MOSFET or a p-type MOSFET.

12. The method for designing semiconductor devices according to claim 8, Each of the plurality of MOS cells consists of one or more n-type MOSFETs and one or more p-type MOSFETs, the number of the one or more n-type MOSFETs being the same as the number of the one or more p-type MOSFETs, and in the first MOS cell and the second MOS cell, the one or more n-type MOSFETs and the one or more p-type MOSFETs are connected in an inverter configuration.

13. The method for designing semiconductor devices according to claim 8, In step (c), the plurality of first MOS cells and the plurality of second MOS cells constituting part of the differential circuit are selected from the plurality of MOS cells. The number of the plurality of first MOS cells is equal to the number of the plurality of second MOS cells, and In step (c), when the plurality of first MOS cells are configured as the first MOS cell group and the plurality of second MOS cells are configured as the second MOS cell group, the coverage of the first MOS cell group covered by the first wiring in the plan view is the same as the coverage of the second MOS cell group covered by the first wiring in the plan view.

14. The method for designing a semiconductor device according to claim 8, further comprising: (d) If the pitch between each wiring formed on the uppermost wiring layer changes after step (c), the first MOS cell and the second MOS cell are reselected from the plurality of MOS cells such that the coverage of the first MOS cell and the coverage of the second MOS cell are the same.

15. The method for designing a semiconductor device according to claim 14, further comprising: (e) Prepare control circuitry and registers electrically connected to the plurality of MOS units. The register stores information about the coverage of each of the plurality of MOS cells in the plan view by the first wiring. In steps (c) and (d), the control circuit automatically selects the first MOS cell and the second MOS cell from the plurality of MOS circuits based on the information in the register, such that the coverage rate covered by the first wiring is the same in the plan view.

16. The method for designing a semiconductor device according to claim 14, further comprising: (f) Fabricating a plurality of second wirings, the plurality of second wirings being formed in the wiring layer below the uppermost wiring layer in the multilayer wiring layers, and for the connection of the differential circuit, and In steps (c) and (d), the first MOS cell and the second MOS cell selected from the plurality of MOS cells are electrically connected to the plurality of second wirings, and other unselected MOS cells are disabled.

17. The method for designing semiconductor devices according to claim 14, In step (c), a plurality of first MOS cells and a plurality of second MOS cells are selected from the plurality of MOS cells to form part of the differential circuit. The number of the plurality of first MOS cells is the same as the number of the plurality of second MOS cells. In step (c), when the plurality of first MOS cells are grouped into a first MOS cell group and the plurality of second MOS cells are grouped into a second MOS cell group, the coverage of the first MOS cell group covered by the first wiring in the plan view is the same as the coverage of the second MOS cell group covered by the first wiring in the plan view, and In step (d), the first MOS cell and the second MOS cell are reselected from the plurality of MOS cells such that the coverage of the first MOS cell group and the coverage of the second MOS cell group are the same.

18. The method for designing a semiconductor device according to claim 17, further comprising: (g) After step (d), at least one or more first MOS cells from the plurality of MOS cells are added to the first MOS cell group, and the same number of second MOS cells as the added first MOS cells from the plurality of MOS cells are added to the second MOS cell group.

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