Vertical heterojunction photoelectric synapse transistor and preparation and application method thereof

Abstract

The invention discloses a vertical heterojunction photoelectric synapse transistor and preparation and application thereof. The device sequentially comprises a back gate substrate (gate / gate medium), a single-layer graphene bottom electrode, a p-type rube layer, an n-type F16-CuPc layer and a top electrode from bottom to top, and rubree / F16-CuPc forms an II-type heterojunction, and short-channel vertical transmission is formed, so that photo-generated excitons are efficiently dissociated on an interface and vertically collect current. According to the device, 365-780nm wide spectrum detection and optical / electric driving synaptic plasticity (including paired pulse promotion and time width / frequency / pulse number dependence) are realized in a single structure, and retina-like denoising and contrast enhancement are realized based on time domain selectivity retention. The invention has the advantages of wide process window, easy array, low dark current, low energy consumption and good stability, and is suitable for wearable vision, weak light imaging and edge cognition processing.

Description

Technical Field

[0001] This invention relates to organic semiconductor devices and neuromorphic electronics, and more particularly to a rubrene / F... 16 -Vertical heterojunction organic field-effect phototransistor with CuPc type II heterojunction and gate-tunable contact of monolayer graphene and its fabrication and application methods. Background Technology

[0002] The development of neuromorphic optoelectronic hardware requires devices to simultaneously achieve broadband optical sensing and intrinsic synaptic plasticity within the same structural system to support real-time sensing and adaptive signal processing in complex environments. Achieving deep integration of multiple functions in compact and energy-efficient devices is a key requirement for brain-like visual systems, cognitive edge processors, and next-generation neuromorphic networks.

[0003] Organic semiconductors, due to their tunable leading-edge orbital energy levels, strong exciton interactions, and excellent mechanical flexibility, are considered ideal material systems for constructing flexible, large-area neuromorphic devices. Among various organic device forms, vertical organic field-effect transistors (VFETs) have become a powerful platform for realizing multifunctional photosynapses due to their short carrier transport paths, good vertical integration scalability, and high functional density. However, existing technologies generally suffer from: narrow spectral response ranges, making it difficult to cover multiple wavelengths from near-ultraviolet to visible; limited photoelectric conversion efficiency and signal-to-noise ratio; and relatively high dark current; and insufficient plasticity for achieving optical / electrical dual-mode within a single scalable structure. These limitations hinder their application in neuromorphic vision, edge cognitive processing, and other related fields. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a dual-function vertical organic field-effect photoelectric synaptic transistor and its fabrication and application method, which simultaneously achieves broadband optical detection, gate voltage modulation of the contact injection barrier, and photoelectric / electric dual-mode synaptic plasticity in a compact vertical structure, and supports retina-like image preprocessing with low power consumption.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: the transistor comprises, from bottom to top, a back gate substrate (including a gate electrode 1 and a gate dielectric layer 2 thereon), a gate-tunable monolayer graphene bottom electrode 3 disposed on the gate dielectric layer 2 and its drain electrode 4, and a p-type rubrene layer 5 and an n-type F layer stacked sequentially. 16 -CuPc layer 6, and top electrode 7; where rubrene / F 16 -CuPc forms a type II interleaved band heterojunction, which is beneficial for efficient exciton dissociation and vertical current collection at the interface; the graphene bottom electrode 3 serves as the drain and the top electrode 7 serves as the source.

[0006] Compared with existing technologies, this invention achieves deep coupling of broadband optical detection and optical / electrical dual-mode flexibility in a single and scalable vertical device, satisfying the integration of front-end "sensing-learning" and improving system integration. Under the test conditions described in the embodiments of the specification, the key indicators of the device can reach: responsivity R reaches 24 A·W. -1 External quantum efficiency (EQE) reaches 82%, and specific detectivity (D) ＊ Reaching 3×10 11 Jones, shutdown current approximately 10 -11 A; Benefiting from the capacitive coupling of graphene-back gate and rubrene / F 16 The synergistic alignment of CuPc energy levels can suppress recombination while maintaining a low injection barrier, resulting in stable transfer characteristics and good repeatability over multiple days. In terms of energy efficiency, the energy consumption of a single photosynaptic event can be ≤10fJ. Based on the temporal-dependent plasticity (SDDP) of the device, retinal-like front-end preprocessing can be achieved. By selectively retaining light stimuli with different temporal widths, noise suppression and edge / contrast enhancement can be achieved, providing high-quality input for subsequent recognition and sensing-memory-computing integrated systems. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a vertical heterojunction photosynaptic transistor.

[0008] Figure 2 This diagram illustrates the optical response of the device at different wavelengths from 365 to 780 nm.

[0009] Figure 3 This is a schematic diagram of the device's output / transfer characteristics.

[0010] Figure 4 The responsivity R, external quantum efficiency EQE, and specific detectivity D of the device are given. ＊ The diagram illustrates the gate voltage dependency relationship.

[0011] Figure 5 This is a schematic diagram of the optical synaptic plasticity of the device.

[0012] Figure 6 This is a schematic diagram of the electrical synaptic plasticity of the device.

[0013] Figure 7 This is a schematic diagram of the preprocessing workflow and noise reduction for retina-like images.

[0014] Explanation of reference numerals in the attached figures: 1—Gate electrode; 2—Gate dielectric layer; 3—Graphene bottom electrode (drain); 4—Drain lead-out electrode; 5—P-type organic semiconductor layer; 6—N-type organic semiconductor layer; 7—Top electrode (source). Detailed Implementation

[0015] The embodiments of the present invention are further described below with reference to the accompanying drawings and experimental data. It should be understood that, even if not explicitly stated in every place below, any substitutions or equivalent modifications that can be conceived by those skilled in the art without inventive effort should fall within the scope of protection of the present invention. Example 1

[0016] like Figure 1 As shown, this device has a vertically stacked structure, consisting of the following layers from bottom to top: a back gate substrate (composed of a gate electrode 1 and a gate dielectric layer 2), a monolayer graphene bottom electrode 3, a drain electrode 4 located on one side of the graphene bottom electrode 3, a p-type rubrene organic semiconductor layer 5, and an n-type F... 16 -CuPc organic semiconductor layer 6 and top electrode 7. Top electrode 7 serves as the source, and graphene bottom electrode 3 serves as the drain. The device employs back-gate capacitive coupling: gate electrode 1 is coupled to graphene 3 via gate dielectric layer 2, achieving gate voltage regulation and channel conductivity modulation of the contact injection barrier.

[0017] Regarding band structure, rubrene / F 16 -CuPc forms a type II cross-band structure, and photogenerated excitons at the interface tend to dissociate: electrons transfer to F 16 -CuPc, holes remain in the rubrene; negative gate voltage enables the band to bend upwards, enhancing hole accumulation and carrier separation in the rubrene, thereby simultaneously enhancing photodetection and synaptic response. Example 2

[0018] The preparation steps for a vertical heterojunction are as follows: S1. Back gate substrate preparation: Heavily doped Si is selected as the gate electrode 1, and a gate dielectric layer 2 is formed on it. The gate dielectric is preferably thermally grown SiO2; Al2O3 or SiN can also be used. x (Silicon nitride) or organic / inorganic composite dielectric, the dielectric thickness and equivalent dielectric constant are selected based on the target gate coupling degree. Pre-cleaning / baking can be performed to ensure a clean and smooth surface.

[0019] S2. Formation and Lead-out of the Bottom Electrode: A monolayer of graphene is formed or transferred onto the surface of the gate dielectric layer 2 to form the bottom electrode 3. Graphene can be obtained by at least one of the following methods: wet transfer, dry lamination, mechanical exfoliation, or in-situ growth. Before transfer, ozone or plasma pretreatment can be performed to enhance adhesion to SiO2, and the transfer is completed at 50-120°C. Subsequently, metal traces are fabricated on one side of the graphene to form the drain electrode 4, ensuring ohmic contact and pattern alignment with the bottom electrode 3 to meet the requirements of upper layer stacking.

[0020] S3. Formation of a p-type rubrene layer: A p-type rubrene organic semiconductor layer is formed on the bottom electrode 3. The rubrene is formed by at least one of the following methods: growth, transfer, stacking, or coating, including but not limited to: physical vapor transport growth, zone deposition growth, solution crystallization / self-assembly, evaporation crystallization, melt recrystallization, mechanical stacking, or transfer using a polymer stamp / microneedle tool. If necessary, mild annealing at 80-150°C for 10-30 min can be performed to improve crystallinity and interfacial adhesion.

[0021] S4, forming n-type F 16 -CuPc layer: n-type F is formed on the rubrene layer. 16 -CuPc organic semiconductor layer. Preferably, vacuum thermal evaporation, sputtering or other physical deposition methods are used, and the process is carried out at a low rate under vacuum or controlled atmosphere to obtain a dense, continuous film and a clean interface.

[0022] S5, Forming of Top Electrode 7: In F 16 A top electrode 7 (e.g., Au, Ag, or a transparent conductive oxide) is deposited or transferred onto the CuPc layer. The top electrode can be formed by evaporation, electroplating, sputtering, or printing / imprinting, and the electrode thickness is preferably 20-80 nm. To achieve light incidence from the top, an opening window can be provided or a semi-transparent electrode solution (e.g., ultrathin metal or TCO) can be used.

[0023] S6. Optional interface treatment and annealing: Without damaging the organic layer and metal electrode, the rubrene layer / F can be treated. 16 - CuPc layers or metal / organic interfaces perform plasma activation, self-assembled monolayers, or mild annealing to optimize energy level alignment, reduce interface traps, and improve interlayer adhesion.

[0024] S7. Arraying and Electro-optical Connection Preparation: Complete the patterning according to single pixel or array requirements; connect the top electrode 7 (source) and drain electrode 4 to the source / drain channels of the semiconductor parameter analyzer, respectively; the gate electrode 1 forms a gate coupling circuit with the graphene 3 through the gate dielectric layer 2; optical incidence is from the top. Characterization can be performed using multi-band LED light sources (365 / 465 / 495 / 575 / 650 / 780nm) and function / arbitrary waveform generators, with driving modes supporting single pulses and pulse sequences. Example 3

[0025] Based on the general process described in Example 2, this example provides a specific process instance: rubrene is grown using physical vapor transport and transferred to the graphene bottom electrode using flexible polymer microneedles. 16 -CuPc forms an n-type layer through thermal evaporation, and the top / lead-out electrodes are formed by imprinting.

[0026] S1. Rubrene Single Crystal Growth: Rubrene powder with a purity >99% was uniformly spread on a clean silicon substrate and placed in a quartz tube (25 cm in length, 1.5 cm in inner diameter) within a single-zone tube furnace. The powder was located in the sublimation zone at approximately 340°C; the growth zone temperature was maintained at approximately 220°C. High-purity argon gas was introduced at a flow rate of 20 sccm to provide an inert atmosphere and promote vapor transport. After approximately 35 minutes, the rubrene recrystallized in the cooler deposition zone to form crystals.

[0027] S2. Crystal Acquisition and Transfer: To avoid surface damage, rubrene crystals are carefully acquired using flexible polymer microneedles. On the back gate substrate and graphene bottom electrode 3 prepared in S1-S2 of Example 2, the obtained crystals are transferred and spread on the surface of the graphene bottom electrode 3, forming a continuous rubrene film / sheet in the electrode region as a p-type organic semiconductor layer 5.

[0028] S3, Forming an n-type layer: F is deposited on the rubrene film via thermal evaporation. 16 -CuPc is used as the n-type semiconductor layer. The pressure inside the evaporation chamber is approximately 5 × 10⁻⁶. -4 Torr, deposition rate approximately The deposition thickness is monitored in real time using a quartz crystal oscillator to ensure uniform film thickness and process control.

[0029] S4. Top / Lead Electrode Forming and Alignment: After the heterojunction is formed, two gold electrodes are fabricated using an imprinting method: one of which covers the F... 16 On the CuPc thin film, one electrode serves as the top electrode (7); the other, aligned and electrically connected to the graphene layer, serves as the drain electrode (4). The opposing region of these two electrodes defines the effective device opening, with a channel width of approximately 90 micrometers and a length of approximately 20 micrometers. This opposing region forms a light incident opening, supporting illumination from top-incident light. This results in a vertical rubrene / F... 16 -CuPc heterojunction organic field-effect transistor structure, with top electrode 7 as the source and graphene bottom electrode 3 as the drain. Example 4

[0030] This embodiment is used to characterize the photoelectric detection capability of the device of the present invention under multi-band illumination and different bias conditions, and is used for subsequent bias calibration of array pixels.

[0031] S1. Fix the device prepared according to Examples 1 and 2 on the probe station. Connect the top electrode 7 (source) and the drain lead 4 (drain) to the source / drain channels of the ammeter / parameter instrument, respectively. The back gate-graphene forms a gate coupling circuit.

[0032] S2. Select a multi-band light source and output continuous or pulsed light incident from the top of the device; the incident light spot covers the effective device area, and the pulse parameters are controlled by a function / arbitrary waveform generator.

[0033] S3. Scan the drain voltage under a fixed gate voltage to obtain the output characteristic curve; scan the gate voltage under a fixed drain voltage to obtain the transfer characteristic curve; record the results under light and dark conditions respectively.

[0034] S4. Under the selected monochromatic wavelength condition, repeatedly collect the relationship curve between current density and gate voltage with multiple incident power levels; if the curve shifts as a whole with the incident power rather than just amplifies in amplitude, it can be determined that the device response is mainly contributed by grating control.

[0035] S5. Based on the curves obtained from S3 and S4, select the working gate voltage and drain-source bias window that meet the application requirements; for the pixel array, scan and record pixel by pixel according to the same process, and establish a pixel-bias calibration table to ensure array consistency and stable operation.

[0036] This embodiment only limits the test procedure and criteria, and does not limit the numerical range. Example 5

[0037] This embodiment describes the process of obtaining short-term and long-term plasticity using light / electric pulse stimulation.

[0038] S1. Under a fixed bias, apply a set of paired light pulses; change the interval Δt between the two pulses, record the peak values ​​of the first and second synaptic currents (EPSC) respectively, and calculate the amplitude ratio as the paired pulse promotion (PPF) index; repeat multiple Δt cycles to obtain the time correlation curve.

[0039] S2. With a fixed pulse amplitude and duration, apply sequences of different pulse numbers (e.g., 1 / 2 / 4 / 8) and record the accumulation and decay behavior of EPSC as the pulse count increases.

[0040] S3. Under a fixed amplitude, change the duration of a single pulse and record the corresponding EPSC peak value and attenuation trajectory to obtain the duration-response mapping.

[0041] S4. Frequency Dependence: Under fixed amplitude and duration, pulse trains with different repetition frequencies are applied, and the change of EPSC with frequency is recorded to form a frequency-response mapping.

[0042] S5. While keeping the optical path closed, use an electrical pulse protocol to perform enhancement / de-enhancement training on the device, and record the reversible adjustment process of the conduction state with the polarity, number, duration and frequency of the training pulses.

[0043] S6. Readout and Recovery: After each test, the synaptic current is sampled within a uniform readout bias and time window; if necessary, a recovery interval is set to avoid interference from the previous stimulus and ensure test independence.

[0044] This embodiment defines the pulse protocol and readout process. Example 6

[0045] This embodiment presents a methodology for image front-end noise reduction and contrast enhancement based on device time-dependent plasticity (SDDP), applicable to both single-pixel scanning and array parallel operation modes.

[0046] S1. Obtaining the weight function (training phase): Using pulse duration as the independent variable, apply several light pulses to a single pixel or representative pixel; read the corresponding ΔEPSC within a fixed sampling window; normalize and fit the (duration, ΔEPSC) samples to obtain the denoising / weight function.

[0047] S2, Pixel-to-Pulse Mapping: The grayscale or RGB three-channel values ​​of the input image are mapped pixel by pixel to the duration of light pulses (or a combination thereof), generating a pulse timing sequence of the same size as the pixel matrix; in array mode, each pixel receives the corresponding pulse in parallel.

[0048] S3. Array driving and readout: Drive the device according to the timing of S2 and read the ΔEPSC matrix within a unified sampling window; to avoid crosstalk, row and column gating or time-division multiplexing strategies can be adopted.

[0049] S4. Pixel-level weight calculation and output: Substitute the ΔEPSC matrix into the weight function obtained in S1 to perform multiplicative noise reduction and contrast enhancement pixel by pixel; depending on the application needs, thresholding / normalization / cropping steps can be set to output grayscale or near-binarized images.

[0050] S5. Robustness and Adaptability: For scenes with different background colors or noise distributions, adaptive processing can be achieved by adjusting the sampling window, threshold, and time width level; the selection of the above parameters is based on ensuring output stability and edge fidelity.

[0051] Performance and Effect like Figure 2 As shown, the device generates significant photocurrent across a broad spectral range from 365 nm to 780 nm, which is attributed to the interaction between rubrene and F. 16 -Complementary absorption properties of CuPc. Broadband optical response was achieved in a compact vertical structure through interface engineering.

[0052] like Figure 3 As shown in a, in V G At 0V, irradiation at different wavelengths significantly shifted the device's output curve upwards, demonstrating its broad spectral response; the modulation at 365nm was the strongest, reflecting the rubrene / F... 16 -Efficient absorption and exciton dissociation at CuPc heterostructures. For example... Figure 3As shown in b, the output characteristics change significantly with gate voltage in the range of 40 to +40V. The negative gate bias brings the highest occupied molecular orbital of rubrene closer to the Fermi level, lowers the hole injection barrier and promotes hole accumulation, while suppressing electrons to F. 16 -CuPc injection. Meanwhile, as Figure 3 As shown in Figure c, the leakage current of the device in the off state is approximately 10⁻¹¹ A.

[0053] like Figure 4 As shown, the device exhibits high-sensitivity detection under gate voltage modulation: the responsivity (R) reaches 24.1 A·W. -1 ( Figure 4 a) At optimal gate bias, the external quantum efficiency (EQE) reaches 81.9%. Figure 4 b) When the incident power is 13.47 nW and the gate voltage V G At approximately 2.4V, the specific detectivity (D) ＊ The peak value reached 3.75 × 10 11 Jones Figure 4 c). The high specific detectivity mentioned above stems from low dark current and strong photogenerating gain, which benefits from the efficient carrier separation and collection brought about by the clean crystal interface and vertical collector path.

[0054] like Figure 5 As shown, the device exhibits finely tunable multimodal synaptic plasticity: firstly, it demonstrates paired pulse promotion (PPF) (A2>A1, decaying with interval Δt) ( Figure 5 a) At a fixed amplitude, the time-width dependence (SDDP) indicates that short pulses produce EPSC with small amplitude and rapid decay, while long pulses produce a higher and slower decay response. Figure 5 b); Pulse number dependent (SNDP) analysis shows that EPSC increases cumulatively with the number of pulses in a continuous optical pulse sequence (365 nm, 0.3 s, 20 nW; 1 / 2 / 4 / 8 pulses). Figure 5 c); it also exhibits frequency dependence, with the response increasing as the frequency increases from 1Hz to 10Hz. Figure 5 d). The above results demonstrate that the synaptic behavior of this device can be synergistically modulated by light intensity and time parameters, meeting the application requirements of neuromorphic visual front-ends. Furthermore, according to... Figure 5 c calculated the device's energy consumption, and under 50ms light pulse conditions, the device's energy consumption can be as low as 8.6fJ, which is comparable to or even lower than that of biological synapses.

[0055] like Figure 6 As shown, in addition to optical modulation, the device also exhibits synaptic plasticity under the influence of electrical pulses (see...). Figure 6a): Positive pulses induce long-term potentiation (LTP), while negative pulses induce long-term depression (LTD), conforming to a Hebbian-like pattern. Its plasticity exhibits multiple dependencies: firstly, it is pulse-number dependent, with EPSC increasing cumulatively with the number of pulses in 1 / 2 / 4 / 8 pulse sequences (…). Figure 6 b); secondly, it is time-width dependent. Within the 50-500ms range, a longer time width produces a larger amplitude EPSC with a slower decay. Figure 6 c); Third, it is frequency-dependent, with a significant increase in response when the frequency increases from 1Hz to 10Hz, reflecting a time-cumulative effect. Figure 6 d). The above results indicate that this device can achieve programmable synaptic weight modulation through pure electrical stimulation, making it suitable for low-power neuromorphic learning tasks.

[0056] Based on SDDP, a retina-like front end is constructed (see...). Figure 7 a) Using time-domain selective retention, short pulses cause the EPSC of background pixels to decay rapidly within the sampling window, while long pulses retain higher EPSC of target pixels, thus achieving noise suppression and enhancement. An 8×8 grayscale letter image "N, J, U, I, C" with 0-0.8 random noise added is used as input. Figure 7 The method maps pixel values ​​to light pulse durations (bd), and acquires ΔEPSC 2 seconds after pulse removal, then normalizes and fits it to obtain a denoising / weighting function. After processing, the background signal is significantly reduced to near zero, stroke contrast is improved, and the output is nearly binarized with clear edges. This method is robust to different color mappings and noise distributions, indicating that this device can serve as a highly efficient front-end for a perception-computation integrated neuromorphic vision system.

Claims

1. A vertical heterojunction photosynaptic transistor, comprising: - Back gate substrate, the back gate substrate including a gate electrode (1) and a gate dielectric layer (2) thereon; - A gate-tunable bottom electrode (3) disposed on the gate dielectric layer (2), wherein the bottom electrode (3) is a single layer of graphene and is capacitively coupled to the gate electrode (1) through the gate dielectric layer (2); - Drain electrode (4) electrically connected to the bottom electrode (3); - A p-type organic semiconductor layer (5) and an n-type organic semiconductor layer (6) are sequentially stacked on the bottom electrode (3); - Top electrode (7) disposed on the n-type organic semiconductor layer (6); The p-type organic semiconductor layer (5) is characterized by being rubrene, and the n-type organic semiconductor layer (6) is hexadecyl copper phthalocyanine (F). 16 -CuPc), the two form a type II crossband heterojunction, which enables photogenerated excitons to dissociate efficiently at the interface and collect electricity in the vertical direction; the graphene bottom electrode (3) serves as the drain and the top electrode (7) serves as the source, so that the device can be used for broadband optical detection and generate synaptic plasticity response under light / electric stimulation in the same structure.

2. The transistor according to claim 1, characterized in that, The rubrene layer (5) is a single crystal with a thickness of 50-1000 nm. 16 - The CuPc layer (6) is a continuous dense film with a thickness of 10-100 nm.

3. The transistor according to claim 1 or 2, characterized in that, The top electrode (7) is one of gold, silver or transparent conductive oxide or a stack thereof.

4. The transistor according to any one of claims 1-3, characterized in that, Under the test conditions described in the embodiments of the specification, the capacitive coupling between the graphene bottom electrode (3) and the gate electrode (1) causes the device to have a turn-off current of less than 1 × 10⁻⁶ at zero or very small gate voltage. -10 A, and supports top-incident lighting.

5. The transistor according to any one of claims 1-4, characterized in that, Under the test conditions described in the embodiments of the specification, its spectral response range covers 365-780 nm, and at a selected gate voltage, it satisfies at least one of the following: responsivity greater than 10 A·W. -1 External quantum efficiency greater than 50%, specific detectivity greater than 1×10⁻⁶ 11 Jones.

6. The transistor according to any one of claims 1-5, characterized in that, Under the test conditions described in the embodiments of the specification, it exhibits at least one of paired pulse promotion, time-width-dependent plasticity, pulse number-dependent plasticity, and frequency-dependent enhancement under photo / electric pulse stimulation; and the energy consumption of a single photosynaptic event is less than 10 fJ under low bias.

7. The transistor according to any one of claims 1-6, characterized in that, The back gate substrate is Si / SiO2 or an equivalent insulating / conductive silicon stack; the gate dielectric is at least one of thermally grown silicon oxide, aluminum oxide, silicon nitride, or an organic / inorganic composite dielectric.

8. A method for manufacturing the transistor of claim 1, characterized in that, include: a) Provide a back gate substrate, the back gate substrate including a gate electrode (1) and a gate dielectric layer (2) thereon; b) A monolayer of graphene is formed or transferred on the gate dielectric layer (2) to form a bottom electrode (3), and a drain electrode (4) is formed on one side of it in ohmic contact with it. c) A p-type rubrene organic semiconductor layer (5) is formed on the bottom electrode (3); d) Forming n-type F on the rubrene layer (5) 16 -CuPc organic semiconductor layer (6); e) in the F 16 - A top electrode (7) is formed on the CuPc layer (6); The feature is that step d) can be performed by vacuum thermal evaporation, sputtering or other physical deposition methods, and in a vacuum or controlled atmosphere; annealing or interface treatment can be set between each step to optimize energy level alignment and interface stability.

9. The method according to claim 8, characterized in that, Includes one or more of the following conditions: (i) The graphene bottom electrode (3) is obtained by at least one of wet transfer, dry lamination, mechanical exfoliation or in-situ growth; the graphene is pretreated with ozone or plasma before transfer to enhance its adhesion to SiO2, and the transfer is completed at 50-120°C. (ii) The rubrene layer (5) is a single crystal or polycrystalline, and is formed by at least one of growth, transfer, stacking or coating, including but not limited to: physical vapor transport growth, zone deposition growth, solution crystallization / self-assembly, evaporation crystallization, melt recrystallization, mechanical stacking or transfer by polymer stamp / microneedle tool; and can be annealed at 80-150℃ for 10-30 min; (iii) The top electrode (7) is formed by evaporation, electroplating, sputtering or printing / imprinting, and the electrode thickness is 20-80 nm. (iv) The interface treatment may include plasma activation, self-assembled monolayer or mild annealing to reduce interface traps and improve energy level alignment.

10. The application of the transistor according to claim 1, characterized in that, It can be used for broadband light detection, low-light imaging front-end, neuromorphic photoelectric synapses, and retina-like image preprocessing based on time-dependent synaptic plasticity.

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