Dual-check error-proofing method and system integrating visual positioning and data comparison

Abstract

The invention relates to the technical field of semiconductor advanced packaging and manufacturing, in particular to a double-verification error-proofing method and system integrating visual positioning and data comparison, and the method comprises the steps: S100, obtaining the actual physical slot position of each wafer based on a slot position image and a predefined FOUP slot position coordinate system; step S200, performing consistency verification on the bonding state, the inspection structure and the process flow data of the wafer based on a preset triple verification logic rule in an MES system to obtain a verification result; if the verification result is qualified, a qualification report is generated, and if the verification result is not qualified, the step S300 is carried out; and step S300, distinguishing an exception type according to a verification result, and then selecting an exception response mechanism according to the exception type. According to the invention, a closed-loop error-proofing system with physical positioning, logic verification and automatic deviation correction is established, so that the automation level and the quality guarantee capability of the wafer bonding process are improved.

Description

Technical Field

[0001] This invention relates to the field of advanced semiconductor packaging manufacturing technology, specifically to a dual-verification error prevention method and system that integrates visual positioning and data comparison. Background Technology

[0002] In the wafer bonding process of advanced semiconductor packaging, the bonding site needs to be inspected before leaving the site. Traditional verification methods have the following technical bottlenecks, which seriously restrict the production efficiency and quality stability of the bonding process in advanced packaging plants: Currently, traditional verification methods typically employ manual visual inspection or fixed-view vision inspection systems. For example, operators must manually check whether the physical slots of the wafers in the FOUP match the bonding relationships recorded by the Manufacturing Execution System (MES) and confirm the bonding status. This manual method is inefficient; a complete verification of an entire box of wafers (typically 25 wafers) takes approximately 10 minutes, and due to human error, the missed detection rate is high, around 2% (e.g., failing to detect wafers that are not fully bonded in time). Furthermore, while fixed-view vision systems can partially replace manual inspection, they are limited by camera field of view and resolution. When the wafer jam height is large (e.g., a standard 300mm wafer jam), a single camera cannot cover all slots, resulting in blind spots. Existing technologies (such as the fixed-view vision system described in CN120600666A) attempt to improve the automation of inspection through visual means, but they still cannot solve the problems of full coverage and accuracy.

[0003] The defects in the existing technology are mainly reflected in the following three aspects: First, the verification process is inefficient and unreliable. Manual verification is tedious and susceptible to fatigue and subjective judgment, leading to missed detections. Fixed vision systems, due to their limited field of view, require multiple adjustments or may not be able to capture complete images, making it difficult to achieve efficient full inspection.

[0004] Second, there is a mismatch in slot bonding. After bonding, wafers are often incorrectly placed in slots that do not match the MES records, with a misplacement rate of about 3%. This causes information reading errors in downstream packaging and testing processes, resulting in data chaos and requiring costly rework. The cost of a single rework can account for a significant proportion of the total production cost.

[0005] Third, the status verification dimension is too narrow. The existing verification only focuses on the bonding status (such as qualified or scrapped), and fails to conduct logical correlation verification with production inspection data (such as bonding strength, alignment accuracy, etc.), resulting in about 0.8% of scrapped wafers being incorrectly marked as qualified, which constitutes a major quality hazard.

[0006] While some improvements attempt to introduce partial automation tools, such as the moving camera and image stitching technology proposed in CN120600666A, these primarily target the physical slot scanning of wafer cassettes and do not address the specific verification requirements of the bonding process (such as bonding quality and data binding). Therefore, existing technologies cannot fundamentally solve the problems of low verification efficiency, poor reliability, and insufficient multi-dimensional data fusion. Summary of the Invention

[0007] To address the problems in existing technologies, this invention provides a dual-verification error prevention method and system that integrates visual positioning and data comparison to improve the automation level and quality assurance capabilities of the wafer bonding process.

[0008] This invention is achieved through the following technical solution: A dual-verification error prevention method integrating visual positioning and data comparison includes: Step S100: Based on the slot image and the predefined FOUP slot coordinate system, obtain the actual physical slot of each wafer; Step S200: Based on the preset triple verification logic rules in the MES system, perform consistency verification on the bonding status, inspection structure and process flow data of the wafer to obtain the verification result; if the verification result is qualified, generate a qualified report; if the verification result is unqualified, proceed to step S300. Step S300: Identify the anomaly type based on the verification result, and then select the anomaly response mechanism based on the anomaly type.

[0009] Preferably, step S100 involves obtaining the actual physical slots of each wafer based on the slot image and a predefined FOUP slot coordinate system, including: Step S101: Use a camera to acquire images of all slots, and then preprocess the images to obtain the Mark points on the wafer edge. Step S102: Based on the predefined FOUP slot coordinate system, the actual slot number of the wafer is calculated according to the identified Mark point position using a pattern recognition algorithm.

[0010] Preferably, in S101, the preprocessing includes noise reduction and edge extraction, wherein the edge extraction employs a sub-pixel-level edge detection algorithm in threshold segmentation technology, with a positioning accuracy of [missing information]. .

[0011] Preferably, in step S200, the bonding status, inspection structure, and process flow data of the wafer are checked for consistency based on the preset triple verification logic rules in the MES system, and the verification results are obtained, including: Step S201: Perform verification using triple verification logic rules to obtain the corresponding verification results: Triple verification logic rules include bond state consistency check, verification result integrity check, and timestamp order check; Step S202: Establish the binding relationship between the wafer's unique ID and the entire process data, including the association between the bonding equipment number and the testing equipment number, whether the batch number of the adhesive used matches the mixing record, and whether the time error between the two is within the allowable range.

[0012] Preferably, in step S201, the bonding status consistency check is that wafers marked as "scrap" in the MES must not appear in the qualified product slot; the inspection result integrity check is that all qualified wafers must be associated with a complete and qualified microscope inspection report; and the timestamp sequence check is that the time when the inspector completes the operation must be later than the bonding completion time of the wafer.

[0013] Preferably, in step 300, the exception types include slot misalignment, state logic error, and missing binding relationship.

[0014] Preferably, the exception response mechanism is selected based on the exception type, including: When the anomaly type is slot misalignment, a moving error correction process is used to grab the wafer from the wrong slot and move it back to the correct slot, followed by a second scan for confirmation. When the exception type is a status logic error, the entire box of wafers is locked to prevent it from being shipped out, and a rework order is generated, requiring manual review and processing. When the exception type is missing binding relationship, a data traceability work order is generated to notify relevant personnel to supplement the association information.

[0015] A dual-verification error prevention system integrating visual positioning and data comparison is used to implement the dual-verification error prevention method integrating visual positioning and data comparison. The first module obtains the actual physical slot of each wafer based on the slot image and the predefined FOUP slot coordinate system. The second module performs consistency verification on the bonding status, inspection structure, and process flow data of the wafer based on the preset triple verification logic rules in the MES system, and obtains the verification results; if the verification results are qualified, a qualified report is generated; if the verification results are unqualified, step S300 is performed. The third module identifies the anomaly type based on the verification results, and then determines the anomaly response mechanism based on the different anomaly types.

[0016] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the method when executing the computer program.

[0017] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method.

[0018] Compared with the prior art, the present invention has the following beneficial effects: This invention presents a dual-verification error-proofing method integrating visual positioning and data comparison, constructing a closed-loop error-proofing system encompassing physical positioning, logical verification, and automatic correction. The method uses a high-precision industrial camera deployed above the exit to capture images of wafers within the FOUP (Folded-Up Unit). Through image processing and recognition algorithms, the actual physical slot position of each wafer is accurately obtained. Then, production logs and inspection reports from the MES (Manufacturing Execution System) are invoked. Based on multiple preset logical rules, a deep consistency verification is performed on the wafer bonding status, inspection results, and process flow data. Finally, based on the verification results, preset handling procedures are executed for different types of anomalies, initiating different response mechanisms according to the anomaly type. This method combines visual positioning (misplacement rate 0.05%) with data comparison (state misjudgment rate 0%), reducing the missed detection rate of bonded wafers from 1% to 0.01%, and improving the error-proofing capability to 99%.

[0019] This system uses visual technology to accurately identify the physical location of wafers and verifies the logical consistency of production data through the MES system. Finally, it automates or streamlines the processing of any detected anomalies. Specifically, it uses 3D visuals to display the real-time status of wafer slots, with abnormal slots flashing red and accompanied by voice prompts, reducing the error rate by 70%. The robotic arm automatically adjusts misplaced wafers, reducing processing time from 2 minutes / wafer to 15 seconds / wafer, improving efficiency by 87.5%. Attached Figure Description

[0020] Figure 1 This is a flowchart of a dual-verification error prevention method integrating visual positioning and data comparison according to the present invention; Figure 2 This is a system architecture diagram of a dual-verification error prevention system integrating visual positioning and data comparison according to the present invention; Figure 3 This is a comparison chart of the slot misplacement rate obtained by the method used in this invention, manual verification, and single-vision verification. Detailed Implementation

[0021] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0022] Exemplary embodiments of the present invention will now be described with reference to the accompanying drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided to fully and completely disclose the invention and to fully convey its scope to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the drawings is not intended to limit the invention. In the drawings, the same units / elements are referred to by the same reference numerals.

[0023] Unless otherwise stated, the terms used herein (including technical terms) have their common meaning as understood by one of ordinary skill in the art. Furthermore, it is understood that terms defined in commonly used dictionaries should be understood to have a meaning consistent with the context of their relevant field, and not to be interpreted as having an idealized or overly formal meaning.

[0024] The present invention will be further described in detail below with reference to specific embodiments. These descriptions are for explanation purposes only and are not intended to limit the scope of the invention.

[0025] This invention discloses a dual-verification error prevention method integrating visual positioning and data comparison, referring to... Figure 1 ,include: Step S100: Based on the slot image and the predefined FOUP slot coordinate system, obtain the actual physical slot of each wafer. Specifically: Step S101: Images of all slots are acquired using a camera, and then the images are preprocessed to obtain the Mark points marking the wafer edges. The preprocessing includes noise reduction and edge extraction. The edge extraction uses a sub-pixel-level edge detection algorithm within threshold segmentation technology, achieving a positioning accuracy of [insert accuracy here]. .

[0026] Step S102: Based on the predefined FOUP slot coordinate system, the actual slot number of the wafer is calculated according to the identified Mark point position using a pattern recognition algorithm.

[0027] Step S200: Based on the preset triple verification logic rules in the MES system, perform consistency verification on the wafer's bonding status, inspection structure, and process flow data to obtain the verification result; if the verification result is qualified, generate a qualified report; if the verification result is unqualified, proceed to step S300; specifically: Step S201: Verify using triple verification logic rules to obtain the corresponding verification results. The triple verification logic rules include bonding state consistency check, inspection result integrity check, and timestamp sequence check. Among them, the bonding state consistency check requires that wafers marked as "scrap" in the MES must not appear in the qualified product slots; the inspection result integrity check requires that all qualified wafers must be associated with complete and qualified microscope inspection reports; and the timestamp sequence check requires that the time when the inspector completes the operation must be later than the bonding completion time of the wafer.

[0028] Step S202: Establish the binding relationship between the wafer's unique ID and the entire process data, including the association between the bonding equipment number and the testing equipment number, whether the batch number of the adhesive used matches the mixing record, and whether the time error between the two is within the allowable range.

[0029] Step S300: Identify the anomaly type based on the verification result, and then select the anomaly response mechanism based on the anomaly type.

[0030] The anomaly types include slot misalignment, state logic error, and missing binding relationship.

[0031] Select the exception response mechanism based on the exception type, including: When the anomaly type is slot misalignment, a moving error correction process is used to grab the wafer from the wrong slot and move it back to the correct slot, followed by a second scan for confirmation. When the exception type is a status logic error, the entire box of wafers is locked to prevent it from being shipped out, and a rework order is generated, requiring manual review and processing. When the exception type is missing binding relationship, a data traceability work order is generated to notify relevant personnel to supplement the association information.

[0032] This invention provides a dual-verification error prevention method integrating visual positioning and data comparison. The method acquires the physical slot information of the wafer within the wafer transfer box (FOUP) using a visual positioning system and compares it with the original slot information recorded in the manufacturing execution system (MES). Then, a data comparison engine verifies the bonding status of the wafer, the logical consistency of the inspection results, and the correlation and integrity of the process flow data. When the above comparison detects an anomaly, the corresponding automatic error correction or process-oriented processing mechanism is triggered according to the anomaly type to achieve a closed loop of error prevention.

[0033] Example Step S100: A high-precision industrial camera deployed above the exit gate acquires images of the wafers within the FOUP. Through image processing and recognition algorithms, the actual physical slot location of each wafer is accurately obtained, including: In step S101, image acquisition and preprocessing, the camera acquires images with a field of view covering all 25 slots. The images are then preprocessed, including: applying Gaussian filtering to suppress noise; extracting Mark points on the wafer edges using threshold segmentation technology; and employing a sub-pixel-level edge detection algorithm to accurately locate the center coordinates of the Mark points, achieving a positioning accuracy of ±0.2μm. In step S102, the slot identification algorithm calculates the actual slot number of the wafer based on the identified Mark point position, using a predefined FOUP slot coordinate system. An optimized pattern recognition algorithm then compares the identified actual slot with the original slot information recorded in the MES system to verify consistency. The allowable physical position deviation is ±0.3mm. The FOUP slot coordinate system (origin at the upper left corner, unit: mm) has a slot spacing of 5mm × 5mm. def calculate_slot_position(x, y): row = int((y - y_offset) / slot_height) + 1 col = int((x - x_offset) / slot_width) + 1 return f"Slot {row*5 + col - 5 if row>1 else col}".

[0034] Step 200: Retrieve production logs and inspection reports from the MES system. Based on multiple preset logical rules, perform a deep consistency check on the wafer bonding status, inspection results, and process flow data, including: In step S201, a state logic verification is performed to verify the following triple logical relationship: 1) Bonding status consistency inspection: Wafers marked as "scrap" in MES must not appear in qualified product slots.

[0035] 2) Inspection of the completeness of inspection results: All qualified wafers must be associated with a complete and qualified microscope inspection report (e.g., the bonding offset must be less than 1μm). 3) Timestamp sequence check: The time when the inspector completes the operation must be later than the bonding completion time of the wafer.

[0036] In step S202, a binding relationship is established for traceability. Data throughout the entire process is traced using the wafer's unique ID, and the following is verified: The correlation between the bonding device number (e.g., Bond004) and the testing device number (e.g., Insp002); The batch number of the glue used must match the mixing record, and the time difference between the two must be within the allowable range. In other words, the time matching between the glue batch and the mixing record must be verified.

[0037] If the verification result is satisfactory, a satisfactory report is generated; otherwise, proceed to step S300.

[0038] Step S300: Based on the verification results, execute the preset handling procedures for different types of anomalies.

[0039] Automatic error correction: When a wafer slot misplacement is detected, the system instructs a high-precision robotic arm (with a repeatability of ±0.05mm) to pick up the wafer from the incorrect slot and move it back to the correct slot, followed by a second scan for confirmation.

[0040] In this embodiment, the method reduces the slot misplacement rate from 3% to below 0.05%; the defective wafer misjudgment rate is basically reduced to zero; the outgoing inspection time is shortened from 10 minutes / box to 30 seconds / box, improving efficiency by 20 times; the production line first pass rate is increased by 2%~3%; and the reliance on manpower and personnel experience is reduced through automation and standardization, fundamentally improving product quality stability.

[0041] The present invention also discloses a dual verification error prevention system integrating visual positioning and data comparison, used to implement the dual verification error prevention method integrating visual positioning and data comparison. The first module obtains the actual physical slot of each wafer based on the slot image and the predefined FOUP slot coordinate system. The second module performs consistency verification on the bonding status, inspection structure, and process flow data of the wafer based on the preset triple verification logic rules in the MES system, and obtains the verification results; if the verification results are qualified, a qualified report is generated; if the verification results are unqualified, step S300 is performed. The third module identifies the anomaly type based on the verification results, and then determines the anomaly response mechanism based on the different anomaly types.

[0042] At the hardware level, such as Figure 2 As shown, the system includes an industrial camera, a robotic arm, an RFID reader, an industrial control system, and a MES system. The industrial camera is used to acquire images of the wafer slots; the robotic arm, controlled by a PLC controller, is used to automatically pick up and reset misplaced wafers in the slots; the RFID reader is used to read the wafer ID of the wafers; the industrial control system is used to process the data transmitted from the industrial camera, robotic arm, and RFID reader; and the MES system is used to receive data from the industrial control system and transmit the corresponding data back to the industrial control system.

[0043] At the software layer, a vision algorithm module was designed, which integrates the OpenCV image library to support mark point detection and slot recognition, with a processing speed of 20ms / wafer. A data comparison engine was also designed, which has 12 preset logical verification rules and supports custom extensions. In addition, a 3D visualization of the FOUP slot layout was designed, with abnormal slots flashing red and accompanied by voice prompts (such as "Slot 7 wafer misplaced, please check").

[0044] The system extracts wafer marker points using a high-precision industrial camera (5472×3648 pixels), achieving sub-pixel-level positioning accuracy. 0.2μm, HOG+SVM algorithm identifies slot number (accuracy 99.98%), compared with 12 status logic rules (such as defective wafers cannot enter qualified slots, inspection time). (bonding time), combined with matching of glue batch and mixing records (time error) 5 minutes), robotic arm ( Automatic error correction (0.05mm accuracy) constructs a closed-loop system for positioning, verification, and correction to prevent errors. A dual-verification standard is established for outbound inspection to ensure consistent slot position error. With a precision of 0.3mm, the false rejection rate for scrapped wafers decreased from 0.8% to 0, meeting the stringent requirements of SEMI E179 for outbound inspection of semiconductor products. The automated error-proofing process replaced manual visual inspection, increasing inspection efficiency tenfold and reducing anomaly handling time from 2 hours to 15 minutes. The "Bonding Site Operation Specifications" were established to reduce quality risks caused by human factors.

[0045] This system combines visual positioning (misplacement rate 0.05%) with data comparison (state misjudgment rate 0%), reducing the missed detection rate of bonded wafers from 1% to 0.01%, improving error prevention capability by 99%. It also uses a robotic arm to automatically adjust misplaced wafers, reducing processing time from 2 minutes / wafer to 15 seconds / wafer, improving efficiency by 87.5%. At the same time, it uses a 3D screen in the industrial control system to display the slot status in real time, with abnormal slots flashing red and providing voice prompts, reducing the operation error rate by 70%.

[0046] Figure 3 The data shows that the method proposed in this invention is significantly better than single-vision verification and manual verification in reducing the "misplacement rate". The manual verification method has the highest misplacement rate and has an overwhelming advantage in quality assurance. This proves the key role of the dual verification error prevention method proposed in this invention in improving detection accuracy and reducing quality risks.

[0047] This invention also discloses a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the method. The processor may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing and control core of the terminal, and is suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions from a computer storage medium to implement the corresponding method flow or corresponding function. This invention also discloses a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method. The computer-readable storage medium is a memory device in a computer device used to store programs and data. It is understood that the computer-readable storage medium here can include both built-in storage media in the computer device and extended storage media supported by the computer device. The computer-readable storage medium provides storage space containing the terminal's operating system. Furthermore, this storage space also contains one or more instructions suitable for loading and execution by a processor; these instructions can be one or more computer programs (including program code). It should be noted that the computer-readable storage medium here can be high-speed RAM or non-volatile memory, such as at least one disk storage device. The processor can load and execute one or more instructions stored in the computer-readable storage medium.

[0048] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0049] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0050] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0051] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0052] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the functions specified in one or more boxes. Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

[0053] The above description is merely a preferred embodiment of the present invention and is not intended to limit the technical solution of the present invention in any way. Those skilled in the art should understand that, without departing from the spirit and principles of the present invention, the technical solution can be modified and replaced in several simple ways, and these modifications and replacements are all within the scope of protection covered by the claims.

Claims

1. A dual-verification error-proofing method integrating visual positioning and data comparison, characterized in that, include: Step S100: Based on the slot image and the predefined FOUP slot coordinate system, obtain the actual physical slot of each wafer; Step S200: Based on the preset triple verification logic rules in the MES system, perform consistency verification on the bonding status, inspection structure and process flow data of the wafer to obtain the verification results. If the verification result is qualified, a qualified report is generated; if the verification result is unqualified, proceed to step S300. Step S300: Identify the anomaly type based on the verification result, and then select the anomaly response mechanism based on the anomaly type.

2. The dual-verification error prevention method integrating visual positioning and data comparison according to claim 1, characterized in that, Step S100: Based on the slot image and the predefined FOUP slot coordinate system, obtain the actual physical slot of each wafer, including: Step S101: Use a camera to acquire images of all slots, and then preprocess the images to obtain the Mark points on the wafer edge. Step S102: Based on the predefined FOUP slot coordinate system, the actual slot number of the wafer is calculated according to the identified Mark point position using a pattern recognition algorithm.

3. The dual-verification error prevention method integrating visual positioning and data comparison according to claim 2, characterized in that, In S101, preprocessing includes noise reduction and edge extraction. The edge extraction employs a sub-pixel-level edge detection algorithm within threshold segmentation technology, achieving a positioning accuracy of [insert accuracy here]. .

4. The dual-verification error prevention method integrating visual positioning and data comparison according to claim 3, characterized in that, S200, based on the preset triple verification logic rules in the MES system, performs consistency verification on the wafer's bonding status, inspection structure, and process flow data, obtaining verification results, including: Step S201: Perform verification using triple verification logic rules to obtain the corresponding verification results: Triple verification logic rules include bond state consistency check, verification result integrity check, and timestamp order check; Step S202: Establish the binding relationship between the wafer's unique ID and the entire process data, including the association between the bonding equipment number and the testing equipment number, whether the batch number of the adhesive used matches the mixing record, and whether the time error between the two is within the allowable range.

5. The dual-verification error prevention method integrating visual positioning and data comparison according to claim 4, characterized in that, In step S201, the bonding status consistency check requires that wafers marked as "scrap" in the MES must not appear in the qualified product slots; the inspection result integrity check requires that all qualified wafers must be associated with a complete and qualified microscope inspection report; and the timestamp sequence check requires that the time when the inspector completes the operation must be later than the bonding completion time of the wafer.

6. The dual-verification error prevention method integrating visual positioning and data comparison according to claim 1, characterized in that, In step 300, the exception types include slot misalignment, state logic error, and missing binding relationship.

7. The dual-verification error prevention method integrating visual positioning and data comparison according to claim 6, characterized in that, Select the exception response mechanism based on the exception type, including: When the anomaly type is slot misalignment, a moving error correction process is used to grab the wafer from the wrong slot and move it back to the correct slot, followed by a second scan for confirmation. When the exception type is a status logic error, the entire box of wafers is locked to prevent it from being shipped out, and a rework order is generated, requiring manual review and processing. When the exception type is missing binding relationship, a data traceability work order is generated to notify relevant personnel to supplement the association information.

8. A dual-verification error prevention system integrating visual positioning and data comparison, used to implement the dual-verification error prevention method integrating visual positioning and data comparison as described in any one of claims 1 to 7, characterized in that, include: The first module obtains the actual physical slots of each wafer based on the slot image and the predefined FOUP slot coordinate system; The second module performs consistency verification on the bonding status, inspection structure, and process flow data of the wafer based on the preset triple verification logic rules in the MES system, and obtains the verification results. If the verification result is qualified, a qualified report is generated; if the verification result is unqualified, proceed to step S300. The third module identifies the anomaly type based on the verification results, and then determines the anomaly response mechanism based on the different anomaly types.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1-7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1-7.

Images