Multi-level adaptive gate drive control

Abstract

Apparatus and related methods of the present disclosure relate to a gate drive timing controller (GDTC). In one exemplary embodiment, the GDTC may generate a power stage activation signal (PSAS) to control the output current of the MOSFET of the power stage. The three pull-up transistors may be electrically connected in parallel to the control output configured to generate a PSAS as a function of a switching node voltage (Vsw) and a source inductance voltage (VLS) of the MOSFET. The first pull-up transistor may be activated upon receiving a PWM signal of a power stage and deactivated according to VLS. The second pull-up transistor may be synchronized with the PWM signal. The third pull-up transistor may be activated when Vsw is detected. Various embodiments may adaptively generate the PSAS to reduce the on-loss of the MOSFET while maintaining a lower transient voltage spike.

Description

Technical Field

[0001] Various embodiments of the present invention generally relate to the fields of power electronics and circuit control. Background Technology

[0002] Hard switching power converters (HSPCs) may include power electronic devices configured to manage the conversion of electrical energy between different voltage levels. In some examples, an HSPC may control the switching between on and off states while maintaining the load current supplied to a (high-power) load. In some examples, an HSPC may include a half-bridge configuration. For example, a half-bridge configuration may include two switches (e.g., two metal-oxide-semiconductor field-effect transistors (MOSFETs)) connected in series between a power source and ground. For example, the connection point between these two switches may form a switching node that defines the output voltage or current supplied to the load.

[0003] For example, the switching node voltage can include the voltage at the connection point between the two MOSFETs in a half-bridge configuration. This voltage can affect the voltage supplied to the load. For example, the load may be connected between the switching node and ground. In some examples, the load may be connected between the switching node and the positive power supply. The behavior of the switching node voltage during MOSFET switching events can determine the (transient and / or steady-state) output power of the HSPC.

[0004] For example, in high-power applications, an HSPC may include multiple MOSFETs connected in parallel. For instance, the MOSFETs connected in parallel may have different response characteristics (e.g., different parasitic impedances, voltage thresholds). Summary of the Invention

[0005] The apparatus and related methods of the present invention relate to a gate drive timing controller (GDTC). In one exemplary embodiment, the GDTC can generate a power stage activation signal (PSAS) to control the output current of a MOSFET in a power stage. For example, three pull-up transistors can be connected in parallel to the control output, configured to generate the PSAS based on the switching node voltage (Vsw) and the source inductance voltage (VLS) of the MOSFET. For example, a first pull-up transistor can be activated upon receiving a PWM signal from the power stage and deactivated based on VLS. For example, a second pull-up transistor can be synchronized with the PWM signal. For example, a third pull-up transistor can be activated upon detecting Vsw. Various embodiments can adaptively generate the PSAS to reduce MOSFET turn-on losses while maintaining low transient voltage spikes.

[0006] Various embodiments can achieve one or more advantages. For example, some embodiments can advantageously reduce the turn-on losses of MOSFETs in the power stage (e.g., connected in parallel). For example, some embodiments can automatically adapt the power stage activation signal to different load currents. For example, some embodiments can advantageously reduce the turn-off losses of MOSFETs (e.g., connected in parallel). For example, some embodiments can automatically adapt the power stage deactivation signal to different load currents.

[0007] Details of various embodiments are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the specification, drawings, and claims. Attached Figure Description

[0008] Figure 1 This illustrates the application of an exemplary adaptive power control system (APCS) in an exemplary use case.

[0009] Figure 2 An exemplary circuit diagram illustrating a multi-level gate control circuit (MSGCC).

[0010] Figure 3 A block diagram illustrating exemplary timing control logic.

[0011] Figure 4 A flowchart illustrating an exemplary adaptive power level activation signal generation method.

[0012] Figure 5 This is an exemplary circuit diagram of an MSGCC that includes a multi-stage shutdown timing scheme.

[0013] Figure 6 A block diagram illustrating exemplary timing control logic for a multi-level shutdown timing scheme.

[0014] The same reference symbols in the various figures denote the same elements. Detailed Implementation

[0015] Figure 1 This illustrates the application of an exemplary adaptive power control system (APCS) in an exemplary use case. In the illustrated example, APCS 100 includes a motor 105 electrically connected to a high-side switching power package (HSPP 110) and a low-side switching power package (LSPP 115). For example, HSPP 110 and LSPP 115 may include silicon (Si) power devices.

[0016] For example, motor 105 may include a hard-switching power converter configured to power motor 105. For example, HSPP 110 and LSPP 115 may be configured in a half-bridge topology. In some embodiments, motor 105 may include high-power applications. For example, motor 105 may include a high-power AC motor.

[0017] In some embodiments, HSPP 110 and LSPP 115 may include switching circuitry. In this example, HSPP 110 and LSPP 115 are connected in series to receive power from DC power supply 120. In some embodiments, HSPP 110 and LSPP 115 may include a plurality of parallel-connected switching transistors (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) configured to supply high current to motor 105. For example, HSPP 110 may include a plurality of parallel-connected power MOSFETs. For example, each power MOSFET may include a source terminal operatively coupled to DC power supply 120.

[0018] In some embodiments, multiple MOSFETs connected in parallel can share the current load to motor 105. For example, multiple MOSFETs connected in parallel can advantageously reduce the overall on-resistance (Rds(on)) of APCS100. In some examples, HSPP 110 and LSPP 115 can be implemented on a printed circuit board (PCB).

[0019] As shown in the figure, HSPP 110 receives a first switching control signal (VGHS) from the high-side power drive circuit (HDM 125), and LSPP 115 receives a second switching control signal (VGLS) from the low-side power drive circuit (LDM 130). For example, HDM 125 and LDM 130 can be configured to control HSPP 110 and LSPP 115 to maintain the voltage and current at switching node 135 at levels suitable for motor 105. For example, APCS 100 can be configured to generate VGHS and VGLS based on the start-up drive scheme in the motor drive application.

[0020] As shown in the figure, HDM 125 receives a control input (pulse width modulation (PWM) signal). HDM 125 includes an adaptive control circuit (AACC 140) that generates VGHS to HSPP 110 based on the PWM signal. In some embodiments, AACC 140 may include timing control logic that generates VGHS based on the sensing input of sensing module 150.

[0021] The sensing module 150 includes a source inductor voltage sensor 155 and a switch node voltage sensor 160. For example, the switch node voltage sensor 160 may be configured to sense at switch node 135 (e.g., based on a predetermined voltage threshold detection). In some embodiments, the source inductor voltage sensor 155 may be configured to measure the bond line voltage of the MOSFET in the HSPP 110. In some embodiments, the source inductor voltage sensor 155 may be configured to measure the copper clip voltage of the MOSFET in the HSPP 110. For example, the source inductor voltage sensor 155 may sense the voltage across the capacitance and inductance of the bond lines in the HSPP 110 package. In some examples, the source inductor voltage sensor 155 may sense the voltage across the inductance of the parasitic inductance of the source terminal of a PCB trace connected to the HSPP 110.

[0022] In some embodiments, AACC 140 can be configured to adaptively time-control VGHS based on the transient response of switching node 135 and the source inductor voltage of HSPP 110 after being activated by a PWM signal. In some examples, AACC 140 can advantageously control the switching losses of HSPP 110 without sacrificing voltage spikes during the transient state of HSPP 110.

[0023] As a non-limiting example, in medium-voltage and / or high-voltage hard-switching power converter topologies, there may be a trade-off between voltage spikes and / or electromagnetic interference (EMI) requirements and switching losses when adjusting the gate drive speed. For example, AACC 140 can be configured to adaptively adjust the turn-on speed of HSPP 110 based on source inductor voltage sensing 155 and switching node voltage sensing 160 to limit voltage spikes during the transient transition of the MOSFET of HSPP 110 from the off state to the on state. Various embodiments can advantageously reduce the turn-on losses of MOSFETs (e.g., connected in parallel) in APCS100.

[0024] In some embodiments, the APCS100 can be configured to include multiple power stages (e.g., high-side and low-side). For example, the multiple power stages can be activated by a multi-stage turn-on power stage activation signal (e.g., VGHS and VGLS). In some embodiments, the multi-stage turn-on power stage activation signal can be generated by the AACC 140 based on sensed MOSFET source inductance voltage and switching node voltage. Various embodiments can advantageously automate power stage activation signals for different load currents (e.g., for AC motor drive applications). In some examples, the AACC 140 can be configured to reduce switching losses without sacrificing the voltage spike requirements of the HSPP 110.

[0025] In various embodiments, the gate drive timing control unit (e.g., APCS 100) may include a control output (e.g., VGHS) operatively coupled to the gate terminal of a power metal-oxide-semiconductor field-effect transistor (power MOSFET) and configured to generate a power stage activation signal to control the power stage of the gate drive timing control unit (e.g., HSPP 110). For example, a PWM signal may be configured to control the output current of the power MOSFET to a load (e.g., motor 105). For example, a sensing circuit (e.g., sensing module 150) may be coupled to the power MOSFET to measure the switching node voltage and source inductor voltage of the power MOSFET. For example, the gate drive timing control unit may include adaptive control circuitry (e.g., AACC 140) configured to generate the power stage activation signal based on the switching node voltage and source inductor voltage. For example, the power stage activation signal may be adaptively generated based on dynamic load conditions to reduce the turn-on losses of the power MOSFET while maintaining low transient voltage spikes.

[0026] Figure 2 This is an exemplary circuit diagram illustrating a multi-level gate control circuit (MSGCC). In this example, MSGCC 200 includes HDM 125 and LDM 130. Some electronic components of HDM 125 are... Figure 2 As depicted in the figure. In some examples, LDM 130 may include an electronic structure similar to that of HDM 125 (e.g., and / or its mirror image).

[0027] In the illustrated example, the AACC 140 of HDM 125 includes timing control logic 205 and three pull-up MOSFETs 210 (pullup1, pullup2, and pullup3). In some embodiments, the timing control logic 205 may generate pull-up stage signals to (independently) control the three pull-up MOSFETs 210. For example, the timing control logic 205 may be activated by a PWM signal. For example, the gate terminal of the power MOSFET 230 in HDM 125 may receive a control signal from a combination (e.g., aggregation) of the outputs of the three pull-up MOSFETs 210. As shown, the timing control logic 205 may receive input from the sensing module 150.

[0028] In this example, sensing module 150 can be configured to sense the voltage at the MOSFET source bond line (e.g., clamp voltage) at source bond line point 215 and the voltage at switching node 135. For example, source inductor voltage sensing 155 can be configured to determine the voltage based on a comparison between the switching node voltage at switching node 135 and the bond line voltage at source bond line point 215.

[0029] As shown in the figure, HDM 125 can generate VGHS by connecting the source terminals of three pull-up MOSFETs 210 (Pullup1, Pullup2, and Pullup3 in this example) in parallel to the gate terminals of each parallel-connected power MOSFET of a high-side switch (HS switch 220). For example, HSPP 110 may include HS switch 220. As shown in the figure, each power MOSFET of HS switch 220 may include different parasitic inductances and resistances 225a, 225b. For example, the voltage between k and s may be the induced voltage of the voltage drop across the source inductor. For example, the source inductor may indicate the change in current flowing through the MOSFET source terminals of HS switch 220.

[0030] Figure 3 This diagram illustrates an exemplary timing control logic 300. For example, timing control logic 205 may include timing control logic 300. As shown, timing control logic 300 includes three outputs, S_pullup1, S_pullup2, and S_pullup3. For example, each S_pullup1, S_pullup2, and S_pullup3 can control three pull-up MOSFETs 210, pullup1, pullup2, and pullup3, respectively.

[0031] For example, timing control logic 300 can be configured to generate power stage activation signals for multi-stage drive schemes. Figure 1 The timing control logic 300 can be configured to adaptively generate power stage activation signals for multi-stage drive schemes under different load conditions (VGHS) to reduce MOSFET turn-on losses while maintaining low transient voltage spikes.

[0032] As shown in the figure, the first stage 305 includes a set-reset latch (SR latch 310). For example, S_pullup1 can be configured to activate the pullup1 MOSFET when the SR latch 310 is set. As shown in the figure, the SR latch 310 is set by edge detection 315 of the PWM signal (e.g., as shown in the figure). Figure 1 (as described above). For example, the first stage 305 can be a fast-turn-on state initiated by a PWM signal. For example, the first stage 305 can include a low pull-up resistor to facilitate a fast turn-on response. In the example shown, the first stage 305 can terminate upon detection of a source inductor voltage. For example, the source inductor voltage can be determined by detecting that VLS is greater than a predetermined reference voltage (Vref1). In this example, the SR latch 310 can be reset after a predetermined delay 320 after detecting the source inductor voltage.

[0033] The timing control logic 300 includes a second stage 325. In some embodiments, the second stage 325 can be configured as a damping stage. For example, the second stage 325 can be connected to a high pull-up resistor. For example, the second stage 325 can be synchronized with a PWM signal.

[0034] The timing control logic 300 includes a third stage 330. In some embodiments, the third stage 330 can be configured as a fast enhancement stage. As shown, the third stage 330 includes a second SR latch 335. For example, the third stage 330 can be activated upon detection of a switching node voltage. In some examples, the third stage 330 can accelerate (e.g., cause) the turn-on of the HDM 125 after a change in the switching node voltage is detected.

[0035] As shown in the figure, S_pullup3 is set by the detection that the switching node voltage is higher than a predetermined second reference voltage (Vref2) and the PWM signal. S_pullup3 is reset by the inversion of the PWM signal (e.g., when the power stage is deactivated). In some embodiments, the third stage 330 can be activated by control logic based on the source inductor voltage VLS.

[0036] Figure 4 This is a flowchart illustrating an exemplary adaptive power stage activation signal generation method. For example, method 400 may be executed by timing control logic 300. In this example, method 400 begins at step 405 when a PWM signal is received from the controller to generate a power stage activation signal by combining the outputs from first, second, and third pull-up signals. For example, timing control logic 300 of AACC 140 may receive the PWM signal received by AACC 140.

[0037] In step 410, the first and second pull-up signals are activated. For example, timing control logic 300 can activate the S_pullup1 and S_pullup2 signals to drive the pull-up MOSFET 210.

[0038] At decision point 415, it is determined whether a source inductor voltage is detected. For example, timing control logic 300 can compare the sensed source inductor voltage with a predetermined threshold. If a source inductor voltage is detected, the first pull-up signal is activated after a predetermined time in step 420. For example, timing control logic 300 can activate S_pullup1 after a delay based on the sensed source inductor voltage. If no source inductor voltage is detected, decision point 415 is repeated.

[0039] Following step 410, through parallel operation, it is determined at decision point 425 whether a switch node voltage higher than a predetermined voltage is detected. For example, timing control logic 300 may check whether the switch node voltage (e.g., the V_SW_sense signal) exceeds a set reference voltage. If the switch node voltage is higher than the predetermined voltage, a third pull-up signal is activated in step 430. For example, timing control logic 300 may activate S_pullup3 to accelerate the opening of HS switch 220. If the switch node voltage is not higher than the predetermined voltage, decision point 425 is repeated.

[0040] At decision point 435, it is determined whether the PWM signal has been deactivated. For example, timing control logic 300 can check whether the PWM signal is no longer active. If the PWM signal has been deactivated, the second and third pull-up signals are deactivated in step 440. For example, timing control logic 300 can deactivate S_pullup2 and S_pullup3 to turn off the corresponding pull-up MOSFET 210, and method 400 ends.

[0041] While some exemplary control methods describe multi-stage turn-on using connected power semiconductor devices, multi-stage turn-off schemes based on source inductor voltage can be used to control the timing of gate signals. For example, multi-stage turn-off control logic can be implemented independently of and / or in conjunction with a multi-stage turn-on scheme.

[0042] Figure 5 This diagram illustrates an exemplary circuit of an MSGCC that incorporates a multi-level shutdown timing scheme. In this example, the MSGCC500 includes timing control logic 505 operatively coupled to three pull-up MOSFETs 210 and three pull-down MOSFETs 510a, 510b, and 510c. For example, the timing control logic 505 can be configured according to... Figure 2-3 The timing logic controls three pull-up MOSFETs 210. In various embodiments, the timing control logic 505 can adaptively control the gate turn-off signal based on the PWM signal and the sensed source inductor voltage VLS_Sense. For example, the timing control logic 505 can advantageously reduce the turn-off losses of the (e.g., parallel-connected) MOSFETs in the power stage (e.g., HS switch 220). For example, when active, the three pull-down MOSFETs 510a, 510b, and 510c can pull down the power stage activation. For example, some embodiments can advantageously adaptively control the turn-off scheme of the power stage activation signal to adapt to different load currents.

[0043] In some embodiments, a gate control signal (e.g., VGHS) can be generated as an aggregate of the outputs of three pull-down MOSFETs 510a, 510b, and 510c. For example, when the power stage (e.g., HS switch 220) is turned off by a PWM signal, the gate control signal can be generated in three stages. For example, in a first stage, the gate control signal can include a first turn-off signal configured to trigger a fast response of the power MOSFET controlled by the gate control signal (e.g., power MOSFET 230). For example, in a second stage, the gate control signal can include a damping signal configured to reduce voltage spikes in the power MOSFET. For example, in a third stage, the gate control signal can include a fast turn-off signal configured to accelerate (e.g., facilitate) the turn-off of the power MOSFET after a second-stage voltage spike during a switching transient.

[0044] Figure 6 This is a block diagram illustrating an exemplary timing control logic 600 for a multi-level shutdown timing scheme. For example, timing control logic 505 may include timing control logic 600. As shown, timing control logic 600 includes three outputs, S_pulldown1, S_pulldown2, and S_pulldown3. For example, each of S_pulldown1, S_pulldown2, and S_pulldown3 can control three pull-down MOSFETs 510a, 510b, and 510c, respectively.

[0045] For example, timing control logic 600 can be configured to generate power stage gate signals for a multi-stage drive scheme to reduce MOSFET turn-off losses while maintaining low transient voltage spikes. For example, timing control logic 600 can be configured to adaptively generate power stage gate signals for a multi-stage drive scheme under different load conditions.

[0046] In this example, the first pull-down stage 605 includes a set-reset latch (SR latch 610). For example, S_pulldown1 can be configured to pull down the gate voltage at HS switch 220 when SR latch 610 is set. As shown, SR latch 610 is set by edge detection 615 of the PWM signal (e.g., as shown in the figure). Figure 1 (as described above). For example, S_pulldown1 can be triggered by the falling edge of the PWM signal. For example, the first stage 605 can be a fast shutdown state initiated by the PWM signal. In the example shown, the first stage 305 can end when the integral of the sensed source inductor voltage (VLS) is lower than a predetermined negative reference voltage (Vref1 620) (e.g., a reset of the SR latch 610).

[0047] The timing control logic 600 includes a second stage 625. In some embodiments, the second stage 625 may be configured as a damping stage. For example, the second stage 625 may be synchronized with a PWM signal.

[0048] The timing control logic 600 includes a third stage 630. The third stage 630 includes a second SR latch 635 connected to the output signal (S_pulldown3). As shown, S_pullup3 is set when the derivative of the sensed source inductor voltage (VLS) is higher than a predetermined positive reference voltage (Vref2 640). S_pullup3 is reset by a PWM signal. Various embodiments can adaptively adjust the turn-off timing of the HS switch 220 based on the source inductor voltage.

[0049] Although various embodiments have been described with reference to the accompanying drawings, other embodiments are also possible. For example, various transistors may be described as p-channel MOSFETs or n-channel MOSFETs. In some embodiments, these transistors can be adapted to different types of MOSFETs by changing some connections in the circuit.

[0050] Although an exemplary system has been described with reference to the accompanying drawings, other embodiments may be deployed in other industrial, scientific, medical, commercial and / or residential applications.

[0051] In some embodiments, the APCS100 can be used in industrial machinery. For example, the motor 105 may include a high-power AC motor for driving pumps and compressors, used in industries such as oil and gas, water treatment, and chemical processing. For example, the motor 105 can power a conveying system for moving heavy materials and / or products.

[0052] In some embodiments, APCS100 can be used to drive a motor in mining equipment. For example, motor 105 can be configured to operate large excavating equipment and drilling rigs. For example, APCS100 can be configured to drive crushing and grinding equipment in mining operations.

[0053] In some embodiments, the APCS100 can be used to drive a high-power AC motor in an induction heating system (e.g., a furnace for melting and processing metals at high temperatures). In some examples, the APCS100 can be used to drive the propulsion motor of electric trains and locomotives.

[0054] In some embodiments, the APCS100 can be used to drive motors in a factory (e.g., in manufacturing applications). In some examples, the APCS100 can be configured to drive motors to operate construction equipment, including, for example, cranes and hoists for lifting and moving heavy objects.

[0055] In one exemplary aspect, the gate drive timing control unit may include a control output operatively coupled to the gate terminal of a power metal-oxide-semiconductor field-effect transistor (power MOSFET). For example, the gate drive timing control unit may be configured to generate a power stage activation signal to control the power stage of the gate drive timing control unit. For example, the power stage activation signal may be configured to control the output current from the power MOSFET to a load.

[0056] For example, the gate drive timing control unit may include sensing circuitry coupled to the power MOSFET, configured to measure the switching node voltage and source inductor voltage of the power MOSFET. For example, the gate drive timing control unit may include at least three pull-up transistors electrically connected in parallel to the control output, configured to generate a power stage activation signal based on the switching node voltage and source inductor voltage.

[0057] For example, the first pull-up transistor of at least three pull-up transistors can be configured to activate upon receiving a PWM signal. For example, the first pull-up transistor can be activated based on the source inductor voltage.

[0058] For example, the second pull-up transistor of at least three pull-up transistors can be configured to synchronize with the PWM signal. For example, the third pull-up transistor of at least three pull-up transistors can be configured to activate when a switching node voltage is detected.

[0059] For example, the control output can be an aggregation of the outputs of a first pull-up transistor, a second pull-up transistor, and a third pull-up transistor. For example, when the power stage is turned on by a PWM signal, the control output can be generated in three stages. For example, in the first stage, the control output can include a first turn-on signal configured to trigger a fast response of the power MOSFET. For example, in the second stage, the control output can include a damping signal configured to reduce voltage spikes in the power MOSFET. For example, in the third stage, the control output can include a fast boost signal configured to accelerate the turn-on of the power MOSFET upon detecting a change in the switching node voltage.

[0060] For example, at least three pull-up transistors may include a first pull-up transistor control circuit coupled to the first pull-up transistor. For example, the first pull-up transistor control circuit may include a set-reset latch configured to generate timing signals based on the set and reset states of the set-reset latch. For example, the first pull-up transistor control circuit may include an edge detection circuit configured to set the set-reset latch when the edge detection circuit detects a PWM signal. For example, the first pull-up transistor control circuit may include a delay circuit configured to reset the set-reset latch when a positive difference exists between the source inductor voltage and the first reference voltage for a predetermined delay time set by the delay circuit. For example, the first pull-up transistor may be activated by a timing signal of the set-reset latch in the set state. For example, the first pull-up transistor may be deactivated by a timing signal of the set-reset latch in the reset state.

[0061] For example, the source inductance voltage can be determined by comparing the switching node voltage and the bond line voltage of the power MOSFET. For instance, the power MOSFET may be packaged in a printed circuit board, and measuring the bond line voltage could include measuring the parasitic inductance of the source terminal of the power MOSFET on the printed circuit board trace.

[0062] For example, the control output can be connected in parallel to the gate terminals of multiple power MOSFETs connected in parallel. For example, the multiple power MOSFETs connected in parallel can include variations in their threshold voltages.

[0063] The gate drive timing control unit may include at least three pull-down transistors electrically connected in parallel to the control output. For example, the at least three pull-down transistors are configured to pull down a power stage activation signal when activated. For example, a first pull-down transistor of the at least three transistors may be configured to activate by detecting the falling edge of a PWM signal. For example, a second pull-down transistor of the at least three transistors may be configured to synchronize with the PWM signal. For example, a third pull-down transistor of the at least three transistors may be configured to activate when the derivative of the source inductor voltage is higher than a predetermined positive reference voltage.

[0064] For example, the first pull-down transistor can be activated when the integral of the source inductor voltage is lower than a predetermined negative reference voltage.

[0065] For example, the control output may include the aggregation of the outputs of a first pull-down transistor, a second pull-down transistor, and a third pull-down transistor. For example, when the power stage is turned off by a PWM signal, the control output may be generated in three stages. For example, in the first stage, the control output may include a first turn-off signal configured to trigger a fast response of the power MOSFET. For example, in the second stage, the control output may include a damping signal configured to reduce voltage spikes in the power MOSFET. For example, in the third stage, the control output may include a fast turn-off signal configured to accelerate the turn-off of the power MOSFET after a voltage spike in the second stage.

[0066] In one exemplary aspect, the half-bridge gate driver may include a high-side drive module comprising a first instance of a gate drive timing control unit in the high side. For example, the half-bridge gate driver may include a low-side drive module. For example, the low-side drive module may include a second instance of a gate drive timing control unit in the low side. For example, the PWM signal of the first instance may be the inverted PWM signal of the second instance.

[0067] In one exemplary aspect, the gate drive timing control unit may include a control output operatively coupled to the gate terminal of a power metal-oxide-semiconductor field-effect transistor (power MOSFET) and configured to generate a power stage activation signal to control the power stage of the gate drive timing control unit. For example, the power stage activation signal may be configured to control the output current of the power MOSFET to a load. For example, the gate drive timing control unit may include sensing circuitry coupled to the power MOSFET, configured to measure the switching node voltage and source inductance voltage of the power MOSFET. For example, the gate drive timing control unit may include adaptive control circuitry configured to generate the power stage activation signal based on the switching node voltage and source inductance voltage. For example, the power stage may include a first stage triggered by a pulse width modulation signal (PWM signal) and terminated by detection of the source inductance voltage. For example, the power stage may include a second stage synchronized with the PWM signal. For example, the power stage may include a third stage triggered by detection of the switching node voltage. For example, the power stage activation signal may be generated adaptively based on load conditions.

[0068] For example, the adaptive control circuit may include at least three pull-up transistors connected in parallel to the control output. For example, a first pull-up transistor of the at least three transistors may be configured to activate upon receiving a PWM signal and deactivate based on the source inductor voltage. For example, a second pull-up transistor of the at least three transistors may be configured to synchronize with the PWM signal. For example, a third pull-up transistor of the at least three transistors may be configured to activate upon detecting a switching node voltage.

[0069] For example, the control output can be an aggregation of the outputs of a first pull-up transistor, a second pull-up transistor, and a third pull-up transistor. For example, when the power stage is turned on by a PWM signal, the control output can be generated in three stages. For example, in the first stage, the control output can include a first turn-on signal configured to trigger a fast response of the power MOSFET. For example, in the second stage, the control output can include a damping signal configured to reduce voltage spikes in the power MOSFET. For example, in the third stage, the control output can include a fast boost signal configured to accelerate the turn-on of the power MOSFET upon detecting a change in the switching node voltage.

[0070] For example, at least three pull-up transistors may include a first pull-up transistor control circuit coupled to the first pull-up transistor. For example, the first pull-up transistor control circuit may include a set-reset latch configured to generate timing signals based on the set and reset states of the set-reset latch. For example, the first pull-up transistor control circuit may include an edge detection circuit configured to set the set-reset latch when the edge detection circuit detects a PWM signal. For example, the first pull-up transistor control circuit may include a delay circuit configured to reset the set-reset latch when a positive difference exists between the source inductor voltage and the first reference voltage for a predetermined delay time set by the delay circuit. For example, the first pull-up transistor may be activated by a timing signal of the set-reset latch in the set state. For example, the first pull-up transistor may be deactivated by a timing signal of the set-reset latch in the reset state.

[0071] For example, the source inductor voltage can be determined based on a comparison of the switching node voltage and the bond line voltage of the power MOSFET.

[0072] For example, a power MOSFET can be packaged in a printed circuit board, and measuring the bond line voltage can include measuring the parasitic inductance of the source terminal of the power MOSFET on the printed circuit board trace.

[0073] For example, the control output can be connected in parallel to the gate terminals of multiple power MOSFETs connected in parallel. For example, the multiple power MOSFETs connected in parallel can include variations in their threshold voltages.

[0074] The gate drive timing control unit may include at least three pull-down transistors electrically connected in parallel to the control output. For example, the at least three pull-down transistors are configured to pull down a power stage activation signal when activated. For example, a first pull-down transistor of the at least three transistors may be configured to activate by detecting the falling edge of a PWM signal. For example, a second pull-down transistor of the at least three transistors may be configured to synchronize with the PWM signal. For example, a third pull-down transistor of the at least three transistors may be configured to activate when the derivative of the source inductor voltage is higher than a predetermined positive reference voltage.

[0075] For example, the first pull-down transistor can be activated when the integral of the source inductor voltage is lower than a predetermined negative reference voltage.

[0076] For example, the control output may include a combination of the outputs of a first pull-down transistor, a second pull-down transistor, and a third pull-down transistor. For instance, when the power stage is turned off by a PWM signal, the control output may be generated in three stages. For example, in the first stage, the control output may include a first turn-off signal configured to trigger a fast response of the power MOSFET. For example, in the second stage, the control output may include a damping signal configured to reduce voltage spikes in the power MOSFET. For example, in the third stage, the control output may include a fast turn-off signal configured to accelerate the turn-off of the power MOSFET after the voltage spike in the second stage.

[0077] In one exemplary aspect, the half-bridge gate driver may include a high-side drive module that includes a first instance of a gate drive timing control unit in the high side. For example, the half-bridge gate driver may include a low-side drive module. For example, the low-side drive module may include a second instance of a gate drive timing control unit in the low side. For example, the PWM signal received by the first instance may be the inverse of a second PWM signal received by the second instance.

[0078] In one exemplary aspect, the adaptive timing gate control signal generation method may include, upon receiving a pulse width modulation signal, generating a power stage activation signal comprising a first pull-up signal and a second pull-up signal, such that a plurality of power transistors are turned on by the power stage activation signal received at their respective gate terminals. For example, upon activation, the plurality of power transistors generate source inductor voltages and switching node voltages.

[0079] For example, an adaptive timing gate control signal generation method may include activating a first pull-up signal of a power stage activation signal after a predetermined delay when the source inductor voltage of a plurality of power transistors is detected.

[0080] For example, an adaptive timing gate control signal generation method may include activating a third pull-up signal upon detection of a switching node voltage. For instance, the power stage activation signal combines a first pull-up signal, a second pull-up signal, and a third pull-up signal as a function of the source inductor voltage and the switching node voltage, each depending on the load connected to the multiple power transistors. For example, the power stage activation signal can be adaptively generated based on load conditions to reduce turn-on losses of the multiple power transistors while maintaining low transient voltage spikes.

[0081] Many implementations have been described herein. However, it should be understood that various modifications can be made. For example, advantageous results can be obtained by performing the steps of the disclosed technology in a different order, by combining the components of the disclosed system in a different manner, or by supplementing the components with other components. Therefore, other embodiments can be contemplated within the scope of the following claims.

Claims

1. A gate drive timing control unit, comprising: a control output operably coupled to a gate terminal of a power metal oxide semiconductor field effect transistor (power MOSFET) and configured to generate a power stage activation signal to control a power stage of the gate drive timing control unit, wherein the power stage activation signal is configured to control an output current of the power MOSFET to a load; a sensing circuit coupled to the power MOSFET and configured to measure a switching node voltage and a source inductor voltage of the power MOSFET; and at least three pull-up transistors electrically connected in parallel to the control output and configured to generate the power stage activation signal based on the switching node voltage and the source inductor voltage, wherein: a first pull-up transistor of the at least three pull-up transistors is configured to activate upon receiving a PWM signal and deactivate based on the source inductor voltage; a second pull-up transistor of the at least three pull-up transistors is configured to synchronize with the PWM signal; and a third pull-up transistor of the at least three pull-up transistors is configured to activate upon detecting the switching node voltage.

2. The gate drive timing control unit of claim 1, wherein the control output is an aggregation of outputs of the first pull-up transistor, the second pull-up transistor, and the third pull-up transistor, wherein the control output is generated in three phases when the power stage is turned on by the PWM signal, wherein: in a first phase, the control output comprises a first turn-on signal configured to trigger a fast response of the power MOSFET; in a second phase, the control output comprises a damping signal configured to reduce voltage spikes of the power MOSFET; and in a third phase, the control output comprises a fast boost signal configured to accelerate the turn-on of the power MOSFET upon detecting a change in the switching node voltage.

3. The gate drive timing control unit of claim 1, wherein the at least three pull-up transistors comprise a first pull-up transistor control circuit coupled to the first pull-up transistor, wherein the first pull-up transistor control circuit comprises: a set-reset latch configured to generate a timing signal based on a set state and a reset state of the set-reset latch; an edge detection circuit configured to set the set-reset latch when the edge detection circuit detects the PWM signal; and a delay circuit configured to reset the set-reset latch when a positive difference between the source inductor voltage and a first reference voltage exists for a predetermined delay time set by the delay circuit, wherein the first pull-up transistor is activated by the timing signal of the set-reset latch in the set state and deactivated by the timing signal of the set-reset latch in the reset state.

4. The gate drive timing control unit of claim 1, wherein the source inductor voltage is determined based on a comparison of the switching node voltage and a bondwire voltage of the power MOSFET.

5. The gate drive timing control unit of claim 4, wherein the power MOSFET is packaged in a printed circuit board, and measuring the bondwire voltage comprises measuring a source terminal parasitic inductance of the power MOSFET of a trace of the printed circuit board.

6. The gate drive timing control unit of claim 1, wherein the control output is connected in parallel to gate terminals of a plurality of parallel connected power MOSFETs, wherein the plurality of parallel connected power MOSFETs comprise variations in threshold voltage.

7. The gate drive timing control unit of claim 1, further comprising at least three pull-down transistors electrically connected in parallel to the control output, wherein the at least three pull-down transistors are configured to pull down the power stage activation signal when activated, wherein: a first pull-down transistor of the at least three pull-down transistors is configured to activate by detecting a falling edge of a PWM signal; a second pull-down transistor of the at least three pull-down transistors is configured to activate in synchronization with the PWM signal; and, a third pull-down transistor of the at least three pull-down transistors is configured to activate when a derivative of a source inductance voltage is above a predetermined positive reference voltage.

8. The gate drive timing control unit of claim 7, wherein the control output comprises an aggregation of outputs of the first pull-down transistor, the second pull-down transistor, and the third pull-down transistor, wherein the control output generates in three phases when the power stage is turned off by the PWM signal, wherein: in a first phase, the control output comprises a first turn-off signal configured to trigger a fast response of the power MOSFET; in a second phase, the control output comprises a damping signal configured to reduce voltage spikes of the power MOSFET; and, in a third phase, the control output comprises a fast turn-off signal configured to accelerate turn-off of the power MOSFET after the voltage spikes of the second phase.

9. A half-bridge gate driver, comprising: a high-side drive module comprising a first instance of the gate drive timing control unit of claim 1 in a high-side; and, a low-side drive module comprising a second instance of the gate drive timing control unit of claim 1 in a low-side, wherein a PWM signal of the first instance is an inverse of a PWM signal of the second instance.

10. A gate drive timing control unit, comprising: a control output operably coupled to a gate of a power MOSFET configured to generate a power stage activation signal to control a power stage of the gate drive timing control unit, wherein the power stage activation signal is used to control an output current of the power MOSFET to a load; a sensing circuit coupled to the power MOSFET configured to measure a switching node voltage and a source inductance voltage of the power MOSFET; and an adaptive control circuit configured to generate the power stage activation signal based on the switching node voltage and the source inductance voltage, comprising: a first phase triggered by a PWM signal and ended upon detecting the source inductance voltage; a second phase synchronized with the PWM signal; and a third phase triggered by detecting the switching node voltage, wherein the power stage activation signal is adaptively generated according to a load condition.

11. The gate drive timing control unit of claim 10, wherein the adaptive control circuit comprises at least three pull-up transistors connected in parallel to the control output, wherein: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ a first pull-up transistor configured to activate upon receiving the PWM signal and deactivate based on the source inductor voltage; a second pull-up transistor configured to synchronize with the PWM signal; and a third pull-up transistor configured to activate upon detecting the switch node voltage.

12. The gate drive timing control unit of claim 11, wherein the control output is an aggregated output of the first, second, and third pull-up transistors, the control output generating in three phases when the power stage is turned on by the PWM signal, wherein: in the first phase, the control output comprises a first turn-on signal to trigger a fast response of the power MOSFET; in the second phase, the control output comprises a damping signal to reduce voltage spikes of the power MOSFET; and in the third phase, the control output comprises a fast boost signal to accelerate the turn-on of the power MOSFET upon detecting a change in the switch node voltage.

13. The gate drive timing control unit of claim 11, wherein the at least three pull-up transistors comprise a first pull-up transistor control circuit connected to the first pull-up transistor, the first pull-up transistor control circuit comprising: a set-reset latch configured to generate a timing signal based on a set state and a reset state of the set-reset latch; an edge detection circuit configured to set the set-reset latch upon detecting the PWM signal; and a delay circuit configured to reset the set-reset latch when a positive difference between the source inductor voltage and a first reference voltage lasts for a predetermined delay time set by the delay circuit, wherein the first pull-up transistor is activated by the timing signal when the set-reset latch is in the set state and deactivated by the timing signal when the set-reset latch is in the reset state.

14. The gate drive timing control unit of claim 10, wherein the source inductor voltage is determined based on a comparison between the switch node voltage and a bondwire voltage of the power MOSFET.

15. The gate drive timing control unit of claim 14, wherein the power MOSFET is packaged in a printed circuit board, and measuring the bondwire voltage comprises measuring a parasitic inductance of a source terminal of the power MOSFET on a trace of the printed circuit board.

16. The gate drive timing control unit of claim 10, wherein the control output is connected in parallel to gates of a plurality of parallel-connected power MOSFETs, the plurality of parallel-connected power MOSFETs having different threshold voltages.

17. The gate drive timing control unit of claim 10, further comprising at least three pull-down transistors connected in parallel to the control output and configured to pull down the power stage activation signal when activated, wherein: a first pull-down transistor is configured to activate upon detecting a falling edge of the PWM signal; a second pull-down transistor is configured to synchronize with the PWM signal; and a third pull-down transistor is configured to activate upon detecting a rising edge of the PWM signal. ​ ​ ​ A third pull-down transistor is configured to activate when a derivative of the source inductor voltage is higher than a predetermined positive reference voltage.

18. The gate drive timing control unit of claim 17, wherein the control output is an aggregate output of the first, second, and third pull-down transistors, and the control output is generated in three phases when the power stage is turned off by the PWM signal, wherein: in the first phase, the control output comprises a first turn-off signal to trigger a fast response of the power MOSFET; in the second phase, the control output comprises a damping signal to reduce voltage spikes of the power MOSFET; and in the third phase, the control output comprises a fast turn-off signal to accelerate the turn-off of the power MOSFET after the voltage spikes in the second phase.

19. A half-bridge gate driver, comprising: a high-side drive module comprising a first instance of the gate drive timing control unit of claim 1 in a high side; and a low-side drive module comprising a second instance of the gate drive timing control unit of claim 1 in a low side, wherein the PWM signal received by the first instance is inverted from the PWM signal received by the second instance.

20. A method of generating adaptive timing gate control signals, comprising: in response to receiving a PWM signal, generating a power stage activation signal comprising a first pull-up signal and a second pull-up signal to turn on a plurality of power transistors through the power stage activation signal received at corresponding gates, wherein the plurality of power transistors generate a source inductor voltage and a switching node voltage upon activation; after detecting the source inductor voltage of the plurality of power transistors, deactivating the first pull-up signal in the power stage activation signal after a predetermined delay; after detecting the switching node voltage, activating a third pull-up signal, wherein the power stage activation signal combines the first, second, and third pull-up signals as a function of the source inductor voltage and the switching node voltage, both of which are dependent on a load connected to the plurality of power transistors, such that the power stage activation signal is adaptively generated according to load conditions to reduce turn-on losses of the plurality of power transistors while maintaining low transient voltage spikes. ​ ​

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