Chip packaging assembly, electronic equipment and preparation method of chip packaging assembly

Abstract

The invention discloses a chip packaging assembly, electronic equipment and a preparation method of the chip packaging assembly. The chip packaging assembly comprises a first substrate layer group, a second substrate layer group and a packaging chip, wherein the second substrate layer group and the first substrate layer group are opposite to each other and are arranged at an interval; the packaging chip is located between the first substrate layer group and the second substrate layer group and comprises a bare chip, a first electroplated layer and a second electroplated layer, the bare chip comprises a first electrode surface and a second electrode surface which are arranged oppositely, the first electroplated layer is electrically connected with the first electrode surface and the first substrate layer group, and the second electroplated layer is electrically connected with the second electrode surface and the second substrate layer group. And the second electroplated layer is conductively connected with the second electrode surface and the second substrate layer group respectively. Therefore, heat generated by the bare chip can be directly transmitted to the first substrate layer group and the second substrate layer group through the electroplated layer, the heat dissipation performance of the packaged chip is improved, and the electrical performance of the packaged chip can also be improved.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to a chip packaging component, an electronic device, and a method for preparing the chip packaging component. Background Technology

[0002] As electronic devices continue to evolve towards thinner, lighter, and smaller designs, the performance requirements for the chip packaging components within these devices are becoming increasingly stringent. Consequently, the chip's temperature rises continuously during operation, affecting its overcurrent capacity and other capabilities. To improve the chip's heat dissipation performance, the structure of the chip packaging component must prioritize structures that provide excellent heat dissipation for the chip.

[0003] Existing chip packaging components include single-sided substrate cooling structures and double-sided substrate cooling structures. Double-sided substrate cooling structures mainly achieve thermal and electrical conduction by stacking multiple layers of pads and solder layers on the chip and then using copper pillars and other methods. This solution has a long heat conduction path, resulting in poor heat dissipation performance. Summary of the Invention

[0004] The main objective of this application is to provide a chip packaging component, an electronic device, and a method for manufacturing the chip packaging component, aiming to solve the aforementioned technical problems existing in the prior art.

[0005] To address the aforementioned problems, this application provides a chip packaging assembly comprising a first substrate layer group, a second substrate layer group, and a packaged chip. The second substrate layer group and the first substrate layer group are disposed opposite to and spaced apart. The packaged chip is located between the first substrate layer group and the second substrate layer group. The packaged chip includes a bare chip, a first electroplating layer, and a second electroplating layer. The bare chip includes a first electrode surface and a second electrode surface disposed opposite to each other. The first electroplating layer conductively connects the first electrode surface and the first substrate layer group, and the second electroplating layer conductively connects the second electrode surface and the second substrate layer group. Thus, the bare chip is conductively connected to the first substrate layer group through the first electroplating layer, and conductively connected to the second substrate layer group through the second electroplating layer. This allows heat generated by the bare chip to be directly transferred to the first substrate layer group and the second substrate layer group through the electroplating layers, improving the heat dissipation performance of the packaged chip. Furthermore, the first electroplating layer shortens the interconnection length between the bare chip and the first substrate layer group, and the second electroplating layer shortens the interconnection length between the bare chip and the second substrate layer group, thereby improving the electrical performance of the packaged chip.

[0006] In some embodiments, the bare chip includes a first electrode and a second electrode spaced apart on a first electrode surface. The first electroplating layer includes a first sub-electroplating layer and a second sub-electroplating layer spaced apart. The first sub-electroplating layer is electrically connected to the first electrode and the first substrate layer group, respectively, and the second sub-electroplating layer is electrically connected to the second electrode and the first substrate layer group, respectively. Thus, the first sub-electroplating layer is electrically connected to the first electrode and the first substrate layer group, and the second sub-electroplating layer is electrically connected to the second electrode and the first substrate layer group. Furthermore, the spaced arrangement of the first and second sub-electroplating layers reduces the risk of mutual interference between different electrodes and improves the electrical performance of the packaged chip.

[0007] In some embodiments, the first electroplated layer is located between the first electrode surface and the first substrate layer group, and the second electroplated layer is located between the second electrode surface and the second substrate layer group. This reduces the molding difficulty of the first and second electroplated layers, improves production efficiency and yield, and shortens the interconnect length between the bare chip and the first substrate layer group, as well as between the second substrate layer groups, further improving the electrical performance of the packaged chip.

[0008] In some embodiments, the packaged chip includes a filler surrounding the bare chip, the first electroplated layer, and the second electroplated layer. Thus, the filler surrounding the bare chip, the first electroplated layer, and the second electroplated layer provides better protection for these components, while also electrically insulating them, thereby improving the electrical performance of the packaged chip.

[0009] In some embodiments, the chip packaging assembly includes a first conductive solder layer located between the packaged chip and a first substrate layer group, wherein the packaged chip is welded and fixed by the first conductive solder layer and the first substrate layer group; and / or, the chip packaging assembly includes a second conductive solder layer located between the packaged chip and a second substrate layer group, wherein the packaged chip is welded and fixed by the second conductive solder layer and the second substrate layer group. Thus, welding the packaged chip to the first substrate layer group via the first conductive solder layer enables conductive connection between the packaged chip and the first substrate layer group while fixing the packaged chip, and / or welding the packaged chip to the second substrate layer group enables conductive connection between the packaged chip and the second substrate layer group while fixing the packaged chip, thereby improving the electrical performance and heat dissipation performance of the packaged chip.

[0010] In some embodiments, the first substrate layer group includes a first conductive substrate and a first heat dissipation substrate. The first conductive substrate and a first electroplated layer are electrically connected, and the first heat dissipation substrate is located on the side of the first conductive substrate opposite to the packaged chip. Thus, the conductive connection between the first conductive substrate and the first electroplated layer, and the location of the first heat dissipation substrate on the side of the first conductive substrate opposite to the packaged chip, allows heat generated by the bare chip to be conducted sequentially through the first electroplated layer and the first conductive substrate to the first heat dissipation substrate for heat dissipation treatment, thereby improving the heat dissipation performance of the chip package assembly.

[0011] In some embodiments, the first heat dissipation substrate includes a first substrate body and a plurality of first heat dissipation fins. The first substrate body is connected to the side of the first conductive substrate opposite to the packaged chip, and the plurality of first heat dissipation fins are spaced apart on the side of the first substrate body opposite to the first conductive substrate. Therefore, by spaced apart on the side of the first substrate body opposite to the first conductive substrate, the heat dissipation area can be increased, thereby enhancing the heat dissipation performance of the first heat dissipation substrate and further improving the heat dissipation performance for the packaged chip.

[0012] In some embodiments, the first substrate layer group includes a first output terminal, which is connected to the side of the first conductive substrate facing the packaged chip. The first output terminal is electrically connected to the bare chip through the first conductive substrate and the first electroplating layer. Thus, the first output terminal is electrically connected to the bare chip through the first conductive substrate and the first electroplating layer, enabling the chip package assembly to be electrically connected to external devices via the first output terminal. This simplifies the switching characteristics of the chip package assembly and improves the stability of the electrical connection between the chip package assembly and external devices.

[0013] In some embodiments, the first substrate layer group includes a first signal terminal and a second signal terminal spaced apart from each other. The first signal terminal and the second signal terminal are connected to the side of the first conductive substrate facing the packaged chip. The first signal terminal and the second signal terminal are electrically connected to the bare chip through the first conductive substrate and the first electroplating layer, respectively. Thus, the first signal terminal and the second signal terminal are electrically connected to the bare chip through the first conductive substrate and the first electroplating layer, respectively, enabling the chip package assembly to be electrically connected to external devices through the first signal terminal and the second signal terminal. This improves the stability of the electrical connection between the chip package assembly and external devices, and facilitates the signal interaction between the bare chip and external devices through the first signal terminal and the second signal terminal.

[0014] In some embodiments, the second substrate layer group includes a second conductive substrate and a second heat-dissipating substrate, the second conductive substrate and the second electroplated layer being conductively connected, and the second heat-dissipating substrate being located on the side of the second conductive substrate opposite to the packaged chip. Thus, the conductive connection between the second conductive substrate and the second electroplated layer, and the location of the second heat-dissipating substrate on the side of the conductive substrate opposite to the packaged chip, allows heat generated by the bare chip to be conducted sequentially through the second electroplated layer and the second conductive substrate to the second heat-dissipating substrate for heat dissipation, thereby improving the heat dissipation performance of the chip package assembly.

[0015] In some embodiments, the second heat dissipation substrate includes a second substrate body and a plurality of second heat dissipation fins. The second substrate body is connected to the side of the second conductive substrate opposite to the packaged chip, and the plurality of second heat dissipation fins are spaced apart on the side of the second substrate body opposite to the second conductive substrate. Therefore, by spaced apart on the side of the second substrate body opposite to the second conductive substrate, the heat dissipation area can be increased, thereby enhancing the heat dissipation performance of the second heat dissipation substrate and further improving the heat dissipation performance for the packaged chip.

[0016] In some embodiments, the second substrate layer group includes a second output terminal, which is connected to the second conductive substrate on the side facing the packaged chip. The second output terminal is electrically connected to the bare chip through the second conductive substrate and the second electroplating layer. Thus, the second output terminal is electrically connected to the bare chip through the second conductive substrate and the second electroplating layer, enabling the chip package assembly to be electrically connected to external devices via the second output terminal. This simplifies the switching characteristics of the chip package assembly and improves the stability of the electrical connection between the chip package assembly and external devices.

[0017] In some embodiments, the chip packaging assembly includes a support structure supported between a first substrate layer group and a second substrate layer group, and the support structure is disposed around the packaged chip. Thus, by supporting the packaged chip between the first and second substrate layer groups, the support structure can provide better support and protection, reducing the risk of damage to the chip packaging assembly due to compression.

[0018] To address the aforementioned problems, this application provides an electronic device that includes the aforementioned chip packaging components.

[0019] To address the aforementioned problems, this application provides a method for fabricating the aforementioned chip packaging assembly. The method includes: fabricating a packaged chip; wherein the packaged chip includes a bare chip, a first electroplating layer, and a second electroplating layer, the bare chip including a first electrode surface and a second electrode surface disposed opposite to each other; and covering the packaged chip with a first substrate layer group and a second substrate layer group on opposite sides, such that the first electroplating layer is electrically connected to the first electrode surface and the first substrate layer group respectively, and the second electroplating layer is electrically connected to the second electrode surface and the second substrate layer group respectively, thereby forming a chip packaging assembly. Therefore, by first fabricating the packaged chip and then covering the packaged chip with the first substrate layer group and the second substrate layer group on opposite sides, a chip packaging assembly can be obtained. This reduces the molding difficulty of the chip packaging assembly, improves production efficiency, and also shortens the interconnect length between the bare chip and the first substrate layer group through the first electroplating layer and the second electroplating layer, thereby improving the electrical performance of the packaged chip.

[0020] In some embodiments, the steps of fabricating the packaged chip include: forming a second electroplated layer on a panel; fixing a bare chip to the side of the second electroplated layer opposite to the panel, so that the second electrode surface and the second electroplated layer are electrically connected; and forming a first electroplated layer on the side of the bare chip opposite to the second electroplated layer, so that the first electrode surface and the first electroplated layer are electrically connected. Thus, by forming the first electroplated layer and the second electroplated layer on opposite sides of the bare chip respectively, heat generated by the bare chip can be easily transferred to the first electroplated layer and the second electroplated layer, improving the heat dissipation performance of the packaged chip. Furthermore, the conductive connection between the first electrode surface and the first electroplated layer, and the conductive connection between the second electrode surface and the second electroplated layer, can shorten the interconnect length between the bare chip and the first substrate layer group through the first electroplated layer, and shorten the interconnect length between the bare chip and the second substrate layer group through the second electroplated layer, thereby improving the electrical performance of the packaged chip.

[0021] In some embodiments, the step of forming a first electroplating layer on the side of the bare die opposite to the second electroplating layer includes: coating a filler onto the outer periphery of the bare die; etching the filler from the side of the bare die opposite to the second electroplating layer to expose a first electrode and a second electrode in a first electrode surface; and forming a first sub-electroplating layer and a second sub-electroplating layer on the side of the bare die opposite to the second electroplating layer, such that the first sub-electroplating layer and the first electrode are electrically connected, and the second sub-electroplating layer and the second electrode are electrically connected, thereby obtaining a packaged chip. Thus, etching the filler from the side of the bare die opposite to the second electroplating layer to expose the first electrode and the second electrode in the first electrode surface facilitates the formation of the first and second electroplating layers, thereby reducing the molding difficulty of the packaged chip and improving production efficiency. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the structure of a packaged chip according to one or more embodiments;

[0024] Figure 2 This is a first structural schematic diagram of a chip packaging assembly according to one or more embodiments;

[0025] Figure 3 This is a second structural schematic diagram of a chip packaging assembly according to one or more embodiments;

[0026] Figure 4 This is a top view of a chip packaging assembly according to one or more embodiments;

[0027] Figure 5 This is a schematic flowchart of a method for fabricating a chip packaging component according to one or more embodiments;

[0028] Figure 6 yes Figure 5 A schematic flowchart of an embodiment of step S501;

[0029] Figure 7 yes Figure 6 A schematic flowchart of an embodiment of step S603;

[0030] Figure 8 This is a schematic diagram of a structure in which a second electroplated layer is formed on a panel according to one or more embodiments;

[0031] Figure 9 This is a schematic diagram of a structure for fixing a bare chip on a second electroplated layer according to one or more embodiments;

[0032] Figure 10 This is a schematic diagram of a structure in which a filler is coated on a bare chip and a second electroplated layer according to one or more embodiments;

[0033] Figure 11 This is a schematic diagram showing the structure of the first and second electrodes of a bare chip according to one or more embodiments;

[0034] Figure 12 This is a schematic diagram of the structure of a packaged chip formed according to one or more embodiments;

[0035] Figure 13This is a schematic diagram of the structure of a chip packaging assembly formed according to one or more embodiments.

[0036] Reference numerals: Chip packaging assembly 10; First substrate layer group 100; First conductive substrate 110; First heat dissipation substrate 120; First substrate body 121; First heat dissipation fin 122; First output terminal 130; First signal terminal 140; Second signal terminal 150; Second substrate layer group 200; Second conductive substrate 210; Second heat dissipation substrate 220; Second substrate body 221; Second heat dissipation fin 222; Second output terminal 230; Packaged chip 300; First electroplating layer 310; First sub-electroplating layer 311; Second sub-electroplating layer 312; Second electroplating layer 320; Bare chip 330; First electrode surface 331; First electrode 3311; Second electrode 3312; Second electrode surface 332; Filler 340; First conductive solder layer 400; Second conductive solder layer 500; Support 600. Detailed Implementation

[0037] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0039] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0040] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0041] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0042] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0043] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0044] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0045] As electronic devices continue to evolve towards thinner, lighter, and smaller designs, the performance requirements for the chip packaging components within these devices are becoming increasingly stringent. Consequently, the chip's temperature rises continuously during operation, affecting its overcurrent capacity and other capabilities. To improve the chip's heat dissipation performance, the structure of the chip packaging component must prioritize structures that provide excellent heat dissipation for the chip.

[0046] Existing chip packaging components include single-sided substrate cooling structures and double-sided substrate cooling structures. Double-sided substrate cooling structures mainly achieve thermal and electrical conduction by stacking multiple layers of pads and solder layers on the chip and then using copper pillars and other methods. This solution has a long heat conduction path, resulting in poor heat dissipation performance.

[0047] To address the technical problems existing in related technologies, this application provides a chip packaging assembly. The chip packaging assembly includes upper and lower substrate layers and a packaged chip. The upper and lower substrate layers are located on both sides of the packaged chip. The packaged chip includes a bare chip and upper and lower electroplated layers. One side surface of the packaged chip is electrically connected to one substrate layer and one substrate layer, and the other side surface of the packaged chip is electrically connected to another substrate layer and another electroplated layer. This allows the heat generated by the bare chip to be directly transferred to the two substrate layers through the electroplated layers, improving the heat dissipation performance of the packaged chip. It also shortens the interconnection length between the bare chip and the two substrate layers, thereby improving the electrical performance of the packaged chip.

[0048] Specifically, see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of a packaged chip according to one or more embodiments. Figure 2 This is a first structural schematic diagram of a chip packaging assembly according to one or more embodiments.

[0049] The chip packaging assembly 10 includes a first substrate layer group 100, a second substrate layer group 200, and a packaged chip 300. The second substrate layer group 200 and the first substrate layer group 100 are disposed opposite to each other and spaced apart. The packaged chip 300 is located between the first substrate layer group 100 and the second substrate layer group 200. The packaged chip 300 includes a bare chip 330, a first electroplating layer 310, and a second electroplating layer 320. The bare chip 330 includes a first electrode surface 331 and a second electrode surface 332 disposed opposite to each other. The first electroplating layer 310 is electrically connected to the first electrode surface 331 and the first substrate layer group 100, respectively. The second electroplating layer 320 is electrically connected to the second electrode surface 332 and the second substrate layer group 200, respectively.

[0050] The packaged chip 300 can be packaged as an integral module between the first substrate layer group 100 and the second substrate layer group 200, and connected to both the first substrate layer group 100 and the second substrate layer group 200. Both the first substrate layer group 100 and the second substrate layer group 200 can have circuit layers to realize corresponding circuit transmission functions. Both the first substrate layer group 100 and the second substrate layer group 200 can have thermal conductivity to conduct heat generated by the packaged chip 300 and effectively realize heat dissipation. Compared with the solution of stacking solder, chips and pads on one substrate and then covering it with another substrate, packaging the packaged chip 300 as an integral module between the first substrate layer group 100 and the second substrate layer group 200 can further improve the production yield and production efficiency of the chip packaging assembly 10.

[0051] The bare die 330 is made of materials including but not limited to silicon and silicon carbide. A bare die 330 refers to an electronic chip that is directly exposed without packaging, finished modules, or connectors. The first electrode surface 331 and the second electrode surface 332 are the two surfaces of the bare die 330 in the thickness direction. The first electroplated layer 310 electrically connects the first electrode surface 331 and the first substrate layer group 100 to achieve circuit transmission between the bare die 330 and the first substrate layer group 100. The second electroplated layer 320 electrically connects the second electrode surface 332 and the second substrate layer group 200 to achieve circuit transmission between the bare die 330 and the second substrate layer group 200. One of the first electrode surface 331 and the second electrode surface 332 includes a gate and a source, and the other includes a drain. Compared to the solution of electrically connecting the bare chip 330 and the substrate through wire bonding, the solution of achieving conductive connection through electroplating and the substrate can shorten the interconnect length between the bare chip 330 and the substrate, thereby reducing the non-interconnection value caused by internal interconnection and improving the electrical performance of the packaged chip 300.

[0052] The bare chip 330 generates a significant amount of heat during operation. This heat can be conducted through the first electroplating layer 310 to the first substrate layer group 100, and through the second electroplating layer 320 to the second substrate layer group 200. The heat is then dissipated through the first substrate layer group 100 and the second substrate layer group 200, achieving bidirectional heat dissipation and enabling the chip packaging assembly 10 to achieve better heat dissipation. The first electroplating layer 310 and the second electroplating layer 320 can be made of materials with electrical conductivity and high thermal conductivity, including but not limited to copper and aluminum, to further improve the heat dissipation efficiency of the bare chip 330. Compared to a solution that stacks solder, chips, and pads on one substrate and then covers it with another substrate, the solution that uses electroplating layers and substrates for heat conduction increases the effective contact area of ​​the bare chip 330 and reduces the heat dissipation path, thereby improving the heat dissipation effect.

[0053] Through the above embodiments, the bare chip 330 is electrically connected to the first substrate layer group 100 through the first electroplating layer 310 and to the second substrate layer group 200 through the second electroplating layer 320. The heat generated by the bare chip 330 can be directly transferred to the first substrate layer group 100 and the second substrate layer group 200 through the electroplating layer, thereby improving the heat dissipation performance of the packaged chip 300. Furthermore, the interconnection length between the bare chip 330 and the first substrate layer group 100 can be shortened through the first electroplating layer 310, and the interconnection length between the bare chip 330 and the second substrate layer group 200 can be shortened through the second electroplating layer 320, thereby improving the electrical performance of the packaged chip 300.

[0054] In some embodiments, the bare chip 330 includes a first electrode 3311 and a second electrode 3312 spaced apart on the first electrode surface 331. The first electroplating layer 310 includes a first sub-electroplating layer 311 and a second sub-electroplating layer 312 spaced apart. The first sub-electroplating layer 311 is electrically connected to the first electrode 3311 and the first substrate layer group 100, respectively. The second sub-electroplating layer 312 is electrically connected to the second electrode 3312 and the first substrate layer group 100, respectively. One of the first electrode 3311 and the second electrode 3312 is a source, and the other is a gate. For example, the first electrode 3311 is the source and the second electrode 3312 is the gate, or the second electrode 3312 is the source and the first electrode 3311 is the gate. The first electrode 3311 is electrically connected to the first substrate layer group 100 via the first sub-plating layer 311, and the second electrode 3312 is electrically connected to the first substrate layer group 100 via the second sub-plating layer 312. The first sub-plating layer 311 and the second sub-plating layer 312 are isolated by insulating plastic, for example, epoxy resin can be coated between the first sub-plating layer 311 and the second sub-plating layer 312. Thus, the first sub-plating layer 311 is electrically connected to the first electrode 3311 and the first substrate layer group 100, and the second sub-plating layer 312 is electrically connected to the second electrode 3312 and the first substrate layer group 100. The first sub-plating layer 311 and the second sub-plating layer 312 are spaced apart, which can reduce the risk of mutual interference between different electrodes and improve the electrical performance of the packaged chip 300.

[0055] In some embodiments, the first electroplated layer 310 is located between the first electrode surface 331 and the first substrate layer group 100, and the second electroplated layer 320 is located between the second electrode surface 332 and the second substrate layer group 200. The first electroplating layer 310 can extend along the spacing direction between the first substrate layer group 100 and the second substrate layer group 200, and the second electroplating layer 320 can extend along the spacing direction between the first substrate layer group 100 and the second substrate layer group 200, so that the first electroplating layer 310 can be columnar and directly connected between the first electrode surface 331 and the first substrate layer group 100, and the second electroplating layer 320 can be columnar and directly connected between the second electrode surface 332 and the second substrate layer group 200, thereby reducing the size of the first electroplating layer 310 in the spacing direction between the first substrate layer group 100 and the second substrate layer group 200, and further reducing the interconnection length between the bare chip 330 and the first substrate layer group 100. When the first electroplating layer 310 includes a first sub-electroplating layer 311 and a second sub-electroplating layer 312, the first sub-electroplating layer 311 and the second sub-electroplating layer 312 extend along the spacing direction between the first substrate layer group 100 and the second substrate layer group 200, respectively. This reduces the molding difficulty of the first electroplating layer 310 and the second electroplating layer 320, improves production efficiency and production qualification rate, and shortens the interconnection length between the bare chip 330 and the first substrate layer group 100 and between the second substrate layer group 200, thereby further improving the electrical performance of the packaged chip 300.

[0056] In some embodiments, the packaged chip 300 includes a filler 340, which surrounds the bare chip 330, the first electroplated layer 310, and the second electroplated layer 320. The filler 340 may include, but is not limited to, epoxy resin. The filler 340 may fill the gaps between the bare chip 330, the first electroplated layer 310, the second electroplated layer 320, the first substrate layer group 100, and the second substrate layer group 200. For example, when the surface of the bare chip 330 facing the first substrate layer group 100 is blocked by the first electroplated layer 310, and the surface facing the second substrate layer group 200 is blocked by the second electroplated layer 320, the filler 340 only needs to surround the periphery of the bare chip 330, the first electroplated layer 310, and the second electroplated layer 320. For example, when the first electroplating layer 310 includes a first sub-electroplating layer 311 and a second sub-electroplating layer 312 spaced apart, and the surface of the bare chip 330 facing the second substrate layer group 200 is blocked by the second electroplating layer 320, the filler 340 needs to surround the bare chip 330, the second electroplating layer 320, the first sub-electroplating layer 311 and the second sub-electroplating layer 312. The filler 340 is also sandwiched between the surface of the first electrode surface 331 that is not blocked by the first sub-electroplating layer 311 and the second sub-electroplating layer 312 and the first substrate layer group 100, so as to achieve electrical insulation between different components. Therefore, the filler 340 is disposed around the bare chip 330, the first electroplating layer 310 and the second electroplating layer 320, which can provide good protection for the bare chip 330, the first electroplating layer 310 and the second electroplating layer 320, and at the same time can make the first electroplating layer 310 and the second electroplating layer 320 electrically insulated, thereby improving the electrical performance of the packaged chip 300.

[0057] In some embodiments, the chip packaging assembly 10 includes a support 600, which is supported between a first substrate layer group 100 and a second substrate layer group 200, and surrounds the packaged chip 300. The support 600 can be injection molded. Specifically, after the first substrate layer group 100 and the second substrate layer group 200 are applied to opposite surfaces of the packaged chip 300, the support 600 is injection molded at the gap between the first substrate layer group 100 and the second substrate layer group 200, so that the support 600 is supported between the first substrate layer group 100 and the second substrate layer group 200 and surrounds the packaged chip 300. Thus, the support 600, supported between the first substrate layer group 100 and the second substrate layer group 200, can provide better support and protection for the packaged chip 300, reducing the risk of damage to the chip packaging assembly 10 due to compression.

[0058] See Figure 3 , Figure 3 This is a second structural schematic diagram of a chip packaging assembly according to one or more embodiments.

[0059] The chip packaging assembly 10 includes a first conductive solder layer 400, which is located between the packaged chip 300 and the first substrate layer group 100. The packaged chip 300 is soldered and fixed to the first substrate layer group 100 via the first conductive solder layer 400. The first conductive solder layer 400 may be formed by solder. The first conductive solder layer 400 has a soldering function. Located between the packaged chip 300 and the first substrate layer group 100, the first conductive solder layer 400 can be used to solder the first substrate layer group 100 and the packaged chip 300 respectively, thereby soldering and fixing the first substrate layer group 100 and the packaged chip 300. The first conductive solder layer 400 also has a conductive function. Located between the packaged chip 300 and the first substrate layer group 100, the first conductive solder layer 400 allows the bare chip 330 to be electrically connected to the first substrate layer group 100 sequentially via the first electroplating layer 310 and the first conductive solder layer 400. Therefore, the packaged chip 300 is fixed by welding the first conductive solder layer 400 and the first substrate layer group 100, which can make the packaged chip 300 and the first substrate layer group 100 electrically connected at the same time as fixing the packaged chip 300, thereby improving the electrical performance of the packaged chip 300 and the heat dissipation performance of the packaged chip 300.

[0060] And / or, the chip packaging assembly 10 includes a second conductive solder layer 500, which is located between the packaged chip 300 and the second substrate layer group 200. The packaged chip 300 is soldered and fixed through the second conductive solder layer 500 and the second substrate layer group 200. The second conductive solder layer 500 may be formed by solder. The second conductive solder layer 500 has a soldering function. Located between the packaged chip 300 and the second substrate layer group 200, the second conductive solder layer 500 can be used to solder the second substrate layer group 200 and the packaged chip 300 respectively, thereby soldering and fixing the second substrate layer group 200 and the packaged chip 300. The second conductive solder layer 500 also has a conductive function. Located between the packaged chip 300 and the second substrate layer group 200, the bare chip 330 can be electrically connected sequentially through the second electroplating layer 320, the second conductive solder layer 500, and the second substrate layer group 200. Therefore, the packaged chip 300 is welded and fixed by the second conductive solder layer 500 and the second substrate layer group 200, which can make the packaged chip 300 and the second substrate layer group 200 electrically connected at the same time as fixing the packaged chip 300, thereby improving the electrical performance and heat dissipation performance of the packaged chip 300.

[0061] In some embodiments, the first substrate layer group 100 includes a first conductive substrate 110 and a first heat dissipation substrate 120. The first conductive substrate 110 and the first electroplated layer 310 are electrically connected, and the first heat dissipation substrate 120 is located on the side of the first conductive substrate 110 facing away from the packaged chip 300. The first conductive substrate 110 may include, but is not limited to, thin-film ceramic substrates (TFC), thick-film printed ceramic substrates (TPC), direct-bonded copper ceramic substrates (DBC), direct-aluminum ceramic substrates (DBA), direct electroplated copper ceramic substrates (DPC), active metal-bonded ceramic substrates (AMB), direct sputtered copper ceramic substrates (DSC), and laser-activated metal-ceramic substrates (LAM). The first conductive substrate 110 may be electrically connected to the first electroplated layer 310 to make the bare chip 330 and the first conductive substrate 110 electrically connected. The first heat dissipation substrate 120 is flat and covers the surface of the first conductive substrate 110 facing away from the packaged chip 300. The first heat dissipation substrate 120 provides heat dissipation for both the first conductive substrate 110 and the packaged chip 300. The heat dissipation method of the first heat dissipation substrate 120 may include, but is not limited to, air cooling or water cooling. Thus, the first conductive substrate 110 and the first electroplated layer 310 are electrically connected. The first heat dissipation substrate 120 is located on the side of the first conductive substrate 110 facing away from the packaged chip 300, allowing the heat generated by the bare chip 330 to be conducted sequentially through the first electroplated layer 310 and the first conductive substrate 110 to the first heat dissipation substrate 120, thereby improving the heat dissipation performance of the chip package assembly 10.

[0062] See Figures 2 to 4 , Figure 4 This is a top view of a chip packaging assembly according to one or more embodiments.

[0063] The first heat dissipation substrate 120 includes a first substrate body 121 and a plurality of first heat dissipation fins 122. The first substrate body 121 is connected to the side of the first conductive substrate 110 opposite to the packaged chip 300. The plurality of first heat dissipation fins 122 are spaced apart on the side of the first substrate body 121 opposite to the first conductive substrate 110. The first substrate body 121 is flat and covers the surface of the first conductive substrate 110 opposite to the packaged chip 300. The first substrate body 121 may be made of a material with high thermal conductivity. The spaced arrangement of the plurality of first heat dissipation fins 122 allows airflow channels to be formed at the intervals between the plurality of first heat dissipation fins 122, and the airflow in the airflow channels can be changed by other air source components to cool the plurality of first heat dissipation fins 122. For example, as Figure 2 or Figure 3As shown in the side view, there are eight first heat dissipation fins 122, which are spaced apart. Airflow channels can be formed between adjacent first heat dissipation fins 122, resulting in a total of seven airflow channels. Alternatively, water-cooling pipes can be laid among the multiple first heat dissipation fins 122, allowing coolant to flow into them, thus facilitating heat exchange between the coolant and the first heat dissipation fins 122 and cooling them. Therefore, by spaced apart on the side of the first substrate body 121 opposite to the first conductive substrate 110, the heat dissipation area can be increased, thereby enhancing the heat dissipation performance of the first heat dissipation substrate 120 and further improving the heat dissipation performance of the packaged chip 300.

[0064] In some embodiments, the first substrate layer 100 includes a first output terminal 130, which is connected to the first conductive substrate 110 on the side facing the packaged chip 300. The first output terminal 130 is electrically connected to the bare chip 330 through the first conductive substrate 110 and the first electroplating layer 310. The first output terminal 130 may include a source output terminal or a drain output terminal. When the first electrode surface 331 includes a source, the first output terminal 130 can be a source output terminal, so that the source output terminal can be electrically connected to the source. When the first electrode surface 331 includes a drain, the first output terminal 130 can be a drain output terminal, so that the drain output terminal can be electrically connected to the drain. Thus, the first output terminal 130 is electrically connected to the bare chip 330 through the first conductive substrate 110 and the first electroplating layer 310, so that the chip package assembly 10 can be electrically connected to external devices through the first output terminal 130, simplifying the switching characteristics of the chip package assembly 10 and improving the stability of the electrical connection between the chip package assembly 10 and external devices.

[0065] Further, the first substrate layer group 100 includes mutually spaced first signal terminals 140 and second signal terminals 150. The first signal terminals 140 and second signal terminals 150 are connected to the side of the first conductive substrate 110 facing the packaged chip 300. The first signal terminals 140 and second signal terminals 150 are electrically connected to the bare chip 330 through the first conductive substrate 110 and the first electroplating layer 310, respectively. One of the first signal terminals 140 and second signal terminals 150 is a gate signal terminal, and the other is a source signal terminal. In this embodiment, the first electrode surface 331 may include a source and a gate. The source signal terminal is electrically connected to the source through the first electroplating layer 310, and the gate signal terminal is electrically connected to the gate through the first electroplating layer 310. The first signal terminals 140 and second signal terminals 150 can be used to connect to external devices and receive and transmit drive signals from external devices. Therefore, the first signal terminal 140 and the second signal terminal 150 are electrically connected to the bare chip 330 through the first conductive substrate 110 and the first electroplating layer 310, respectively. This allows the chip packaging assembly 10 to be electrically connected to external devices through the first signal terminal 140 and the second signal terminal 150, thereby improving the stability of the electrical connection between the chip packaging assembly 10 and external devices, and facilitating the signal interaction between the bare chip 330 and external devices through the first signal terminal 140 and the second signal terminal 150.

[0066] In some embodiments, the second substrate layer group 200 includes a second conductive substrate 210 and a second heat dissipation substrate 220. The second conductive substrate 210 and the second electroplated layer 320 are electrically connected, and the second heat dissipation substrate 220 is located on the side of the second conductive substrate 210 opposite to the packaged chip 300. The second conductive substrate 210 may include, but is not limited to, thin-film ceramic substrates (TFC), thick-film printed ceramic substrates (TPC), direct-bonded copper ceramic substrates (DBC), direct-aluminum ceramic substrates (DBA), direct-plated copper ceramic substrates (DPC), active metal-bonded ceramic substrates (AMB), direct-sputtered copper ceramic substrates (DSC), and laser-activated metal-ceramic substrates (LAM). The second conductive substrate 210 may be electrically connected to the second electroplated layer 320 to make the bare chip 330 and the second conductive substrate 210 electrically connected. The second heat dissipation substrate 220 is flat and covers the surface of the second conductive substrate 210 opposite to the packaged chip 300. The second heat dissipation substrate 220 provides heat dissipation for both the second conductive substrate 210 and the packaged chip 300. The heat dissipation method of the second heat dissipation substrate 220 may include, but is not limited to, air cooling or water cooling. Thus, the second conductive substrate 210 and the second electroplated layer 320 are electrically connected. The second heat dissipation substrate 220 is located on the side of the conductive substrate opposite to the packaged chip 300, allowing the heat generated by the bare chip 330 to be conducted sequentially through the second electroplated layer 320 and the second conductive substrate 210 to the second heat dissipation substrate 220, thereby improving the heat dissipation performance of the chip package assembly 10.

[0067] Further, the second heat dissipation substrate 220 includes a second substrate body 221 and a plurality of second heat dissipation fins 222. The second substrate body 221 is connected to the side of the second conductive substrate 210 facing away from the packaged chip 300, and the plurality of second heat dissipation fins 222 are spaced apart on the side of the second substrate body 221 facing away from the second conductive substrate 210. The second substrate body 221 is flat and covers the surface of the second conductive substrate 210 facing away from the packaged chip 300. The second substrate body 221 may be made of a material with high thermal conductivity. The spaced arrangement of the plurality of second heat dissipation fins 222 allows airflow channels to be formed at the intervals between the plurality of second heat dissipation fins 222, and the airflow in the airflow channels can be changed by other air source components to cool the plurality of second heat dissipation fins 222. For example, as shown in the figure... Figure 2 or Figure 3As shown in the side view, there are eight first heat dissipation fins 122, which are spaced apart. Airflow channels can be formed between adjacent first heat dissipation fins 122, resulting in a total of seven airflow channels. Alternatively, water-cooling pipes can be laid within the multiple second heat dissipation fins 222, allowing coolant to flow into them, thus facilitating heat exchange between the coolant and the second heat dissipation fins 222 and cooling them. Therefore, by spaced apart, the multiple second heat dissipation fins 222 on the side of the second substrate body 221 opposite to the second conductive substrate 210, the heat dissipation area can be increased, thereby enhancing the heat dissipation performance of the second heat dissipation substrate 220 and further improving the heat dissipation performance of the packaged chip 300.

[0068] In some embodiments, the second substrate layer 200 includes a second output terminal 230, which is connected to the side of the second conductive substrate 210 facing the packaged chip 300. The second output terminal 230 is electrically connected to the bare chip 330 through the second conductive substrate 210 and the second electroplating layer 320. The second output terminal 230 may include a source output terminal or a drain output terminal. For example, when the first output terminal 130 is a source output terminal, the second output terminal 230 is a drain output terminal. Exemplarily, when the second electrode surface 332 includes a source, the second output terminal 230 can be a source output terminal so that the source output terminal can be electrically connected to the source; when the second electrode surface 332 includes a drain, the second output terminal 230 can be a drain output terminal so that the drain output terminal can be electrically connected to the drain. Thus, the second output terminal 230 is electrically connected to the bare chip 330 through the second conductive substrate 210 and the second electroplating layer 320, so that the chip package assembly 10 can be electrically connected to external devices through the second output terminal 230, which simplifies the switching characteristics of the chip package assembly 10 and improves the stability of the electrical connection between the chip package assembly 10 and external devices.

[0069] In summary, the bare chip 330 is electrically connected to the first substrate layer group 100 through the first electroplating layer 310 and to the second substrate layer group 200 through the second electroplating layer 320. This allows the heat generated by the bare chip 330 to be directly transferred to the first substrate layer group 100 and the second substrate layer group 200 through the electroplating layers, thereby improving the heat dissipation performance of the packaged chip 300. Furthermore, the first electroplating layer 310 can shorten the interconnection length between the bare chip 330 and the first substrate layer group 100, and the second electroplating layer 320 can shorten the interconnection length between the bare chip 330 and the second substrate layer group 200, thereby improving the electrical performance of the packaged chip 300.

[0070] To address the technical problems existing in the relevant embodiments, this application also provides an electronic device, which includes the chip packaging component 10 as described in any of the above embodiments. The electronic device may include, but is not limited to, inverters, rectifiers, cellular phones, smartphones, other wireless communication devices, personal digital assistants, audio players, other media players, music recorders, video recorders, cameras, other media recorders, radios, medical devices, calculators, programmable remote controls, pagers, netbooks, personal digital assistants (PDAs), portable multimedia players (PMPs), Moving Image Experts Group (MPEG-1 or MPEG-2) audio layer 3 (MP3) players, portable medical devices, and digital cameras and combinations thereof.

[0071] To address the technical problems existing in the relevant embodiments, this application also provides a method for preparing the chip packaging component 10 as described in any of the above embodiments, see [link to relevant documentation]. Figure 5 , Figure 5 This is a schematic flowchart illustrating a method for fabricating a chip packaging assembly according to one or more embodiments. Specifically, it includes the following steps S501 to S502.

[0072] Step S501: Prepare a packaged chip, wherein the packaged chip includes a bare chip, a first electroplating layer and a second electroplating layer, and the bare chip includes a first electrode surface and a second electrode surface disposed opposite to each other.

[0073] Can be combined Figure 12 , Figure 12This is a schematic diagram of the structure of the packaged chip 300 after being formed according to one or more embodiments. The packaged chip 300 can be formed by a fan-out process so that the packaged chip 300 can be used as an integral module. Then, the packaged chip 300 is connected to the first substrate layer group 100 and the second substrate layer group 200 by welding or sintering to form a complete integral module. The material of the bare chip 330 includes, but is not limited to, silicon, silicon carbide, etc. The bare chip 330 refers to an electronic chip that is directly exposed without packaging, finished modules, and connectors. The first electrode surface 331 and the second electrode surface 332 are two surfaces of the bare chip 330 in the thickness direction. The first electroplated layer 310 conductively connects the first electrode surface 331 and the first substrate layer group 100 to realize the circuit transmission function between the bare chip 330 and the first substrate layer group 100. The second electroplated layer 320 conductively connects the second electrode surface 332 and the second substrate layer group 200 to realize the circuit transmission function between the bare chip 330 and the second substrate layer group 200. One of the first electrode surface 331 and the second electrode surface 332 includes a gate and a source, and the other includes a drain. Compared with the scheme of conductively connecting the bare chip 330 and the substrate through wire bonding, the scheme of achieving conductive connection through the electroplated layer and the substrate can shorten the interconnect length between the bare chip 330 and the substrate, thereby reducing the noise value caused by internal interconnection and improving the electrical performance of the packaged chip 300.

[0074] Step S502: The first substrate layer group and the second substrate layer group are covered on opposite sides of the packaged chip, so that the first electroplated layer is electrically connected to the first electrode surface and the first substrate layer group respectively, and the second electroplated layer is electrically connected to the second electrode surface and the second substrate layer group respectively, so as to form a chip package assembly.

[0075] Can be combined Figure 13 , Figure 13 This is a schematic diagram of the structure of a chip packaging assembly 10 formed according to one or more embodiments. After the packaged chip 300 is fabricated, the first substrate layer group 100 and the second substrate layer group 200 can be connected to opposite sides of the packaged chip 300 by welding or sintering, so that the first electroplated layer 310 is electrically connected to the first electrode surface 331 and the first substrate layer group 100, and the second electroplated layer 320 is electrically connected to the second electrode surface 332 and the second substrate layer group 200. Then, a support 600 can be injected between the first substrate layer group 100 and the second substrate layer group 200 so that the support 600 surrounds the packaged chip 300, thereby obtaining the chip packaging assembly 10. In the process of fabricating the packaged chip 300, the first substrate layer group 100 and the second substrate layer group 200 can be fabricated simultaneously. After the fabrication of each component is completed, they are assembled to form the chip packaging assembly 10.

[0076] Through the above embodiments, a packaged chip 300 is first prepared, and then the first substrate layer group 100 and the second substrate layer group 200 are covered on opposite sides of the packaged chip 300 to obtain the chip package assembly 10. This can reduce the molding difficulty of the chip package assembly 10 and improve production efficiency. At the same time, the interconnection length between the bare chip 330 and the first substrate layer group 100 can be shortened by the first electroplating layer 310, and the interconnection length between the bare chip 330 and the second substrate layer group 200 can be shortened by the second electroplating layer 320, thereby improving the electrical performance of the packaged chip 300.

[0077] See Figure 6 , Figure 6 yes Figure 5 A schematic flowchart of an embodiment of step S501. Specifically, it includes the following steps S601 to S603.

[0078] Step S601: Form a second electroplated layer 320 on the panel.

[0079] Can be combined Figure 8 , Figure 8 This is a schematic diagram illustrating the formation of a second electroplated layer 320 on a panel according to one or more embodiments. The panel can be selected with specific dimensions, such as a 400mm*500mm panel. Multiple second electroplated layers 320 can be formed simultaneously on one panel to ultimately fabricate multiple packaged chips 300. Specifically, the surface of the panel can be roughened first, then a polymer film (such as epoxy resin) can be coated on the entire surface of the panel. Next, the locations where the second electroplated layer 320 needs to be formed can be etched using a laser, and finally, the second electroplated layer 320 is formed through the etched areas. The second electroplated layer 320 can be made of materials with electrical conductivity and high thermal conductivity, including but not limited to copper and aluminum.

[0080] Step S602: Fix the bare chip 330 to the side of the second electroplated layer 320 away from the panel, so that the second electrode surface 332 and the second electroplated layer 320 are electrically connected.

[0081] Can be combined Figure 9 , Figure 9 This is a schematic diagram of a structure in which a bare chip 330 is fixed on a second electroplated layer 320 according to one or more embodiments. The drain of the bare chip 330 may face the second electroplated layer 320, and the bare chip 330 may be fixedly connected to the second electroplated layer 320, thereby making the drain of the bare chip 330 and the second electroplated layer 320 electrically connected.

[0082] Step S603: A first electroplating layer 310 is formed on the side of the bare chip 330 away from the second electroplating layer 320, so that the first electrode surface 331 and the first electroplating layer 310 are electrically connected.

[0083] The surface of the bare chip 330 facing away from the second electroplating layer 320 may include a source and a gate. A first electroplating layer 310 may be formed on the side of the bare chip 330 facing away from the second electroplating layer 320. The first electroplating layer 310 and the bare chip 330 are fixedly connected, and the source and gate of the bare chip 330 are electrically connected to the first electroplating layer 310, thereby forming a packaged chip 300, so that the packaged chip 300 is a complete module. Therefore, by forming a first electroplating layer 310 and a second electroplating layer 320 on opposite sides of the bare chip 330, the heat generated by the bare chip 330 can be easily transferred to the first electroplating layer 310 and the second electroplating layer 320, thereby improving the heat dissipation performance of the packaged chip 300. Furthermore, the first electrode surface 331 and the first electroplating layer 310 are electrically connected, and the second electrode surface 332 and the second electroplating layer 320 are electrically connected. This allows the interconnection length between the bare chip 330 and the first substrate layer group 100 to be shortened by the first electroplating layer 310, and the interconnection length between the bare chip 330 and the second substrate layer group 200 to be shortened by the second electroplating layer 320, thereby improving the electrical performance of the packaged chip 300.

[0084] See Figure 7 , Figure 7 yes Figure 6 A schematic flowchart of an embodiment of step S603. Specifically, it includes the following steps S701 to S703.

[0085] Step S701: Apply filler 340 to the outer periphery of bare chip 330.

[0086] Can be combined Figure 10 , Figure 10 This is a schematic diagram of a structure in which filler 340 is coated on a bare die 330 and a second electroplated layer 320 according to one or more embodiments. After the bare die 330 is fixed to the side of the second electroplated layer 320 away from the panel, filler 340 can be coated on the side surfaces of the second electroplated layer 320 and the bare die 330, as well as on the surface of the bare die 330 away from the second electroplated layer 320, so as to cover the second electroplated layer 320 and the bare die 330 by means of filler 340.

[0087] Step S702: Etch filler 340 from the side of bare chip 330 away from the second electroplated layer 320 to expose the first electrode 3311 and the second electrode 3312 in the first electrode surface 331.

[0088] Can be combined Figure 11 , Figure 11This is a schematic diagram showing the structure of the first electrode 3311 and the second electrode 3312 of the bare die 330 according to one or more embodiments. After the filler 340 is coated onto the outer periphery of the bare die 330, the filler 340 can be laser-etched at the positions corresponding to the first electrode 3311 and the second electrode 3312, thereby exposing the first electrode 3311 and the second electrode 3312 from the side of the filler 340 away from the second electroplated layer 320.

[0089] Step S703: A first sub-plating layer 311 and a second sub-plating layer 312 are formed on the side of the bare chip 330 opposite to the second plating layer 320, so that the first sub-plating layer 311 and the first electrode 3311 are electrically connected, and the second sub-plating layer 312 and the second electrode 3312 are electrically connected.

[0090] Can be combined Figure 12 , Figure 12 This is a schematic diagram of the structure of the packaged chip 300 after being formed according to one or more embodiments. After exposing the first electrode 3311 and the second electrode 3312, a first channel exposing the first electrode 3311 and a second channel exposing the second electrode 3312 can be formed due to the thickness of the filler 340. Then, a first sub-plating layer 311 can be formed in the first channel to make the first sub-plating layer 311 and the first electrode 3311 electrically connected. A second sub-plating layer 312 is formed in the second channel to make the second sub-plating layer 312 and the second electrode 3312 electrically connected. Finally, the formed packaged chip 300 and the insert are peeled off so that the packaged chip 300 is a complete module. Finally, the first substrate layer group 100 and the second substrate layer group 200 are covered on opposite sides of the packaged chip 300 to form a structure as shown in the figure. Figure 13 The chip packaging assembly 10 is shown. Thus, the filler 340 is etched from the side of the bare chip 330 away from the second electroplating layer 320 to expose the first electrode 3311 and the second electrode 3312 in the first electrode surface 331, which facilitates the formation of the first electroplating layer 310 and the second electroplating layer 320, thereby reducing the molding difficulty of the packaged chip 300 and improving production efficiency.

[0091] In summary, by first preparing the packaged chip 300, and then covering the opposite sides of the packaged chip 300 with the first substrate layer group 100 and the second substrate layer group 200, the chip package assembly 10 can be obtained. This reduces the molding difficulty of the chip package assembly 10 and improves production efficiency. At the same time, the interconnection length between the bare chip 330 and the first substrate layer group 100 can be shortened by the first electroplating layer 310, and the interconnection length between the bare chip 330 and the second substrate layer group 200 can be shortened by the second electroplating layer 320, thereby improving the electrical performance of the packaged chip 300.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A chip package assembly, comprising: The chip package assembly comprises: a first substrate layer set; a second substrate layer set, opposite and spaced apart from the first substrate layer set; a package chip, located between the first substrate layer set and the second substrate layer set, the package chip comprising a bare chip, a first electroplating layer and a second electroplating layer, the bare chip comprising a first electrode surface and a second electrode surface arranged oppositely, the first electroplating layer being electrically connected to the first electrode surface and the first substrate layer set respectively, and the second electroplating layer being electrically connected to the second electrode surface and the second substrate layer set respectively.

2. The chip package assembly of claim 1, wherein, The bare chip comprises a first electrode and a second electrode spaced apart from each other on the first electrode surface, and the first electroplating layer comprises a first sub-electroplating layer and a second sub-electroplating layer spaced apart from each other, the first sub-electroplating layer being electrically connected to the first electrode and the first substrate layer set respectively, and the second sub-electroplating layer being electrically connected to the second electrode and the first substrate layer set respectively.

3. The chip package assembly of claim 1 or 2, wherein, The first electroplating layer is located between the first electrode surface and the first substrate layer set, and the second electroplating layer is located between the second electrode surface and the second substrate layer set.

4. The chip package assembly of any one of claims 1 to 3, wherein, The package chip comprises a filler, which is arranged around the bare chip, the first electroplating layer and the second electroplating layer.

5. The chip package assembly according to any one of claims 1 to 4, wherein the chip package assembly comprises a first conductive solder layer, which is located between the package chip and the first substrate layer set, and the package chip is soldered and fixed to the first substrate layer set through the first conductive solder layer; and / or the chip package assembly comprises a second conductive solder layer, which is located between the package chip and the second substrate layer set, and the package chip is soldered and fixed to the second substrate layer set through the second conductive solder layer. The first substrate layer set comprises a first conductive substrate and a first heat dissipation substrate, the first conductive substrate is electrically connected to the first electroplating layer, and the first heat dissipation substrate is located on a side of the first conductive substrate away from the package chip.

6. The chip package assembly of any one of claims 1 to 5, wherein, The first heat dissipation substrate comprises a first substrate body and a plurality of first heat dissipation fins, the first substrate body is connected to the side of the first conductive substrate away from the package chip, and the plurality of first heat dissipation fins are spaced apart from each other on a side of the first substrate body away from the first conductive substrate.

7. The chip package assembly of claim 6, wherein, The first substrate layer set comprises a first output terminal, which is connected to a side of the first conductive substrate facing the package chip, and the first output terminal is electrically connected to the bare chip through the first conductive substrate and the first electroplating layer.

8. The chip package assembly of claim 6 or 7, wherein, The first substrate layer set comprises a first signal terminal and a second signal terminal spaced apart from each other, the first signal terminal and the second signal terminal are connected to a side of the first conductive substrate facing the package chip, and the first signal terminal and the second signal terminal are electrically connected to the bare chip through the first conductive substrate and the first electroplating layer respectively.

9. The chip package assembly of any one of claims 6 to 8, wherein, ​ 10. The chip package assembly of any one of claims 1 to 9, wherein, The second substrate layer set comprises a second conductive substrate and a second heat dissipation substrate, the second conductive substrate is conductively connected with the second plating layer, and the second heat dissipation substrate is located on the side of the second conductive substrate away from the packaged chip.

11. The chip package assembly of claim 10, wherein, The second heat dissipation substrate comprises a second substrate body and a plurality of second heat dissipation fins, the second substrate body is connected to the side of the second conductive substrate away from the packaged chip, and the plurality of second heat dissipation fins are arranged on the side of the second substrate body away from the second conductive substrate.

12. The chip package assembly of claim 10 or 11, wherein, The second substrate layer set comprises a second output terminal, the second output terminal is connected to the side of the second conductive substrate facing the packaged chip, and the second output terminal is conductively connected with the bare chip through the second conductive substrate and the second plating layer.

13. The chip package assembly of any one of claims 1 to 12, wherein, The chip packaging assembly comprises a support, the support is supported between the first substrate layer set and the second substrate layer set, and the support surrounds the packaged chip.

14. An electronic device, comprising: The electronic device comprises the chip packaging assembly according to any one of claims 1 to 13.

15. A method of manufacturing a chip package assembly as claimed in any one of claims 1 to 13, characterized in that, The preparation method comprises: Preparation of a packaged chip; wherein the packaged chip comprises a bare chip, a first plating layer and a second plating layer, the bare chip comprises a first electrode surface and a second electrode surface arranged oppositely; The first substrate layer set and the second substrate layer set are arranged on the two opposite sides of the packaged chip, so that the first plating layer is conductively connected with the first electrode surface and the first substrate layer set respectively, and the second plating layer is conductively connected with the second electrode surface and the second substrate layer set respectively, to form the chip packaging assembly.

16. The method of claim 15, wherein, The preparation of the packaged chip comprises: Forming a second plating layer on a panel; Fixing the bare chip on the side of the second plating layer away from the panel, so that the second electrode surface is conductively connected with the second plating layer; Forming a first plating layer on the side of the bare chip away from the second plating layer, so that the first electrode surface is conductively connected with the first plating layer.

17. The method of claim 16, wherein the method further comprises, The step of forming a first plating layer on the side of the bare chip away from the second plating layer comprises: Applying a filler to the peripheral side of the bare chip; Etching the filler from the side of the bare chip away from the second plating layer to expose the first electrode and the second electrode in the first electrode surface; Forming a first sub-plating layer and a second sub-plating layer on the side of the bare chip away from the second plating layer, so that the first sub-plating layer is conductively connected with the first electrode, and the second sub-plating layer is conductively connected with the second electrode, to obtain the packaged chip.

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