Semiconductor chip and semiconductor package including same

Abstract

A semiconductor chip and a semiconductor package including the same are provided. The semiconductor chip includes a semiconductor substrate including a first surface and a second surface opposite to the first surface; a wiring layer disposed on the first surface of the semiconductor substrate; a plurality of through electrodes extending from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate; a plurality of chip pads disposed on the second surface of the semiconductor substrate and electrically connected to the plurality of through electrodes; and a passivation layer disposed on the second surface of the semiconductor substrate and in contact with side surfaces of the plurality of chip pads. The passivation layer includes an insulating layer and an oxide layer disposed on the insulating layer. The insulating layer includes an insulating pattern having a first width along a horizontal direction. The oxide layer includes a first oxide pattern having a second width along the horizontal direction. The first width is greater than the second width.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0117942, filed on August 30, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to semiconductor chips and semiconductor packages, and more specifically, to semiconductor chips including through electrodes and semiconductor packages including semiconductor chips. Background Technology

[0003] Driven by the rapid development of the electronics industry and user demands, electronic devices have become larger, smaller, and more multifunctional, requiring more integrated semiconductor chips. As a result, semiconductor packages have been developed that incorporate highly integrated semiconductor chips with more connection terminals for input / output (I / O) and ensure reliable connections. Summary of the Invention

[0004] Various aspects of the inventive concept provide a semiconductor chip with improved adhesion to a molding layer and a semiconductor package including the semiconductor chip.

[0005] The technical ideas of the inventive concept seek to achieve purposes not limited to those described above, and other purposes will be clearly understood by those skilled in the art from the following description.

[0006] According to one aspect of the inventive concept, a semiconductor chip is provided, comprising: a semiconductor substrate including a first surface and a second surface opposite to the first surface; a wiring layer disposed on the first surface of the semiconductor substrate; a plurality of through electrodes extending from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate; a plurality of chip pads disposed on the second surface of the semiconductor substrate and electrically connected to the plurality of through electrodes; and a passivation layer disposed on the second surface of the semiconductor substrate and in contact with the side surfaces of the plurality of chip pads. The passivation layer includes an insulating layer and an oxide layer, the oxide layer being disposed on the insulating layer. The insulating layer includes an insulating pattern having a first width along a horizontal direction. The oxide layer includes a first oxide pattern having a second width along a horizontal direction. The first width is greater than the second width.

[0007] According to another aspect of the inventive concept, a semiconductor chip is provided, comprising: a semiconductor substrate including a first surface and a second surface opposite to the first surface; a wiring layer disposed on the first surface of the semiconductor substrate; a plurality of through electrodes extending from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate; a plurality of chip pads disposed on the second surface of the semiconductor substrate and electrically connected to the plurality of through electrodes; and a passivation layer disposed on the second surface of the semiconductor substrate and contacting the side surfaces of the plurality of chip pads, and comprising an insulating layer and an oxide layer, the oxide layer being disposed on the insulating layer. The surface area of ​​the upper surface of the oxide layer is smaller than the surface area of ​​the upper surface of the insulating layer. In a plan view, the semiconductor substrate has a first region and a second region, the second region surrounding the first region. In a plan view, the first region has a rectangular shape. The oxide layer is disposed on the first region and the second region. The oxide layer includes an opening located in the second region. The opening is recessed from the upper surface of the oxide layer to the lower surface of the oxide layer. The oxide layer includes a first oxide pattern, and the insulating layer includes an insulating pattern. In a plan view, the side surfaces of the first oxide pattern are disposed within and separate from the side surfaces of the insulating pattern.

[0008] According to another aspect of the inventive concept, a semiconductor package is provided, including a first semiconductor chip. The first semiconductor chip includes: a first semiconductor substrate including a first surface and a second surface opposite to the first surface; a plurality of first through electrodes passing through the first semiconductor substrate; a passivation layer disposed on the second surface of the first semiconductor substrate; and a plurality of first chip pads contacting the plurality of first through electrodes and surrounded by the passivation layer. The semiconductor package further includes a second semiconductor chip and a molding layer, the second semiconductor chip being stacked on the first semiconductor chip and having a width smaller than that of the first semiconductor chip, the molding layer being disposed on the passivation layer of the first semiconductor chip and contacting at least a portion of a side surface of the second semiconductor chip. The passivation layer of the first semiconductor chip includes an insulating layer and an oxide layer, the oxide layer being disposed on the insulating layer. The insulating layer includes an insulating pattern having a first width along a horizontal direction. The oxide layer includes a first oxide pattern having a second width along a horizontal direction. The first width is greater than the second width, and in a plan view, the side surface of the first oxide pattern of the passivation layer is disposed within the insulating pattern of the passivation layer. The second semiconductor chip is in contact with the first oxide pattern of the passivation layer of the first semiconductor chip.

[0009] According to another aspect of the inventive concept, a method for manufacturing a semiconductor package is provided, the method comprising: mounting a first semiconductor substrate on a carrier substrate such that a first surface of the first semiconductor substrate points toward the carrier substrate; forming a passivation layer on a second surface of the first semiconductor substrate; forming a plurality of first chip pads on the passivation layer such that the plurality of first chip pads are electrically connected to a plurality of first through electrodes passing through the first semiconductor substrate; forming a trench extending from an upper surface of the passivation layer into the passivation layer such that the sidewalls of the trench are disposed separately from the side surfaces of the plurality of first chip pads; mounting a semiconductor chip on the passivation layer; and forming a molding layer on the passivation layer to surround the semiconductor chip. Attached Figure Description

[0010] The embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 This is a schematic plan view of a first semiconductor chip according to an embodiment.

[0012] Figure 2 It is schematically shown along Figure 1 The line A-A' cuts Figure 1 A cross-sectional view of the first semiconductor chip.

[0013] Figure 3 It is shown schematically. Figure 2 An enlarged view of part EX1 of the first semiconductor chip.

[0014] Figure 4 This is a schematic cross-sectional view of a first semiconductor chip according to an embodiment.

[0015] Figure 5 This is a schematic plan view of a first semiconductor chip according to an embodiment.

[0016] Figure 6 It is schematically shown along Figure 5 The line B-B' cut Figure 5 A cross-sectional view of the first semiconductor chip.

[0017] Figure 7 It is shown schematically. Figure 6 An enlarged view of part EX2 of the first semiconductor chip.

[0018] Figure 8 This is a schematic cross-sectional view of a first semiconductor chip according to an embodiment.

[0019] Figure 9 This is a schematic plan view of a first semiconductor chip according to an embodiment.

[0020] Figure 10 This is a schematic plan view of a first semiconductor chip according to an embodiment.

[0021] Figure 11 This is a schematic plan view of a first semiconductor chip according to an embodiment.

[0022] Figure 12 This is a schematic cross-sectional view of a semiconductor package according to an embodiment.

[0023] Figure 13 This is a schematic cross-sectional view of a semiconductor package according to an embodiment.

[0024] Figure 14 This is a schematic cross-sectional view of a semiconductor package according to an embodiment.

[0025] Figures 15A to 15G Each is a diagram illustrating a method for manufacturing a semiconductor package according to an embodiment. Detailed Implementation

[0026] Because the inventive concept allows for various modifications and numerous embodiments, embodiments will be shown in the accompanying drawings and described in detail in the written description. However, this is not intended to limit the invention to the specific description.

[0027] For example, as can be seen in the accompanying drawings, items described herein in the singular may be provided in the plural. Therefore, unless the context otherwise requires, a description of a single item provided in the plural form should be understood to apply to the remaining multiple items.

[0028] Throughout this specification, when a component is described as "comprising" a specific element or group of elements, it should be understood that, unless the context otherwise requires, the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with other elements to form the component. On the other hand, the term "composed of" indicates that the component is formed solely by the listed elements.

[0029] As used herein, terms such as “identical,” “equal,” “planar,” “coplanar,” “parallel,” and “perpendicular” cover near-identical properties, including similarity or variations that may arise from conventional manufacturing processes. Unless the context or other statement otherwise indicates otherwise, the term “basically” may be used herein to emphasize this meaning.

[0030] Ordinal numbers such as "first," "second," and "third" can be simply used as labels to distinguish specific elements, steps, etc., from one another. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Furthermore, terms referenced in a particular claim using a specific ordinal number (e.g., "first") may be described elsewhere in the specification or in other claims using a different ordinal number (e.g., "second").

[0031] Figure 1 This is a schematic plan view of the first semiconductor chip 100 according to an embodiment. Figure 2 It is schematically shown along Figure 1 The line A-A' cuts Figure 1 A cross-sectional view of the first semiconductor chip 100. Figure 3 It is shown schematically. Figure 2 An enlarged view of part EX1 of the first semiconductor chip 100.

[0032] Reference Figures 1 to 3 The first semiconductor chip 100 may include: a first semiconductor substrate 110, a first wiring structure 120, a plurality of first through electrodes 140, a plurality of first chip pads (or solder pads) 130_P, and a first passivation layer 130.

[0033] Unless otherwise specified, the direction parallel to the upper surface of the first semiconductor substrate 110 is defined as the first horizontal direction (X direction), the direction perpendicular to the upper surface of the first semiconductor substrate 110 is defined as the vertical direction (Z direction), and the direction perpendicular to both the first horizontal direction (X direction) and the vertical direction (Z direction) is defined as the second horizontal direction (Y direction). The direction obtained by combining the first horizontal direction (X direction) and the second horizontal direction (Y direction) is defined as the horizontal direction.

[0034] The first semiconductor substrate 110 may include an active surface 110_A and an active surface 110_UA. In some embodiments, the active surface 110_A of the first semiconductor substrate 110 may be referred to as the front surface of the first semiconductor substrate 110, and the active surface 110_UA of the first semiconductor substrate 110 may be referred to as the rear surface of the first semiconductor substrate 110.

[0035] The first semiconductor substrate 110 may include a semiconductor material such as silicon (Si). Alternatively, the first semiconductor substrate 110 may include a semiconductor material such as germanium (Ge).

[0036] An integrated circuit comprising multiple individual devices (components) of various types may be formed on the active surface 110_A of the first semiconductor substrate 110. The multiple individual devices formed on the first semiconductor substrate 110 may include microelectronic devices (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs) or complementary metal-oxide-semiconductor (CMOS) transistors). For example, the integrated circuit may include large-scale integration (LSI), image sensors (e.g., CMOS imaging sensors (CIS)), microelectromechanical systems (MEMS), active devices, and / or passive devices.

[0037] The first wiring structure 120 may be a first wiring layer disposed on the active surface 110_A of the first semiconductor substrate 110. The first wiring structure 120 may be electrically connected to a semiconductor device disposed on the active surface 110_A of the first semiconductor substrate 110.

[0038] The first wiring structure 120 may be a composite layer including a first wiring pattern 121 and a first wiring insulating layer 122 surrounding the first wiring pattern 121. The first wiring pattern 121 may include a first wiring line 121_L and a first wiring via 121_V, the first wiring line 121_L extending in a horizontal direction and the first wiring via 121_V extending from the first wiring line 121_L in a vertical direction (Z direction). The first wiring pattern 121 may be electrically connected to a plurality of individual devices on the first semiconductor substrate 110.

[0039] A portion of the first wiring line 121_L of the first wiring pattern 121 of the first wiring structure 120 may be exposed to the outside (external environment). For example, the exposed portion of the first wiring line 121_L may be referred to as a first frontpad. An external connection terminal CT may be attached to the first frontpad. For example, each first frontpad may be electrically connected to a corresponding first through electrode 140.

[0040] The external connection terminal CT can electrically and physically connect the first semiconductor chip 100 to an external device on which the first semiconductor chip 100 is mounted. The external connection terminal CT can be, for example, a solder ball or a solder bump, or can be formed from, for example, solder balls or solder bumps.

[0041] Each of the plurality of first through electrodes 140 may extend from an active surface 110_A of the first semiconductor substrate 110 to an active surface 110_UA of the first semiconductor substrate 110. For example, each of the plurality of first through electrodes 140 may pass through at least a portion of the first semiconductor substrate 110. For example, the plurality of first through electrodes 140 may be electrically connected to a first wiring structure 120.

[0042] Multiple first chip pads 130_P may be disposed on the non-active surface 110_UA of the first semiconductor substrate 110. The first chip pads 130_P may also be referred to as first back pads. For example, the multiple first chip pads 130_P may be exposed to the outside. For example, the lower surface of each of the multiple first chip pads 130_P may contact a plurality of first through electrodes 140, and the upper surface of each of the multiple first chip pads 130_P may be exposed to the outside.

[0043] Each of the plurality of first chip pads 130_P is electrically connected to each of the plurality of first through electrodes 140. For example, the plurality of first chip pads 130_P may each correspond to a plurality of first through electrodes 140. For example, each of the plurality of first chip pads 130_P is electrically connected to a corresponding one of the plurality of first through electrodes 140. For example, although Figure 2 The diagram shows a plurality of first chip pads 130_Ps that are distinguishable from a plurality of first through electrodes 140, but the plurality of first chip pads 130_Ps and the plurality of first through electrodes 140 can be integrated. For example, a corresponding pair of first chip pads 130_Ps and first through electrodes 140 can be integrally formed from the same material (together) without a boundary interface between them.

[0044] In some embodiments, the plurality of first through electrodes 140 and the plurality of first chip pads 130_P may comprise copper, nickel, stainless steel or beryllium copper.

[0045] The first passivation layer 130 may be disposed on the non-active surface 110_UA of the first semiconductor substrate 110. For example, the first passivation layer 130 may be disposed separately from the first wiring structure 120, with the first semiconductor substrate 110 located between the first passivation layer 130 and the first wiring structure 120. For example, the first passivation layer 130 may be referred to as a post-passivation layer.

[0046] A first passivation layer 130 may surround a plurality of first chip pads 130_P. For example, the first passivation layer 130 may contact the side surfaces of the plurality of first chip pads 130_P. The first passivation layer 130 may externally protect the plurality of first chip pads 130_P.

[0047] The first passivation layer 130 may include an insulating layer 131 and an oxide layer 132. The oxide layer 132 may be disposed on the insulating layer 131. For example, the lower surface of the insulating layer 131 may contact the first semiconductor substrate 110, and the upper surface of the insulating layer 131 may contact the oxide layer 132. In some embodiments, the hardness of the insulating layer 131 may be greater than the hardness of the oxide layer 132. For example, the insulating layer 131 may include silicon nitride. The oxide layer 132 may include silicon oxide. In some embodiments, the upper surface of each of the plurality of first chip pads 130_P may be coplanar with the upper surface of the oxide layer 132 of the passivation layer 130L.

[0048] The width of oxide layer 132 may be smaller than the width of insulating layer 131. The side surface of insulating layer (or insulating pattern) 131 may be aligned with the side surface of first semiconductor substrate 110 in the vertical direction (Z direction). The side surface of oxide layer 132 may be superimposed on the upper surface of insulating layer 131 in the vertical direction (Z direction). The side surface of oxide layer 132 may be arranged separately from the side surface of insulating layer 131. For example, a portion of the upper surface of insulating layer 131 may not be covered by oxide layer 132.

[0049] In some embodiments, insulating layer 131 may include an insulating pattern. In a plan view, the side surface of the insulating pattern of the first passivation layer 130 may be aligned with the side surface of the first semiconductor substrate 110. Oxide layer 132 may include an oxide pattern. In a plan view, the side surface of the oxide pattern of the first passivation layer 130 may be disposed within the insulating pattern of the first passivation layer 130. The insulating pattern and the oxide pattern may each have a first width and a second width along a horizontal direction. The first width may be greater than the second width. The oxide pattern may have a via in which the first chip pad 130_P is disposed.

[0050] The thickness of the first passivation layer 130 may include regions having different thicknesses from each other. For example, the thickness (i.e., vertical dimension) of the combination of insulating layer 131 and oxide layer 132 may vary across different regions. For example, the first passivation layer 130 may include a region in which both oxide layer 132 and insulating layer 131 are present and another region in which only insulating layer 131 is present, and these two regions may have different thicknesses from each other. The thickness of the first passivation layer 130 in the region in which both oxide layer 132 and insulating layer 131 are present may be greater than the thickness of the first passivation layer 130 in the region in which only insulating layer 131 is present.

[0051] In some embodiments, in a plan view, the insulating layer 131 of the first passivation layer 130 may have a first region 131_A1 and a second region 131_A2, with the second region 131_A2 surrounding the first region 131_A1. In the first region 131_A1 of the insulating layer 131, the upper surface of the insulating layer 131 may be covered by an oxide layer 132, and in the second region 131_A2 of the insulating layer 131, the upper surface of the insulating layer 131 may be exposed to the outside. For example, the portion of the first passivation layer 130 disposed in the first region 131_A1 of the insulating layer 131 in a plan view may be thicker than the portion of the first passivation layer 130 disposed in the second region 131_A2 of the insulating layer 131 in a plan view.

[0052] For example, in a plan view, the first region 131_A1 of the insulating layer 131 may include the center of the upper surface of the insulating layer 131, and the second region 131_A2 of the insulating layer 131 may include the side portion of the upper surface of the insulating layer 131. For example, in a plan view, the second region 131_A2 of the insulating layer 131 may include the peripheral region of the upper surface of the insulating layer 131. The first region 131_A1 of the insulating layer 131 may be referred to as the central region, and the second region 131_A2 of the insulating layer 131 may be referred to as the edge region.

[0053] Multiple first through electrodes 140 and multiple first chip pads 130_P may be stacked with the first region 131_A1 of the insulating layer 131 of the first passivation layer 130 in the vertical direction (Z direction). For example, the upper surfaces of the multiple first chip pads 130_P may be arranged on the same plane as the upper surface of the oxide layer 132 of the first passivation layer 130. The multiple first through electrodes 140 and multiple first chip pads 130_P may be arranged separately from the portion of the first passivation layer 130 where the oxide layer 132 is not present. The multiple first through electrodes 140 and multiple first chip pads 130_P may be arranged separately from the second region 131_A2 of the insulating layer 131 of the first passivation layer 130 in the horizontal direction.

[0054] Reference Figure 3 The shape of the oxide layer 132 and the insulating layer 131 of the first passivation layer 130 is described.

[0055] The oxide layer 132 of the first passivation layer 130 may have a width that varies with its distance from the insulating layer 131. The oxide layer 132 may have a horizontal width that increases with proximity to the insulating layer 131. For example, the side surfaces and the top surface of the oxide layer 132 may form an obtuse angle. In some embodiments, in the process of forming the oxide layer 132, a photolithography process may be performed on the oxide layer 132, and the width of the oxide layer 132 may increase downward in the vertical direction (Z direction). For example, the oxide layer 132 may be patterned to form an oxide pattern with a trapezoidal vertical cross-section. The oxide pattern may have a width that increases horizontally from its top surface to its bottom surface. The width at the top surface is smaller than the width at the bottom surface. The sidewalls of the oxide pattern may have an inclination relative to the top surface of the first semiconductor substrate 110. The first region 131_A1 of the insulating layer 131 may be covered by the oxide layer 132, and the second region 131_A2 of the insulating layer 131 may be exposed to the outside. In the first region 131_A1 of the insulating layer 131, the upper surface of the insulating layer 131 may have a flat shape, and in the second region 131_A2 of the insulating layer 131, the upper surface of the insulating layer 131 may have a concave shape.

[0056] In some embodiments, by performing a photolithography process on an insulating layer 131 and an oxide layer 132 conformally formed on an active surface 110_UA of a first semiconductor substrate 110, the oxide layer 132 can be partially removed, exposing a second region 131_A2 of the insulating layer 131 to the outside. During the photolithography process, in the first region 131_A1 of the insulating layer 131, the upper surface of the insulating layer 131 may be located below and protected from the oxide layer 132, and maintain a flat shape. On the other hand, during the photolithography process (and associated etching process), in the second region 131_A2 of the insulating layer 131, the upper surface of the insulating layer 131 may be partially removed together with the oxide layer 132, and the upper surface of the insulating layer 131 may have a concave shape in the second region 131_A2 of the insulating layer 131.

[0057] Figure 4 This is a schematic cross-sectional view of a first semiconductor chip 100a according to an embodiment.

[0058] The components constituting the first semiconductor chip 100a described below, and the materials included in those components, are consistent with the above references. Figure 2 The components and materials described are essentially the same or similar. Therefore, for simplicity, the focus will be on... Figure 4 The first semiconductor chip 100a and Figure 2 The embodiments are described using the differences between the first semiconductor chips 100.

[0059] Reference Figure 4 The first semiconductor chip 100a may include a first semiconductor substrate 110, a first wiring structure 120, a plurality of first through electrodes 140, a plurality of first chip pads 130_P, and a first passivation layer 130a.

[0060] A plurality of first through electrodes 140 may extend from the active surface 110_A of the first semiconductor substrate 110 to the non-active surface 110_UA of the first semiconductor substrate 110. In some embodiments, a portion of each of the plurality of first through electrodes 140 may protrude over the non-active surface 110_UA of the first semiconductor substrate 110.

[0061] Multiple first chip pads 130_P may be disposed on portions of multiple first through electrodes 140 that protrude beyond the first semiconductor substrate 110. For example, multiple first chip pads 130_P may be disposed on the upper surface of multiple first through electrodes 140. In some embodiments, the multiple first chip pads 130_P may be integrated with the multiple first through electrodes 140.

[0062] The first passivation layer 130a may include an intermediate oxide layer 134, an insulating layer 131, and an oxide layer 132. The intermediate oxide layer 134 may be disposed on the non-active surface 110_UA of the first semiconductor substrate 110, the insulating layer 131 may be disposed on the upper surface of the intermediate oxide layer 134, and the oxide layer 132 may be disposed on the upper surface of the insulating layer 131. For example, the intermediate oxide layer 134 may be disposed between the insulating layer 131 and the first semiconductor substrate 110. The intermediate oxide layer 134 may be disposed between the insulating layer 131 and the first semiconductor substrate 110 to suppress delamination of the insulating layer 131. For example, the intermediate oxide layer 134 may include silicon oxide, the insulating layer 131 may include silicon nitride, and the oxide layer 132 may include silicon oxide.

[0063] In some embodiments, the width of the intermediate oxide layer 134 may be substantially the same as the width of the insulating layer 131. The side surfaces of the intermediate oxide layer 134 may be aligned with the side surfaces of the first semiconductor substrate 110 in the vertical direction (Z direction). In some embodiments, the width of the oxide layer 132 may be smaller than the width of the insulating layer 131. The side surfaces of the oxide layer 132 may overlap with the upper surface of the insulating layer 131 in the vertical direction. For example, the intermediate oxide layer 134 may include an intermediate oxide pattern. In this case, the width of the intermediate oxide pattern of the intermediate oxide layer 134 may be substantially the same as the width of the insulating layer 131 (or the insulating pattern). In a plan view, the side surfaces of the oxide pattern of the oxide layer 132 may be arranged within the intermediate oxide pattern.

[0064] In some embodiments, a first passivation layer 130a may surround a plurality of first through electrodes 140 and a plurality of first chip pads 130_P. In some embodiments, an oxide layer 132 of the first passivation layer 130a may surround the side surfaces of the plurality of first chip pads 130_P, and an insulating layer 131 and an intermediate oxide layer 134 may partially surround the side surfaces of the plurality of first through electrodes 140.

[0065] Figure 5 This is a schematic plan view of the first semiconductor chip 100b according to an embodiment. Figure 6 It is schematically shown along Figure 5 The line B-B' cut Figure 5 A cross-sectional view of the first semiconductor chip 100b. Figure 7 It is shown schematically. Figure 6 An enlarged view of part EX2 of the first semiconductor chip 100b.

[0066] The components constituting the first semiconductor chip 100b described below, and the materials included in those components, are consistent with the above references. Figure 2The components and materials described are essentially the same or similar. Therefore, for simplicity, the focus will be on... Figure 6 The first semiconductor chip 100b and Figure 2 The embodiments are described using the differences between the first semiconductor chips 100.

[0067] Reference Figures 5 to 7 The first semiconductor chip 100b may include a first semiconductor substrate 110, a first wiring structure 120, a plurality of first through electrodes 140, a plurality of first chip pads 130_P and a first passivation layer 130b.

[0068] The first semiconductor substrate 110 may include an active surface 110_A and an active surface 110_UA opposite to the active surface 110_A, with multiple individual devices arranged on the active surface 110_A. For example, the active surface 110_A of the first semiconductor substrate 110 may be referred to as the front surface, and the active surface 110_UA of the first semiconductor substrate 110 may be referred to as the rear surface.

[0069] The first wiring structure 120 may be disposed on the active surface 110_A of the first semiconductor substrate 110. The first wiring structure 120 may be electrically connected to a plurality of individual devices on the active surface 110_A of the first semiconductor substrate 110.

[0070] The first wiring structure 120 may include a first wiring pattern 121 and a first wiring insulation layer 122, the first wiring insulation layer 122 surrounding the first wiring pattern 121. The first wiring pattern 121 may include a first wiring line 121_L and a first wiring via 121_V, the first wiring line 121_L extending in a horizontal direction, and the first wiring via 121_V extending from the first wiring line 121_L in a vertical direction (Z direction). The portion of the first wiring line 121_L arranged at the bottom and exposed to the outside may be referred to as a first front pad. An external connection terminal CT may be attached to the first front pad.

[0071] Multiple first through electrodes 140 may extend from the active surface 110_A of the first semiconductor substrate 110 to the non-active surface 110_UA of the first semiconductor substrate 110. For example, the multiple first through electrodes 140 may be connected to multiple individual devices of the first wiring structure 120 and the first semiconductor substrate 110.

[0072] Multiple first chip pads 130_P may be disposed on the upper surface of multiple first through electrodes 140. In some embodiments, the width of the multiple first chip pads 130_P may be greater than the width of the multiple first through electrodes 140. The multiple first chip pads 130_P may be disposed on the non-active surface 110_UA of the first semiconductor substrate 110, and the multiple first chip pads 130_P may be referred to as multiple first back pads.

[0073] The first passivation layer 130b may be disposed on the non-active surface 110_UA of the first semiconductor substrate 110. The first passivation layer 130b may be disposed separately from the first wiring structure 120 in the vertical direction (Z direction). For example, the first passivation layer 130b may be disposed separately from the first wiring structure 120, with the first semiconductor substrate 110 located between the first passivation layer 130b and the first wiring structure 120.

[0074] For example, the first passivation layer 130b may contact the side surfaces of a plurality of first chip pads 130_P. The first passivation layer 130b may externally protect the plurality of first chip pads 130_P. For example, the first passivation layer 130b may be referred to as a post-passivation layer.

[0075] The first passivation layer 130b may include an insulating layer 131 and an oxide layer 133, with the oxide layer 133 disposed on the insulating layer 131. The hardness of the insulating layer 131 may be greater than the hardness of the oxide layer 133. For example, the insulating layer 131 may include silicon nitride, and the oxide layer 133 may include silicon oxide.

[0076] The width of the insulating layer 131 may be the same as the width of the first semiconductor substrate 110, and the width of the oxide layer 133 may be smaller than the width of the insulating layer 131. The side surfaces of the oxide layer 133 may overlap with the upper surface of the insulating layer 131 in the vertical direction (Z direction). The side surfaces of the oxide layer 133 may be arranged separately from the side surfaces of the insulating layer 131. For example, a portion of the upper surface of the insulating layer 131 may be covered by the oxide layer 133, and the remaining portion of the upper surface of the insulating layer 131 may be exposed to the outside.

[0077] The central region of the insulating layer 131 may be covered by the oxide layer 133, and the edge regions of the insulating layer 131 may be exposed to the outside. A portion of the upper surface of the insulating layer 131 located at the edge of the oxide layer 133 may be exposed to the outside. For example, a portion of the upper surface of the insulating layer 131 located further outward than the side surface of the peripheral region 133_P of the oxide layer 133 may be exposed to the outside.

[0078] The oxide layer 133 may include a planar region 133_C and a peripheral region 133_P. The peripheral region 133_P may surround the planar region 133_C. For example, the planar region 133_C of the oxide layer 133 may include the center of the upper surface of the oxide layer 133, and the peripheral region 133_P of the oxide layer 133 may include the side surface of the oxide layer 133. In some embodiments, the planar region 133_C of the oxide layer 133 may be where a second semiconductor chip 200 is stacked (see...). Figure 12 ( ) area.

[0079] For example, the first semiconductor substrate 110 may have a first region and a second region, with the second region surrounding the first region. In a plan view, the first region has a rectangular shape (a solid rectangle). In a plan view, the second region has a rectangular ring shape. In a plan view, the second semiconductor chip 200 (see...) Figure 12 It can be overlaid with the first region of a rectangular shape.

[0080] In the peripheral region 133_P of oxide layer 133 (or on the second region), a groove (opening) 133_R may be arranged recessed from the upper surface of oxide layer 133 toward the lower surface of oxide layer 133. A portion of the upper surface of insulating layer 131 located below the groove 133_R of oxide layer 133 may be exposed to the outside. For example, a portion of the upper surface of insulating layer 131 may be exposed to the outside through groove 133_R. A portion of oxide layer 133 located in the planar region 133_C of oxide layer 133 may be referred to as a planar surface (or first oxide pattern) 1331. A portion of oxide layer 133 located in the peripheral region 133_P of oxide layer 133 may be referred to as a plurality of second oxide patterns 1332. For example, in the peripheral region 133_P of oxide layer 133, the unrecessed portion of oxide layer 133 may be referred to as a plurality of second oxide patterns 1332.

[0081] For example, oxide layer 133 may be disposed on a first region and a second region. Planar region 133_C and peripheral region 133_P correspond to the first region and the second region, respectively. Oxide layer 133 may include multiple oxide patterns. The multiple oxide patterns may include a first oxide pattern 1331 and multiple second oxide patterns 1332. First oxide pattern 1331 may be disposed on the first region, and multiple second oxide patterns 1332 may be disposed on the second region. For example, in the first region, the upper surface of insulating layer 131 may be covered by oxide layer 133. In the second region, a portion of the upper surface of insulating layer 131 may be covered by multiple second oxide patterns, and other portions of the upper surface of insulating layer 131 may be exposed relative to oxide layer 133.

[0082] The vertical height of the upper surface of plane 1331 may be the same as the vertical height of the upper surface of each of the plurality of second oxide patterns 1332. For example, the plurality of second oxide patterns 1332 may be unrecessed areas of oxide layer 133 and may be substantially the same as plane 1331. For example, after patterning (partially removing) oxide layer 133, plane 1331 and the plurality of second oxide patterns 1332 may be the remaining (unremoved) portion of oxide layer 133.

[0083] Multiple first chip pads 130_P may be arranged in a planar region 133_C of oxide layer 133. For example, multiple first through electrodes 140 may be located below the multiple first chip pads 130_P and may be stacked with the planar region 133_C of oxide layer 133 in the vertical direction (Z direction). For example, each of the multiple first chip pads 130_P may contact a corresponding first through electrode of the multiple first through electrodes 140 and be surrounded by a first passivation layer 130b. Oxide layer 133 may contact the side surfaces of the multiple first chip pads 130_P. The sidewalls of the oxide pattern may be sloped relative to the upper surface of the first semiconductor substrate 110.

[0084] Reference Figure 7 In the planar region 133_C of oxide layer 133, the width of the plane (first oxide pattern) 1331 may increase toward the insulating layer 131. In the peripheral region 133_P of oxide layer 133, the width of each of the plurality of second oxide patterns 1332 may increase toward the insulating layer 131.

[0085] A first portion of the upper surface of the insulating layer 131 of the first passivation layer 130b, located below the groove 133_R of the oxide layer 133, and a second portion of the upper surface of the insulating layer 131 of the first passivation layer 130b, located at the edge of the oxide layer 133, may be exposed to the outside. The first and second portions of the upper surface of the insulating layer 131 exposed to the outside may have a concave shape. For example, in a process of partially removing the oxide layer 133 to expose the upper surface of the insulating layer 131, a portion of the upper surface of the insulating layer 131 may be removed and may have a concave shape.

[0086] Reference Figure 5 Multiple second oxide patterns 1332 may be arranged horizontally separate from the plane 1331. The multiple second oxide patterns 1332 may be arranged horizontally separate from each other. For example, the upper surfaces of the multiple second oxide patterns 1332 may have the same surface area. The multiple second oxide patterns 1332 may be spaced apart from each other by a certain distance. In some embodiments, the upper surface of each of the multiple second oxide patterns 1332 may have a quadrilateral shape.

[0087] In some embodiments, in the peripheral region 133_P of the oxide layer 133, the surface area of ​​the upper surface of the oxide layer 133 may represent the sum of the surface areas of the upper surfaces of a plurality of second oxide patterns 1332. In the peripheral region 133_P of the oxide layer 133, the surface area of ​​the upper surface of the oxide layer 133 may be smaller than the surface area of ​​the portion of the upper surface of the insulating layer 131 exposed to the outside. The sum of the upper surfaces of the plurality of second oxide patterns 1332 may be smaller than the surface area of ​​the portion of the upper surface of the insulating layer 131 exposed to the outside.

[0088] Figure 8 This is a schematic cross-sectional view of a first semiconductor chip 100c according to an embodiment.

[0089] The components constituting the first semiconductor chip 100c described below, and the materials included in those components, are consistent with the above references. Figure 6 The components and materials described are essentially the same or similar. Therefore, for simplicity, the focus will be on... Figure 8 The first semiconductor chip 100c and Figure 6 The embodiments are described using the differences between the first semiconductor chip 100b.

[0090] Reference Figure 8 The first semiconductor chip 100c may include: a first semiconductor substrate 110, a first wiring structure 120, a plurality of first through electrodes 140, a plurality of first chip pads 130_P, and a first passivation layer 130c.

[0091] The first passivation layer 130c may include an intermediate oxide layer 134, an insulating layer 131, and an oxide layer 133. The intermediate oxide layer 134 may be disposed on the non-active surface 110_UA of the first semiconductor substrate 110, the insulating layer 131 may be disposed on the upper surface of the intermediate oxide layer 134, and the oxide layer 133 may be disposed on the upper surface of the insulating layer 131. For example, the intermediate oxide layer 134 may be disposed between the insulating layer 131 and the first semiconductor substrate 110.

[0092] An intermediate oxide layer 134 may be disposed between the insulating layer 131 and the first semiconductor substrate 110 to suppress delamination of the insulating layer 131. For example, the intermediate oxide layer 134 may include silicon oxide, the insulating layer 131 may include silicon nitride, and the oxide layer 133 may include silicon oxide.

[0093] In some embodiments, the width of the intermediate oxide layer 134 may be substantially the same as the width of the insulating layer 131. The side surfaces of the intermediate oxide layer 134 may be aligned with the side surfaces of the first semiconductor substrate 110 in the vertical direction (Z direction). In some embodiments, the width of the oxide layer 133 may be smaller than the width of the insulating layer 131. The side surfaces of the oxide layer 133 may overlap with the upper surface of the insulating layer 131 in the vertical direction. For example, the intermediate oxide layer 134 may include an intermediate oxide pattern. In a plan view, the side surfaces of the first oxide pattern of the oxide layer 133 may be disposed within the intermediate oxide pattern.

[0094] In some embodiments, the first passivation layer 130c may surround a plurality of first through electrodes 140 and a plurality of first chip pads 130_P. In some embodiments, the plane 1331 of the oxide layer 133 of the first passivation layer 130c (see...) Figure 6The insulating layer 131 and the intermediate oxide layer 134 may partially surround the side surfaces of the multiple first through electrodes 140, which may surround the side surfaces of the multiple first through electrodes 140.

[0095] Figure 9 This is a schematic plan view of a first semiconductor chip 100d according to an embodiment. Figure 10 This is a schematic plan view of the first semiconductor chip 100e according to an embodiment. Figure 11 This is a schematic plan view of the first semiconductor chip 100f according to an embodiment.

[0096] The following description of most of the components constituting the first semiconductor chip (100d, 100e, and 100f), as well as the materials included in the components, are consistent with the above references. Figure 5 The components and materials described are essentially the same or similar. Therefore, for convenience, the focus will be on... Figures 9 to 11 The first semiconductor chips 100d, 100e and 100f and Figure 5 The embodiments are described using the differences between the first semiconductor chip 100b.

[0097] Reference Figure 9 The first passivation layer 130d may include an insulating layer 131 and an oxide layer 133d, with the oxide layer 133d disposed on the insulating layer 131. The surface area of ​​the upper surface of the oxide layer 133d may be smaller than the surface area of ​​the upper surface of the insulating layer 131. A portion of the upper surface of the insulating layer 131 may not be covered by the oxide layer 133d and may be exposed to the outside.

[0098] The oxide layer 133d may include a planar region 133d_C and a peripheral region 133d_P. The peripheral region 133d_P of the oxide layer 133d may surround the planar region 133d_C of the oxide layer 133d. The planar region 133d_C of the oxide layer 133d may include the center of the upper surface of the oxide layer 133d. For example, in a plan view, the planar region 133d_C of the oxide layer 133d may occupy the center of the upper surface of the insulating layer 131. The peripheral region 133d_P of the oxide layer 133d may include a groove (opening) 133d_R recessed from the upper surface of the oxide layer 133d toward the lower surface of the oxide layer 133d.

[0099] For example, the portion of the oxide layer 133d located in the planar region 133d_C of the oxide layer 133d may be referred to as the plane 1331, and the portion of the oxide layer 133d located in the peripheral region 133d_P of the oxide layer 133d may be referred to as a plurality of protrusions 1332d. For example, the side surfaces of the plurality of protrusions 1332d may define the side surfaces of the groove 133d_R.

[0100] Multiple protrusions 1332d may be connected to the plane 1331. For example, the multiple protrusions 1332d may be integrated with the plane 1331. For example, the multiple protrusions 1332d and the plane 1331 may be a single body or a single pattern with no boundary interface between them. Each of the multiple protrusions 1332d may extend from a side surface of the plane 1331 toward a side surface of the insulating layer 131. In some embodiments, in a plan view, the multiple protrusions 1332d may extend from the edge of the planar region 133d_C (or the first region) in a direction toward the side surface of the insulating layer 131 (or the insulating pattern). For example, when a first protrusion, as one of the multiple protrusions 1332d, contacts a first side surface of the plane 1331, the first protrusion may extend in a direction perpendicular to the first side surface of the plane 1331.

[0101] However, the inventive concept is not limited thereto, and the first protrusion may extend in a direction inclined relative to the first side surface of the plane 1331 and toward the side surface of the insulating layer 131. Each of the plurality of protrusions 1332d may extend in a horizontal direction obtained by combining (and thus creating) a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0102] In some embodiments, the side surface of each of the plurality of protrusions 1332d that contacts the plane 1331 may overlap with the upper surface of the insulating layer 131 in the vertical direction (Z direction). For example, in a plan view, the side surface of the plane 1331 and the plurality of protrusions 1332d may be arranged within the insulating pattern (or insulating layer 131) of the first passivation layer 130d. Among the side surfaces of the plurality of protrusions 1332d, the side surface adjacent to the side surface that contacts the plane 1331 (e.g., one side surface of each protrusion 1332d in the Z direction) may define the side surface of the groove 133d_R. For example, in a plan view, the side surface of the plane 1331 between adjacent protrusions 1332d and the mutually facing side surfaces of the adjacent protrusions 1332d among the plurality of protrusions 1332d may define the side surface of the groove 133d_R.

[0103] Reference Figure 10 The first passivation layer 130e may include an insulating layer 131 and an oxide layer 133e, with the oxide layer 133e disposed on the insulating layer 131. In a plan view, the oxide layer 133e may have a smaller surface area than the insulating layer 131. The side surfaces of the oxide layer 133e may overlap with the upper surface of the insulating layer 131 in the vertical direction (Z direction). For example, a portion of the upper surface of the insulating layer 131 may not be covered by the oxide layer 133e.

[0104] The oxide layer 133e may include a planar region 133e_C and a peripheral region 133e_P. The peripheral region 133e_P of the oxide layer 133e may surround the planar region 133e_C of the oxide layer 133e. The planar region 133e_C of the oxide layer 133e may include the center of the upper surface of the oxide layer 133e. The peripheral region 133e_P of the oxide layer 133e may include a groove 133e_R recessed from the upper surface of the oxide layer 133e toward the lower surface of the oxide layer 133e.

[0105] For example, a portion of oxide layer 133e located in planar region 133e_C of oxide layer 133e may be referred to as a plane (first oxide pattern) 1331, and a portion of oxide layer 133e located in peripheral region 133e_P of oxide layer 133e may be referred to as a plurality of second oxide patterns 1332e. For example, the side surfaces of the plurality of second oxide patterns 1332e may define the side surfaces of groove 133e_R.

[0106] Multiple second oxide patterns 1332e may be arranged horizontally separate from plane 1331. For example, plane 1331 may have a rectangular column shape, and each of the multiple second oxide patterns 1332e may have a rectangular ring shape. The multiple second oxide patterns 1332e may surround plane 1331. For example, the multiple second oxide patterns 1332e may be arranged horizontally separate from each other. The multiple second oxide patterns 1332e may be rectangular rings with different side lengths but with the same center.

[0107] Reference Figure 11 The first passivation layer 130f may include an insulating layer 131 and an oxide layer 133f, with the oxide layer 133f disposed on the insulating layer 131. In a plan view, the oxide layer 133f may have a smaller surface area than the insulating layer 131. The side surfaces of the oxide layer 133f may overlap with the upper surface of the insulating layer 131 in the vertical direction (Z direction). For example, a portion of the upper surface of the insulating layer 131 may not be covered by the oxide layer 133f.

[0108] The oxide layer 133f may include a planar region 133f_C and a peripheral region 133f_P. The peripheral region 133f_P of the oxide layer 133f may surround the planar region 133f_C of the oxide layer 133f. The planar region 133f_C of the oxide layer 133f may include the center of the upper surface of the oxide layer 133f. The peripheral region 133f_P of the oxide layer 133f may include a groove 133f_R recessed from the upper surface of the oxide layer 133f toward the lower surface of the oxide layer 133f.

[0109] For example, the portion of oxide layer 133f located in the planar region 133f_C of oxide layer 133f may be referred to as plane 1331, and the portion of oxide layer 133f located in the peripheral region 133f_P of oxide layer 133f may be referred to as protrusion 1332f. For example, oxide layer 133f may be patterned to form an oxide pattern. The portion of oxide layer 133f located in the peripheral region 133f_P may be referred to as the peripheral portion 1332f of the oxide pattern. For example, the side surface of the peripheral portion 1332f of the oxide pattern may define the side surface of the groove 133f_R.

[0110] The outer portion 1332f of the oxide pattern can be connected to the plane 1331 to form a single body. For example, the single body may have a mesh shape in the planar view. Multiple grooves 133f_R may exist, and the multiple grooves 133f_R may be arranged apart from each other in the horizontal direction.

[0111] Figure 12 This is a schematic cross-sectional view of a semiconductor package 1000 according to an embodiment.

[0112] Reference Figure 12 The semiconductor package 1000 may include: a first semiconductor chip 100, a second semiconductor chip (a plurality of second semiconductor chips) 200, and a molding layer ML.

[0113] In some embodiments, the first semiconductor chip 100 may include a serial-to-parallel conversion circuit and may be a semiconductor chip for controlling the second semiconductor chip 200, and the second semiconductor chip 200 may be a memory chip including memory cells.

[0114] In some embodiments, the semiconductor package 1000 may be a high-bandwidth memory (HBM), the first semiconductor chip 100 may be referred to as an HBM controller die, and the second semiconductor chip 200 may be referred to as a DRAM die.

[0115] The first semiconductor chip 100 may include a first semiconductor substrate 110, a first wiring structure 120, a plurality of first through electrodes 140, a plurality of first chip pads 130_P, and a first passivation layer 130. The first semiconductor chip 100 may be associated with the aforementioned first semiconductor chip (…). Figure 2 100 and Figure 4 It is basically the same as 100a).

[0116] The first semiconductor substrate 110 may include an active surface 110_A and an active surface 110_UA opposite to the active surface 110_A, with multiple individual devices arranged on the active surface 110_A. For example, the active surface 110_A of the first semiconductor substrate 110 may be referred to as the front surface, and the active surface 110_UA of the first semiconductor substrate 110 may be referred to as the rear surface.

[0117] The first wiring structure 120 may be disposed on the active surface 110_A of the first semiconductor substrate 110. The first wiring structure 120 may be electrically connected to a plurality of individual devices on the active surface 110_A of the first semiconductor substrate 110.

[0118] The first wiring structure 120 may include a first wiring pattern 121 and a first wiring insulation layer 122, the first wiring insulation layer 122 surrounding the first wiring pattern 121. The first wiring pattern 121 may include a first wiring line 121_L and a first wiring via 121_V, the first wiring line 121_L extending in a horizontal direction, and the first wiring via 121_V extending from the first wiring line 121_L in a vertical direction (Z direction). The portion of the first wiring line 121_L arranged at the bottom and exposed to the outside may be referred to as a first front pad. An external connection terminal CT may be attached to the first front pad.

[0119] For example, semiconductor package 1000 may be part of a package-in-package or a system-in-package (sub-package). For example, semiconductor package 1000 may be part of a 2.5D semiconductor package. A 2.5D semiconductor package may include an intermediate, on which semiconductor package 1000, as a sub-package, may be disposed. 2.5D packaging can refer to a technique of horizontally placing a semiconductor chip (or sub-package) on a silicon intermediate. For example, the external connection terminal CT of semiconductor package 1000, as a sub-package, may be configured to contact the silicon intermediate.

[0120] Multiple first through electrodes 140 may extend from the active surface 110_A of the first semiconductor substrate 110 to the non-active surface 110_UA of the first semiconductor substrate 110. For example, the multiple first through electrodes 140 may be connected to multiple individual devices of the first wiring structure 120 and the first semiconductor substrate 110.

[0121] Multiple first chip pads 130_P may be disposed on the upper surface of multiple first through electrodes 140. In some embodiments, the width of the multiple first chip pads 130_P may be greater than the width of the multiple first through electrodes 140 in the horizontal direction (e.g., the X direction). The multiple first chip pads 130_P may be disposed on the non-active surface 110_UA of the first semiconductor substrate 110, and the multiple first chip pads 130_P may be referred to as multiple first back pads.

[0122] The first passivation layer 130 may be disposed on the non-active surface 110_UA of the first semiconductor substrate 110. The first passivation layer 130 may be disposed separately from the first wiring structure 120 in the vertical direction (Z direction). For example, the first passivation layer 130 may be disposed separately from the first wiring structure 120, with the first semiconductor substrate 110 located between the first passivation layer 130 and the first wiring structure 120.

[0123] For example, the first passivation layer 130 may contact the side surfaces of a plurality of first chip pads 130_P. The first passivation layer 130 may externally protect the plurality of first chip pads 130_P. For example, the first passivation layer 130 may be referred to as a post-passivation layer.

[0124] The first passivation layer 130 may include an insulating layer 131 and an oxide layer 132, with the oxide layer 132 disposed on the insulating layer 131. The hardness of the insulating layer 131 may be greater than the hardness of the oxide layer 132. For example, the insulating layer 131 may include silicon nitride, and the oxide layer 132 may include silicon oxide.

[0125] In the horizontal direction (in a plan view), the width of the insulating layer 131 may be the same as the width of the first semiconductor substrate 110, and in the horizontal direction, the width of the oxide layer 132 may be smaller than the width of the insulating layer 131. The side surfaces of the oxide layer 132 may overlap the upper surface of the insulating layer 131 in the vertical direction (Z direction). The side surfaces of the oxide layer 132 may be arranged separately from the side surfaces of the insulating layer 131. In some embodiments, the center of the upper surface of the oxide layer 132 and the center of the upper surface of the insulating layer 131 may be aligned in the vertical direction (Z direction). For example, in a plan view, the center of the upper surface of the oxide layer 132 may be located at the same position as the center of the upper surface of the insulating layer 131.

[0126] The insulating layer 131 may have a first region 131_A1 and a second region 131_A2, the second region 131_A2 surrounding the first region 131_A1. The second region 131_A2 of the insulating layer 131 may include a side portion of the upper surface of the insulating layer 131, and the first region 131_A1 of the insulating layer 131 may include (contain) the center of the insulating layer 131. For example, in a plan view, the second region 131_A2 of the insulating layer 131 may include a peripheral region of the upper surface of the insulating layer 131. The upper surface of the first region 131_A1 of the insulating layer 131 may contact the oxide layer 132, and the upper surface of the second region 131_A2 of the insulating layer 131 may contact the molding layer ML. For example, the central region of the insulating layer 131 may contact the oxide layer 132, and the edge region of the insulating layer 131 may contact the molding layer ML. The portion of the upper surface of the insulating layer 131 located at the edge of the oxide layer 132 may contact the molding layer ML.

[0127] Multiple first through electrodes 140 and multiple first chip pads 130_P may be stacked in the vertical direction (Z direction) with the first region 131_A1 of the first passivation layer 130 of the first semiconductor chip 100. The multiple first through electrodes 140 and multiple first chip pads 130_P may be arranged in the lower part of the region in which the oxide layer 132 of the first passivation layer 130 is disposed.

[0128] For example, the side surface of the oxide layer 132 of the first passivation layer 130 of the first semiconductor chip 100 can be completely covered by the molding layer ML. The oxide layer 132 may not be exposed to the outside of the semiconductor package 1000. The insulating layer 131 may have better water resistance than the oxide layer 132. Since the oxide layer 132 is not exposed to the outside of the semiconductor package 1000, water can be prevented from penetrating into the semiconductor package 1000 through the oxide layer 132. Therefore, delamination between the first semiconductor chip 100 and the molding layer ML caused by water can be suppressed.

[0129] The second semiconductor chip 200 can be stacked on the first semiconductor chip 100. For simplicity, the case where the semiconductor package 1000 includes four second semiconductor chips 200 is described. Although Figure 2 The diagram shows four second semiconductor chips 200 stacked on top of a first semiconductor chip 100 in a semiconductor package 1000, but the number of second semiconductor chips 200 is not limited to this.

[0130] The width of the second semiconductor chip 200 in the horizontal direction may be smaller than the width of the first semiconductor chip 100. For example, the second semiconductor chip 200 may be stacked on the first passivation layer 130 of the first semiconductor chip 100. The second semiconductor chip 200 may be stacked with the first region 131_A1 of the insulating layer 131 of the first passivation layer 130 of the first semiconductor chip 100 in the vertical direction (Z direction). In some embodiments, in the horizontal direction, the width of the first region 131_A1 of the insulating layer 131 of the first passivation layer 130 may be the same as the width of the oxide layer 132, and the width of the oxide layer 132 may be the same as the width of the second semiconductor chip 200.

[0131] The second semiconductor chip 200 may not be stacked with the second region 131_A2 of the insulating layer 131 of the first passivation layer 130 of the first semiconductor chip 100 in the vertical direction (Z direction). The second semiconductor chip 200 may be arranged separately from the insulating layer 131 of the first passivation layer 130 of the first semiconductor chip 100.

[0132] For convenience, the following description refers to a semiconductor package 1000 comprising four second semiconductor chips 200. In some embodiments, the second semiconductor chip 200 located at the highest height among the four second semiconductor chips 200 may be referred to as the uppermost second semiconductor chip 200H. The second semiconductor chip 200 located at the lowest height among the four second semiconductor chips 200 may be referred to as the lowermost second semiconductor chip 200L.

[0133] Each of the second semiconductor chips 200 may include a second semiconductor substrate 210 and a second wiring structure 220. The thickness of the second semiconductor chip 200 (i.e., its length in the vertical direction (Z direction)) may be approximately 20 mm. Up to approximately 80 For example, the thickness of the uppermost second semiconductor chip 200H can be greater than the thickness of the other second semiconductor chips 200.

[0134] The second semiconductor substrate 210 may include an active surface and an active surface opposite to the active surface. For example, the second semiconductor substrate 210 may include semiconductor materials such as silicon (Si) or germanium (Ge). The second semiconductor substrate 210 may include compound semiconductor materials such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP).

[0135] An integrated circuit comprising multiple individual devices (components) of various types can be formed on the active surface of the second semiconductor substrate 210. The multiple individual devices formed on the second semiconductor substrate 210 may include microelectronic devices (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs) or complementary metal-oxide-semiconductor (CMOS) transistors). For example, the integrated circuit may include large-scale integration (LSI), image sensors (e.g., CMOS imaging sensors (CIS)), microelectromechanical systems (MEMS), active devices, and / or passive devices. A second wiring structure 220 may be disposed on the active surface of the second semiconductor substrate 210. The second wiring structure 220 may be electrically connected to the multiple individual devices of the second semiconductor substrate 210.

[0136] The second wiring structure 220 may include a second wiring pattern 221 and a second wiring insulation layer 222, the second wiring insulation layer 222 surrounding the second wiring pattern 221. The second wiring pattern 221 may include a second wiring line 221_L and a second wiring via 221_V. The second wiring pattern 221 may include a second wiring line 221_L extending in a horizontal direction and a second wiring via 221_V extending from the second wiring line 221_L in a vertical direction (Z direction). The portion of the second wiring line 221_L located at the lowest point of the second wiring insulation layer 222 and exposed to the outside of the second wiring insulation layer 222 may be referred to as a second front pad. For example, the second front pad may be formed in a recess formed in the surface of the second wiring insulation layer 222.

[0137] The second semiconductor chip 200 may further include a plurality of second through electrodes 210_V, which extend from the non-active surface of the second semiconductor substrate 210 toward the active surface. The plurality of second through electrodes 210_V of the second semiconductor chip 200 may be electrically connected to the second wiring structure 220 of the second semiconductor chip 200.

[0138] The second semiconductor chip 200 may further include a plurality of second back pads 230_P disposed on the non-active surface of the second semiconductor substrate 210. The plurality of second back pads 230_P may be disposed on a plurality of second through electrodes 210_V.

[0139] The second semiconductor chip 200 may include a back oxide layer 230 disposed on the non-active surface of the second semiconductor substrate 210. The back oxide layer 230 may surround the side surfaces of a plurality of second back pads 230_P. The uppermost second semiconductor chip 200H may not include a plurality of second through electrodes 210_V, a plurality of second back pads 230_P, and the back oxide layer 230.

[0140] In some embodiments, the second semiconductor chip 200 may be arranged such that the active surface of the second semiconductor substrate 210 points toward the first semiconductor chip 100. For example, the second wiring structure 220 of the second semiconductor chip 200 may point downward in the vertical direction (Z direction), and the back oxide layer 230 of the second semiconductor chip 200 may point upward in the vertical direction.

[0141] In some embodiments, the lowermost second semiconductor chip 200L may be in contact with the oxide layer 132 of the first semiconductor chip 100. For example, in the horizontal direction, the width of the second semiconductor chip 200 may be the same as the width of the oxide layer 132 of the first passivation layer 130 of the first semiconductor chip 100. For example, the side surface of the second semiconductor chip 200 may be stacked with the upper surface of the insulating layer 131 of the first passivation layer 130 of the first semiconductor chip 100 in the vertical direction (Z direction).

[0142] The adhesion between the molding layer ML and the insulating layer 131 of the first passivation layer 130 can be stronger than the adhesion between the molding layer ML and the oxide layer 132 of the first passivation layer 130. For example, the oxide layer 132 of the first passivation layer 130 of the first semiconductor chip 100 may only exist in the portion where the second semiconductor chip 200 will be mounted, and may not exist in other portions. Therefore, by distributing the oxide layer 132 of the first passivation layer 130 only on the portion where the second semiconductor chip 200 will be mounted, the first semiconductor chip 100 and the second semiconductor chip 200 can be hybrid-bonded to each other, and by removing the oxide layer 132 in other areas, the adhesion between the molding layer ML and the first semiconductor chip 100 can be improved.

[0143] A plurality of first chip pads 130_P of the first semiconductor chip 100 and a plurality of second front pads of the second wiring structure 220 of the lowest second semiconductor chip 200L can be thermally diffused together and integrated. For example, each of the plurality of first chip pads 130_P of the first semiconductor chip 100 can be integrally bonded to a corresponding one of the plurality of second front pads of the second wiring structure 220 of the lowest second semiconductor chip 200L without any boundary interface between them. During the thermal diffusion bonding of the plurality of first chip pads 130_P and the plurality of second front pads, the oxide layer 132 of the first passivation layer 130 of the first semiconductor chip 100 and the second wiring insulating layer 222 of the second wiring structure 220 of the lowest second semiconductor chip 200L can be thermally covalently bonded and integrated. In some embodiments, the first semiconductor chip 100 and the second semiconductor chip 200 can be combined with each other by hybrid bonding.

[0144] In some embodiments, the method of combining (bonding) the second semiconductor chip 200 may be substantially the same as the method of combining the first semiconductor chip 100 and the lowermost second semiconductor chip 200L. For example, the bonding between a pair of second semiconductor chips 200H, 200M2, 200M1 and 200L may be performed using the same method as the bonding between the second semiconductor chip 200L and the first semiconductor chip 100. Hereinafter, the bonding of the lower second semiconductor chips 200M1 and 200L will be described as an example.

[0145] A plurality of second back pads 230_P located on the upper surface of the second semiconductor chip 200L and a plurality of second front pads located on the lower surface of the second semiconductor chip 200L can be diffusely bonded to each other and can be integrated. During the diffusion bonding of the plurality of second back pads 230_P and the plurality of second front pads, the back oxide layer 230 of the second semiconductor chip 200L and the second wiring insulating layer 222 of the second wiring structure 220 of the second semiconductor chip 200M1 can be covalently bonded to each other and can be integrated.

[0146] A molding layer ML may be disposed on the first semiconductor chip 100 and may contact at least a portion of the side surface of the second semiconductor chip 200. For example, the molding layer ML may completely surround the side surface of the second semiconductor chip 200. The upper surface of the molding layer ML may be coplanar with the upper surface of the uppermost second semiconductor chip 200H.

[0147] The molding layer ML may contact the side surface of the oxide layer 132 and the upper surface of the second region 131_A2 of the insulating layer 131 of the first passivation layer 130 of the first semiconductor chip 100. In some embodiments, the molding layer ML may include epoxy resin, polyimide resin, etc. The molding layer ML may include, for example, an epoxy molding compound (EMC).

[0148] Figure 13 This is a schematic cross-sectional view of a semiconductor package 1000a according to an embodiment.

[0149] The components constituting the semiconductor package 1000a described below, and the materials included in the components, are consistent with the above references. Figure 12 The components and materials described are essentially the same or similar. Therefore, for simplicity, the focus will be on... Figure 13 Semiconductor package 1000a and Figure 12 The embodiments are described using the differences between the semiconductor packages 1000.

[0150] Reference Figure 13The semiconductor package 1000a may include a first semiconductor chip 100L, a second semiconductor chip 200, and a molding layer ML. The second semiconductor chip 200 may be stacked on the first semiconductor chip 100L. The molding layer ML may be disposed on the first semiconductor chip 100L and may contact the side surface of the second semiconductor chip 200.

[0151] In some embodiments, in a plan view, the surface area of ​​the lower surface of the second semiconductor chip 200 may be smaller than the surface area of ​​the lower surface of the first semiconductor chip 100L. In some embodiments, the side surface of the second semiconductor chip 200 may be superimposed on the upper surface of the first semiconductor chip 100L in the vertical direction (Z direction).

[0152] The first passivation layer 130L may include an insulating layer 131 and an oxide layer 132L. In the horizontal direction, the width of the oxide layer 132L may be smaller than the width of the insulating layer 131. The side surface of the oxide layer 132L may overlap with the upper surface of the insulating layer 131 in the vertical direction (Z direction). For example, in a plan view, the side surface of the first oxide pattern of the oxide layer 132L may be arranged within the insulating pattern of the insulating layer 131. For example, in a plan view, the side surface of the first oxide pattern of the oxide layer 132L may protrude horizontally beyond the side surface of the second semiconductor chip 200.

[0153] The second semiconductor chip 200 may be disposed on the first passivation layer 130L of the first semiconductor chip 100L. The second semiconductor chip 200 may be disposed on the oxide layer 132L of the first passivation layer 130L of the first semiconductor chip 100L, and may be in contact with the oxide layer 132L. The second semiconductor chip 200 may be arranged to be separated from the insulating layer 131 of the first passivation layer 130L of the first semiconductor chip 100L in the vertical direction (Z direction).

[0154] In a plan view (horizontally), the width of the oxide layer 132L of the first passivation layer 130L may be greater than the width of the second semiconductor chip 200. For example, the surface area of ​​the upper surface of the oxide layer 132L of the first passivation layer 130L may be greater than the surface area of ​​the lower surface of the second semiconductor chip 200. The width of the insulating layer 131 of the first passivation layer 130L may be greater than the width of the oxide layer 132L and the width of the second semiconductor chip 200.

[0155] The side surface of the oxide layer 132L of the first passivation layer 130L may be disposed on the upper surface of the insulating layer 131 of the first passivation layer 130L, and the side surface of the second semiconductor chip 200 may be disposed on the upper surface of the oxide layer 132L of the first passivation layer 130L. For example, a portion of the upper surface of the insulating layer 131 of the first passivation layer 130L may be in contact with the molding layer ML, and a portion of the upper surface of the oxide layer 132L of the first passivation layer 130L may be in contact with the molding layer ML.

[0156] Since the surface area of ​​the oxide layer 132L of the first passivation layer 130L is larger than the surface area of ​​the second semiconductor chip 200, the difficulty of the assembly process can be reduced in the process of combining (bonding) the second semiconductor chip 200 onto the oxide layer 132L of the first passivation layer 130L of the first semiconductor chip 100L, thereby increasing the alignment tolerance.

[0157] Figure 14 This is a schematic cross-sectional view of a semiconductor package 1000b according to an embodiment.

[0158] Most of the components constituting the semiconductor package 1000b and the materials included in the components described below are consistent with the above reference. Figure 12 The components and materials described are essentially the same or similar. Therefore, for simplicity, the focus will be on... Figure 14 Semiconductor package 1000b and Figure 12 The embodiments are described using the differences between the semiconductor packages 1000.

[0159] Reference Figure 14 The semiconductor package 1000b may include a first semiconductor chip 100b, a second semiconductor chip 200, and a molding layer ML. The second semiconductor chip 200 may be stacked on the first semiconductor chip 100b. The molding layer ML may be disposed on the first semiconductor chip 100b and may contact the side surface of the second semiconductor chip 200. The first semiconductor chip 100b may be the first semiconductor chip described above (…). Figure 6 100b Figure 8 100c Figure 9 100d, Figure 10 100e or Figure 11 (of 100f).

[0160] The second semiconductor chip 200 may be disposed on the first passivation layer 130b of the first semiconductor chip 100b. The first passivation layer 130b may include an insulating layer 131 and an oxide layer 133, with the oxide layer 133 disposed on the insulating layer 131. The width of the oxide layer 133 may be smaller than the width of the insulating layer 131. The side surface of the oxide layer 133 may be superimposed on the upper surface of the insulating layer 131 in the vertical direction (Z direction).

[0161] In some embodiments, a portion of the insulating layer 131 not covered by the second semiconductor chip 200 may contact the molding layer ML. For example, a portion of the insulating layer 131 of the first passivation layer 130b not covered by the oxide layer 133 may contact the molding layer ML. The central region of the insulating layer 131 may contact the oxide layer 133, and a portion of the edge region of the insulating layer 131 may contact the molding layer ML.

[0162] In the plan view, the central region of the insulating layer 131 may include the center of the upper surface of the insulating layer 131, and the edge region of the insulating layer 131 may include the side portion of the upper surface of the insulating layer 131. The second semiconductor chip 200 may be located on the central region of the insulating layer 131.

[0163] The oxide layer 133 may include a planar region 133_C and a peripheral region 133_P, with the peripheral region 133_P surrounding the planar region 133_C. The planar region 133_C may be disposed on the central region of the insulating layer 131. In a plan view, a plurality of first chip pads 130_P are disposed within the portion of the oxide layer 133 located in the planar region 133_C. In the planar region 133_C, the portion of the oxide layer 133 together with the plurality of first chip pads 130_P may have a flat, non-recessed surface. In the peripheral region 133_P of the oxide layer 133, a groove (opening) 133_R may be disposed recessed from the upper surface of the oxide layer 133 toward the lower surface of the oxide layer 133. For example, in the peripheral region 133_P of the oxide layer 133, the upper surface of the insulating layer 131 located below the groove 133_R may face the molding layer ML (contact with the molding layer ML).

[0164] The portion of oxide layer 133 located in the planar region 133_C of oxide layer 133 may be referred to as a planar region (or first oxide pattern) 1331, and the portion of oxide layer 133 located in the peripheral region 133_P of oxide layer 133 may be referred to as a plurality of protrusions (or second oxide pattern) 1332.

[0165] The upper surface of the insulating layer 131 may contact at least one of the plane 1331 of the oxide layer 133, the plurality of protrusions 1332, and the molding layer ML. For example, the portion of the upper surface of the insulating layer 131 located at the edge of the oxide layer 133 and the portion located at the lower part of the groove 133_R may contact the molding layer ML.

[0166] A portion of the molding layer ML may be located between a plurality of protrusions 1332 of the oxide layer 133 of the first passivation layer 130b of the first semiconductor chip 100b. For example, the molding layer ML may contact the side surfaces of the plurality of protrusions 1332. The side surfaces and the top surface of the plurality of protrusions 1332 may be surrounded by the molding layer ML. The portion of the molding layer ML located between the plurality of protrusions 1332 (i.e., the portion of the molding layer ML located in the groove 133_R) may contact the top surface of the insulating layer 131 of the first passivation layer 130b of the first semiconductor chip 100b. The second semiconductor chip 200 may be stacked vertically with the planar region 133_C of the oxide layer 133 of the first passivation layer 130b of the first semiconductor chip 100b. The second semiconductor chip 200 may be disposed within the planar region 133_C of the oxide layer 133 of the first passivation layer 130b of the first semiconductor chip 100b. For example, the second wiring insulating layer 222 of the second wiring structure 220 of the second semiconductor chip 200 and the planar region 1331 of the first passivation layer 130b of the first semiconductor chip 100b may be covalently bonded to each other.

[0167] Figures 15A to 15G Each is a diagram illustrating a method for manufacturing a semiconductor package 1000a according to an embodiment. Figures 15A to 15G Each shows the manufacturing process. Figure 12 Method for semiconductor package 1000a.

[0168] Reference Figures 15A to 15G A method of manufacturing a semiconductor package may include: mounting a first semiconductor substrate 110 on a carrier substrate CR; forming a first passivation layer 130 on a non-active surface 110_UA of the first semiconductor substrate 110; forming a plurality of first chip pads 130_P on the non-active surface 110_UA of the first semiconductor substrate 110; forming trenches 130L_T in the first passivation layer 130, the trenches 130L_T extending from the upper surface of the first passivation layer 130L to the interior of the first passivation layer 130L; mounting a second semiconductor chip 200 on the first semiconductor chip 100L; and forming a molding layer ML on the first semiconductor chip 100L to surround the side surface of the second semiconductor chip 200.

[0169] Reference Figure 15AA first semiconductor substrate 110 can be mounted on a carrier substrate CR. In some embodiments, the first semiconductor substrate 110 may be a wafer that has not been diced into multiple dies.

[0170] The first semiconductor substrate 110 may include an active surface 100_A and an active surface 110_UA opposite to the active surface 100_A. A first wiring structure 120 may be located on the active surface 100_A of the first semiconductor substrate 110. A plurality of first through electrodes 140 may extend from the active surface 100_A of the first semiconductor substrate 110 to the active surface 110_UA of the first semiconductor substrate 110.

[0171] Before mounting the first semiconductor substrate 110 onto the carrier substrate CR, a first wiring structure 120 and a plurality of first through electrodes 140 may be formed on the first semiconductor substrate 110. After forming the first wiring structure 120 and the plurality of first through electrodes 140 on the first semiconductor substrate 110, the first semiconductor substrate 110 is attached to the carrier substrate CR. In some embodiments, the first semiconductor substrate 110 may be attached to the carrier substrate CR by means of an adhesive film RL.

[0172] For example, the first semiconductor substrate 110 can be attached to the carrier substrate CR such that the active surface 100_A of the first semiconductor substrate 110 points towards the carrier substrate CR. In some embodiments, the first semiconductor substrate 110 can be attached to the carrier substrate CR after the external connection terminal CT is attached to the first wiring structure 120. However, the inventive concept is not limited thereto, and the external connection terminal CT can be attached in a subsequent process.

[0173] In some embodiments, a plurality of first through electrodes 140 may extend through the first semiconductor substrate 110. For example, a portion of each of the plurality of first through electrodes 140 may protrude over the non-active surface 110_UA of the first semiconductor substrate 110.

[0174] Reference Figure 15B A first passivation layer 130L can be formed on the non-active surface 110_UA of the first semiconductor substrate 110. For example, the first passivation layer 130L can be referred to as a first post-passivation layer.

[0175] Forming the first passivation layer 130L may include forming an insulating layer 131 on the non-active surface 110_UA of the first semiconductor substrate 110, and forming an oxide layer 132L on the insulating layer 131. For example, the insulating layer 131 may be conformally formed on the non-active surface 110_UA to cover the non-active surface 110_UA of the first semiconductor substrate 110, and the oxide layer 132L may be conformally formed on the upper surface of the insulating layer 131 to cover the insulating layer 131 of the first passivation layer 130L. The upper surface of the insulating layer 131 may be in contact with the oxide layer 132L, and the lower surface of the insulating layer 131 may be in contact with the first semiconductor substrate 110.

[0176] In some embodiments, the first passivation layer 130L may surround a portion of the plurality of first through electrodes 140 that protrudes toward the non-active surface 110_UA of the first semiconductor substrate 110.

[0177] Reference Figure 15C Multiple first chip pads 130_P can be formed on the first passivation layer 130L. The multiple first chip pads 130_P can be disposed on the non-active surface 110_UA of the first semiconductor substrate 110. The multiple first chip pads 130_P can be referred to as multiple first back pads.

[0178] Multiple first chip pads 130_P can be electrically connected to multiple first through electrodes 140. In some embodiments, the multiple first chip pads 130_P can be physically contacted with the multiple first through electrodes 140 respectively. For example, the multiple first chip pads 130_P can be integrated with the multiple first through electrodes 140 respectively.

[0179] Reference Figure 15D A trench 130L_T may be formed in the first passivation layer 130L. The trench 130L_T may extend from the upper surface of the first passivation layer 130L to the interior of the first passivation layer 130L. For example, the trench 130L_T may not completely penetrate the first passivation layer 130L, and may partially penetrate the first passivation layer 130L.

[0180] The trench 130L_T can extend from the upper surface of the oxide layer 132L of the first passivation layer 130L to the lower surface of the oxide layer 132L, such that the upper surface of the insulating layer 131 of the first passivation layer 130L can be partially exposed. For example, the insulating layer 131 can be exposed to the outside through the trench 130L_T.

[0181] The trench 130L_T can be arranged separately from the plurality of first chip pads 130_P. For example, the trench 130L_T can be not stacked with the plurality of first chip pads 130_P and the plurality of first through electrodes 140 in the vertical direction (Z direction). The side surfaces of the plurality of first chip pads 130_P can contact the oxide layer 132L of the first passivation layer 130L.

[0182] In some embodiments, the trench 130L_T can be formed by partially removing the oxide layer 132L via a photolithography and patterning process. Therefore, the horizontal width of the remaining oxide layer 132L can increase towards the insulating layer 131. Furthermore, since the insulating layer 131 is partially removed along with the oxide layer 132L, the upper surface of the insulating layer 131 exposed to the outside through the trench 130L_T can have a concave shape.

[0183] In some embodiments, the region of the insulating layer 131 of the first passivation layer 130L in which the oxide layer 132L is present may be referred to as the first region 132L_A1 of the insulating layer 131, and the region of the insulating layer 131 exposed through the trench 130L_T may be referred to as the second region 132L_A2. In some embodiments, the second region 132L_A2 of the insulating layer 131 may be the edge region of the insulating layer 131 of the first passivation layer 130L of a first semiconductor chip 100L after the first semiconductor substrate 110 has been diced. For example, in the process of forming the trench 130L_T, the oxide layer 132L located at the edge region of the insulating layer 131 of the first passivation layer 130L of the first semiconductor chip 100L may be removed.

[0184] The first wiring structure 120, the first semiconductor substrate 110, the plurality of first through electrodes 140, the plurality of first chip pads 130_P and the first passivation layer 130L can be collectively referred to as the first semiconductor chip 100L.

[0185] Reference Figure 15E The second semiconductor chip 200 can be stacked on the first semiconductor chip 100L. The second semiconductor chip 200 can be disposed on the oxide layer 132L of the first passivation layer 130L of the first semiconductor chip 100L.

[0186] Multiple second semiconductor chips 200 can be sequentially stacked and mounted on a first semiconductor chip 100L. The second semiconductor chips 200 can be mounted on the upper portion of the first region 132L_A1 of the insulating layer 131 of the first passivation layer 130L of the first semiconductor chip 100L. The width of the second semiconductor chip 200 can be smaller than the width of the oxide layer 132L of the first passivation layer 130L of the first semiconductor chip 100L. The second semiconductor chips 200 can be arranged to be separated from the insulating layer 131 of the first passivation layer 130L of the first semiconductor chip 100L in the vertical direction (Z direction).

[0187] In some embodiments, the second wiring insulating layer 222 of the second wiring structure 220 of the second semiconductor chip 200 can be covalently bonded to the oxide layer 132L of the first passivation layer 130L of the first semiconductor chip 100L. A plurality of second front pads of the second semiconductor chip 200 can be integrated with a plurality of first chip pads 130_P of the first semiconductor chip 100L via diffusion bonding. For example, the second semiconductor chip 200 can be combined with the first semiconductor chip 100L (e.g., bonded to the first semiconductor chip 100L) via hybrid bonding.

[0188] Reference Figure 15F A molding layer ML can be formed on the first semiconductor chip 100L to contact the side surface of the second semiconductor chip 200. For example, after the molding layer ML is formed on the first passivation layer 130L of the first semiconductor chip 100L to cover the second semiconductor chip 200, the molding layer ML can be partially removed until the uppermost surface of the second semiconductor chip 200 is exposed.

[0189] The molding layer ML can fill the trench 130L_T of the first passivation layer 130L of the first semiconductor chip 100L. For example, the molding layer ML can contact the upper surface of the second region 132L_A2 of the insulating layer 131 of the first passivation layer 130L of the first semiconductor chip 100L. In addition, the molding layer ML can contact the upper surface of the oxide layer 132L of the first passivation layer 130L of the first semiconductor chip 100L that is not covered by the second semiconductor chip 200.

[0190] Reference Figure 15G It can perform SL cutting along the saw line. Figure 15F The resulting steps can remove the adhesive film RL and the carrier substrate CR, thereby manufacturing multiple semiconductor packages 1000a.

[0191] For example, the molding layer ML, the insulating layer 131 of the first passivation layer 130L, the first semiconductor substrate 110, and the first wiring structure 120 can be cut along the saw line SL to manufacture a plurality of semiconductor packages 1000a. The side surfaces of the semiconductor packages 1000a can be defined along the saw line SL. As a result of the cutting, the side surfaces of the semiconductor substrate can be aligned vertically with the side surfaces of the insulating pattern of the passivation layer.

[0192] The sawing line SL can be arranged horizontally to be separated from the oxide layer 132L of the first passivation layer 130L. For example, the oxide layer 132L may not be exposed to the outside of the semiconductor package 1000a. The side surface of the semiconductor package 1000a may not include the side surface of the oxide layer 132L. The side surface of the oxide layer 132L may be located inside the semiconductor package 1000a.

[0193] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor chip comprising: a semiconductor base including a first surface and a second surface opposite to the first surface; a wiring layer disposed on the first surface of the semiconductor base; a plurality of through electrodes extending from the first surface of the semiconductor base to the second surface of the semiconductor base; a plurality of chip pads disposed on the second surface of the semiconductor base and electrically connected with the plurality of through electrodes; and a passivation layer disposed on the second surface of the semiconductor base and in contact with side surfaces of the plurality of chip pads, wherein the passivation layer includes an insulating layer and an oxide layer disposed on the insulating layer, the insulating layer includes an insulating pattern having a first width along a horizontal direction, the oxide layer includes a first oxide pattern having a second width along the horizontal direction, and the first width is greater than the second width. 2.The semiconductor chip of claim 1, wherein in a plan view, the insulating layer of the passivation layer has a first region and a second region, in the first region of the insulating layer, an upper surface of the insulating layer is covered with the oxide layer, and in the second region of the insulating layer, the upper surface of the insulating layer is exposed with respect to the oxide layer. 3.The semiconductor chip of claim 2, wherein in the first region of the insulating layer of the passivation layer, the upper surface of the insulating layer is flat, and in the second region of the insulating layer of the passivation layer, the upper surface of the insulating layer is concave downward. the plurality of through electrodes and the plurality of chip pads are superposed on the first region of the insulating layer of the passivation layer in a vertical direction, and are disposed separately from the second region of the insulating layer of the passivation layer in a horizontal direction.

4. The semiconductor chip of claim 2, wherein, an upper surface of each of the plurality of chip pads is coplanar with an upper surface of the oxide layer of the passivation layer.

5. The semiconductor chip of claim 4, wherein, 6.The semiconductor chip of claim 1, wherein a side surface of the semiconductor base is aligned with a side surface of the insulating pattern of the passivation layer in a vertical direction, and in a plan view, a side surface of the first oxide pattern of the passivation layer is disposed within the insulating pattern of the passivation layer. a width of the first oxide pattern of the passivation layer increases toward the insulating layer.

7. The semiconductor chip of claim 6, wherein, a hardness of the insulating layer of the passivation layer is greater than a hardness of the oxide layer.

8. The semiconductor chip of claim 1, wherein, 9.The semiconductor chip of claim 1, wherein the passivation layer further includes an intermediate oxide layer, and the intermediate oxide layer is disposed between the insulating layer of the passivation layer and the second surface of the semiconductor base. 10.The semiconductor chip of claim 9, wherein the intermediate oxide layer includes an intermediate oxide pattern, and a width of the intermediate oxide pattern of the passivation layer is the same as a width of the insulating pattern of the passivation layer. 11.A semiconductor chip comprising: a semiconductor base including a first surface and a second surface opposite to the first surface; a wiring layer disposed on the first surface of the semiconductor base; a plurality of through electrodes extending from the first surface of the semiconductor base to the second surface of the semiconductor base; a plurality of chip pads disposed on the second surface of the semiconductor base and electrically connected with the plurality of through electrodes; and a passivation layer disposed on the second surface of the semiconductor base and in contact with side surfaces of the plurality of chip pads, the passivation layer including an insulating layer and an oxide layer disposed on the insulating layer, ​ ​ wherein a surface area of the upper surface of the oxide layer is smaller than a surface area of the upper surface of the insulating layer, in a plan view, the semiconductor base has a first region and a second region, the second region surrounding the first region, in a plan view, the first region has a rectangular shape, the oxide layer is disposed on the first region and the second region, the oxide layer includes an opening on the second region, the opening is recessed from an upper surface of the oxide layer to a lower surface of the oxide layer, the oxide layer includes a first oxide pattern, the insulating layer includes an insulating pattern, and in a plan view, side surfaces of the first oxide pattern are arranged within the insulating pattern and are arranged separately from side surfaces of the insulating pattern.

12. The semiconductor chip according to claim 11, wherein a portion of the upper surface of the insulating layer of the passivation layer, which is located at a lower portion of the opening, and a portion of the upper surface of the insulating layer of the passivation layer, which is located at an edge of the oxide layer, are exposed with respect to the oxide layer.

13. The semiconductor chip of claim 12, wherein, the exposed portion of the upper surface of the insulating layer of the passivation layer has a downwardly concave shape.

14. The semiconductor chip of claim 12, wherein, in the second region, a surface area of the upper surface of the oxide layer is smaller than a surface area of the exposed portion of the upper surface of the insulating layer of the passivation layer.

15. The semiconductor chip according to claim 11, wherein the oxide layer includes a plurality of second oxide patterns arranged separately from the first oxide pattern in a horizontal direction, the first oxide pattern is located on the first region, the plurality of second oxide patterns are located on the second region, and the plurality of second oxide patterns are separated from each other in the horizontal direction.

16. The semiconductor chip according to claim 11, wherein the oxide layer includes a plurality of protrusions extending from the first region in a plan view, in a plan view, the plurality of protrusions extend from an edge of the first region in a direction toward the side surfaces of the insulating pattern.

17. The semiconductor chip according to claim 11, wherein the oxide layer includes a second oxide pattern arranged separately from the first oxide pattern in a horizontal direction, the first oxide pattern is located on the first region, the second oxide pattern is located on the second region, and the second oxide pattern has a rectangular ring shape.

18. The semiconductor chip of claim 11, wherein, in a plan view, the plurality of chip pads are arranged separately from the second region.

19. The semiconductor chip according to claim 11, wherein in a plan view, the plurality of chip pads are arranged in the first region, and in a plan view, the plurality of through electrodes are superimposed on the first region.

20. A semiconductor package comprising: a first semiconductor chip including a first semiconductor base including a first surface and a second surface opposite to the first surface, a plurality of first through electrodes passing through the first semiconductor base, a passivation layer arranged on the second surface of the first semiconductor base, and a plurality of first chip pads in contact with the plurality of first through electrodes and surrounded by the passivation layer; a second semiconductor chip stacked on the first semiconductor chip and having a width smaller than a width of the first semiconductor chip; and a molding layer arranged on the passivation layer of the first semiconductor chip and in contact with at least a portion of side surfaces of the second semiconductor chip. The passivation layer of the first semiconductor chip includes an insulating layer and an oxide layer, the oxide layer is arranged on the insulating layer, The insulating layer includes an insulating pattern, the insulating pattern has a first width along a horizontal direction, The oxide layer includes a first oxide pattern, the first oxide pattern has a second width along the horizontal direction, The first width is greater than the second width, In a plan view, a side surface of the first oxide pattern of the passivation layer is arranged within the insulating pattern of the passivation layer, and The second semiconductor chip is in contact with the first oxide pattern of the passivation layer of the first semiconductor chip.

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