Lithium-based synaptic transistor device based on surface packaging technology and preparation method thereof
By introducing a surface encapsulation layer on the outer layer of the synaptic transistor to isolate oxygen and moisture and buffer mechanical stress, the problems of insufficient long-term stability and environmental adaptability of the synaptic transistor are solved, and excellent conductivity regulation characteristics and retention are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-07
- Publication Date
- 2026-03-17
AI Technical Summary
Existing synaptic transistors have shortcomings in long-term stability and environmental adaptability, especially in performance degradation under oxidation, hydrolysis and mechanical stress, which affects their conductivity regulation and retention.
A dense surface encapsulation layer is introduced on the outermost layer of the synaptic transistor. By depositing materials such as silicon oxide, aluminum oxide, silicon nitride, or magnesium fluoride, oxygen and moisture are isolated, mechanical stress is buffered, and the stability and long-term reliability of the device are improved.
This significantly improves the conductivity regulation characteristics and retention of synaptic transistors in complex environments, ensuring the consistency and reliability of the device during long-term cyclic operation.
Smart Images
Figure CN121693247A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of neuromorphic computing and electronic device fabrication technology, specifically to a lithium-based synaptic transistor device based on surface encapsulation technology and its fabrication method. Background Technology
[0002] With the rapid development of emerging fields such as artificial intelligence, the Internet of Things, and high-performance computing, neuromorphic computing, as a novel computing paradigm that simulates the neural network structure and information processing methods of the human brain, has attracted widespread attention. Compared with the traditional von Neumann computing architecture, neuromorphic computing emphasizes parallel processing and event-driven operation, which can significantly improve computing efficiency and reduce energy consumption. Against this backdrop, electronic devices used to simulate the plastic behavior of biological synapses have become a research hotspot. Among them, synaptic transistors, due to their continuously adjustable conductance states, low-power operation characteristics, and structural compatibility, are gradually becoming important candidate devices for the next generation of neuromorphic computing units.
[0003] However, despite the progress made by synaptic transistors in realizing biological learning functions such as pulse modulation, long-range enhancement (LTP), and long-range inhibition (LTD), they still have shortcomings in long-term stability and environmental adaptability. Specifically: First, the channel material is prone to oxidation or hydrolysis under the influence of external oxygen and water vapor, leading to degradation of the channel layer's electrical properties and a decrease in the device's conductivity control capability. Second, external mechanical stress can easily cause defect propagation or crack formation at the channel layer-electrode interface, thus affecting the stability of the ion migration channel. Third, the non-uniformity of ion migration and the accumulation of interface defects during repeated operation also lead to decreased retention and insufficient device durability. The combined effect of these factors makes it difficult for synaptic transistors to maintain stable and repeatable conductivity control characteristics under long-term operating conditions, limiting their application in complex environments.
[0004] To address these issues, researchers have proposed various improvement methods, including optimizing the channel layer material composition, introducing an interface modulation layer, and using novel gate dielectric materials. However, these methods often have limitations, such as complex material processing, poor compatibility with existing processes, or the inability to simultaneously ensure electrical performance and environmental stability. Therefore, how to improve the environmental adaptability and long-term reliability of devices while ensuring excellent synaptic function remains a pressing technical challenge in this field.
[0005] Surface mount technology (SMT), as a mature semiconductor device protection method, has been widely used in memory chips, display panels, and power devices. By depositing or covering a dense protective layer on the device surface, it is possible to effectively isolate the penetration of external oxygen and moisture, while buffering the damage caused by mechanical stress. Furthermore, the encapsulation layer can reduce interface defect density to a certain extent and stabilize ion migration paths, thereby improving the device's retention and durability. Introducing SMT into the fabrication process of synaptic transistors can not only effectively improve the device's operational stability under air, humidity, and stress environments, but also ensure its consistency and reliability during long-term cyclic operation. This approach provides a new solution to the problems of high environmental sensitivity and poor retention characteristics in existing synaptic transistors. Summary of the Invention
[0006] This invention aims to provide a lithium-based synaptic transistor device and its fabrication method based on surface encapsulation technology. This method effectively protects the channel layer and its electrode interface by introducing a dense surface encapsulation layer on the outermost layer of the device, thereby suppressing the effects of external oxygen, moisture, and mechanical stress on the channel layer. Surface encapsulation significantly improves the environmental adaptability and long-term stability of the synaptic transistor, enabling it to maintain excellent conductivity control characteristics, retention, and repeatability even in complex application scenarios.
[0007] The technical solution adopted in this invention is as follows:
[0008] This invention first provides a lithium-based synaptic transistor device based on surface encapsulation technology, the structure of which includes: a substrate, a source electrode and a drain electrode, a channel layer, an electrolyte layer, a gate electrode, and a surface encapsulation layer; wherein, the channel layer, the source electrode, and the drain electrode are formed on the surface of the substrate, the source electrode and the drain electrode are arranged in parallel and their two ends are in ohmic contact with the channel layer, the electrolyte layer covers the channel layer, the gate electrode is disposed above the electrolyte layer, and the surface encapsulation layer is disposed outside the gate electrode and covers the entire surface of the device. The device achieves non-volatile conductivity control through gate voltage-induced ion migration.
[0009] The substrate is made of LaAlO3, SrRuO3, SrTaO3, SrTiO3 or Al2O3 material.
[0010] The channel layer is formed from a functional thin film material that allows lithium ions to migrate, such as lithium-based oxides, lithium-based sulfides, or lithium-based halides.
[0011] The electrolyte layer is formed from inorganic solid electrolyte materials, including but not limited to LiPON, Li3PO4, and Li7La3Zr2O. 12 (LLZO), Li 1.5 Al 0.5 Ge 1.5(PO4)3 (LAGP) or other solid electrolyte films with high ionic conductivity and good electrochemical stability.
[0012] The surface encapsulation layer is made of silicon oxide (SiO2). x ), aluminum oxide (Al2O3), silicon nitride (SiN) x It is formed from one or more of the following materials: magnesium fluoride (MgF2).
[0013] The source electrode and drain electrode are preferably highly conductive metal electrodes.
[0014] The gate electrode can be made of inert noble metals such as Au, Pt, and Al, or highly conductive materials.
[0015] Furthermore, the source electrode, drain electrode, and gate electrode are made of conductive metals such as gold (Au), platinum (Pt), titanium / gold (Ti / Au), or aluminum (Al), with a thickness of 40-80 nm.
[0016] The thickness of the surface encapsulation layer is 10-500nm. Through dense coverage, it effectively blocks the penetration of oxygen and water vapor, and at the same time plays a buffering and protective role when the device is subjected to external stress, so as to improve the stability and maintain the characteristics of the device.
[0017] The present invention also provides a method for fabricating the lithium-based synaptic transistor device based on surface encapsulation technology, comprising the following steps:
[0018] 1) The substrate was sequentially cleaned with acetone, alcohol, and deionized water, and then treated with argon plasma to remove surface contaminants;
[0019] 2) Spin-coat the substrate surface with an adhesion promoter and a positive photoresist in sequence, and then perform soft baking to remove the solvent and stabilize the photoresist layer. Then expose and develop the photoresist layer to obtain the electrode patterned area.
[0020] 3) Deposit metal electrode material in the patterned area of the electrode, and remove the metal in the non-patterned area by a stripping process, thereby forming source and drain electrodes on the substrate surface;
[0021] 4) Deposit a trench layer on the surface of the substrate;
[0022] 5) Deposit an electrolyte layer on the surface of the channel layer;
[0023] 6) Deposit a gate electrode above the electrolyte layer;
[0024] 7) Deposit encapsulation material across the entire device surface to form a surface encapsulation layer;
[0025] 8) Spin-coat photoresist onto the surface of the encapsulation layer and perform photolithography to obtain the opening pattern at the corresponding electrode position;
[0026] 9) Perform dry etching in the opening region to expose the gate electrode, source electrode, and drain electrode.
[0027] Furthermore, the surface encapsulation layer in step 7) is formed using processes such as atomic layer deposition (ALD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), or magnetron sputtering (MS).
[0028] The present invention also provides a neuromorphic computing system comprising an array of lithium-based synaptic transistor devices described herein, the array being configured to implement weight updates for an artificial neural network.
[0029] The essential features of this invention are as follows: By introducing a surface encapsulation layer on the outermost layer of the synaptic transistor device, the device is less susceptible to corrosion from oxygen and moisture in an air environment, while simultaneously reducing the risk of defect propagation caused by mechanical stress, significantly improving the stability of the channel layer and electrode interface. This encapsulation layer not only effectively delays the degradation of the channel material but also reduces the density of interface trap states, ensuring the controllability of ion migration, thereby improving the uniformity and long-term retention of the device's conductivity regulation. Compared with traditional methods that rely solely on channel material modification or gate dielectric optimization, this invention achieves overall device protection through the encapsulation structure, making it more universal and compatible with various processes.
[0030] The beneficial effects of this invention are as follows:
[0031] 1) The synaptic transistor device and its fabrication method based on surface encapsulation technology provided by this invention have a simple structure, good process compatibility, and can be widely applied to existing semiconductor processes.
[0032] 2) By depositing a sealing layer on the device surface, the penetration of oxygen and water vapor is effectively suppressed, significantly improving the stability of the channel layer and the retention of conductivity regulation.
[0033] 3) The encapsulation layer acts as a buffer against external mechanical stress, reducing performance fluctuations of the device under external forces such as bending and compression.
[0034] 4) The synaptic transistors prepared by this invention exhibit excellent reversible conductance control characteristics and consistency during long-term cyclic operation, and are suitable for fields such as neuromorphic computing, artificial intelligence hardware circuits and flexible electronic devices.
[0035] 5) By introducing surface encapsulation technology, this invention provides a practical and feasible technical approach to solve the problems of high environmental sensitivity and insufficient long-term stability of synaptic transistors. Attached Figure Description
[0036] Figure 1 This is a simplified cross-sectional view of the synaptic transistor structure of the present invention.
[0037] Figure 2 This is a schematic diagram of the synaptic transistor prepared in Example 1.
[0038] Figure 3 This is a schematic cross-sectional view of the synaptic transistor prepared in Example 1.
[0039] Figure 4 The SiO2 surface encapsulation layer of the synaptic transistor prepared in Example 1 x The atomic force microscopy (AFM) images show its surface morphology and roughness characteristics.
[0040] Figure 5 The images are scanning electron microscope (SEM) images of the synaptic transistors prepared in Example 1, where the left image shows the surface morphology of the unencapsulated top LiPON film, and the right image shows the surface morphology after SiO2 deposition. x Surface morphology of the encapsulated film.
[0041] Figure 6 The conductivity modulation characteristic curves of the synaptic transistor prepared in Example 1 under different humidity conditions. Detailed Implementation
[0042] like Figure 1 As shown, a lithium-based synaptic transistor device based on surface encapsulation technology includes the following structure: a substrate 1, a source electrode 2 and a drain electrode 3, a channel layer 4, an electrolyte layer 5, a gate electrode 6, and a surface encapsulation layer 7; wherein, the channel layer 4, the source electrode 2, and the drain electrode 3 are formed on the surface of the substrate 1, the source electrode 2 and the drain electrode 3 are arranged in parallel and their two ends are in ohmic contact with the channel layer 4, the electrolyte layer 5 covers the channel layer 4, the gate electrode 6 is disposed on the electrolyte layer 5, and the surface encapsulation layer 7 is disposed outside the gate electrode 6 and covers the entire surface of the device.
[0043] Example 1
[0044] 1) Take a size of 10×10mm 2 The single-sided polished SrTiO3 (STO) single crystal substrate was ultrasonically cleaned in acetone, alcohol and deionized water for 30 minutes in sequence, then the substrate surface was dried with a nitrogen gun, and then the substrate surface was cleaned with argon plasma.
[0045] 2) Spin-coat hexamethyldisiloxane (HMDS) adhesion promoter and MIR-701 positive photoresist onto the surface of the STO substrate. The HMDS adhesion promoter was spin-coated at 2000 rpm for 20 s. The MIR-701 positive photoresist was first spin-coated at 1400 rpm for 20 s, and then immediately a second spin-coating was performed at 2000 rpm for 30 s. Subsequently, the substrate was immediately soft-baked at 100°C for 10 minutes to remove the solvent and stabilize the photoresist layer.
[0046] 3) Ultraviolet exposure was performed for 14 seconds using a 248nm KrF light source, with an exposure energy of 66.6mJ / cm². 2 The electrode patterned area was obtained by developing in 2.38% TMAH developer for about 40 seconds.
[0047] 4) Apply gold electrodes to the developed pattern area using magnetron sputtering equipment, and pump the deposition chamber to 5×10⁻⁶ m³ / s. -5 Below Pa, argon gas is introduced, the sputtering working pressure is increased to 0.5 Pa, the sputtering power is adjusted to 120 W, the deposition time is 180 s, the sample / target spacing is fixed at 10 cm, and the film thickness is controlled at about 50 nm.
[0048] 5) After metal deposition is completed in the photoresist patterned area, the metal in the non-patterned area is removed by stripping liquid, thereby obtaining the source electrode and drain electrode on the substrate surface;
[0049] In this step, N-methylpyrrolidone (NMP) is used as the stripping solution. The patterned sample is immersed in the stripping solution for at least 20 minutes to thoroughly remove the photoresist layer. After immersion, the sample and stripping solution are placed together in an ultrasonic cleaning device for auxiliary cleaning to ensure complete removal of residual photoresist. Subsequently, the sample is ultrasonically cleaned sequentially with acetone, anhydrous ethanol, and deionized water at 40% of the rated output for 10 minutes to further remove surface organic residues and impurities. After cleaning, the sample surface is dried using a nitrogen stream and baked at 100°C for 10 minutes to complete the post-processing, thereby obtaining a metal electrode pattern with clear boundaries and good adhesion.
[0050] 6) Deposition of smooth and highly crystalline Li4Ti5O on STO. 12 (LTO) thin film, forming LTO channel layer;
[0051] The LTO channel layer was fabricated via reactive magnetron sputtering. First, a molecular pump was used to pump the deposition chamber to 5 × 10⁻⁶ m³ / s. -5 The base vacuum was set to Pa, and the sputtering working pressure was increased to 0.5 Pa. A single crystal substrate was used as the deposition substrate and current collector. The total gas flow rate was controlled at 50 sccm. The Ar:O2 ratio during deposition was controlled at 28.3:10.1. The deposition RF power supply was set to 100W. The sample / target spacing was fixed at 10 cm. The deposition time was 40 min. The film thickness was controlled at approximately 100 nm.
[0052] 7) An amorphous electrolyte layer (LiPON) is deposited by reactive sputtering to cover the entire LTO channel layer;
[0053] The electrolyte layer, LiPON, was fabricated via reactive magnetron sputtering. First, a molecular pump was used to pump the deposition chamber to a depth of 5 × 10⁻⁶ m². - 5 The base vacuum was set to Pa, and the sputtering working pressure was increased to 0.5 Pa. A single crystal substrate was used as the deposition substrate and current collector. The total gas flow rate was controlled at 50 sccm. The Ar:N2 ratio during deposition was controlled at 28.3:40. The deposition RF power supply was set to 80W. The sample / target spacing was fixed at 10 cm. The deposition time was 120 min. The film thickness was controlled at approximately 400 nm.
[0054] 8) Deposit a gold gate electrode above the LiPON electrolyte layer:
[0055] The gold gate electrode has the same fabrication parameters as the source and drain electrodes mentioned above.
[0056] 9) Deposit a SiO2 encapsulation layer on the entire device surface. x :
[0057] Encapsulation layer SiO x The material was prepared by reactive magnetron sputtering. First, the deposition chamber was pumped to 5 × 10⁻⁶ m³ / s. -5 The base vacuum was set to 0.5 Pa, and the sputtering working pressure was adjusted to 0.5 Pa. A single crystal substrate was used as the deposition substrate and current collector. The total gas flow rate was controlled at 50 sccm, the Ar:O2 ratio during deposition was controlled at 28.3:40, the deposition RF power was set to 80 W, the sample / target spacing was fixed at 10 cm, the deposition time was 14 min, and the film thickness was controlled at approximately 50 nm.
[0058] 10) Selectively expose the gate, source, and drain electrodes of the device using a dry etching process;
[0059] The dry etching process is as follows: First, a photoresist layer is formed on the device surface, and an opening pattern corresponding to the electrode position is fabricated in the photoresist layer using a photolithography process; then, the substrate is placed in a reactive ion etching system, and a fluorine-containing gas (such as CF4, CHF3, and O2 as an auxiliary gas if necessary) is introduced. Under the action of a radio frequency electric field, plasma is excited, causing the SiO2 in the opening region to precipitate. x The layer is gradually removed through chemical reactions and physical bombardment; etching terminates when the underlying metal electrodes (including Ti / Pt source / drain electrodes and Ti / Au gate electrodes) are fully exposed. Subsequently, a resist stripping process is used to remove residual photoresist, thereby creating exposure windows for the gate, source, and drain electrodes on the device surface, while preserving the SiO₂ in the non-electrode regions. x The encapsulation layer provides complete coverage to enable electrode lead-out and ensure the stability and reliability of the rest of the device.
[0060] Figure 4The fabricated synaptic transistor was demonstrated by surface-mount SiO2. x Subsequent atomic force microscopy (AFM) images reveal its surface morphology and roughness characteristics. The sample surface is smooth and dense, with an average roughness R0. a = 0.723 nm, root mean square roughness R q =0.916nm, indicating that the deposited SiO x The encapsulation layer is continuous, uniform, and of excellent quality.
[0061] Figure 5 The results are from scanning electron microscopy (SEM). Unencapsulated devices exposed to high humidity exhibit slight morphological degradation and moisture-absorbing bubble expansion, indicating their sensitivity to humidity. However, after being placed in an environment with 85% relative humidity for 100 hours, the surface morphology and structural integrity of the encapsulated devices remained largely stable, with no obvious cracks, peeling, or interface delamination observed. Electrodes and SiO₂ x The encapsulation layer is tightly bonded, and there is no obvious interface degradation, which fully demonstrates the effectiveness of SiO2. x The effectiveness of encapsulation in improving the moisture resistance and structural stability of devices.
[0062] Figure 6 The long-term duration enhancement (LTP) and long-term duration inhibition (LTD) pulse training characteristics of the packaged synaptic transistor under different relative humidity conditions (30%, 40%, 50%, 70%, 80%, 90%) are demonstrated. The device exhibits stable and adjustable conductance changes under continuous positive and negative gate pulse stimulation, displaying good linearity and symmetry, enabling precise control of synaptic weights and demonstrating excellent neuromorphic plasticity. With increasing relative humidity, the on-state and off-state trends of the device remain consistent, and the LTP / LTD curve morphology remains essentially unchanged, indicating that SiO2... x The encapsulation effectively suppresses the instability caused by moisture adsorption and ion migration, thereby ensuring the training consistency and operational stability of the device in high humidity environments.
Claims
1. A lithium-based synaptic transistor device based on surface packaging technology, characterized by, The structure comprises: a substrate, a source electrode and a drain electrode, a channel layer, an electrolyte layer, a gate electrode and a surface encapsulation layer; wherein the channel layer, the source electrode and the drain electrode are formed on the surface of the substrate, the source electrode and the drain electrode are arranged in parallel and have both ends respectively in ohmic contact with the channel layer, the electrolyte layer is covered on the channel layer, the gate electrode is arranged above the electrolyte layer, and the surface encapsulation layer is arranged outside the gate electrode and covers the entire surface of the device.
2. The lithium-based synaptic transistor device based on surface packaging technology according to claim 1, wherein, The substrate is formed of LaAlO3, SrRuO3, SrTaO3, SrTiO3 or Al2O3 material.
3. The lithium-based synaptic transistor device based on surface packaging technology according to claim 1, wherein, The channel layer is formed of lithium-based oxide, lithium-based sulfide or lithium-based halide.
4. The lithium-based synaptic transistor device based on surface packaging technology according to claim 1, wherein, The electrolyte layer is formed from LiPON, Li3PO4, Li7La3Zr2O 12 or Li 1.5 Al 0.5 Ge 1.5 (PO4)3.
5. The lithium-based synaptic transistor device based on surface packaging technology according to claim 1, wherein, The surface encapsulation layer is formed of one or more than one material selected from silicon oxide, aluminum oxide, silicon nitride and magnesium fluoride.
6. The lithium-based synaptic transistor device based on surface packaging technology according to claim 1, wherein, The source electrode, the drain electrode or the gate electrode is formed of conductive metal material, and the conductive metal material is gold, platinum, titanium-gold mixture or aluminum.
7. The lithium-based synaptic transistor device based on surface packaging technology according to claim 1, wherein, The thickness of the source electrode, the drain electrode or the gate electrode is 40-80 nm, and the thickness of the surface encapsulation layer is 10-500 nm.
8. The method of claim 1-7, wherein the method is a method of fabricating a lithium-based synapse transistor device based on surface packaging technology. The method comprises the following steps: 1) sequentially cleaning the substrate with acetone, alcohol and deionized water, and treating the substrate with argon plasma to remove surface contaminants; 2) sequentially spin-coating adhesion promoter and positive photoresist on the surface of the substrate, and performing soft baking to remove solvent and stabilize the photoresist layer, then exposing and developing the photoresist layer to obtain an electrode patterned area; 3) depositing metal electrode material on the electrode patterned area, and removing the metal in the non-patterned area by a stripping process to form the source electrode and the drain electrode on the surface of the substrate; 4) depositing the channel layer on the surface of the substrate; 5) depositing the electrolyte layer on the surface of the channel layer; 6) depositing the gate electrode on the electrolyte layer; 7) depositing encapsulation layer material on the entire surface of the device to form the surface encapsulation layer; 8) spin-coating photoresist on the surface of the encapsulation layer and performing photolithography to obtain an opening pattern corresponding to the electrode position; 9) performing dry etching on the opening area to expose the gate electrode, the source electrode and the drain electrode.
9. The method of claim 8, wherein the method further comprises: The surface encapsulation layer in step 7) is formed by atomic layer deposition, molecular beam epitaxy, plasma-enhanced chemical vapor deposition or magnetron sputtering process.
10. A neuromorphic computing system, comprising: The array comprises the lithium-based synaptic transistor device according to any one of claims 1-7.