PIN photoelectric detector based on epitaxial Ge on Si and preparation method

Abstract

The invention discloses a PIN photoelectric detector based on epitaxial Ge on Si and a preparation method, and relates to the technical field of semiconductor photoelectric devices. The intrinsic Ge epitaxial layer is positioned on the upper surface of the N-type Si substrate; the P-type Ge region is positioned in the intrinsic Ge epitaxial layer and is close to the upper surface of the intrinsic Ge epitaxial layer; the first metal electrode and the second metal electrode are in ohmic contact with the P-type Ge region and the N-type Si substrate respectively. The intrinsic Ge layer is epitaxially grown on the N-type Si substrate to serve as an absorption region, a Si / Ge heterojunction PIN structure is constructed, and reverse injection of carriers is effectively inhibited by utilizing an energy band potential barrier of the Si / Ge heterojunction, so that the dark current of the device is remarkably reduced. Meanwhile, by accurately controlling the thickness of the intrinsic Ge epitaxial layer, the bandwidth and the responsivity of the device can be flexibly balanced so as to meet the requirements of different application scenes such as high-speed communication or high-sensitivity detection.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor optoelectronic device technology, specifically relating to a PIN photodetector based on Ge epitaxial growth on Si and its fabrication method. Background Technology

[0002] Near-infrared photodetectors are crucial in optical communication, sensing, and imaging. Currently, the mainstream high-performance detectors in this field primarily use indium gallium arsenide (InGaAs), which exhibits high responsivity and sensitivity in the 1550 nm communication band. However, InGaAs detectors are expensive to fabricate, require complex heteroepitaxial growth techniques, and are incompatible with mainstream silicon-based CMOS processes, limiting their widespread application in low-cost, large-scale integrated systems.

[0003] In recent years, colloidal quantum dot (such as PbS quantum dot) detectors have attracted attention due to their advantages such as solution-handleability and low cost. However, they have problems such as poor stability, low carrier mobility, and difficulty in integration with silicon processes, and their performance and reliability are still difficult to meet commercial requirements.

[0004] In contrast, germanium (Ge), as a traditional semiconductor material, has excellent light absorption characteristics in the near-infrared band (especially up to 1850 nm), and its fabrication process is highly compatible with silicon-based CMOS processes, making it an ideal candidate material for achieving low-cost, high-performance on-chip optoelectronic integration.

[0005] However, traditional Ge-based photodetectors also face their own challenges. Metal-semiconductor-metal (MSM) detectors based on germanium materials typically suffer from high dark current, leading to low device sensitivity. Furthermore, many structures using bulk germanium for PIN photodetectors exhibit very high dark current due to their large I-region. However, without the I-region, the recombination rate of photogenerated carriers is high, making it difficult to improve device responsivity. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a PIN photodetector based on Ge epitaxial growth on Si and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a PIN photodetector based on Si-epitaxy Ge, comprising: N-type Si substrate; An intrinsic Ge epitaxial layer is located on the upper surface of the N-type Si substrate; The P-type Ge region is located within the intrinsic Ge epitaxial layer and close to the upper surface of the intrinsic Ge epitaxial layer; The first metal electrode is located on the upper surface of the P-type Ge region and forms an ohmic contact with the P-type Ge region. The second metal electrode is located on the lower surface of the N-type Si substrate and forms an ohmic contact with the N-type Si substrate.

[0007] In one embodiment of the present invention, the resistivity of the N-type Si substrate does not exceed 0.05 Ω·cm.

[0008] In one embodiment of the present invention, the thickness of the N-type Si substrate is 300-500 μm.

[0009] In one embodiment of the present invention, the thickness of the intrinsic Ge epitaxial layer is 0.1-2 μm.

[0010] In one embodiment of the present invention, the doping concentration of the p-type Ge region is 1×10⁻⁶. 18 -1×10 20 cm -3 .

[0011] In one embodiment of the present invention, the ion implantation depth of the P-type Ge region is 50-200 nm.

[0012] In one embodiment of the present invention, the materials of the first metal electrode and the second metal electrode are gold, silver or aluminum.

[0013] This invention provides a method for fabricating a PIN photodetector based on Ge epitaxial growth on Si, applicable to the PIN photodetector based on Ge epitaxial growth on Si described in any of the above embodiments. The fabrication method includes: Step 1: Select an N-type Si substrate; Step 2: An intrinsic Ge epitaxial layer is formed on the upper surface of the N-type Si substrate using an epitaxial process; Step 3: Perform ion implantation or diffusion on the upper surface of the intrinsic Ge epitaxial layer to form a P-type Ge region; Step 4: Electrode deposition is performed on the upper surface of the P-type Ge region and the lower surface of the N-type Si substrate to form a first metal electrode and a second metal electrode.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The PIN photodetector based on Si epitaxial Ge of the present invention effectively suppresses dark current through a heterojunction PIN structure design of N-type Si substrate / intrinsic Ge epitaxial layer / P-type Ge region. The SiGe heterojunction formed between N-type Si and intrinsic Ge provides an additional barrier for carrier transport due to the conduction band and valence band shift. This barrier can effectively block the diffusion and drift of majority carriers under zero bias or small reverse bias, further reducing the device's dark current.

[0015] 2. The PIN photodetector based on Si epitaxial Ge of the present invention optimizes the thickness of the intrinsic Ge epitaxial layer (i-Ge layer) to be smaller than that of the I-region of conventional bulk germanium PIN detectors (typically tens to hundreds of micrometers) by precisely controlling the thickness of the epitaxial layer (e.g., 0.1-2 μm). The thinner depletion region significantly reduces the dark current component generated by thermally generated carriers in the bulk region. In addition, the i-Ge layer can also effectively achieve photogenerated carrier separation.

[0016] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a PIN photodetector based on Si epitaxial Ge provided in an embodiment of the present invention; Figure 2 This is a flowchart of a method for fabricating a PIN photodetector based on epitaxial Ge on Si, provided by an embodiment of the present invention.

[0018] Icons: 1- N-type Si substrate; 2- Intrinsic Ge epitaxial layer; 3- P-type Ge region; 4- First metal electrode; 5- Second metal electrode. Detailed Implementation

[0019] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for fabricating a PIN photodetector based on Si epitaxial Ge and its preparation.

[0020] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0021] In one aspect, embodiments of the present invention provide a PIN photodetector based on epitaxial Ge on Si, the core of which lies in the effective suppression of dark current through the heterojunction PIN structure design of N-type Si substrate / intrinsic Ge epitaxial layer / P-type Ge region.

[0022] Please see Figure 1 , Figure 1This is a schematic diagram of a PIN photodetector based on Si-based epitaxial Ge provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the PIN photodetector based on Si-based epitaxial Ge in this embodiment includes: an N-type Si substrate 1, an intrinsic Ge epitaxial layer 2, a P-type Ge region 3, a first metal electrode 4, and a second metal electrode 5. The intrinsic Ge epitaxial layer 2 is located on the upper surface of the N-type Si substrate 1; the P-type Ge region 3 is located within the intrinsic Ge epitaxial layer 2 and close to its upper surface; the first metal electrode 4 is located on the upper surface of the P-type Ge region 3, forming an ohmic contact with it; and the second metal electrode 5 is located on the lower surface of the N-type Si substrate 1, forming an ohmic contact with it.

[0023] In this embodiment, the resistivity of the N-type Si substrate 1 does not exceed 0.05 Ω·cm, for example, it can be 0.002 Ω·cm, 0.004 Ω·cm, 0.01 Ω·cm or 0.03 Ω·cm.

[0024] Optionally, the thickness of the N-type Si substrate 1 is 300-500 μm. For example, it can be 300 μm, 400 μm, or 500 μm.

[0025] In this embodiment, a high-quality intrinsic (i-type) germanium layer can be grown on the upper surface of the N-type Si substrate 1 by epitaxial processes such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) to form an intrinsic Ge epitaxial layer 2.

[0026] Optionally, the thickness of the intrinsic Ge epitaxial layer 2 is 0.1-2 μm. For example, it can be 100 nm, 200 nm, 1.5 μm or 2 μm.

[0027] It is understandable that when a photodetector pursues a large bandwidth, in order to reduce the carrier transit time, the thickness of the intrinsic Ge epitaxial layer 2 needs to be reduced, and its thickness can be controlled at around 100-500nm; while when a photodetector pursues high absorption efficiency, the thickness of the intrinsic Ge epitaxial layer 2 needs to be increased to improve the detector's responsivity.

[0028] For example, when the thickness of the intrinsic Ge epitaxial layer 2 is 200 nm, this thickness can ensure a certain initial light absorption at a communication wavelength of 1550 nm, while the core objective is to minimize the transit time of photogenerated carriers. Although the intrinsic Ge epitaxial layer is very thin, the conduction band shift at the N-Si / i-Ge heterojunction interface can still effectively suppress the reverse injection of electrons from N-Si to the i-Ge region. This heterojunction barrier enables the device in this embodiment to achieve high-speed performance while its dark current is still much lower than that of a homojunction Ge photodiode.

[0029] For example, when the thickness of the intrinsic Ge epitaxial layer 2 is 1.5 μm, this thickness is slightly greater than the absorption depth of Ge at a wavelength of 1550 nm, aiming to ensure that incident photons are fully absorbed. A thicker intrinsic Ge epitaxial layer does not linearly increase the dark current because the depletion region width is mainly determined by the bias voltage and doping concentration. Thanks to the barrier effect of the N-Si / i-Ge heterojunction and the lower defect density of the intrinsic Ge epitaxial layer compared to bulk Ge, the photodetector of this embodiment achieves high responsivity while maintaining a low dark current, thus ensuring excellent signal-to-noise ratio in low-light environments.

[0030] In this embodiment, the doping concentration of the p-type Ge region 3 is 1×10⁻⁶. 18 -1×10 20 cm -3 The ion implantation depth is 50-200 nm.

[0031] Optionally, the p-type Ge region 3 can be prepared using an ion implantation process. For example, boron (B) ions are implanted into the upper surface region of the intrinsic Ge epitaxial layer 2 to form a doping concentration of 5 × 10⁻⁶. 19 cm -3 The P-type Ge region 3 has a junction depth of 150 nm. The P-type Ge region 3 constitutes the P region of the PIN junction. It should be noted that after ion implantation, rapid thermal annealing (RTA) is required to activate the dopant and repair lattice damage.

[0032] In other alternative embodiments, a diffusion process can be used to form the p-type Ge region 3. Exemplarily, a boron-containing solid source is used as the dopant source, and diffusion is performed at 600°C to form a doping concentration of approximately 1 × 10⁻⁶. 20 cm -3 3. A P-type Ge region with a junction depth of approximately 180 nm.

[0033] Alternatively, the P-type Ge region can also achieve ohmic contact through a combination of low-concentration ion implantation and high-concentration ion implantation, with the high-concentration ion implantation region being smaller than the low-concentration ion implantation region.

[0034] In this embodiment, the first metal electrode 4 and the second metal electrode 5 are made of gold, silver or aluminum.

[0035] Optionally, on the upper surface of the p-type Ge region 3, a metal layer (e.g., sequentially depositing 20 nm Ti (adhesion layer), 30 nm Pt (barrier layer), and 200 nm Au (conductive layer)) can be deposited by electron beam evaporation or thermal evaporation, and a patterned electrode can be formed by photolithography to form an ohmic contact with the p-type Ge region. On the lower surface of the n-type Si substrate 1, a 300 nm Al layer is deposited over the entire back side to form an ohmic contact.

[0036] The Si-based epitaxial Ge PIN photodetector of this invention effectively suppresses dark current through a heterojunction PIN structure design of an N-type Si substrate / intrinsic Ge epitaxial layer / P-type Ge region. The SiGe heterojunction formed between the N-type Si and intrinsic Ge provides an additional barrier for carrier transport due to the conduction and valence band shifts. This barrier effectively blocks the diffusion and drift of majority carriers under zero bias or small reverse bias, further reducing the device's dark current. By precisely controlling the thickness of the intrinsic Ge epitaxial layer (i-Ge layer) (e.g., 0.1-2 μm), its thickness can be optimized to be smaller than the I-region of a conventional bulk germanium PIN detector (typically tens to hundreds of micrometers). The thinner depletion region significantly reduces the dark current component generated by thermally generated carriers in the bulk region. In addition, the i-Ge layer can also effectively achieve photogenerated carrier separation.

[0037] The PIN photodetector based on Si-based epitaxial Ge in this invention can balance responsivity and bandwidth by adjusting the thickness of the intrinsic Ge epitaxial layer to adapt to different application scenarios. When the device requires high-speed response, a thinner intrinsic Ge epitaxial layer (e.g., 100-300 nm) can be fabricated. The thinner absorption layer shortens the transit time of photogenerated carriers, thereby improving the device's bandwidth. When the device requires high quantum efficiency, a thicker intrinsic Ge epitaxial layer (e.g., 1-2 μm) can be fabricated. A thicker absorption layer increases the absorption length for incident light (especially in the 1550-1600 nm band), thereby improving the device's responsivity.

[0038] Secondly, embodiments of the present invention provide a method for fabricating a PIN photodetector based on Si-epitaxy Ge, applicable to the PIN photodetector based on Si-epitaxy Ge proposed in the first aspect.

[0039] Please see Figure 2 , Figure 2 This is a flowchart illustrating a method for fabricating a PIN photodetector based on epitaxial Ge on Si, as provided in an embodiment of the present invention. Figure 2 As shown, the fabrication method of the PIN photodetector based on Si epitaxial Ge according to an embodiment of the present invention includes the following steps: Step 1: Select an N-type Si substrate.

[0040] In this embodiment, the resistivity of the N-type Si substrate does not exceed 0.05 Ω·cm. This low-resistivity substrate facilitates the formation of low-resistivity ohmic contacts with metal electrodes, reducing the series resistance of the device. Optionally, the thickness of the N-type Si substrate is 300-500 μm to provide sufficient mechanical support strength for subsequent processing. The use of a highly doped N-type substrate provides an ideal electron collection terminal for the device, and its low-resistivity characteristics are fundamental to achieving efficient charge extraction and low-power operation.

[0041] After selecting an N-type Si substrate, the silicon wafer is cleaned using a standard RCA cleaning process to remove surface organic matter, metal particles, and the natural oxide layer, resulting in a clean, hydrophilic surface.

[0042] Step 2: An intrinsic Ge epitaxial layer is formed on the upper surface of an N-type Si substrate using an epitaxial process.

[0043] Optionally, a high-quality intrinsic germanium (i-Ge) epitaxial layer can be grown on the upper surface of the N-type Si substrate using epitaxial processes such as chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). The thickness of the intrinsic Ge epitaxial layer is precisely controlled within the range of 0.1-2 μm.

[0044] For example, the cleaned silicon wafer can be placed in an ultra-high vacuum chemical vapor deposition (UHV-CVD) reaction chamber for initial low-temperature buffer layer growth: at approximately 400°C, GeH4 is introduced to grow a low-temperature Ge buffer layer approximately 50 nm thick to alleviate the lattice mismatch between Ge and Si. This is followed by high-temperature cyclic annealing and epitaxy: the temperature is raised to 600-700°C, and multiple short-time annealing cycles are performed (e.g., 1 minute each, 5 cycles) to promote the formation of low-dislocation crystals. Then, at the same high or slightly lower temperature, GeH4 is continued to be introduced to epitaxially grow an intrinsic Ge epitaxial layer of the desired thickness. By precisely controlling the epitaxial time, the thickness of the i-Ge layer can be precisely controlled.

[0045] In this embodiment, by precisely controlling the thickness of the intrinsic Ge epitaxial layer (i-Ge layer) (e.g., 0.1-2 μm), its thickness can be optimized to be smaller than the I-region of a conventional bulk germanium PIN detector (typically tens to hundreds of micrometers). A thinner depletion region significantly reduces the dark current component generated by thermally generated carriers in the bulk region. By adjusting the thickness of the intrinsic Ge epitaxial layer, a trade-off between responsivity and bandwidth can be struck to suit different application scenarios.

[0046] Step 3: Perform ion implantation or diffusion on the upper surface of the intrinsic Ge epitaxial layer to form a P-type Ge region.

[0047] Photoresist is spin-coated onto the surface of the intrinsic Ge epitaxial layer after epitaxy is completed, and the P-type region pattern is defined by photolithography. Then, ion implantation or diffusion processes are performed to form the P-type Ge region.

[0048] In this embodiment, the doping concentration of the p-type Ge region 3 is 1×10⁻⁶. 18 -1×10 20 cm -3 The ion implantation depth is 50-200 nm.

[0049] For example, an ion implanter can be used to implant boron (B) +The dopant is implanted as a dopant source, and the implantation parameters can be adjusted according to the performance of the target device. For example, for high-speed devices, a medium energy (e.g., 30 keV) and a dose (e.g., 5 × 10⁻⁶) can be used. 14 cm -2 This allows for the acquisition of a shallower (~150 nm) P-type Ge region. For high-sensitivity devices, higher energies or thermal diffusion processes can be used to achieve a deeper junction depth (~180 nm) and ensure an effective depletion region with the thicker intrinsic Ge epitaxial layer underneath.

[0050] After ion implantation, rapid thermal annealing (RTA, e.g., 600°C, 30s) is performed in an inert atmosphere (e.g., N2) to activate dopant ions and repair implantation damage.

[0051] In this embodiment, the dark current is effectively suppressed by the heterojunction PIN structure design of N-type Si substrate / intrinsic Ge epitaxial layer / P-type Ge region. The SiGe heterojunction formed between N-type Si and intrinsic Ge provides an additional barrier for carrier transport due to the conduction band and valence band shift. This barrier can effectively block the diffusion and drift of majority carriers under zero bias or small reverse bias, further reducing the device dark current.

[0052] Step 4: Electrode deposition is performed on the upper surface of the P-type Ge region and the lower surface of the N-type Si substrate to form the first metal electrode and the second metal electrode.

[0053] Optionally, an electrode region window can be defined on the surface of the P-type Ge region using photolithography and dry / wet etching processes. Then, Ti (adhesion layer, 20 nm), Pt (barrier layer, 30 nm), and Au (conductive layer, 200 nm) are deposited sequentially using an electron beam evaporation device. Subsequently, a lift-off process is used to form the first metal electrode. If necessary, the back side of the silicon wafer can be thinned and cleaned by grinding, and then a 300 nm thick layer of aluminum can be deposited on the entire back side of the silicon wafer to form the second metal electrode.

[0054] After all electrodes are formed, the device can be alloyed (e.g., annealed in a H2 / N2 atmosphere at 400°C) to optimize the metal-semiconductor contact resistance and improve ohmic contact.

[0055] The present invention discloses a method for fabricating a PIN photodetector based on Si-based epitaxial Ge. Through UHV-CVD epitaxy and ion implantation / diffusion processes, the thickness, crystal quality, doping concentration, and junction depth of the intrinsic Ge epitaxial layer can be precisely and independently controlled, providing a solid process foundation for customizable device performance. All key steps involved in this method (CVD, ion implantation, photolithography, and metallization) are standard or finely tuned silicon-based processes, requiring no special materials or extreme process conditions. This allows the detector to be seamlessly integrated onto existing silicon-based photoelectric integrated circuits (PICs) or wafers with readout circuitry, significantly reducing manufacturing costs and integration complexity.

[0056] For details regarding the fabrication method of the PIN photodetector based on Si epitaxial Ge and its corresponding beneficial effects, please refer to the relevant content on the PIN photodetector based on Si epitaxial Ge provided in the first aspect, which will not be repeated here.

[0057] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0058] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0059] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A PIN photodetector based on Ge epitaxial growth on Si, characterized in that, include: N-type Si substrate (1); The intrinsic Ge epitaxial layer (2) is located on the upper surface of the N-type Si substrate (1); The P-type Ge region (3) is located within the intrinsic Ge epitaxial layer (2) and close to the upper surface of the intrinsic Ge epitaxial layer (2); The first metal electrode (4) is located on the upper surface of the P-type Ge region (3) and forms an ohmic contact with the P-type Ge region (3); The second metal electrode (5) is located on the lower surface of the N-type Si substrate (1) and forms an ohmic contact with the N-type Si substrate (1).

2. The PIN photodetector based on Si-based epitaxial Ge according to claim 1, characterized in that, The resistivity of the N-type Si substrate (1) is no more than 0.05 Ω·cm.

3. The PIN photodetector based on Si-based epitaxial Ge according to claim 1, characterized in that, The thickness of the N-type Si substrate (1) is 300-500 μm.

4. The PIN photodetector based on Si-based epitaxial Ge according to claim 1, characterized in that, The thickness of the intrinsic Ge epitaxial layer (2) is 0.1-2 μm.

5. The PIN photodetector based on Ge epitaxial growth on Si according to claim 1, characterized in that, The doping concentration of the P-type Ge region (3) is 1×10⁻⁶. 18 -1×10 20 cm -3 .

6. The PIN photodetector based on Si-epitaxy Ge according to claim 1, characterized in that, The ion implantation depth of the P-type Ge region (3) is 50-200 nm.

7. The PIN photodetector based on Si-epitaxy Ge according to claim 1, characterized in that, The first metal electrode (4) and the second metal electrode (5) are made of gold, silver or aluminum.

8. A method for fabricating a PIN photodetector based on Ge epitaxial growth on Si, characterized in that, The method for fabricating a PIN photodetector based on Si epitaxial Ge, applicable to any one of claims 1-7, comprises: Step 1: Select an N-type Si substrate; Step 2: An intrinsic Ge epitaxial layer is formed on the upper surface of the N-type Si substrate using an epitaxial process; Step 3: Perform ion implantation or diffusion on the upper surface of the intrinsic Ge epitaxial layer to form a P-type Ge region; Step 4: Electrode deposition is performed on the upper surface of the P-type Ge region and the lower surface of the N-type Si substrate to form a first metal electrode and a second metal electrode.

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