FPGA-based spin lock software semi-physical simulation test method

Abstract

The invention relates to a spin lock software semi-physical simulation test method based on an FPGA (Field Programmable Gate Array), and solves the technical problems that the existing spin lock software test method occupies design time, influences the integrity of tested software or has a galloping risk. The method is applied to simulation debugging and fault testing of spin lock software in a three-self-inertia combination product, an equivalent mathematical model of a spin lock mechanism is achieved through an FPGA, relevant parameters of the mathematical model in the FPGA are modified through external key operation, various data information of a locking motor and a frame motor is simulated, and a simulation testing platform is constructed; the simulation test platform can flexibly inject data and simulate the real state of the spin lock software in a whole machine real object, including a normal working condition and an abnormal working condition, so that the test work of the spin lock software is efficiently and reliably completed.

Description

TECHNICAL FIELD

[0001] The present application relates to spin-locked software testing technology, in particular to a spin-locked software semi-physical simulation testing method based on FPGA. BACKGROUND

[0002] The inertial measurement unit is the core technology of modern high-precision navigation, guidance and control, and has strategic significance for space development and industrial progress. With the development of technology, the intelligent three-self inertial measurement unit emerges as the times require. The spin-locked system is an important part of the three-self inertial measurement unit. In the research and development process, the spin-locked system as the only servo device, its testing work is very critical, which will directly affect the function and delivery schedule of the whole inertial measurement unit product.

[0003] Generally, the testing of the spin-locked software needs to be completed in the inertial measurement unit real machine environment, and the function testing of the self-checking instruction, the locking instruction, the unlocking instruction and the rotation instruction. By inserting test code in the running process of the spin-locked software, or connecting the simulator to inject abnormal data online, the abnormal branch is constructed to realize the simulation of the inertial measurement unit working in abnormal conditions, and the correctness and effectiveness of the fault handling mechanism of the spin-locked software are verified in combination with the normal conditions.

[0004] However, the function testing in the above method needs to occupy a large amount of inertial measurement unit development time, which affects the delivery schedule of the whole machine. Inserting test code in the software running process not only needs to spend the design time of the test personnel, but also affects the integrity of the software being tested. And by connecting the simulator to inject abnormal data online, there are risks of online debugging of the simulator and imperfect design of the fault handling mechanism. SUMMARY

[0005] In order to solve the technical problems of occupying design time, affecting the integrity of the software being tested, or existing the risk of flying car in the existing testing method of the spin-locked software, the present application provides a spin-locked software semi-physical simulation testing method based on FPGA.

[0006] In order to achieve the above purpose, the present application adopts the following technical scheme: A spin-locked software semi-physical simulation testing method based on FPGA, which is characterized by comprising the following steps: S0, a semi-physical simulation testing platform is built; The semi-physical simulation testing platform comprises a DSP development board, an FPGA development board connected with the DSP development board, and a coarse adjustment key, a fine adjustment key and a switch group connected with the FPGA development board respectively; S1, running the spin-locked software program in the DSP development board; running the equivalent mathematical model of the spin-locked mechanism in the FPGA development board, which is used to simulate the real physical environment corresponding to the spin-locked software program; The equivalent mathematical model comprises a locking motor model and a frame motor model. S2, communication between the DSP and the FPGA is established, used for transmitting a locking motor enable signal, a locking stroke feedback value, a locking current feedback value, a frame motor enable signal, a frame angle feedback value and a frame current feedback value; communication between the DSP development board and the host computer is established, used for transmitting an instruction of the host computer and a response of the DSP development board; S3, the DSP development board and the FPGA development board are powered on, and at this time, the DSP development board and the FPGA development board work in an initial state; S4, according to a selected adjustment mode, the state of the switch group is changed; The adjustment mode comprises a locking stroke adjustment mode, a locking current adjustment mode, a frame current adjustment mode and a frame angle adjustment mode. S5, based on the adjustment mode, parameters of the equivalent mathematical model are adjusted through the coarse adjustment key and the fine adjustment key to simulate different working conditions of the spinlock mechanism; S6, under different working conditions, the host computer sends a test instruction to the DSP development board, and the DSP development board feeds back response information to the host computer according to a test result; S7, the host computer receives the response information, and judges whether a working state of the spinlock software program meets an expectation, if not, the DSP development board and the FPGA development board are powered off, the spinlock software program is modified, and the modified spinlock software program is run in the DSP development board again, and step S3 is executed; otherwise, step S8 is executed. S8, the adjustment mode is changed, and step S4 is returned until all adjustment modes are tested, the DSP development board and the FPGA development board are powered off, and the semi-physical simulation test is completed.

[0007] Further, in step S0, the DSP development board and the FPGA development board are respectively connected with corresponding DSP reset keys and FPGA reset keys; The switch group comprises a locking switch, a steering switching switch, a frame switching switch, a locking selection switch and a rotation selection switch.

[0008] Further, in step S2, the DSP development board establishes communication with the host computer through a serial communication interface; The DSP development board establishes communication with the FPGA development board through an XINTF interface; The FPGA development board collects signals of the coarse adjustment key, the fine adjustment key and the switch group through an I / O interface; In step S5, the parameters of the equivalent mathematical model comprise a feedback current digital quantity of the locking motor, a feedback current digital quantity of the frame motor, an infrared pulse digital quantity and a rotation target angle.

[0009] Further, step S4 is specifically: When the locking current adjustment mode is selected, the current parameter of the locking motor model needs to be adjusted, the locking switch is turned on, and the locking selection switch is turned on. At this time, the feedback current digital quantity can be adjusted; When the locking stroke adjustment mode is selected, the stroke parameter of the locking motor model needs to be adjusted, the locking switch is turned on, and the locking selection switch is turned off. At this time, the infrared pulse digital quantity can be adjusted; By changing the steering switch, the locking rotation of the locking motor or the unlocking rotation of the locking motor is selected; When the frame current adjustment mode is selected, the current parameter of the frame motor model needs to be adjusted, the locking switch is turned off, and the rotation position selection switch is turned on. At this time, the feedback current digital quantity can be adjusted; By changing the frame switch, the outer frame motor or the inner frame motor is selected; By changing the steering switch, the forward rotation or the reverse rotation is selected; When the frame angle adjustment mode is selected, the angle parameter of the frame motor model needs to be adjusted, the locking switch is turned off, and the rotation position selection switch is turned off. At this time, the rotation position target angle can be adjusted; By changing the frame switch, the outer frame motor or the inner frame motor is selected; By changing the steering switch, the forward rotation or the reverse rotation is selected.

[0010] Further, in step S5, the method of adjusting includes: By long pressing the coarse adjustment key, the parameter is reset to the maximum value; By short pressing the coarse adjustment key, the parameter is coarsely adjusted; By short pressing the fine adjustment key, the parameter is finely adjusted; In step S5, the coarse adjustment value range and the fine adjustment value range of the infrared pulse digital quantity are 5% to 10% of the maximum value and 0.5% to 1% of the maximum value, respectively; The coarse adjustment value range and the fine adjustment value range of the feedback current digital quantity are 1% to 5% of the maximum value and 0.1% to 0.5% of the maximum value, respectively; The maximum value of the rotation position target angle is 360°; The coarse adjustment value range and the fine adjustment value range of the rotation position target angle are 60° to 120° and 1° to 5°, respectively.

[0011] Further, in step S5, the maximum value, the coarse adjustment value, and the fine adjustment value of the infrared pulse digital quantity are 160, 10, and 1, respectively; The maximum value, the coarse adjustment value, and the fine adjustment value of the feedback current digital quantity are 4096, 100, and 10, respectively; The coarse adjustment value and the fine adjustment value of the rotation target angle are 90 degrees and 1 degree respectively.

[0012] Further, the step S6 specifically comprises: S6-1, under different working conditions, sending a test instruction to the DSP development board through the upper computer, executing the test instruction by the DSP development board, and sending a locking motor enable signal or a frame motor enable signal to the FPGA development board; S6-2, calculating the locking current feedback value, the locking stroke feedback value, the frame current feedback value and the frame angle feedback value corresponding to the test instruction based on the equivalent mathematical model after adjustment of the FPGA development board, and sending them to the DSP development board; S6-3, calculating and analyzing the test results according to the locking current feedback value, the locking stroke feedback value, the frame current feedback value and the frame angle feedback value by the locking software program, and sending the response information to the upper computer.

[0013] Further, in the step S7, the test instruction comprises a self-checking instruction, an unlocking instruction, a locking instruction and a rotation instruction. The step S8 specifically comprises: calculating the corresponding locking current feedback value based on the feedback current digital quantity of the locking motor according to the parameters of the equivalent mathematical model in the FPGA development board; calculating the corresponding frame angle feedback value based on the feedback current digital quantity of the frame motor; calculating the corresponding locking stroke feedback value based on the infrared pulse digital quantity; and calculating the corresponding frame angle feedback value based on the rotation target angle. The locking current feedback value, the locking stroke feedback value, the frame current feedback value and the frame angle feedback value are sent to the DSP development board.

[0014] Further, in the step S8, the changing of the adjustment mode specifically comprises: According to the next parameter adjustment requirement, the DSP development board and the FPGA development board are reset by long pressing the DSP reset key and the FPGA reset key respectively, or the DSP development board and the FPGA development board are re-powered, and then the step S4 is executed.

[0015] Further, in the step S0, the DSP development board adopts a TMS320F28335 development board; and the FPGA development board adopts an XC6SLX25-3FTG256I development board.

[0016] Compared with the prior art, the present application has the following beneficial technical effects: 1. This invention provides a semi-physical simulation testing method for spinlock software based on FPGA. It uses an FPGA to simulate the real physical environment corresponding to the spinlock software program, enabling simulation debugging and fault testing of spinlock software in three-auto-inertial combination products. Without causing any damage to the physical machine, it utilizes an FPGA to implement an equivalent mathematical model of the spinlock mechanism. By modifying relevant parameters of the equivalent mathematical model, it simulates information such as the frame position, locking mechanism stroke, and feedback current values ​​of each motor, completing real-time simulation and fault injection for different operating conditions of the spinlock software. This achieves a safe, convenient, flexible, and efficient simulation testing environment, significantly shortening the spinlock software testing cycle and effectively improving the safety of abnormal branch testing of the spinlock software.

[0017] 2. This invention provides a hardware-in-the-loop (HIL) software semi-physical simulation testing method based on FPGA. It fully considers the actual needs of HIL software testing. Through the HIL software semi-physical simulation testing platform and the settings of switch groups, coarse adjustment keys, and fine adjustment keys, it realizes data information and fault injection under different working modes of the HIL mechanism, thereby achieving safe and efficient testing of the HIL software. After the HIL software semi-physical simulation testing platform is powered on, the test content of the HIL software can be selected via buttons, and data from the locking motor and frame motor in the HIL mechanism can be flexibly injected to conduct normal and abnormal tests under different working conditions. At the same time, it effectively improves the safety and reliability of HIL software testing, avoiding the risk of runaway due to imperfect fault handling mechanism design. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the system structure in an embodiment of the FPGA-based spinlock software semi-physical simulation test method of the present invention. Figure 2 This is a flowchart of an embodiment of the present invention; Figure 3 This is a program logic diagram of an embodiment of the present invention. Detailed Implementation

[0019] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] FPGA (Field-Programmable Gate Array) is a digital circuit developed based on logic devices such as PAL and GAL. As a highly flexible and powerful application-specific semi-custom circuit, it frequently appears in the field of application-specific integrated circuits (ASICs). Its main characteristics are that it can be programmed during use without needing to remove the chip and return it to the manufacturer for modification, and it can achieve different functions through rearrangement. Hardware-in-the-loop (HIL) simulation is a hardware simulation technique where some parts of the simulation system use actual physical objects, while other parts are replaced by corresponding mathematical models. In HIL simulation, real-time data exchange occurs between the physical components and the simulation model, simulating the actual state of the object under test in a real physical environment. This allows for testing the normal function and handling of abnormal states of the actual physical object within a simulation environment.

[0021] This invention is applied to the simulation debugging and fault testing of spinlock software in three-self inertial combination products. It realizes the equivalent mathematical model of the spinlock mechanism through FPGA, and modifies the relevant parameters of the mathematical model in the FPGA through external button operation, simulating various data information of the locking motor and frame motor, and constructing a simulation test platform. The simulation test platform can flexibly inject data to simulate the real state of the spinlock software under the whole machine, including normal working conditions and abnormal working conditions, thereby efficiently and reliably completing the testing of the spinlock software.

[0022] This invention provides a hardware-in-the-loop simulation testing method for spinlock software based on FPGA, such as... Figure 2 As shown, it includes the following steps: S0, Reference Figure 1 Build a hardware-in-the-loop simulation testing platform; The hardware-in-the-loop simulation test platform includes a DSP development board, an FPGA development board connected to the DSP development board, and coarse adjustment keys, fine adjustment keys, and a switch group connected to the FPGA development board respectively. The DSP and FPGA development boards are also connected to corresponding DSP and FPGA reset keys, respectively. The switch group includes a locking switch, a direction switching switch, a frame switching switch, a locking selection switch, and a rotation selection switch.

[0023] In this embodiment, the DSP development board uses the TMS320F28335 development board; the FPGA development board uses the XC6SLX25-3FTG256I development board.

[0024] S1, run the spinlock software program on the DSP development board, and test the logic reference. Figure 3 The equivalent mathematical model of the rotary lock mechanism is run on the FPGA development board to simulate the real physical environment corresponding to the rotary lock software program. The equivalent mathematical model includes the locking motor model and the frame motor model (including the inner frame motor and the outer frame motor).

[0025] S2 establishes communication between the DSP and FPGA to transmit the locking motor enable signal, locking stroke feedback value, locking current feedback value, frame motor enable signal, frame angle feedback value, and frame current feedback value; and establishes communication between the DSP development board and the host computer to transmit the host computer's instructions and the DSP development board's responses.

[0026] The DSP development board establishes communication with the host computer through a serial communication interface; the DSP development board establishes communication with the FPGA development board through the XINTF interface; the FPGA development board acquires signals from the coarse adjustment key, fine adjustment key, and switch group through the I / O interface.

[0027] S3, power on the DSP development board and FPGA development board. At this time, the DSP development board and FPGA development board are working in the initial state.

[0028] S4, change the state of the switch group according to the selected adjustment mode of the FPGA development board; The adjustment modes include locking stroke adjustment mode, locking current adjustment mode, frame current adjustment mode, and frame angle adjustment mode.

[0029] When the locking current adjustment mode is selected, the current parameters of the locking motor model need to be adjusted, the locking switch needs to be turned on, and the locking selection switch needs to be turned on. At this time, the digital value of the feedback current can be adjusted. When the locking stroke adjustment mode is selected, the stroke parameters of the locking motor model need to be adjusted, the locking switch is turned on, and the locking selection switch is turned off. At this time, the digital value of the infrared pulse can be adjusted. By changing the direction switching switch, you can select the locking motor to lock or the locking motor to unlock. When the frame current adjustment mode is selected, the current parameters of the frame motor model need to be adjusted, the locking switch is turned off, and the index selection switch is turned on. At this time, the digital value of the feedback current can be adjusted. By changing the frame switching switch, you can select to simulate the outer frame motor or the inner frame motor. By changing the direction switching switch, you can select to simulate forward rotation or reverse rotation. When selecting the frame angle adjustment mode, you need to adjust the angle parameters of the frame motor model, turn off the locking switch, and turn off the indexing selection switch. At this time, the indexing target angle can be adjusted. By changing the frame switching switch, you can select to simulate the outer frame motor or the inner frame motor. By changing the direction switching switch, you can select to simulate forward rotation or reverse rotation.

[0030] S5, based on the adjustment mode, allows for the adjustment of the parameters of the equivalent mathematical model via coarse and fine adjustment keys to simulate different working conditions of the rotary lock mechanism; the parameters of the equivalent mathematical model include the digital feedback current of the locking motor, the digital feedback current of the frame motor, the digital infrared pulse, and the rotation target angle (digital unit converted by the external circuit).

[0031] The selectable adjustment methods are: long press the coarse adjustment button to reset the parameter to its maximum value; short press the coarse adjustment button to coarsely adjust the parameter; short press the fine adjustment button to finely adjust the parameter. Based on the parameters of the DSP and FPGA development boards used in this embodiment, the maximum value, coarse adjustment value, and fine adjustment value of the infrared pulse digital quantity are 160, 10, and 1, respectively; the maximum value, coarse adjustment value, and fine adjustment value of the feedback current digital quantity are 4096, 100, and 10, respectively; and the maximum value, coarse adjustment value, and fine adjustment value of the rotation target angle are 360°, 90°, and 1°, respectively. These values ​​are selected to satisfy both the minimum envelope of the given values ​​for different working conditions and the speed requirements of actual operation.

[0032] S6 sends test commands to the DSP development board via the host computer under different operating conditions, and the DSP development board sends response information back to the host computer based on the test results.

[0033] S6-1 sends test commands to the DSP development board via the host computer under different operating conditions. The DSP development board executes the test commands and sends a locking motor enable signal or a frame motor enable signal to the FPGA development board. The test commands include self-test commands, unlock commands, locking commands, and rotation commands.

[0034] S6-2, the FPGA development board calculates the corresponding locking current feedback value based on the digital value of the locking motor's feedback current, the corresponding frame angle feedback value based on the digital value of the frame motor's feedback current, the corresponding locking stroke feedback value based on the digital value of the infrared pulse, and the corresponding frame angle feedback value based on the indexing target angle, according to the parameters adjusted by the equivalent mathematical model. The locking current feedback value, locking stroke feedback value, frame current feedback value, and frame angle feedback value are then sent to the DSP development board.

[0035] S6-3, the rotary lock software program calculates and analyzes the test results based on the locking current feedback value, locking stroke feedback value, frame current feedback value, and frame angle feedback value, and sends response information to the host computer.

[0036] S7. Receive the response information through the host computer and determine whether the working status (including normal and abnormal working conditions) of the spinlock software program meets expectations. If it does not meet expectations, power off the DSP development board and FPGA development board, correct the spinlock software program, and rerun the corrected spinlock software program on the DSP development board, and execute step S3; otherwise, execute step S8.

[0037] S8. According to the next parameter adjustment needs, press and hold the DSP reset button to reset the DSP development board, press and hold the FPGA reset button to reset the FPGA development board, or power on the DSP development board and FPGA development board again, and then execute step S4 until all adjustment modes are tested. Then power off the DSP development board and FPGA development board to complete the semi-physical simulation test.

[0038] In this embodiment, the injection of locking motor test parameters includes the injection of locking current feedback value and locking stroke feedback value (infrared pulse value), and the injection of frame motor test parameters includes the injection of frame current feedback value and frame angle feedback value. The test procedure is as follows: a) Locking current feedback value injection test procedure 1. After powering on the hardware-in-the-loop test platform, close the locking switch and locking selection switch. At this time, the locking current feedback value can be adjusted to enter the locking current adjustment mode.

[0039] 2. If you need to set the feedback current digital value to the maximum, press and hold the coarse adjustment button for more than 30 seconds to set it to 4096.

[0040] 3. If you need to coarsely adjust the digital value of the feedback current, click the coarse adjustment button. Each click increases the digital value of the feedback current by 100. You can click it multiple times.

[0041] IV. If you need to fine-tune the digital value of the feedback current, click the fine adjustment button. Each click increases the digital value of the feedback current by 10. You can click it multiple times.

[0042] 5. If other parameter adjustments are required, proceed as follows: Press and hold the FPGA reset button for more than 30 seconds to reload the FPGA; press and hold the DSP reset button for more than 30 seconds to reload the DSP. Then adjust the parameters accordingly.

[0043] 6. The host computer sends the test command, and the rotary lock software responds to the host computer with test process data and test results.

[0044] 7. Analyze and determine, based on the data received by the host computer, whether the locking current feedback value of the locking motor is correct when different digital feedback current values ​​are injected.

[0045] b) Locking stroke feedback value injection test procedure 1. After powering on the hardware-in-the-loop test platform, close the locking switch and disconnect the locking selection. At this time, the locking stroke feedback value can be adjusted to enter the locking stroke adjustment mode.

[0046] 2. Select the forward or reverse rotation of the locking motor by using the direction switching switch to simulate the locking motor's locking rotation or the locking motor's unlocking rotation.

[0047] 3. If you need to set the infrared pulse digital value to the maximum, press and hold the coarse adjustment button for more than 30 seconds to set it to 160.

[0048] IV. If you need to coarsely adjust the digital value of the infrared pulse, click the coarse adjustment button. Each click increases the digital value of the feedback current by 10. You can click it multiple times.

[0049] 5. If you need to fine-tune the digital value of the infrared pulse, click the fine adjustment button. Each click increases the digital value of the feedback current by 1. You can click it multiple times.

[0050] VI. If other parameter adjustments are required, proceed as follows: Press and hold the FPGA reset button for more than 30 seconds to reload the FPGA; press and hold the DSP reset button for more than 30 seconds to reload the DSP. Then adjust the parameters accordingly.

[0051] 7. The host computer sends the test command, and the rotary lock software responds to the host computer with test process data and test results.

[0052] 8. Analyze and determine, based on the data received by the host computer, whether the locking stroke feedback value of the locking motor is correct when different digital infrared pulse values ​​are injected.

[0053] c) Frame current feedback value injection test procedure 1. After powering on the hardware-in-the-loop test platform, disconnect the locking switch and use the frame switch to select the inner frame motor or the outer frame motor for parameter adjustment.

[0054] 2. Select the forward or reverse rotation of the frame motor by using the direction switching switch to simulate forward or reverse rotation conditions.

[0055] 3. Close the indexing selector switch. At this time, the frame current feedback value can be adjusted to enter the frame current adjustment mode.

[0056] IV. If you need to set the feedback current digital value to the maximum, press and hold the coarse adjustment button for more than 30 seconds to set it to 4096.

[0057] 5. If you need to coarsely adjust the digital value of the feedback current, click the coarse adjustment button. Each click increases the digital value of the feedback current by 100. You can click it multiple times.

[0058] 6. If you need to fine-tune the digital value of the feedback current, click the fine adjustment button. Each click increases the digital value of the feedback current by 10, and you can click it multiple times.

[0059] 7. If other parameter adjustments are required, proceed as follows: Press and hold the FPGA reset button for more than 30 seconds to reload the FPGA; press and hold the DSP reset button for more than 30 seconds to reload the DSP. Then adjust the parameters accordingly.

[0060] 8. The host computer sends test commands, and the rotary lock software responds to the host computer with test process data and test results.

[0061] 9. Analyze and determine, based on the data received by the host computer, whether the frame current feedback value of the frame motor is correct when different digital feedback current values ​​are injected.

[0062] d) Framework Angle Feedback Value Injection Test Process 1. After powering on the hardware-in-the-loop test platform, disconnect the locking switch and use the frame switch to select the inner frame motor or the outer frame motor for parameter adjustment.

[0063] 2. Select the forward or reverse rotation of the frame motor by using the direction switching switch to simulate forward or reverse rotation conditions.

[0064] 3. Turn off the indexing selector switch. At this time, you can adjust the frame angle feedback value and enter the frame angle adjustment mode.

[0065] IV. If you need to set the target rotation angle to the maximum, press and hold the coarse adjustment button for more than 30 seconds to set it to 360 (degrees).

[0066] 5. If coarse adjustment of the target rotation angle is required, click the coarse adjustment button. Each click increases the digital value of the feedback current by 90 degrees. Multiple clicks are allowed.

[0067] 6. If fine adjustment of the target rotation angle is required, click the fine adjustment button. Each click increases the digital value of the feedback current by 1 degree. Multiple clicks are allowed.

[0068] 7. If other parameter adjustments are required, proceed as follows: Press and hold the FPGA reset button for more than 30 seconds to reload the FPGA; press and hold the DSP reset button for more than 30 seconds to reload the DSP. Then adjust the parameters accordingly.

[0069] 8. The host computer sends test commands, and the rotary lock software responds to the host computer with test process data and test results.

[0070] 9. Analyze and judge the data received by the host computer to determine whether the frame angle feedback value of the frame motor is correct when different rotation target angles are injected.

[0071] Taking the infrared pulse monitoring test during the unlocking process of the rotary lock mechanism as a specific example, the usage method of the above procedure b is as follows: 1. Normal operating conditions After the hardware-in-the-loop simulation test platform is powered on, the locking switch is closed, and the locking motor test parameter injection process begins. The locking selection switch is turned on, and the simulated locking motor unlocking rotation is selected. The infrared pulse digital quantity is adjusted and set within the normal range. The host computer sends an unlocking command to the DSP development board according to the rotary lock software communication protocol. After the rotary lock software acquires the infrared pulse digital quantity injected by the FPGA, it determines whether the locking motor's movement stroke is correct based on the feedback value of the locking stroke, thus confirming the correctness of the rotary lock software processing. Unlocking tests can be performed multiple times using the adjusted infrared pulse digital quantity injected by the FPGA, based on the theoretical value of the infrared pulse during the actual unlocking process of the rotary lock mechanism, to confirm the correctness of the rotary lock software processing.

[0072] 2. Abnormal operating conditions After the hardware-in-the-loop simulation test platform is powered on, the locking switch is closed, and the locking motor test parameter injection process begins. The locking selection switch is turned on, and the simulated locking motor unlocking rotation is selected. The infrared pulse values ​​outside the normal range are adjusted, i.e., typical and boundary abnormal values. The host computer sends an unlocking command to the DSP development board according to the rotary lock software communication protocol. After the rotary lock software acquires the digital infrared pulses injected by the FPGA, it determines whether the locking motor's movement stroke is abnormal based on the data, thus confirming the correctness and reliability of the rotary lock software's handling of abnormal situations. Then, abnormal situations during the actual unlocking process of the rotary lock mechanism are covered, and the digital infrared pulses are adjusted to perform unlocking tests, covering all abnormal branches handled by the rotary lock software, confirming the correctness of the rotary lock software's abnormal handling process.

[0073] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present invention should be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A hardware-in-the-loop simulation test method for spinlock software based on FPGA, characterized in that, Includes the following steps: S0, Build a hardware-in-the-loop simulation test platform; the hardware-in-the-loop simulation test platform includes a DSP development board, an FPGA development board connected to the DSP development board, and coarse adjustment keys, fine adjustment keys and switch groups respectively connected to the FPGA development board; S1, Run the rotary lock software program on the DSP development board; Run the equivalent mathematical model of the rotary lock mechanism on the FPGA development board to simulate the real physical environment corresponding to the rotary lock software program; The equivalent mathematical model includes a locking motor model and a frame motor model; S2 establishes communication between the DSP and FPGA to transmit the locking motor enable signal, locking stroke feedback value, locking current feedback value, frame motor enable signal, frame angle feedback value, and frame current feedback value; and establishes communication between the DSP development board and the host computer to transmit the host computer's instructions and the DSP development board's responses. S3, Power on the DSP development board and FPGA development board. At this time, the DSP development board and FPGA development board are working in the initial state. S4, change the state of the switch group according to the selected adjustment mode; the adjustment modes include locking stroke adjustment mode, locking current adjustment mode, frame current adjustment mode, and frame angle adjustment mode; S5, based on the adjustment mode, uses coarse and fine adjustment keys to adjust the parameters of the equivalent mathematical model to simulate different working conditions of the rotary lock mechanism. S6 sends test commands to the DSP development board via the host computer under different operating conditions, and the DSP development board sends response information back to the host computer based on the test results; S7. Receive the response information through the host computer and determine whether the working status of the spinlock software program meets the expectations. If it does not meet the expectations, power off the DSP development board and FPGA development board, correct the spinlock software program, and rerun the corrected spinlock software program on the DSP development board, and execute step S3. Otherwise, proceed to step S8; S8, change the adjustment mode, return to step S4, and continue until all adjustment modes have been tested. Then, power off the DSP development board and FPGA development board to complete the hardware-in-the-loop simulation test.

2. The FPGA-based semi-physical simulation testing method for spinlock software, as described in claim 1, is characterized in that: In step S0, the DSP development board and the FPGA development board are also respectively connected to corresponding DSP reset buttons and FPGA reset buttons; The switch group includes a locking switch, a direction switching switch, a frame switching switch, a locking selection switch, and a rotation selection switch.

3. The FPGA-based semi-physical simulation testing method for spinlock software, as described in claim 2, is characterized in that: In step S2, the DSP development board establishes communication with the host computer through a serial communication interface; The DSP development board establishes communication with the FPGA development board through the XINTF interface; The FPGA development board acquires signals from the coarse adjustment key, fine adjustment key, and switch group through the I / O interface; In step S5, the parameters of the equivalent mathematical model include the digital value of the feedback current of the locking motor, the digital value of the feedback current of the frame motor, the digital value of the infrared pulse, and the rotation target angle.

4. The FPGA-based hardware-in-the-loop simulation test method for spinlocks according to claim 3, characterized in that, Step S4 is as follows: When the locking current adjustment mode is selected, the current parameters of the locking motor model need to be adjusted, the locking switch needs to be turned on, and the locking selection switch needs to be turned on. At this time, the digital value of the feedback current can be adjusted. When the locking stroke adjustment mode is selected, the stroke parameters of the locking motor model need to be adjusted, the locking switch is turned on, and the locking selection switch is turned off. At this time, the digital value of the infrared pulse can be adjusted. By changing the direction switching switch, you can select the locking motor to lock or the locking motor to unlock. When the frame current adjustment mode is selected, the current parameters of the frame motor model need to be adjusted, the locking switch is turned off, and the index selection switch is turned on. At this time, the digital value of the feedback current can be adjusted. By changing the frame switching switch, you can select to simulate the outer frame motor or the inner frame motor. By changing the direction switching switch, you can select to simulate forward rotation or reverse rotation. When selecting the frame angle adjustment mode, you need to adjust the angle parameters of the frame motor model, turn off the locking switch, and turn off the indexing selection switch. At this time, the indexing target angle can be adjusted. By changing the frame switching switch, you can select to simulate the outer frame motor or the inner frame motor. By changing the direction switching switch, you can select to simulate forward rotation or reverse rotation.

5. The FPGA-based semi-physical simulation test method for spinlock software according to claim 4, characterized in that: In step S5, the adjustment method includes: resetting the parameter to its maximum value by long-pressing the coarse adjustment key; coarsely adjusting the parameter by short-pressing the coarse adjustment key; and finely adjusting the parameter by short-pressing the fine adjustment key. In step S5, the coarse adjustment range and fine adjustment range of the infrared pulse digital value are 5%~10% and 0.5%~1% of the maximum value, respectively. The coarse adjustment range and fine adjustment range of the digital feedback current are 1% to 5% and 0.1% to 0.5% of the maximum value, respectively. The maximum value of the target rotation angle is 360°; The coarse adjustment range and fine adjustment range of the target rotation angle are 60°~120° and 1°~5°, respectively.

6. The FPGA-based hardware-in-the-loop simulation test method for spinlocks according to claim 5, characterized in that: In step S5, the maximum value, coarse adjustment value, and fine adjustment value of the infrared pulse digital quantity are 160, 10, and 1, respectively; The maximum value, coarse adjustment value, and fine adjustment value of the feedback current digital quantity are 4096, 100, and 10, respectively. The coarse adjustment value and the fine adjustment value of the target rotation angle are 90° and 1°, respectively.

7. The FPGA-based hardware-in-the-loop simulation test method for spinlocks according to claim 6, characterized in that, Step S6 is as follows: S6-1 sends test commands to the DSP development board via the host computer under different working conditions. The DSP development board executes the test commands and sends a locking motor enable signal or a frame motor enable signal to the FPGA development board. S6-2, the FPGA development board calculates the locking current feedback value, locking stroke feedback value, frame current feedback value and frame angle feedback value of the corresponding test command based on the equivalent mathematical model after parameter adjustment, and sends them to the DSP development board. S6-3, the rotary lock software program calculates and analyzes the test results based on the locking current feedback value, locking stroke feedback value, frame current feedback value, and frame angle feedback value, and sends response information to the host computer.

8. The FPGA-based hardware-in-the-loop simulation test method for spinlocks according to claim 7, characterized in that: In step S7, the test instructions include self-test instructions, unlock instructions, lock instructions, and rotation instructions; Step S8 specifically involves: calculating the corresponding locking current feedback value based on the digital value of the locking motor's feedback current, according to the parameters of the equivalent mathematical model on the FPGA development board. The corresponding frame angle feedback value is calculated based on the digital value of the feedback current of the frame motor. The corresponding locking stroke feedback value is calculated based on the digital value of the infrared pulse; The corresponding frame angle feedback value is calculated based on the target rotation angle; The locking current feedback value, locking stroke feedback value, frame current feedback value, and frame angle feedback value are sent to the DSP development board.

9. The FPGA-based hardware-in-the-loop simulation test method for spinlocks according to claim 8, characterized in that, The change of adjustment mode in step S8 specifically refers to: Depending on the next parameter adjustment requirements, press and hold the DSP reset button to reset the DSP development board, press and hold the FPGA reset button to reset the FPGA development board, or power on both the DSP and FPGA development boards again, and then execute step S4.

10. The FPGA-based semi-physical simulation testing method for spinlock software as described in claim 9, characterized in that: In step S0, the DSP development board uses the TMS320F28335 development board; the FPGA development board uses the XC6SLX25-3FTG256I development board.

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