Data transmission device, method, chip, system, storage medium and program product

Abstract

The application relates to a data transmission device, method, chip, system, storage medium and program product. The device comprises a routing module, a SOC module and a DMA module. The routing module is used for receiving and analyzing a notification sent by a host, obtaining notification information, and routing the notification information to the SOC module. The SOC module is used for generating a first command descriptor according to the notification information. The DMA module is used for reading the first command descriptor, reading target data from the host according to the first command descriptor, and writing the target data into the SOC module according to the first command descriptor. The SOC module is further used for generating a second command descriptor in response to the target data being written into the SOC module. The DMA module is further used for reading the second command descriptor and sending the second command descriptor to the host to notify the host that the target data has been written into the first cache unit. The device can improve the flexibility of the data transmission device.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a data transmission device, method, chip, system, storage medium, and program product. Background Technology

[0002] In cloud computing virtualization technology, to allow multiple guest operating systems to run independently of the host operating system on the same hardware, a virtualization layer, the Virtual Machine Monitor (VMM), is added. Machine Emulator and Virtualizer (QEMU), as a VMM, provides a fully virtualized environment. In a fully virtualized environment, the guest operating system is unaware that it is a virtual machine and does not require modification. However, because all operations in a fully virtualized environment require software emulation, frequent traps and escapes occur during device access, leading to serious performance issues. Therefore, semi-virtualized Virtual I / O Device (VIRTIO) technology emerged.

[0003] Among related technologies, VIRTIO is a general-purpose paravirtualization framework. Virtual Machines (VMMs) use VIRTIO to emulate a series of virtualized devices. To improve performance, VIRTIO technology has continuously evolved, leading to hardware offloading techniques for the VIRTIO data plane. This means the data plane is implemented by hardware logic, allowing direct communication between the virtual machine and the underlying hardware. Specifically, the hardware part uses Single Root I / O Virtualization (SRIOV) technology to virtualize a single PCIe controller into multiple Virtual Function (VF) devices. Each VF device utilizes hardware logic to implement the functionality of the VIRTIO backend device, and these VF devices are then transparently transmitted to the guest virtual machine.

[0004] However, for VIRTIO back-end devices, although the data plane can achieve high performance after being implemented by hardware logic, the logic behavior cannot be changed arbitrarily once it is designed, resulting in poor flexibility of VIRTIO back-end devices. Summary of the Invention

[0005] Therefore, it is necessary to provide a data transmission device, method, chip, system, storage medium, and program product that can improve the flexibility of data transmission equipment in response to the above-mentioned technical problems.

[0006] In a first aspect, this application provides a data transmission device that communicates with a host, the device comprising:

[0007] The routing module is used to receive and parse the notification sent by the host, obtain the notification information, and route the notification information to the SOC module;

[0008] The SOC module is used to generate a first command descriptor based on the notification information;

[0009] The DMA module is used to read the first command descriptor, read target data from the host according to the first command descriptor, and write the target data into the SOC module according to the first command descriptor.

[0010] The SOC module is also configured to generate a second command descriptor in response to the target data being written to the SOC module;

[0011] The DMA module is also used to read the second command descriptor and send the second command descriptor to the host to notify the host that the target data has been written into the SOC module.

[0012] In one embodiment, the notification information includes the device identifier of the target device, the data transmission device further includes a VIRTIO backend hardware device and an IMU, and the routing module is specifically used for:

[0013] When the device identifier is a first preset value, the notification information is routed to the SOC module according to the routing table; when the device identifier is a second preset value, the notification information is routed to the VIRTIO backend hardware device according to the routing table; when the device identifier is a third preset value, the notification information is routed to the IMU according to the routing table.

[0014] In one embodiment, the DMA module is further configured to generate a third command descriptor after the target data is written to the SOC module;

[0015] The SOC module is also used to read and parse the third command descriptor, release the corresponding cache space according to the parsing result, and generate the second command descriptor.

[0016] In one embodiment, the SOC module includes a first cache unit, a third cache unit, and a target data cache unit.

[0017] The first command descriptor includes at least the following information: the command identifier corresponding to the first command descriptor, the host memory address, the host memory length, the memory address of the target data cache unit, and the memory length of the target data cache unit;

[0018] The DMA module is further configured to: read the first command descriptor from the first cache unit; read descriptor table information based on the first command descriptor; read the target data from the host based on the descriptor table information; write the target data into the target data cache unit; generate a third command descriptor and write the third command descriptor into the third cache unit.

[0019] In one embodiment, the SOC module includes a notification information receiving unit, a first record table cache unit, a second record table cache unit, and a VBE unit;

[0020] The first record table caching unit is used to cache the first record table, which caches the correspondence between the function identifier, queue identifier and global queue number corresponding to the notification information;

[0021] The second record table cache unit is used to cache the second record table, which caches the correspondence between the global queue number and the corresponding target index. The target index includes the available ring table index and / or the descriptor table index.

[0022] The notification information receiving unit is used to receive notification information routed to the SOC module, query the first record table to obtain the corresponding global queue number according to the function identifier and queue identifier in the notification information, and update the target index corresponding to the global queue number queried in the second record table with the target index in the notification information.

[0023] The VBE unit is used to poll the second record table in the second record table cache unit to obtain the target index and generate the first command descriptor based on the target index.

[0024] Secondly, this application also provides a data transmission method applied to a data transmission device, the data transmission device communicating with a host, the data transmission device including a routing module, a SOC module, and a DMA module, the method comprising:

[0025] The routing module receives and parses the notification sent by the host, obtains the notification information, and routes the notification information to the SOC module;

[0026] The SOC module generates a first command descriptor based on the notification information;

[0027] The DMA module reads the first command descriptor, reads target data from the host according to the first command descriptor, and writes the target data into the SOC module according to the first command descriptor.

[0028] The SOC module generates a second command descriptor in response to the target data being written to the SOC module.

[0029] The DMA module reads the second command descriptor and sends the second command descriptor to the host to notify the host that the target data has been written into the SOC module.

[0030] In one embodiment, the notification information includes the device identifier of the target device, and the data transmission device further includes a VIRTIO backend hardware device and an IMU. Routing the notification information to the SOC module includes:

[0031] When the device identifier is a first preset value, the routing module routes the notification information to the SOC module according to the routing table;

[0032] The method further includes: when the device identifier is a second preset value, the routing module routes the notification information to the VIRTIO backend hardware device according to the routing table;

[0033] When the device identifier is a third preset value, the routing module routes the notification information to the IMU according to the routing table.

[0034] In one embodiment, the method further includes:

[0035] After writing the target data into the SOC module, the DMA module generates a third command descriptor.

[0036] The SOC module reads and parses the third command descriptor, releases the corresponding cache space based on the parsing result, and generates the second command descriptor.

[0037] In one embodiment, the SOC module includes a first cache unit, a third cache unit, and a target data cache unit; the first command descriptor includes at least the following information: the command identifier corresponding to the first command descriptor, the host memory address, the host memory length, the memory address of the target data cache unit, and the memory length of the target data cache unit;

[0038] The method further includes:

[0039] The DMA module reads the first command descriptor from the first cache unit;

[0040] The DMA module reads the descriptor table information according to the first command descriptor;

[0041] The DMA module reads the target data from the host according to the descriptor table information; and writes the target data into the target data cache unit.

[0042] The DMA module generates a third command descriptor and writes the third command descriptor into a third cache unit.

[0043] In one embodiment, the SOC module includes a notification information receiving unit, a first record table caching unit, a second record table caching unit, and a VBE unit; the first record table caching unit is used to cache a first record table, which caches the correspondence between the function identifier, queue identifier, and global queue number corresponding to the notification information; the second record table caching unit is used to cache a second record table, which caches the correspondence between the global queue number and the corresponding target index, wherein the target index includes an available ring table index and / or a descriptor table index;

[0044] The method further includes: the notification information receiving unit receives notification information routed to the SOC module, queries the first record table to obtain the corresponding global queue number according to the function identifier and queue identifier in the notification information, and updates the target index corresponding to the global queue number queried in the second record table with the target index in the notification information;

[0045] The VBE unit polls the second record table in the second record table cache unit to obtain the target index, and generates the first command descriptor based on the target index.

[0046] Thirdly, this application also provides a chip, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the data transmission method of the first aspect described above.

[0047] Fourthly, this application also provides a VIRTIO system, including the chip and host described in the third aspect above.

[0048] Fifthly, this application also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the data transmission method of the first aspect.

[0049] Sixthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the data transmission method of the first aspect.

[0050] The aforementioned data transmission apparatus, method, chip, system, storage medium, and program product include a routing module for receiving and parsing notifications sent by the host, obtaining notification information, and routing the notification information to the SOC module; the SOC module for generating a first command descriptor based on the notification information; a DMA module for reading the first command descriptor, reading target data from the host based on the first command descriptor, and writing the target data to the SOC module based on the first command descriptor; the SOC module is also used to generate a second command descriptor in response to the target data being written to the SOC module; the DMA module is also used to read the second command descriptor and send the second command descriptor to the host to notify the host that the target data has been written to the first cache unit. The routing module routes the notification information sent by the host to the SOC module for processing, and the SOC module generates the first command descriptor, thereby enabling the DMA module to read the target data from the host and write it to the SOC module based on the first command descriptor. Since the software in the SOC module can emulate the functions of the VIRTIO backend device, the functions of the VIRTIO backend device emulated by the SOC module are editable and can be dynamically updated as the VIRTIO frontend driver and chip environment change. Because the data transmission device includes the aforementioned SOC module, the flexibility of the data transmission device is improved. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of a VIRTIO backend device implemented in related technologies;

[0053] Figure 2 This is a schematic diagram of another VIRTIO backend device provided in related technologies;

[0054] Figure 3 This is a schematic diagram illustrating the interaction between the VIRTIO front-end driver and the VIRTIO back-end hardware device in related technologies.

[0055] Figure 4 This is an application scenario diagram of a data transmission method provided in an embodiment of this application;

[0056] Figure 5 A flowchart illustrating a data transmission method provided in an embodiment of this application;

[0057] Figure 6A schematic diagram illustrating the principle of the data transmission method provided in the embodiments of this application;

[0058] Figure 7 An interactive schematic diagram of a DMA module provided in an embodiment of this application;

[0059] Figure 8 A flowchart illustrating another data transmission method provided in an embodiment of this application;

[0060] Figure 9 A structural block diagram of a data transmission device provided in an embodiment of this application;

[0061] Figure 10 This is an internal structural diagram of a computer device provided in an embodiment of this application. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0063] The relevant technologies will be explained below.

[0064] Figure 1 This is a schematic diagram of a VIRTIO backend device implemented in related technologies, such as... Figure 1 As shown, the VIRTIO framework includes the VIRTIO front-end driver, the VIRTIO back-end hardware devices, and virtualization queues. The VIRTIO front-end driver and the VIRTIO back-end hardware devices interact through virtualization queues.

[0065] The VIRTIO front-end driver is the driver for the VIRTIO emulated devices (e.g., VIRTIO network devices, VIRTIO disk devices, etc.) inside the virtual machine. The VIRTIO front-end driver receives user-space requests, encapsulates these requests according to the protocol to form send / receive requests, and sends them to the VIRTIO back-end hardware device. The VIRTIO back-end hardware device can be implemented in QEMU. It receives the send / receive requests sent by the VIRTIO front-end driver, parses them, completes the send / receive requests from the actual physical device, and notifies the VIRTIO front-end driver via an interrupt mechanism.

[0066] To improve performance, VIRTIO technology has evolved, leading to hardware offloading of the VIRTIO data plane. This means the data plane is implemented by hardware logic, allowing direct communication between the virtual machine and the underlying hardware. (Continue to refer to...) Figure 1Multiple virtual machines (VMs) run simultaneously on the server's host operating system. Inside each VM runs a guest operating system, which loads VIRTIO front-end drivers. A single VM can load multiple VIRTIO front-end drivers concurrently. The hardware uses SRIOV technology to virtualize a single PCIe controller into multiple VF devices. Each VF device implements the functionality of a VIRTIO back-end device using hardware logic, and these VF devices are then transparently passed to the guest VMs.

[0067] Figure 2 This is a schematic diagram of another implementation of the VIRTIO backend device provided in related technologies. For example... Figure 2 As shown, the Data Processing Unit (DPU) chip includes a routing module implemented with hardware logic and a VIRTIO backend hardware device. The VIRTIO backend hardware device is a VIRTIO backend hardware device implemented with hardware logic. The routing module includes a high-speed serial computer expansion bus interface (Peripheral Component Interconnect express, PCIe) logic unit, a receive (RX) logic unit, and a transmit (TX) logic unit. The PCIe logic unit is used to interconnect with the host via the PCIe bus and send and receive Transaction Layer Packet (TLP) messages. The RX logic unit is used to receive various requests from the host. The TX logic unit is used to initiate Direct Memory Access (DMA) read / write requests to the host memory.

[0068] The DPU chip also includes a Central Processing Unit (CPU) subsystem, which comprises a System-on-Chip (SOC) core, an Integrated Management Unit (IMU) core, and a Coherent Mesh Network (CMN) interconnect bus. Network offloading software provided by the DPU chip (e.g., Data Plane Development Kit (DPDK) and Open vSwitch (OVS)) runs on the SOC core, as does storage offloading software (e.g., Storage Performance Development Kit (SPDK)). The IMU core is responsible for the DPU chip's management and device emulation functions.

[0069] The following is based on Figure 2 Taking path 1 as an example, we will explain the control plane of the VIRTIO backend hardware device.

[0070] The control plane may include device topology simulation and device base address register (BAR) space simulation.

[0071] For example, in device topology simulation, the host can initiate a read access request to the Vendor ID register in the configuration space of the VIRTIO backend hardware device via the Enhanced Configuration Access Mechanism (ECAM). This read access request is forwarded to the DPU chip via the PCIe bus, and then sent to the IMU core via the PCIe logic unit, RX logic unit, and CMN interconnect bus. The software running on the IMU core responds to the read access request. If the configuration allows presenting the VIRTIO backend hardware device to the host, it returns the pre-configured Vendor ID value sequentially via the CMN logic unit, TX logic unit, and PCIe interconnect bus path. If the configuration does not allow presenting the VIRTIO backend hardware device to the host, it returns an indication message 0xFFFF. Subsequently, the host continues to initiate read and write accesses to the BAR register in the configuration space of the VIRTIO backend hardware device via ECAM, allocating system address space to the device. Through this process, a VIRTIO backend hardware device is presented in the host's PCIe bus topology.

[0072] The Vendor ID can be a unique 16-bit code assigned to each hardware device manufacturer. For example, the Vendor ID can be 0x8086, 0x1F53, etc.

[0073] It should be noted that since the DPU will present hundreds or thousands of devices to the host, the IMU will first simulate multiple layers of PCIe switch devices, and then connect the endpoint devices to these PCIe switches.

[0074] For example, a PCIe device, acting as a VIRTIO backend hardware device, maps its BAR space to the system space, allowing the host to subsequently read and write to the device's BAR space. VIRTIO backend hardware devices typically implement common and device-specific spaces within the BAR space. During the host's loading of the VIRTIO frontend driver, the driver initiates read and write access to the common space, as shown below:

[0075] First, the host initiates a read access request for the BAR space address of the VIRTIO backend hardware device in the COMMON space. This read access request is then forwarded to the DPU chip via the PCIe bus. Within the DPU chip, it passes through PCIe logic units, RX logic units, and the CMN interconnect bus before finally being sent to the IMU core. Finally, the software running on the IMU core "responds" to the read request, simulating the BAR space of the VIRTIO backend hardware device, and returns the read request result to the host sequentially via the PCIe logic unit, RX logic unit, and CMN interconnect bus path.

[0076] The following is based on Figure 2 Taking path 2 as an example, we will explain the data plane of the VIRTIO backend hardware device.

[0077] For example, when the host device's VIRTIO front-end driver has data to send or receive to the VIRTIO back-end hardware device, the front-end driver will send a notification message to the VIRTIO back-end hardware device to initiate DMA read and write operations on the cached descriptors.

[0078] Figure 3 This is a schematic diagram illustrating the interaction between the VIRTIO front-end driver and the VIRTIO back-end hardware device in related technologies, such as... Figure 3 As shown, taking a split-type VIRTIO device as an example, the software and hardware interaction between the VIRTIO front-end driver and the VIRTIO back-end hardware device can be achieved through the available ring table, the used ring table, and the descriptor table, as shown below:

[0079] First, the VIRTIO frontend driver prepares the data packets to be sent, stores them in the host's data cache, and adds the corresponding data cache information as an entry to the descriptor table, including the address, length, flags, and next-hop address. The VIRTIO frontend driver then uses the position information of the added entries in the descriptor table as pointer information to fill the available ring table, and simultaneously updates the index value of the available ring table.

[0080] Secondly, the VIRTIO front-end driver sends a notification message to the VIRTIO back-end hardware device to inform it that new content has been injected into the VIRTIO back-end hardware device software.

[0081] Next, the VIRTIO backend device reads the pointer information in the available ring table based on the notification information; it then reads the corresponding entry in the descriptor table based on the read pointer information to obtain the data cache information corresponding to the data packet; and finally, it reads the data cache based on the data cache information corresponding to the data packet to obtain the data packet.

[0082] Finally, the VIRTIO backend hardware device can update the used ring table in the VIRTIO frontend driver and send an interrupt notification to the software that data transmission has been completed.

[0083] In related technologies, for VIRTIO backend devices, performance can be greatly improved because the data plane is implemented by hardware logic. For example, if the VIRTIO backend device is a VIRTIO network device, when implemented by hardware logic, the transmission rate of 64-byte (Byte, B) small data packets can reach 250 million packets per second (Mpps), and the bandwidth of 1024-byte (1024B) large data packets can reach 400 gigabits per second (Gbps).

[0084] However, in public clouds, customer virtual machines come in various types, making it difficult for hardware-implemented VIRTIO backend devices to adapt to all version combinations. Furthermore, the VIRTIO protocol is constantly evolving, with its functionality continuously being added and improved. Hardware-implemented VIRTIO backend devices struggle to support newer versions. Finally, to improve VIRTIO performance, there are instances where the VIRTIO frontend driver needs modification; the fixed VIRTIO backend device cannot support these modified frontend drivers. Therefore, hardware-implemented VIRTIO backend devices suffer from poor flexibility.

[0085] To address the aforementioned issues, embodiments of this application provide a data transmission device, method, chip, system, storage medium, and program product. A routing module routes notification information sent by the host to a System-on-Chip (SOC) module for processing. The SOC module generates a first command descriptor, enabling a DMA module to read target data from the host and write it to the SOC module based on the first command descriptor. Since the software in the SOC module can emulate the functionality of a VIRTIO backend device, the emulated VIRTIO backend device functionality is editable and can be dynamically updated as the VIRTIO frontend driver and chip environment change. Because the data transmission device includes the aforementioned SOC module, the flexibility of the data transmission device is improved.

[0086] The application scenarios of the data transmission method provided in the embodiments of this application will be described below.

[0087] Figure 4 This is an application scenario diagram of a data transmission method provided in an embodiment of this application, such as... Figure 4 As shown, the data transmission device 102 communicates with the host 101. The data transmission device 102 includes a routing module, a SOC module, and a DMA module. The routing module receives and parses the notification sent by the host, obtains the notification information, and routes the notification information to the SOC module. The SOC module generates a first command descriptor based on the notification information. The DMA module reads the first command descriptor, reads target data from the host according to the first command descriptor, and writes the target data into the SOC module according to the first command descriptor. In response to the target data being written into the SOC module, the SOC module generates a second command descriptor. The DMA module reads the second command descriptor and sends it to the host to notify the host that the target data has been written into the SOC module.

[0088] It should be understood that the above data transmission method can be applied to communication between a host and a data transmission device. The data transmission device can be a network interface card (NIC) device that includes a DPU chip.

[0089] In one exemplary embodiment, such as Figure 5 The diagram illustrates a data transmission method applied to a data transmission device that communicates with a host. The data transmission device includes a routing module, a SOC module, and a DMA module. The method includes steps S201 to S205.

[0090] S201. The routing module receives and parses the notification sent by the host, obtains the notification information, and routes the notification information to the SOC module.

[0091] In this application, when the VIRTIO front-end driver in the host needs to send target data to the VIRTIO back-end hardware device, the VIRTIO front-end driver in the host can store the target data to be transmitted in the host's data cache and send a notification message of the target data to the data transmission device. Correspondingly, the routing module parses the notification message and routes it to the SOC module.

[0092] It should be understood that the embodiments of this application do not limit the type of target data, which can be any type and size of data packet.

[0093] In some embodiments, the notification information includes a target index corresponding to the target data, and the target index includes an available ring table index and / or a descriptor table index. The available ring table is used to store a target pointer, which indicates the target data's descriptor table information on the host.

[0094] For example, after storing the target data to be transmitted in the host's data cache, the VIRTIO front-end driver in the host can add the address information of the target data as an entry in the descriptor table information. Subsequently, the descriptor table information corresponding to the target data is filled into the available ring table as a target pointer, and the available ring table index information is updated. The VIRTIO front-end driver in the host can add the available ring table index information to the notification information, so that the VIRTIO back-end hardware device or SOC module in the data transmission device can generate a first command descriptor through the available ring table index to read the target data.

[0095] The target data's address information may include the target data's address in the host's data cache, the target data's storage length, the target data's flag, and the next-hop address. This available ring table index information is used to read the descriptor table information's memory address and length on the host side.

[0096] In some embodiments, the data transmission device may include a SOC module and a VIRTIO backend hardware device. Accordingly, the data transmission device may implement the functions of the VIRTIO backend device through the VIRTIO backend hardware device, or it may implement the functions of the VIRTIO backend device through a VIRTIO backend device emulated by the SOC module. This application embodiment does not impose any limitations on this.

[0097] In some embodiments, the notification information includes the device identifier of the target device. The data transmission device stores multiple routing destinations for the notification information, including VIRTIO backend hardware devices, IMU, and SOC modules. Accordingly, after receiving communication information sent by the host, the routing module of the data transmission device can determine the routing destination of the notification information based on the device identifier and the routing table.

[0098] In some embodiments, when the device identifier is a first preset value, the routing module can route the notification information to the SOC module according to the routing table. When the device identifier is a second preset value, the routing module can route the notification information to the VIRTIO backend hardware device according to the routing table. When the device identifier is a third preset value, the routing module can route the notification information to the IMU (Inertial Measurement Unit) according to the routing table.

[0099] For example, the device identifier can be a Bus Device Function (BDF) number, which is the device number in the PCIe bus. The device BDF number can be, for example, 01:00.1, 01:00.2, 01:00.3, etc.

[0100] In some embodiments, each device BDF number is configured with its corresponding routing destination. By taking different values ​​of the device BDF number, the routing destination of the notification information can be determined.

[0101] For example, the first preset value is device BDF number 01:00.1, and its corresponding route destination is the VIRTIO backend hardware device. For example, the second preset value is device BDF number 01:00.2, and its corresponding route destination is the SOC module. For example, the third preset value is device BDF number 01:00.3, and its corresponding route destination is the IMU. For example, Table 1 is a schematic diagram of a routing table provided in an embodiment of this application. As shown in Table 1, different device identifier values ​​can correspond to different route destinations.

[0102] Table 1

[0103]

[0104] It should be understood that because the SOC module is implemented in software, the functions of the VIRTIO backend device simulated by the SOC module are programmable. When the VIRTIO frontend driver changes, the VIRTIO protocol changes, or the version combination of the client virtual machine that needs to be adapted changes, the SOC module can be updated synchronously. Compared with the hardware-fixed VIRTIO backend device, the flexibility is greatly improved.

[0105] For example, Figure 6 A schematic diagram illustrating the principle of the data transmission method provided in the embodiments of this application, as shown below. Figure 6As shown, the routing module includes a PCIe logical unit, an RX logical unit, and a TX logical unit. Notification information sent by the host is routed from the PCIe logical unit to the RX logical unit. Subsequently, the RX logical unit parses the device identifier of the VIRTIO backend device to which the target data is to be transmitted from the notification information, and, combining the device identifier with the routing table, determines the routing destination of the notification information.

[0106] Continue to refer to Figure 6 The chip includes multiple routing paths for notification information. The first routing path sends the notification information to the VIRTIO backend hardware device, which then reads the target data from the host based on the notification information. The second routing path sends the notification information to the SOC module, which then reads the target data from the host. The third routing path sends the notification information to the IMU.

[0107] The SOC module runs on the chip's SOC core. The SOC module is used to simulate the functions of the VIRTIO backend device through software. That is, the SOC module can simulate the hardware logic of the VIRTIO backend device for operations such as reading available ring tables, reading descriptor tables, reading and writing data BUFs, and updating used ring tables.

[0108] In some embodiments, the routing table can be pre-configured and updated in real time based on instructions, thereby dynamically adjusting whether the notification information is routed to the hardware path corresponding to the VIRTIO backend hardware device or to the software path corresponding to the SOC module.

[0109] For example, when the VIRTIO backend hardware device can meet the functional requirements, the notification information can be routed to the corresponding hardware path of the VIRTIO backend hardware device, thereby improving processing performance. When the VIRTIO backend hardware device cannot meet the functional requirements, the notification information can be routed to the corresponding software path of the SOC module, thereby improving compatibility.

[0110] It should be noted that the data transmission method provided in this application embodiment, in terms of the implementation of the control plane, routes the read / write requests for the device configuration space and the read / write requests for the BAR space to the IMU, which is then simulated by the IMU. This application embodiment will not elaborate further on this.

[0111] In some embodiments, the SOC module includes a notification information receiving unit, a first record table cache unit, a second record table cache unit, and a Virtio Backend Emulator (VBE) unit. Accordingly, the notification information receiving unit can receive notification information routed to the SOC module, query the first record table to obtain the corresponding global queue number based on the function identifier and queue identifier in the notification information, and update the target index corresponding to the queried global queue number in the second record table with the target index in the notification information. The VBE unit can poll the second record table in the second record table cache unit to obtain the target index and generate a first command descriptor based on the target index.

[0112] The first record table cache unit is used to cache the first record table, which caches the correspondence between the function identifier, queue identifier and global queue number corresponding to the notification information; the second record table cache unit is used to cache the second record table, which caches the correspondence between the global queue number and the corresponding target index, and the target index includes the available ring table index and / or descriptor table index.

[0113] It should be understood that when a chip is deployed on a server, the processing power of the server's host CPU is far greater than that of the CPU within the SOC on the chip. This can lead to a situation where, when routing notification information to the software path corresponding to the SOC module on the SOC, the host CPU may send communication information too quickly, causing the SOC CPU to be unable to process it in time. This can put back pressure on the PCIe bus, thereby reducing the overall performance of the DPU. Therefore, the memory space of the SOC in this application can be configured with a second record table to record the available ring table index information in the communication information received by the SOC module.

[0114] For example, after parsing the function identifier and queue identifier from the notification information, the notification information receiving unit can query the first record table using the function identifier and queue identifier to obtain the global queue number. Subsequently, it queries and updates the target index corresponding to the global queue number in the second record table.

[0115] For example, Table 2 is a schematic table of a second record table provided in an embodiment of this application. As shown in Table 2, the second record table cache unit records the second record table, thereby recording the correspondence between the global queue number and the corresponding target index. The second record table cache unit can record whether a Notify has been sent, and the latest target index. If the communication information does not carry the target index, it can be recorded as FFFF in the second notification record table.

[0116] Table 2

[0117]

[0118] It should be understood that the embodiments of this application do not limit the time interval for polling the second record table in the second record table cache unit, and can be set according to the actual situation. For example, it can be set to poll once per second, poll once every three seconds, etc.

[0119] The second record table provided in this application embodiment can record the target index in the notification information without blocking, and will not put back pressure on the PCIe bus due to the slow processing of the SOC's CPU. The SOC module can poll the second record table and read the target index added from the previous polling to the current polling for processing.

[0120] It should be noted that since the host CPU's processing power is greater than the chip's SOC CPU's processing power, there may be a situation where a target index record for a global queue number is overwritten by a new target index of that queue before it has been processed by the SOC module. In this case, when the SOC module polls for that global queue number, it can directly use the latest target index.

[0121] Based on the notification information, the S202 and SOC modules generate the first command descriptor.

[0122] In some embodiments, the SOC module can generate a first command descriptor based on the available ring table index information in the notification information.

[0123] The first descriptor describes the migration command for the target data. The first command descriptor includes at least the following information: the command identifier corresponding to the first command descriptor, the host-side memory address, the host-side memory length, the memory address of the target cache unit, and the memory length of the target cache unit.

[0124] For example, in split mode, if the target index is the available ring table index, the SOC module can determine the host-side memory address corresponding to the available ring table using the available ring table index and the base address of the available ring table. Subsequently, the SOC module generates a first command descriptor based on the host-side memory address, combined with the command identifier of the migration command, the host memory length, the memory address of the target cache unit, and the memory length of the target cache unit. The base address of the available ring table is stored in the IMU, and the SOC module can obtain the base address of the available ring table from the IMU.

[0125] For example, in Packet mode, if the target index is a descriptor table index, the SOC module can determine the host-side memory address corresponding to the descriptor table information using the descriptor table index and the base address of the descriptor table. Subsequently, the SOC module generates a first command descriptor based on the host-side memory address corresponding to the descriptor table information, combined with the command identifier of the migration command, the host memory length, the memory address of the target cache unit, and the memory length of the target cache unit. The base address of the descriptor table is stored in the IMU, and the SOC module can obtain the base address of the descriptor table from the IMU.

[0126] It should be noted that the SOC module does not need to obtain the base address of the available ring table and / or the base address of the descriptor table from the IMU every time it receives a notification. As long as the IMU has sent the base address of the available ring table and / or the base address of the descriptor table to the SOC module, the SOC module can directly use the base address of the available ring table and / or the base address of the descriptor table in subsequent communications.

[0127] For example, Table 3 is a content field description table of a first descriptor provided in an embodiment of this application. As shown in Table 3, the first descriptor includes at least the following information: the command identifier corresponding to the first command descriptor, the host memory address, the host memory length, the memory address of the target data cache unit, and the memory length of the target data cache unit.

[0128] Table 3

[0129]

[0130] For example, the first descriptor may also include the migration direction. For example, Figure 7 This is an interactive diagram of a DMA module provided in an embodiment of this application. Figure 7 Path 1 in the diagram moves the data packets from Buf0 of the SOC module to Buf1 on the HOST side. The HOST memory address in its first descriptor is Buf1 on the OST side, and the SOC memory address is Buf0 of the SOC module. The migration direction is 1. Figure 7 Path 2 involves moving data packets from Buf0 on the HOST side to Buf1 on the SOC module. The HOST memory address in the SQ descriptor is Buf0 on the HOST side, and the SOC memory address is Buf1 on the SOC module. The migration direction is 0.

[0131] S203, the DMA module reads the first command descriptor, reads the target data from the host according to the first command descriptor, and writes the target data into the SOC module according to the first command descriptor.

[0132] In some embodiments, the DMA module may first read a first command descriptor from a first cache unit. The DMA module then reads descriptor table information based on the first command descriptor. Based on the descriptor table information, the DMA module reads target data from the host and writes the target data into a target data cache unit. Finally, the DMA module generates a third command descriptor and writes the third command descriptor into a third cache unit.

[0133] For example, in split mode, if the target index in the notification information is an available ring table index, the SOC module can add a first descriptor to the Submit Queue (SQ) ring of the first cache unit based on the available ring table index. Correspondingly, the DMA module reads the first descriptor from the SQ ring of the first cache unit to determine the host-side memory address and host-side memory length corresponding to the available ring table. Subsequently, the DMA module reads the target pointer from the available ring table based on the host-side memory address and host-side memory length, and then reads the descriptor table information based on the target pointer. Finally, the DMA module reads the target data from the host based on the address information of the target data in the descriptor table information, moves the target data to the SOC's memory, and writes it to the target data cache unit.

[0134] For example, in Packet mode, the target index in the notification information is a descriptor table index. The SOC module can add a first descriptor to the Submit Queue (SQ) ring of the first cache unit based on the descriptor table index. Correspondingly, the DMA module reads the first descriptor from the SQ ring of the first cache unit to determine the host-side memory address and host-side memory length corresponding to the descriptor table information. Subsequently, the DMA module reads the descriptor table information based on the host-side memory address and host-side memory length. Finally, the DMA module reads the target data from the host based on the address information of the target data in the descriptor table information, moves the target data to the SOC's memory, and writes it to the target data cache unit.

[0135] The descriptor table information includes the address information of the target data. For example, the address information of the target data may include the address of the target data in the host's data cache, the storage length of the target data, the flag of the target data, and the next-hop address.

[0136] For example, continue to refer to Figure 7The DMA module interacts with the SOC module through the SQ ring in the first cache unit and the Complete Queue (CQ) ring in the third cache unit. Migration commands initiated by the SOC module can be injected into the SQ ring as first descriptors. When the SOC module injects a new first descriptor, it notifies the DMA module of the existence of a new first descriptor corresponding to a migration command by writing to the notification register in the DMA module. Subsequently, the DMA module reads the SQ ring, obtains the first descriptor, and parses it.

[0137] S204. In response to the target data being written to the SOC module, the SOC module generates a second command descriptor.

[0138] In some embodiments, after the target data is written to the SOC module, the SOC module may generate a second command descriptor.

[0139] For example, the DMA module can first generate a third command descriptor after writing the target data to the SOC module. Subsequently, the SOC module reads and parses the third command descriptor, releases the corresponding cache space based on the parsing result, and generates a second command descriptor.

[0140] The third command descriptor includes the identifier of the migration command corresponding to the target data after migration is complete. The second command descriptor is used to notify the host that the target data has been written to the SOC module.

[0141] For example, after writing the target data to the SOC module, the DMA module can add a third command descriptor to the CQ queue ring in the third cache unit. Subsequently, the SOC module reads the third descriptor from the CQ queue ring in the third cache unit, releases the cache space of the migration command according to the identifier of the migration command in the third descriptor, and generates a second command descriptor.

[0142] For example, Table 4 is a content field description table of a third descriptor provided in an embodiment of this application. The content of the third descriptor can be as shown in Table 4.

[0143] Table 4

[0144]

[0145] It should be noted that, in order to make the most of the multi-core performance of the SOC, multiple SQ queues can be configured in the first cache unit and multiple CQ queues can be configured in the third cache unit, so that migration commands can be processed in parallel, thereby improving processing performance.

[0146] S205, the DMA module reads the second command descriptor and sends the second command descriptor to the host to notify the host that the target data has been written into the SOC module.

[0147] The second command descriptor is used to notify the host that the target data has been written into the SOC module.

[0148] In some embodiments, the DMA module, in response to a second command descriptor, can also initiate a write operation to the host on the used ring table. The write operation is used to update information about the target data in the used ring table, such as updating at least one of the pointer, length, and index information in the used ring table.

[0149] The data transmission method provided in this application embodiment includes a routing module receiving and parsing a notification sent by a host to obtain notification information, and routing the notification information to a SOC module. The SOC module generates a first command descriptor based on the notification information. A DMA module reads the first command descriptor, reads target data from the host based on the first command descriptor, and writes the target data to the SOC module based on the first command descriptor. In response to the target data being written to the SOC module, the SOC module generates a second command descriptor. The DMA module reads the second command descriptor and sends it to the host to notify the host that the target data has been written to the SOC module. By routing the notification information sent by the host to the SOC module for processing through the routing module, and by generating the first command descriptor through the SOC module, the DMA module can read the target data from the host and write it to the SOC module based on the first command descriptor. Since the software in the SOC module can emulate the functions of a VIRTIO backend device, the functions of the VIRTIO backend device emulated by the SOC module are editable and can be dynamically updated as the VIRTIO frontend driver and chip environment change. Because the data transmission device includes the aforementioned SOC module, the flexibility of the data transmission device is improved.

[0150] In one exemplary embodiment, such as Figure 8 The diagram illustrates another data transmission method applied to a data transmission device that communicates with a host. The data transmission device includes a routing module, a data transmission method, and a DMA module. The data transmission method comprises steps S301 to S309:

[0151] S301 The routing module receives and parses the notification sent by the host, obtains the notification information, and routes the notification information to the SOC module.

[0152] In some embodiments, the notification information includes the device identifier of the target device, and the data transmission device further includes a VIRTIO backend hardware device and an IMU. When the device identifier is a first preset value, the routing module routes the notification information to the SOC module according to the routing table; when the device identifier is a second preset value, the routing module routes the notification information to the VIRTIO backend hardware device according to the routing table; when the device identifier is a third preset value, the routing module routes the notification information to the IMU according to the routing table.

[0153] Based on the notification information, the S302 and SOC modules generate the first command descriptor.

[0154] In some embodiments, the SOC module includes a first cache unit, a third cache unit, and a target data cache unit; the first command descriptor includes at least the following information: the command identifier corresponding to the first command descriptor, the host memory address, the host memory length, the memory address of the target data cache unit, and the memory length of the target data cache unit.

[0155] S303, the DMA module reads the first command descriptor from the first cache unit.

[0156] S304, the DMA module reads the descriptor table information according to the first command descriptor.

[0157] S305, the DMA module reads the target data from the host according to the descriptor table information; and writes the target data into the target data cache unit.

[0158] S306, the DMA module generates a third command descriptor and writes the third command descriptor into the third cache unit.

[0159] After writing the target data to the SOC module, the S307 DMA module generates a third command descriptor.

[0160] The S308 and SOC modules read and parse the third command descriptor, release the corresponding cache space based on the parsing result, and generate the second command descriptor.

[0161] S309, the DMA module reads the second command descriptor and sends the second command descriptor to the host to notify the host that the target data has been written into the SOC module.

[0162] The data transmission method provided in this application embodiment includes a routing module receiving and parsing a notification sent by a host to obtain notification information, and routing the notification information to a SOC module. The SOC module generates a first command descriptor based on the notification information. A DMA module reads the first command descriptor, reads target data from the host based on the first command descriptor, and writes the target data to the SOC module based on the first command descriptor. In response to the target data being written to the SOC module, the SOC module generates a second command descriptor. The DMA module reads the second command descriptor and sends it to the host to notify the host that the target data has been written to the SOC module. By routing the notification information sent by the host to the SOC module for processing through the routing module, and by generating the first command descriptor through the SOC module, the DMA module can read the target data from the host and write it to the SOC module based on the first command descriptor. Since the software in the SOC module can emulate the functions of a VIRTIO backend device, the functions of the VIRTIO backend device emulated by the SOC module are editable and can be dynamically updated as the VIRTIO frontend driver and chip environment change. Because the data transmission device includes the aforementioned SOC module, the flexibility of the data transmission device is improved.

[0163] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0164] Based on the same inventive concept, this application also provides a data transmission apparatus for implementing the data transmission method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, specific limitations in one or more data transmission apparatus embodiments provided below can be found in the limitations of the data transmission method described above, and will not be repeated here.

[0165] In one exemplary embodiment, such as Figure 9 As shown, a data transmission device 400 is provided, including: a routing module 401, a SOC module 402, and a DMA module 403, wherein:

[0166] The routing module 401 is used to receive and parse the notification sent by the host, obtain the notification information, and route the notification information to the SOC module 402;

[0167] SOC module 402 is used to generate a first command descriptor based on the notification information;

[0168] DMA module 403 is used to read the first command descriptor, read target data from the host according to the first command descriptor, and write the target data into SOC module 402 according to the first command descriptor.

[0169] SOC module 402 is also used to generate a second command descriptor in response to the writing of target data to SOC module 402;

[0170] The DMA module 403 is also used to read the second command descriptor and send the second command descriptor to the host to notify the host that the target data has been written into the SOC module 402.

[0171] In some embodiments, the notification information includes the device identifier of the target device, the data transmission device further includes a VIRTIO backend hardware device and an IMU, and the routing module 401 is specifically used for:

[0172] If the device identifier is the first preset value, the notification information is routed to the SOC module 402 according to the routing table; if the device identifier is the second preset value, the notification information is routed to the VIRTIO backend hardware device according to the routing table; if the device identifier is the third preset value, the notification information is routed to the IMU according to the routing table.

[0173] In some embodiments, the DMA module 403 is further configured to generate a third command descriptor after writing the target data to the SOC module 402;

[0174] SOC module 402 is also used to read and parse the third command descriptor, release the corresponding cache space based on the parsing result, and generate the second command descriptor.

[0175] In some embodiments, the SOC module 402 includes a first cache unit, a third cache unit, and a target data cache unit;

[0176] The first command descriptor includes at least the following information: the command identifier corresponding to the first command descriptor, the host memory address, the host memory length, the memory address of the target data cache unit, and the memory length of the target data cache unit;

[0177] The DMA module 403 is also used to read a first command descriptor from a first cache unit; read descriptor table information according to the first command descriptor; read target data from the host according to the descriptor table information; write the target data into a target data cache unit; generate a third command descriptor and write the third command descriptor into a third cache unit.

[0178] In some embodiments, the SOC module 402 includes a notification information receiving unit, a first record table cache unit, a second record table cache unit, and a VBE unit;

[0179] The first record table cache unit is used to cache the first record table, which caches the correspondence between the function identifier, queue identifier and global queue number corresponding to the notification information;

[0180] The second record table cache unit is used to cache the second record table, which caches the correspondence between global queue numbers and corresponding target indexes. The target indexes include available ring table indexes and / or descriptor table indexes.

[0181] The notification information receiving unit is used to receive notification information routed to the SOC module, query the first record table to obtain the corresponding global queue number according to the function identifier and queue identifier in the notification information, and update the target index corresponding to the global queue number queried in the second record table with the target index in the notification information.

[0182] The VBE unit is used to poll the second record table in the second record table cache unit to obtain the target index and generate the first command descriptor based on the target index.

[0183] Each module in the aforementioned data transmission device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.

[0184] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 10As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a data transmission method.

[0185] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0186] In one embodiment, a chip is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-described data transmission method.

[0187] In one embodiment, a VIRTIO system is provided, including the data transmission device and host described above.

[0188] In one embodiment, a computer-readable storage medium is provided on which a computer program is stored, which, when executed by a processor, implements the above-described data transmission method.

[0189] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described data transmission method.

[0190] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0191] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0192] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A data transmission device, wherein the data transmission device communicates with a host, characterized in that, The device includes: The routing module is used to receive and parse the notification sent by the host, obtain the notification information, and route the notification information to the SOC module; The SOC module is used to generate a first command descriptor based on the notification information; The DMA module is used to read the first command descriptor, read target data from the host according to the first command descriptor, and write the target data into the SOC module according to the first command descriptor. The SOC module is also configured to generate a second command descriptor in response to the target data being written to the SOC module; The DMA module is also used to read the second command descriptor and send the second command descriptor to the host to notify the host that the target data has been written into the SOC module.

2. The apparatus according to claim 1, characterized in that, The notification information includes the device identifier of the target device; the data transmission device further includes a VIRTIO backend hardware device and an IMU; the routing module is specifically used for: When the device identifier is a first preset value, the notification information is routed to the SOC module according to the routing table; when the device identifier is a second preset value, the notification information is routed to the VIRTIO backend hardware device according to the routing table; when the device identifier is a third preset value, the notification information is routed to the IMU according to the routing table.

3. The apparatus according to claim 2, characterized in that, The DMA module is also used to generate a third command descriptor after the target data is written to the SOC module; The SOC module is also used to read and parse the third command descriptor, release the corresponding cache space according to the parsing result, and generate the second command descriptor.

4. The apparatus according to claim 3, characterized in that, The SOC module includes a first cache unit, a third cache unit, and a target data cache unit; The first command descriptor includes at least the following information: the command identifier corresponding to the first command descriptor, the host memory address, the host memory length, the memory address of the target data cache unit, and the memory length of the target data cache unit; The DMA module is further configured to read the first command descriptor from the first cache unit; and read descriptor table information based on the first command descriptor; The target data is read from the host according to the descriptor table information; Write the target data into the target data cache unit; A third command descriptor is generated and written into a third cache unit.

5. The apparatus according to any one of claims 1-4, characterized in that, The SOC module includes a notification information receiving unit, a first record table cache unit, a second record table cache unit, and a VBE unit; The first record table caching unit is used to cache the first record table, which caches the correspondence between the function identifier, queue identifier and global queue number corresponding to the notification information; The second record table cache unit is used to cache the second record table, which caches the correspondence between the global queue number and the corresponding target index. The target index includes the available ring table index and / or the descriptor table index. The notification information receiving unit is used to receive notification information routed to the SOC module, query the first record table to obtain the corresponding global queue number according to the function identifier and queue identifier in the notification information, and update the target index corresponding to the global queue number queried in the second record table with the target index in the notification information. The VBE unit is used to poll the second record table in the second record table cache unit to obtain the target index and generate the first command descriptor based on the target index.

6. A data transmission method, characterized in that, Applied to a data transmission device that communicates with a host, the data transmission device includes a routing module, a SOC module, and a DMA module, the method includes: The routing module receives and parses the notification sent by the host, obtains the notification information, and routes the notification information to the SOC module; The SOC module generates a first command descriptor based on the notification information; The DMA module reads the first command descriptor, reads target data from the host according to the first command descriptor, and writes the target data into the SOC module according to the first command descriptor. The SOC module generates a second command descriptor in response to the target data being written to the SOC module. The DMA module reads the second command descriptor and sends the second command descriptor to the host to notify the host that the target data has been written into the SOC module.

7. The method according to claim 6, characterized in that, The notification information includes the device identifier of the target device. The data transmission device also includes a VIRTIO backend hardware device and an IMU. Routing the notification information to the SOC module includes: When the device identifier is a first preset value, the routing module routes the notification information to the SOC module according to the routing table; The method further includes: when the device identifier is a second preset value, the routing module routes the notification information to the VIRTIO backend hardware device according to the routing table; When the device identifier is a third preset value, the routing module routes the notification information to the IMU according to the routing table.

8. The method according to claim 7, characterized in that, The method further includes: After writing the target data into the SOC module, the DMA module generates a third command descriptor. The SOC module reads and parses the third command descriptor, releases the corresponding cache space based on the parsing result, and generates the second command descriptor.

9. The method according to claim 8, characterized in that, The SOC module includes a first cache unit, a third cache unit, and a target data cache unit; the first command descriptor includes at least the following information: the command identifier corresponding to the first command descriptor, the host memory address, the host memory length, the memory address of the target data cache unit, and the memory length of the target data cache unit; The method further includes: The DMA module reads the first command descriptor from the first cache unit; The DMA module reads the descriptor table information according to the first command descriptor; The DMA module reads the target data from the host according to the descriptor table information; and writes the target data into the target data cache unit. The DMA module generates a third command descriptor and writes the third command descriptor into a third cache unit.

10. The method according to any one of claims 6-9, characterized in that, The SOC module includes a notification information receiving unit, a first record table caching unit, a second record table caching unit, and a VBE unit. The first record table caching unit is used to cache a first record table, which caches the correspondence between the function identifier, queue identifier, and global queue number corresponding to the notification information. The second record table caching unit is used to cache a second record table, which caches the correspondence between the global queue number and the corresponding target index. The target index includes an available ring table index and / or a descriptor table index. The method further includes: the notification information receiving unit receives notification information routed to the SOC module, queries the first record table to obtain the corresponding global queue number according to the function identifier and queue identifier in the notification information, and updates the target index corresponding to the global queue number queried in the second record table with the target index in the notification information; The VBE unit polls the second record table in the second record table cache unit to obtain the target index, and generates the first command descriptor based on the target index.

11. A chip comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 6 to 10.

12. A VIRTIO system, characterized in that, Includes the chip and host as described in claim 11.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 6 to 10.

14. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 6 to 10.

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