A ring-shaped photonic crystal-based chip and a preparation method thereof

Abstract

The application relates to the chip preparation technical field and provides a chip based on a ring-shaped photonic crystal and a preparation method thereof. The preparation method comprises the following steps: growing a nucleation layer on a substrate; growing a superlattice structure on the side, away from the substrate, of the nucleation layer; sequentially growing an n-type cladding layer, an n-type waveguide layer, a quantum well and a p-type electron blocking layer on the side, away from the nucleation layer, of the superlattice structure; etching a plurality of ring-shaped cavities on the p-type electron blocking layer to form a ring-shaped photonic crystal; growing a p-type extended contact layer on the side, away from the quantum well, of the p-type electron blocking layer; and performing in-situ annealing treatment. The preparation method can effectively adjust the directionality of a photonic band gap, can form uniform light waves in all directions of the side surface, can thereby inhibit the leakage of laser from the side surface non-light-out area, can improve the light-out efficiency, and can effectively ensure the light beam quality due to the periodic distribution of the ring-shaped photonic crystal.

Description

Technical Field

[0001] This application relates to the field of chip fabrication technology, and in particular to a chip based on a ring photonic crystal and its fabrication method. Background Technology

[0002] Photonic crystals play a crucial role in chips, becoming one of the key enabling technologies for miniaturized, high-performance, and low-power optoelectronic devices and integrated systems through their unique photonic bandgap characteristics.

[0003] The photonic bandgap is a core characteristic of photonic crystals. By designing periodic dielectric structures, the propagation of light waves of specific wavelengths can be confined. Existing side-emitting lasers mostly use ordinary photonic crystals (such as strip or square lattice structures) for light confinement, attempting to reduce light escape through the photonic bandgap effect. However, these non-ring structures have inherent defects: their photonic bandgap has insufficient directional control, making it difficult to uniformly confine light waves from all sides, resulting in some laser leakage from the non-emitting areas on the side, reducing the effective extraction efficiency of the emitting surface; at the same time, the periodic distribution of the non-ring structure has a low matching degree with the laser mode of side-emitting lasers, which easily leads to mode disorder, further affecting the extraction efficiency and beam quality. Summary of the Invention

[0004] This application provides a chip based on a ring photonic crystal and its fabrication method, which effectively improves light extraction efficiency and ensures beam quality.

[0005] In a first aspect, this application provides a method for fabricating a chip based on a ring photonic crystal, comprising: growing a nucleation layer on a substrate; the growth temperature of the nucleation layer being a first temperature; growing a superlattice structure on the side of the nucleation layer away from the substrate; wherein the growth temperature of the superlattice structure is a second temperature, the first temperature being lower than the second temperature, and the superlattice structure comprising periodically arranged AlN layers and AlGaN layers; the AlN layers and AlGaN layers having the same thickness; growing an n-type cladding layer, an n-type waveguide layer, a quantum well, and a p-type electron blocking layer sequentially on the side of the superlattice structure away from the nucleation layer; etching multiple ring cavities on the p-type electron blocking layer to form a ring photonic crystal; wherein the center of the ring cavity coincides with the center of the p-type electron blocking layer, and the etching direction of the ring cavity is opposite to the growth direction of the p-type electron blocking layer; the multiple ring cavities are spaced apart, and the depth of the multiple ring cavities is greater than zero and less than or equal to the sum of the thicknesses of the p-type electron blocking layer and the quantum well; growing a p-type extended contact layer on the side of the p-type electron blocking layer away from the quantum well; and performing in-situ annealing.

[0006] In some feasible implementations, the number of annular cavities is 5-10, and the thickness of the annular cavities is 50nm-120nm.

[0007] In some feasible implementations, multiple annular cavities are etched on the p-type electron blocking layer to form a ring photonic crystal, including: coating a first mask layer on the p-type electron blocking layer; etching the first mask layer using electron beam lithography to form multiple annular grooves; wherein the etching depth of the annular grooves is the same as the coating thickness of the first mask layer; etching the p-type electron blocking layer using inductively coupled plasma technology to form a ring photonic crystal; the ring photonic crystal includes multiple annular cavities, and the annular cavities correspond one-to-one with the annular grooves; and removing the unetched first mask layer.

[0008] In some feasible implementations, the Al composition of the n-type cladding layer gradually decreases from the side closer to the superlattice structure to the side farther away from the superlattice structure.

[0009] In some feasible implementations, the number of periods in the quantum well is 3-8; the quantum well includes a well structure and a barrier structure; after the well structure is grown, the well structure is flushed with NH3 atmosphere for a first preset time, and the barrier structure is regrown, with the Al component in the barrier structure being greater than the Al component in the well structure.

[0010] In some feasible implementations, the Al composition in the p-type extended contact layer gradually decreases from the side closer to the p-type electron blocking layer to the side farther away from the p-type electron blocking layer.

[0011] In some feasible implementations, after in-situ annealing, the fabrication method of the chip based on the ring photonic crystal further includes: growing a patterned transparent conductive layer on the p-type extended contact layer; wherein the center of the patterned transparent conductive layer coincides with the center of the p-type extended contact layer; along the etching direction of the ring cavity, the projection of the patterned transparent conductive layer on the p-type extended contact layer is located within the enclosed area of ​​multiple ring cavities and does not overlap with the multiple ring cavities; and growing electrodes on the patterned transparent conductive layer.

[0012] The method for fabricating a chip based on a ring photonic crystal provided in the first aspect of this application can effectively adjust the directionality of the photonic bandgap, forming a uniform light wave in all directions from the side, thereby suppressing laser leakage from the non-light-emitting area on the side and improving the light-emitting efficiency. Moreover, the ring photonic crystal is periodically distributed and has a high degree of matching with the laser mode emitted from the side, effectively ensuring the beam quality.

[0013] Secondly, this application provides another method for fabricating a chip based on a ring photonic crystal, comprising: growing a nucleation layer on a substrate; the growth temperature of the nucleation layer being a first temperature; growing a superlattice structure on the side of the nucleation layer away from the substrate; the growth temperature of the superlattice structure being a second temperature, the first temperature being lower than the second temperature, the superlattice structure comprising an AlN layer and an AlGaN layer arranged sequentially; the AlN layer and the AlGaN layer having the same thickness; growing an n-type cladding layer, an n-type waveguide layer, a quantum well, a p-type electron blocking layer, and a p-type extended contact layer sequentially on the side of the superlattice structure away from the nucleation layer; etching multiple ring cavities on the p-type extended contact layer to form a ring photonic crystal; wherein the center of the ring cavity coincides with the center of the p-type extended contact layer, and the etching direction of the ring cavity is opposite to the growth direction of the p-type extended contact layer; the multiple ring cavities are spaced apart, the depth of the multiple ring cavities being greater than the thickness of the p-type extended contact layer, and less than or equal to the sum of the thicknesses of the p-type extended contact layer, the p-type electron blocking layer, and the quantum well; and performing in-situ annealing.

[0014] Thirdly, this application provides a chip based on a ring photonic crystal, comprising: a substrate; a nucleation layer grown on the substrate; the nucleation layer being grown at a first temperature; a superlattice structure grown on the side of the nucleation layer away from the substrate; the superlattice structure being grown at a second temperature, the first temperature being lower than the second temperature, the superlattice structure comprising an AlN layer and an AlGaN layer sequentially disposed thereon; the AlN layer and the AlGaN layer having the same thickness; an n-type cladding layer grown on the side of the superlattice structure away from the nucleation layer; and an n-type waveguide layer grown on the side of the n-type cladding layer away from the substrate. One side of the superlattice structure; a quantum well, grown on the side of the n-type waveguide layer away from the n-type cladding layer; a p-type electron blocking layer, grown on the side of the quantum well away from the n-type waveguide layer; a p-type extended contact layer, grown on the side of the p-type electron blocking layer away from the quantum well; a ring photonic crystal, comprising multiple ring cavities, with at least one ring cavity disposed in the p-type electron blocking layer, the center of the ring cavity coinciding with the center of the p-type electron blocking layer, and the etching direction of the ring cavity opposite to the growth direction of the p-type electron blocking layer; the multiple ring cavities are spaced apart.

[0015] In some feasible implementations, the annular cavity is disposed in a p-type electron blocking layer, and the depth of the annular cavity is greater than zero and less than or equal to the thickness of the p-type electron blocking layer; or, the annular cavity is disposed in a p-type electron blocking layer and a quantum well, and the depth of the annular cavity is greater than the thickness of the p-type electron blocking layer and less than or equal to the sum of the thicknesses of the p-type electron blocking layer and the quantum well; or, the annular cavity is disposed in a p-type extended contact layer and a p-type electron blocking layer, and the depth of the annular cavity is greater than the thickness of the p-type extended contact layer and less than or equal to the sum of the thicknesses of the p-type electron blocking layer and the p-type extended contact layer; or, the annular cavity is disposed in a p-type extended contact layer, a p-type electron blocking layer and a quantum well, and the depth of the annular cavity is greater than the sum of the thicknesses of the p-type extended contact layer and the p-type electron blocking layer and less than or equal to the sum of the thicknesses of the p-type extended contact layer, the p-type electron blocking layer and the quantum well.

[0016] The beneficial technical effects of the second and third aspects can be found in the first aspect, and will not be repeated here. Attached Figure Description

[0017] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic flowchart of the first method for fabricating a chip based on a ring photonic crystal provided in this application embodiment;

[0019] Figure 2 This is one of the process schematic diagrams of the first method for fabricating a chip based on a ring photonic crystal provided in the embodiments of this application;

[0020] Figure 3 This is a schematic diagram of the fabrication process of the first type of ring photonic crystal provided in the embodiments of this application;

[0021] Figure 4A This is the second schematic diagram of the process for fabricating a chip based on a ring photonic crystal, as provided in the embodiments of this application.

[0022] Figure 4B yes Figure 4A Top view;

[0023] Figure 5 This is a schematic diagram of the ring photonic crystal provided in an embodiment of this application;

[0024] Figure 6 This is the third schematic diagram of the process for fabricating a chip based on a ring photonic crystal, as provided in the embodiments of this application.

[0025] Figure 7 This is the fourth schematic diagram of the process for fabricating a chip based on a ring photonic crystal, as provided in the embodiments of this application.

[0026] Figure 8 yes Figure 7 The top view shown in (c) is shown in the middle.

[0027] Figure 9 This is the fifth schematic diagram of the process for fabricating a chip based on a ring photonic crystal, as provided in the embodiments of this application.

[0028] Figure 10 This is a schematic flowchart of the second method for fabricating a chip based on a ring photonic crystal provided in the embodiments of this application;

[0029] Figure 11 This is a schematic diagram of the fabrication method of the second chip based on a ring photonic crystal provided in the embodiments of this application;

[0030] Figure 12 This is a schematic diagram of the structure of a chip based on a ring photonic crystal provided in an embodiment of this application.

[0031] Illustration markings:

[0032] 100. Chips based on ring photonic crystals;

[0033] 101. Substrate; 102. Nucleation layer; 103. Superlattice structure; 104. n-type cladding layer; 105. n-type waveguide layer; 106. Quantum well; 107. p-type electron blocking layer; 108. p-type extended contact layer; 10a. Ring cavity; 10a-1. First ring cavity; 10a-2. Second ring cavity; 10a-3. Third ring cavity; b1. First mask layer; b2. Second mask layer; 109. Patterned transparent conductive layer; 110. Electrode. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the protection scope of this application.

[0035] In the following description, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0036] Furthermore, in this application, directional terms such as "upper," "lower," "inner," and "outer" are defined relative to the indicated placement of the components in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the placement of the components in the accompanying drawings.

[0037] With the rise of 3D printing, the requirements for photopolymerization technology are gradually increasing, making the core requirement for stable product quality—deep ultraviolet (light emitting diode, LED)—more urgent. Compared with traditional ultraviolet mercury lamps, deep ultraviolet LEDs have outstanding advantages such as small size, energy saving and environmental protection (mercury-free), instant switching, ultra-long lifespan, and precisely customizable wavelength. This makes deep ultraviolet LEDs particularly crucial for addressing the issues of "surface curing" and "high-precision curing."

[0038] In deep ultraviolet (DUV) LEDs, light extraction in the transverse magnetic mode (TM) is a core technological challenge. As the emission wavelength of DUV LEDs shortens, their emission characteristics gradually shift from being dominated by the common transverse electric mode (TE) to being dominated by the TM mode. In the TM mode, photons are mainly emitted from the side of the chip, significantly reducing the light extraction efficiency at the emitting surface.

[0039] The essence of a photonic crystal lies in the periodic arrangement of its dielectric constant in space. When light propagates within it, it encounters countless interfaces with abrupt changes in refractive index, resulting in scattering at each interface. For light of a specific frequency (whose wavelength is comparable to the lattice constant), these wavelets scattered from different lattice planes satisfy the condition of coherent destructive interference in a specific propagation direction. When the optical path difference between adjacent scattering paths is an odd multiple of half the wavelength, these scattered waves are out of phase. In a perfectly periodic structure, this destructive interference effect works synergistically and superimposes throughout the entire space, ultimately preventing light waves of that frequency from forming a stable propagation mode. This suppression capability is directly determined by the lattice constant, structural symmetry, and the refractive index contrast of the medium; high contrast is key to generating a wide and strong photonic bandgap.

[0040] The photonic bandgap is a core characteristic of photonic crystals. By designing periodic dielectric structures, the propagation of light waves of specific wavelengths can be confined. Existing side-emitting lasers mostly use ordinary photonic crystals (such as strip or square lattice structures) for light confinement, attempting to reduce light escape through the photonic bandgap effect. However, these non-ring structures have inherent defects: their photonic bandgap has insufficient directional control, making it difficult to uniformly confine light waves from all sides, resulting in some laser leakage from the non-emitting areas on the side, reducing the effective extraction efficiency of the emitting surface; at the same time, the periodic distribution of the non-ring structure has a low matching degree with the laser mode of side-emitting lasers, which easily leads to mode disorder, further affecting the extraction efficiency and beam quality.

[0041] To address the aforementioned technical problems, this application provides a chip based on a ring photonic crystal and its fabrication method, which can effectively improve light extraction efficiency and ensure beam quality.

[0042] Figure 1 This is a schematic flowchart of the first method for fabricating a chip based on a ring photonic crystal provided in this application embodiment; Figure 2 This is one of the process schematic diagrams of the first method for fabricating a chip based on a ring photonic crystal provided in the embodiments of this application.

[0043] Combination Figure 1 and Figure 2 As shown, the first method for fabricating a chip based on a ring photonic crystal provided in this application embodiment may include the following steps S11 to S16.

[0044] Step S11: Growing a nucleation layer 102 on substrate 101.

[0045] In this step, metal-organic chemical vapor deposition (MOCVD) technology can be used to epitaxially grow a nucleation layer 102 on the substrate 101, which can form a high-density island nucleus to reduce subsequent high-temperature layer dislocations.

[0046] The nucleation layer 102 can be aluminum nitride (AlN). The growth environment of the nucleation layer 102 may include: a pressure of 100 mbar, a flow rate of trimethylaluminum (TMAl) of 25 standard milliliters per minute (sccm), and a flow rate of ammonia (NH3) of 3000 standard milliliters per minute (sccm).

[0047] In some feasible implementations, the growth temperature of the nucleation layer 102 is a first temperature, which can be set between 550℃ and 650℃.

[0048] For example, the first temperature can be one of 550°C, 575°C, 600°C, 625°C, or 650°C. Of course, the first temperature can also be any other value between 550°C and 650°C.

[0049] In some feasible implementations, the growth thickness of the nucleation layer 102 can be 20nm-50nm.

[0050] For example, the thickness of the nucleation layer 102 can be 20 nm, 30 nm, 40 nm, or 50 nm. Of course, the thickness of the nucleation layer 102 can also be other values ​​between 20 nm and 50 nm.

[0051] In one specific implementation, the nucleation layer 102 is grown at a temperature of 600℃ and has a thickness of 30nm.

[0052] Step S12: A superlattice structure 103 is grown on the side of the nucleation layer 102 away from the substrate 101; wherein the growth temperature of the superlattice structure 103 is a second temperature, and the first temperature is lower than the second temperature.

[0053] In this step, periodic superlattice structures 103 are alternately grown on the nucleation layer 102 using MOCVD technology for stress relief and dislocation filtering.

[0054] The superlattice structure 103 includes periodically arranged AlN and AlGaN layers (not shown in the figure). The AlN and AlGaN layers have the same growth thickness. The growth environment for the AlN and AlGaN layers may include: a pressure of 50 mbar, a flow rate of trimethylaluminum™Al of 40 sccm, and a flow rate of ammonia (NH3) of 5000 sccm.

[0055] In some feasible implementations, the second temperature is higher than the first temperature, and the second temperature can be set between 800℃ and 1300℃.

[0056] For example, the second temperature can be one of 800°C, 900°C, 1000°C, 1100°C, or 1300°C. Of course, the second temperature can also be any other value between 800°C and 1300°C.

[0057] In some feasible implementations, the AlN and AlGaN layers in each period of the superlattice structure 103 have the same thickness, ranging from 5 nm to 20 nm.

[0058] For example, the thickness of the AlN and AlGaN layers can be 5 nm, 10 nm, 15 nm, or 20 nm. Of course, the thickness of the AlN and AlGaN layers can also be other values ​​between 5 nm and 20 nm.

[0059] In some feasible implementations, the superlattice structure 103 has a period number of 3-8.

[0060] For example, the number of periods in the superlattice structure 103 can be 3, 4, 5, 6, 7 or 8.

[0061] In one specific implementation, the growth temperature of the superlattice structure 103 is 1250℃, the thickness of the AlN layer and the AlGaN layer in each period is 10nm, the number of periods of the superlattice structure 103 is 5, and the growth thickness of the superlattice structure 103 is 5×(10nm+10nm)=1.0 µm.

[0062] Step S13: On the side of the superlattice structure 103 away from the nucleation layer 102, an n-type cladding layer 104, an n-type waveguide layer 105, a quantum well 106, and a p-type electron blocking layer 107 are grown sequentially.

[0063] In the n-type cladding layer 104, the Al composition gradually decreases from the side closer to the superlattice structure 103 to the side farther away from the superlattice structure 103, so as to reduce the polarization field and lower the series resistance.

[0064] In this step, each structural layer can be constructed using MOCVD technology. Specifically, step S13 may include steps S131 to S134.

[0065] Step S131: Grow an n-type cladding layer 104 on the side of the superlattice structure 103 away from the nucleation layer 102.

[0066] In this step, the n-type cladding layer 104 can be produced using MOCVD technology. The n-type cladding layer 104 can be an n-type doped aluminum gallium nitride alloy (n-Al). 0.4 Ga 0.6 In the n-type cladding layer 104, the Al composition gradually decreases from the side closer to the superlattice structure 103 to the side closer to the n-type waveguide layer 105. The initial molar fraction of Al is 40%, the initial molar fraction of Ga is 60%, the final molar fraction of Al is 30%, and the final molar fraction of Ga is 70%. Along the growth direction of the n-type cladding layer 104, the Al composition gradually decreases from 40% to 30%. The growth environment of the n-type cladding layer 104 may include: a pressure of 200 mbar and a SiH4 doping concentration of 5 × 10⁻⁶. 18 cm -3 .

[0067] In some feasible implementations, the growth temperature of the n-type coating 104 can be between 800℃ and 1200℃.

[0068] For example, the growth temperature of the n-type coating 104 can be one of 800℃, 900℃, 1000℃, 1100℃, or 1200℃. Of course, the growth temperature of the n-type coating 104 can also be other values ​​between 800℃ and 1200℃.

[0069] In some feasible implementations, the growth thickness of the n-type coating layer 104 can be between 0.5 μm and 1.5 μm.

[0070] For example, the growth thickness of the n-type coating 104 can be 0.5 μm, 1.0 μm, or 1.5 μm. Of course, the thickness of the n-type coating 104 can also be other values ​​between 0.5 μm and 1.5 μm.

[0071] In one specific implementation, the n-type coating layer 104 is grown at a temperature of 1020℃ and has a thickness of 1.0 μm.

[0072] Step S132: Grow an n-type waveguide layer 105 on the n-type cladding layer 104.

[0073] In this step, the n-type waveguide layer 105 is an n-type doped aluminum gallium nitride alloy (n-Al). 0.3 Ga 0.7 Specifically, the growth environment of the n-type waveguide layer 105 can be the same as that of the n-type cladding layer 104. The growth thickness of the n-type waveguide layer 105 can be 80 nm.

[0074] Step S133: Grow a quantum well 106 on the n-type waveguide layer 105.

[0075] In this step, the quantum well 106 can be a periodic structure, with each period including a well structure and a barrier structure (not shown in the figure) grown sequentially. Step S133 may include steps S1331 to S1333.

[0076] Step S1331: Grow a well structure on the n-type waveguide layer 105.

[0077] In this step, the growth environment of the trap structure includes: growth pressure maintained at 150 mbar, source flow rate: 18 sccm for TMAl, 12 sccm for trimethylgallium TMGa, and 6000 sccm for NH3.

[0078] Step S1332: Use NH3 to flush the trap structure for the first preset time.

[0079] In this step, the purpose of flushing the trap structure is to suppress AlGaN intermixing. The first preset time can be 1s-5s.

[0080] In one specific implementation, the first preset time can be 2 seconds.

[0081] Step S1333: Grow a barrier structure on the well structure.

[0082] In this step, the growth environment for the well structure and the barrier structure is the same, but the Al composition in the barrier structure is greater than that in the well structure to provide sufficient band-level confinement carriers. The well structure can be Al... 0.25 Ga 0.75 N, the barrier structure can be Al 0.45 Ga 0.55 N.

[0083] In some feasible implementations, the growth temperature of the quantum well 106 can be 600℃-1000℃.

[0084] For example, the growth temperature of quantum well 106 can be 600°C, 800°C, or 1000°C. Of course, the growth temperature of quantum well 106 can also be other values ​​between 600°C and 1000°C.

[0085] In one specific implementation, the growth temperature of the quantum well 106 is 880°C.

[0086] In some feasible implementations, the growth thickness of the well structure can be 1nm-4nm, the growth thickness of the barrier structure can be 10nm-15nm, and the number of periods of the quantum well 106 can be 3-8.

[0087] For example, the growth thickness of the well structure can be 2 nm, 3 nm or 4 nm, the growth thickness of the barrier structure can be 10 nm, 12 nm or 15 nm, and the number of periods of the quantum well 106 can be 3, 5 or 7.

[0088] In one specific implementation, the growth thickness of the well structure is 2.5 nm, the growth thickness of the barrier structure is 13 nm, the number of periods is 5, the total growth thickness of the quantum well 106 is 5 × (2.5 nm + 13 nm) = 77.5 nm, and the peak wavelength is 275 nm.

[0089] Step S134: Grow a p-type electron blocking layer 107 on the quantum well 106.

[0090] In this step, the purpose of growing the p-type electron blocking layer 107 is to block electron overflow and reduce Auger recombination. The p-type electron blocking layer 107 can be p-Al. 0.4 Ga 0.6 N:Mg. The growth environment for the p-type electron blocking layer 107 may include a pressure of 150 mbar and a flow rate of 0.15 sccm for magnesia-Cp2Mg.

[0091] In some feasible implementations, the growth temperature of the p-type electron blocking layer 107 is 800℃-1000℃, and the growth thickness of the p-type electron blocking layer 107 is 80nm-120nm.

[0092] For example, the growth temperature of the p-type electron blocking layer 107 can be 800°C, 900°C or 1000°C, and the growth thickness of the p-type electron blocking layer 107 can be 80nm, 100nm or 120nm.

[0093] In one specific implementation, the growth temperature of the p-type electron blocking layer 107 is 960℃, and the growth thickness of the p-type electron blocking layer 107 is 100nm.

[0094] After step S13 is completed, the following can be obtained: Figure 2 The structure shown.

[0095] Step S14: Etch multiple annular cavities 10a on the p-type electron blocking layer 107 to form an annular photonic crystal; wherein, the center of the annular cavity 10a coincides with the center of the p-type electron blocking layer 107, and the etching direction of the annular cavity 10a is opposite to the growth direction of the p-type electron blocking layer 107; the multiple annular cavities 10a are spaced apart, and the depth of the multiple annular cavities 10a is greater than zero and less than or equal to the sum of the thicknesses of the p-type electron blocking layer 107 and the quantum well 106.

[0096] Figure 3 This is a schematic diagram of the fabrication process of the first type of ring photonic crystal provided in the embodiments of this application.

[0097] Among some feasible implementation methods, see Figure 3 As shown, step S14 may include steps S141 to S144.

[0098] Step S141: Coat the first mask layer b1 on the p-type electron blocking layer 107.

[0099] In this step, the first mask layer b1 can be made of photoresist material and uniformly covered on the surface of the p-type electron blocking layer 107 by spin coating.

[0100] After step S141 is completed, the following can be obtained: Figure 3 The structure shown in (a) is shown in the middle.

[0101] Step S142: The first mask layer b1 is etched using electron beam lithography to form multiple annular grooves; wherein the etching depth of the annular grooves is the same as the coating thickness of the first mask layer b1.

[0102] In this step, the bottom of the etched annular groove exposes the surface of the p-type electron blocking layer 107.

[0103] Specifically, the centers of multiple annular grooves coincide, and the centers of multiple annular grooves coincide at the center of the p-type electron blocking layer 107. The multiple annular grooves are distributed in concentric circles, and the radii increase sequentially.

[0104] After step S142 is completed, the following can be obtained: Figure 3 The structure shown in (b) is as follows.

[0105] Step S143: The p-type electron blocking layer 107 is etched using inductively coupled plasma technology to form a ring photonic crystal; the ring photonic crystal includes multiple ring cavities 10a, and the ring cavities 10a correspond one-to-one with the ring grooves.

[0106] In this step, the p-type electron blocking layer 107 is etched according to the position and shape of the annular groove. The etching direction is opposite to the growth direction of the p-type electron blocking layer 107. The etching forms multiple annular cavities 10a spaced apart, so that the annular cavities 10a correspond one-to-one with the annular grooves, and the center of the annular cavity 10a coincides with the center of the p-type electron blocking layer 107.

[0107] After step S143 is completed, the following can be obtained: Figure 3 The structure shown in (c) is as follows.

[0108] Step S143: Remove the first mask layer b1 that has not been etched.

[0109] In this step, the remaining first mask layer b1 is removed, residual photoresist material on the sample surface is cleaned, and the surface of the p-type electron blocking layer 107 is exposed to ensure the structural strength of subsequent structural layers.

[0110] Figure 4A This is the second schematic diagram of the process for fabricating a chip based on a ring photonic crystal, as provided in the embodiments of this application. Figure 4B yes Figure 4A Top view.

[0111] After step S143 is completed, the following can be obtained: Figure 4A and Figure 4B The structure shown. In Figure 4A and Figure 4B In the process, the depth of the annular cavity 10a is greater than zero and less than the growth thickness of the p-type electron blocking layer 107.

[0112] The multiple concentric ring arrays of ring cavities 10a formed by the above steps can effectively confine and control photons of specific wavelengths. A periodic refractive index distribution is formed between adjacent ring cavities 10a. This structural characteristic ensures that photons are affected by the photon bandgap during propagation, allowing them to propagate only within a specific frequency range, thus achieving precise control over photons. The ring photonic crystal can effectively adjust the directionality of the photon bandgap, forming uniform light waves from all sides, thereby suppressing laser leakage from non-emitting areas on the sides, improving light extraction efficiency. Furthermore, the periodic distribution of the ring photonic crystal ensures a high degree of matching with the laser mode emitted from the sides, guaranteeing beam quality. The radius, spacing, and etching depth of the ring cavities 10a can be designed and adjusted according to actual application requirements to meet the control requirements of photons of different wavelengths, providing a flexible structural basis for chip applications in optical communication, optical sensing, and other fields.

[0113] Figure 5 This is a schematic diagram of the ring photonic crystal provided in the embodiments of this application. Figure 5 In the middle (a) to (d), there are ring-shaped photonic crystals with different etching depths.

[0114] See Figure 5 As shown in (a), the etching depth of the annular cavity 10a is the growth thickness of the p-type electron blocking layer 107. In this implementation, the annular cavity 10a completely penetrates the p-type electron blocking layer 107, and the bottom of the annular cavity 10a exposes the surface of the quantum well 106.

[0115] See Figure 5 As shown in (b), the etching depth of the annular cavity 10a is greater than the growth thickness of the p-type electron blocking layer 107, and less than the sum of the growth thicknesses of the p-type electron blocking layer 107 and the quantum well 106. In this implementation, the annular cavity 10a penetrates the p-type electron blocking layer 107 and extends into the interior of the quantum well 106.

[0116] See Figure 5 As shown in (c), the etching depth of the annular cavity 10a is equal to the sum of the growth thicknesses of the p-type electron blocking layer 107 and the quantum well 106. In this implementation, the annular cavity 10a penetrates the p-type electron blocking layer 107 and the quantum well 106, and the bottom of the annular cavity 10a exposes the surface of the n-type waveguide layer 105.

[0117] See Figure 5As shown in (d), the etching depths of the multiple annular cavities 10a are different. The first annular cavity 10a-1 is located within the p-type electron blocking layer 107, and its etching depth is less than the growth thickness of the p-type electron blocking layer 107, such as 60 nm. The second annular cavity 10a-2 penetrates the p-type electron blocking layer 107 and extends into the quantum well 106, and its etching depth is less than the sum of the growth thicknesses of the p-type electron blocking layer 107 and the quantum well 106. The third annular cavity 10a-3 penetrates both the p-type electron blocking layer 107 and the quantum well 106, and its etching depth is equal to the sum of the thicknesses of the p-type electron blocking layer 107 and the quantum well 106.

[0118] In some feasible implementations, the etching thickness D of the annular cavity 10a can be 50nm-120nm. The distance L between any two adjacent annular cavities 10a can be 10nm-40nm, and the number of annular cavities 10a is 5-10. The etching width D of the annular cavity 10a is the dimension along the length or width direction of the substrate 101, that is, the dimension along the diameter direction of the inner or outer circle of the annular cavity 10a. The distance L between any two adjacent annular cavities 10a refers to the minimum spacing between two adjacent annular cavities 10a.

[0119] See also Figure 5 As shown in (d), the distance between the first annular cavity 10a-1 and the second annular cavity 10a-2 is L1, and the distance between the second annular cavity 10a-2 and the third annular cavity 10a-3 is L2. L1 and L2 can be equal or unequal to adapt to the usage requirements of different annular photonic crystals. Here, L includes L1 and L2.

[0120] For example, the etching width D of the annular cavity 10a can be 50nm, 70nm, 90nm or 120nm, the distance L between any two adjacent annular cavities 10a can be 15nm, 25nm or 35nm, and the number of annular cavities 10a can be 6, 7, 8, 9 or 10.

[0121] In one specific implementation, the etching width D of the annular cavity 10a is 70nm, the distance L between any two adjacent annular cavities 10a can be 30nm, and the number of annular cavities 10a is 6.

[0122] Thus, the structure of the multiple annular cavities 10a provided in this application embodiment can be flexibly adjusted. The etching depth between the multiple annular cavities 10a can be the same or different, and the distance between any one annular cavity 10a and its two adjacent annular cavities 10a can be the same or different.

[0123] Figure 6This is the third schematic diagram of the process for fabricating a chip based on a ring photonic crystal, as provided in the embodiments of this application.

[0124] Step S15: Grow a p-type extended contact layer 108 on the side of the p-type electron blocking layer 107 away from the quantum well 106.

[0125] Combination Figure 1 and Figure 6 As shown, in step S16, the p-type extended contact layer 108 serves both as a current spreader and an ohmic contact. The growth environment of the p-type extended contact layer 108 includes a growth temperature of 950°C and a pressure of 150 mbar.

[0126] In some feasible implementations, the p-type extended contact layer 108 is a graded structure from p-AlGaN+Mg doping to p-GaN. p-AlGaN+Mg doping can serve as a current spreading layer, and p-GaN can serve as an ohmic contact layer. Specifically, the Al composition in the p-type extended contact layer 108 changes from p-Al... 0.2 Ga 0.8 N+Mg doping is gradually transitioned to p-GaN, with a gradient in Al composition to achieve a smooth band transition, reduce the hole injection barrier, and improve carrier injection efficiency. The p-GaN can be grown to a thickness of 150 nm for ohmic contacts.

[0127] After step S15 is completed, the following can be obtained: Figure 6 The structure shown.

[0128] Step S16: Perform in-situ annealing.

[0129] In-situ annealing is a technique that involves annealing the material directly in the same equipment or environment used for material preparation, without removing the material or cooling it to room temperature. In this step, in-situ annealing can achieve p-type activation, improving crystal quality.

[0130] In one specific implementation, in-situ annealing can be performed under a nitrogen atmosphere at a temperature of 750°C for 20 minutes to activate the Mg-H complex and increase the hole concentration to >3 × 10⁻⁶. 17 cm -3 .

[0131] Figure 7 This is the fourth schematic diagram of the process for fabricating a chip based on a ring photonic crystal, as provided in the embodiments of this application. Figure 8 yes Figure 7 The top view shown in (c). Figure 7 The different steps for preparing the transparent conductive layer are shown in (a) to (d).

[0132] In some feasible implementations, after in-situ annealing, the fabrication method of the chip based on the ring photonic crystal provided in this application embodiment may further include steps S17 and S18.

[0133] Step S17: A patterned transparent conductive layer 109 is grown on the p-type extended contact layer 108; wherein the center of the patterned transparent conductive layer 109 coincides with the center of the p-type extended contact layer 108; and along the etching direction of the annular cavity 10a, the projection of the patterned transparent conductive layer 109 on the p-type extended contact layer 108 is located within the area enclosed by the multiple annular cavities 10a, and does not overlap with the multiple annular cavities 10a.

[0134] For example, the patterned transparent conductive layer 109 can be circular, and the center of the patterned transparent conductive layer 109 coincides with the center of the p-type extended contact layer 108.

[0135] Among some feasible implementation methods, see Figure 7 and Figure 8 As shown, step S17 may include steps S171 to S174.

[0136] Step S171: Grow a transparent conductive layer on the p-type extended contact layer 108.

[0137] In this step, a transparent conductive layer can be grown using MOCVD technology.

[0138] After step S171 is completed, the following can be obtained: Figure 7 In the structure shown in (a), a transparent conductive layer is uniformly covered on the surface of the p-type extended contact layer 108.

[0139] Step S172: Coat the second mask layer b2 on the transparent conductive layer.

[0140] In this step, the second mask layer b2 can be a photoresist material, as described in step S141 above.

[0141] After step S172 is completed, the following can be obtained: Figure 7 As shown in (b), the second mask layer b2 uniformly covers the surface of the p-type extended contact layer 108.

[0142] Step S173: Use photolithography to etch circular grooves in the second mask layer b2 to form a patterned mask layer.

[0143] In this step, the second mask layer b2 is etched using photolithography to form a circular groove, as described in step S142 above.

[0144] After etching is complete, the center of the circular groove coincides with the center of the transparent conductive layer. Along the etching direction of the annular cavity 10a, the projection of the circular groove onto the transparent conductive layer lies within the area enclosed by multiple annular cavities 10a, and does not overlap with them. In other words, the circular groove can be understood as a circular region formed by taking the inner diameter of the innermost annular cavity 10a as its radius, with the center of the transparent conductive layer as the circle, ensuring that the transparent conductive layer does not overlap or cover the annular photonic crystal.

[0145] After step S173 is completed, the following can be obtained: Figure 7 The structure shown in (c) is as follows.

[0146] Step S174: The patterned mask layer and the transparent conductive layer covered by the patterned mask layer are etched using inductively coupled plasma technology to obtain the patterned transparent conductive layer 109.

[0147] In this step, the patterned mask layer and the underlying transparent conductive layer are etched to a depth equal to the sum of the growth thicknesses of the patterned mask layer and the transparent conductive layer.

[0148] After step S174 is completed, the following can be obtained: Figure 7 (d) and Figure 8 The structure shown.

[0149] Step S18: Grow electrode 110 on patterned transparent conductive layer 109.

[0150] In this step, see Figure 9 As shown, electrodes 110 are grown simultaneously on the surfaces of the patterned transparent conductive layer 109 and the p-type extended contact layer 108. The electrode material 110 is uniformly deposited through a vapor deposition process to form an ohmic contact, ensuring efficient current injection.

[0151] After the electrode 110 is grown, it is processed by peeling to form a structure with the same shape as the patterned transparent conductive layer 109, so that the electrode 110 can just cover the patterned transparent conductive layer 109. At this time, annealing is performed to optimize ohmic contact performance and reduce contact resistance. After step S18 is completed, the chip 100 based on the ring photonic crystal is obtained.

[0152] In some feasible implementations, step S18 may be followed by step S19.

[0153] Step S19: Deposit a passivation layer SiN on the surface of the chip 100 based on the ring photonic crystal, thin or dic the substrate 101, and package it.

[0154] In some feasible implementations, the fabrication method of the chip based on the ring photonic crystal may also include step S10 before step S11.

[0155] Step S10: Pre-baking substrate 101 for the second preset time.

[0156] In this step, pre-baking can effectively remove moisture and organic matter adsorbed on the surface of substrate 101. The pre-baking environment may include: a pre-baking temperature of 1050 °C, an H2 atmosphere, and a second preset time of 5 minutes.

[0157] The method for fabricating a chip based on a ring photonic crystal provided in this application combines electron beam lithography with secondary epitaxy, eliminating the need for backfilling the ring cavity 10a. This method offers greater simplicity and flexibility, solving complex design and simulation challenges, and addressing the polarization sensitivity issues of related methods. The resulting ring photonic crystal-based chip 100 effectively improves light extraction efficiency, reduces process damage, facilitates large-scale development, enhances new functions and performance, and significantly improves production yield.

[0158] Figure 10 This is a schematic flowchart of the second method for fabricating a chip based on a ring photonic crystal provided in the embodiments of this application; Figure 11 This is a schematic diagram of the fabrication method of the second chip based on a ring photonic crystal provided in the embodiments of this application.

[0159] See Figure 10 and Figure 11 As shown, the second method for fabricating a chip based on a ring photonic crystal provided in this application includes the following steps S21 to S26.

[0160] Step S21: A nucleation layer 102 is grown on the substrate 101; the growth temperature of the nucleation layer 102 is the first temperature.

[0161] Step S21 can use the same preparation process as step S11 in the preparation method described in the previous embodiment.

[0162] Step S22: A superlattice structure 103 is grown on the side of the nucleation layer 102 away from the substrate 101; the growth temperature of the superlattice structure 103 is a second temperature, and the first temperature is lower than the second temperature. The superlattice structure 103 includes an AlN layer and an AlGaN layer arranged sequentially, and the AlN layer and the AlGaN layer have the same thickness.

[0163] Step S22 can use the same preparation process as step S12 in the preparation method described in the previous embodiment.

[0164] Step S23: An n-type cladding layer 104, an n-type waveguide layer 105, a quantum well 106, a p-type electron blocking layer 107, and a p-type extended contact layer 108 are sequentially grown on the side of the superlattice structure 103 away from the nucleation layer 102. The Al composition in the n-type cladding layer 104 gradually decreases from the side closer to the superlattice structure 103 to the side farther away from the superlattice structure 103.

[0165] Step S23 can use the same preparation process as step S13 or step S15 in the preparation method described above.

[0166] After step S23 is completed, the following can be obtained: Figure 11 The structure shown in (a) is shown in the middle.

[0167] Step S24: Etch multiple annular cavities 10a on the p-type extended contact layer 108 to form an annular photonic crystal; wherein, the center of the annular cavity 10a coincides with the center of the p-type electron blocking layer 107, and the etching direction of the annular cavity 10a is opposite to the growth direction of the p-type extended contact layer 108; the multiple annular cavities 10a are spaced apart, and the depth of the multiple annular cavities 10a is greater than the thickness of the p-type extended contact layer 108, and less than or equal to the sum of the thicknesses of the p-type extended contact layer 108, the p-type electron blocking layer 107, and the quantum well 106.

[0168] Step S24 can employ the same preparation process as S14 in the aforementioned embodiment. After step S24 is completed, the desired result can be obtained as shown below. Figure 11 The structure shown in (b) is shown in the middle.

[0169] Step S25: Perform in-situ annealing.

[0170] In particular, step S25 can use the same preparation process as S16 in the preparation method of the aforementioned embodiment.

[0171] Step S26: A patterned transparent conductive layer 109 is grown on the p-type extended contact layer 108; wherein, the patterned transparent conductive layer 109 can be circular, and the center of the patterned transparent conductive layer 109 coincides with the center of the p-type extended contact layer 108; and along the etching direction of the annular cavity 10a, the projection of the patterned transparent conductive layer 109 on the p-type extended contact layer 108 is located within the area enclosed by multiple annular cavities 10a, and does not overlap with the multiple annular cavities 10a.

[0172] Step S26 can use the same preparation process as step S17 in the preparation method described in the previous embodiment.

[0173] Step S27: Grow electrode 110 on patterned transparent conductive layer 109.

[0174] Step S27 can employ the same preparation process as step S18 in the aforementioned embodiment. After step S27 is completed, the desired result can be obtained. Figure 11 The chip 100 based on a ring photonic crystal is shown in (c).

[0175] In some feasible implementations, step S27 may be followed by step S28.

[0176] Step S28: Deposit a passivation layer SiN on the surface of the chip 100 based on the ring photonic crystal, thin or dic the substrate 101, and package it.

[0177] Step S28 can use the same preparation process as step S19 in the preparation method described in the previous embodiment.

[0178] In some feasible implementations, the chip fabrication method based on a ring photonic crystal provided in the embodiments of this application may include step S20 before step S21.

[0179] Step S20: Pre-bake the substrate 101.

[0180] Step S20 can use the same preparation process as step S10 in the preparation method described in the previous embodiment.

[0181] It should be emphasized that the chip fabrication method based on a ring photonic crystal provided in this embodiment differs from the aforementioned chip fabrication method based on a ring photonic crystal in that the etching position of the ring photonic crystal is different. In this implementation, the ring cavity 10a is fabricated in the p-type extended contact layer 108 structure. The etching depth of the ring cavity 10a is greater than the growth thickness of the p-type extended contact layer 108, and less than or equal to the sum of the thicknesses of the p-type extended contact layer 108, the p-type electron blocking layer 107, and the quantum well 106. The fabrication process and parameters used in the remaining steps can be the same as those provided in the aforementioned embodiment.

[0182] Corresponding to the aforementioned embodiments of the fabrication method of a chip based on a ring photonic crystal, this application also provides a chip 100 based on a ring photonic crystal.

[0183] Figure 12 This is a schematic diagram of the structure of a chip 100 based on a ring photonic crystal provided in an embodiment of this application. Figure 12 The diagrams (a) to (d) show different distributions of the ring-shaped photonic crystal.

[0184] See Figure 12As shown, the chip 100 based on a ring photonic crystal provided in this application embodiment includes a substrate 101, a nucleation layer 102, a superlattice structure 103, an n-type cladding layer 104, an n-type waveguide layer 105, a quantum well 106, a p-type electron blocking layer 107, a p-type extended contact layer 108, a ring photonic crystal, a patterned transparent conductive layer 109, and an electrode 110.

[0185] The nucleation layer 102 is grown on the substrate 101; the growth temperature of the nucleation layer 102 is the first temperature.

[0186] The nucleation layer 102 can be prepared by step S11 or step S21 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0187] The superlattice structure 103 is grown on the side of the nucleation layer 102 away from the substrate 101; the growth temperature of the superlattice structure 103 is a second temperature, and the first temperature is lower than the second temperature. The superlattice structure 103 includes an AlN layer and an AlGaN layer arranged sequentially, and the AlN layer and the AlGaN layer have the same thickness.

[0188] The superlattice structure 103 can be prepared by step S12 or step S22 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0189] The n-type cladding layer 104 grows on the side of the superlattice structure 103 away from the nucleation layer 102; the Al composition in the n-type cladding layer 104 gradually decreases from the side closer to the superlattice structure 103 to the side farther away from the superlattice structure 103.

[0190] The n-type cladding layer 104 can be prepared by step S131 or step S23 in the embodiment of the above-described method for fabricating a chip based on a ring photonic crystal.

[0191] The n-type waveguide layer 105 is grown on the side of the n-type cladding layer 104 that is away from the superlattice structure 103.

[0192] The n-type waveguide layer 105 can be prepared by step S132 or step S23 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0193] The quantum well 106 is grown on the side of the n-type waveguide layer 105 away from the n-type cladding layer 104.

[0194] The quantum well 106 can be prepared by step S133 or step S23 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0195] p-type electron blocking layer 107 is grown on the side of quantum well 106 away from n-type waveguide layer 105.

[0196] The p-type electron blocking layer 107 can be prepared by step S134 or step S23 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0197] p-type extended contact layer 108 is grown on the side of p-type electron blocking layer 107 away from quantum well 106.

[0198] The p-type extended contact layer 108 can be prepared by step S15 or step S23 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0199] The ring photonic crystal includes multiple ring cavities 10a, which are at least disposed in a p-type electron blocking layer 107. The center of the ring cavity 10a coincides with the center of the p-type electron blocking layer 107, and the etching direction of the ring cavity 10a is opposite to the growth direction of the p-type electron blocking layer 107. The multiple ring cavities 10a are spaced apart.

[0200] The ring photonic crystal can be prepared by step S14 or step S24 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0201] A patterned transparent conductive layer 109 is grown on the side of the p-type extended contact layer 108 that is away from the p-type electron blocking layer 107.

[0202] The patterned transparent conductive layer 109 can be prepared by step S17 or step S26 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0203] Electrode 110 is disposed on patterned transparent conductive layer 109.

[0204] The electrode 110 can be prepared by step S18 or step S27 in the embodiment of the above-described method for preparing a chip based on a ring photonic crystal.

[0205] See also Figure 12 As shown in (a), the annular cavity 10a is disposed in the p-type electron blocking layer 107, and the etching depth of the annular cavity 10a is greater than zero and less than or equal to the thickness of the p-type electron blocking layer 107.

[0206] See also Figure 12 As shown in (b), an annular cavity 10a is disposed between the p-type electron blocking layer 107 and the quantum well 106. The etching depth of the annular cavity 10a is greater than the thickness of the p-type electron blocking layer 107 and less than or equal to the sum of the thicknesses of the p-type electron blocking layer 107 and the quantum well 106.

[0207] Specifically, in Figure 12In the implementation shown in (a) and (b), the annular cavity 10a can be prepared by step S14 in the embodiment of the above-described method for preparing a chip based on annular photonic crystal.

[0208] See also Figure 12 In (c), an annular cavity 10a is disposed between the p-type extended contact layer 108 and the p-type electron blocking layer 107. The etching depth of the annular cavity 10a is greater than the growth thickness of the p-type extended contact layer 108, and less than or equal to the sum of the thicknesses of the p-type extended contact layer 108 and the p-type electron blocking layer 107.

[0209] See also Figure 12 In the middle (d), an annular cavity 10a is disposed in the p-type extended contact layer 108, the p-type electron blocking layer 107 and the quantum well 106. The etching depth of the annular cavity 10a is greater than the sum of the thicknesses of the p-type extended contact layer 108 and the p-type electron blocking layer 107, and less than or equal to the sum of the thicknesses of the p-type extended contact layer 108, the p-type electron blocking layer 107 and the quantum well 106.

[0210] Specifically, in Figure 12 In the implementations shown in (c) and (d), the annular cavity 10a can be prepared by step S25 in the embodiment of the above-described method for fabricating a chip based on annular photonic crystal.

[0211] It should be noted that, upon considering the specification and practicing the application disclosed herein, those skilled in the art will readily conceive of other embodiments of this application. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0212] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The true scope is indicated by this application.

Claims

1. A method for fabricating a chip based on a ring photonic crystal, characterized in that, include: A nucleation layer is grown on a substrate; the growth temperature of the nucleation layer is a first temperature. A superlattice structure is grown on the side of the nucleation layer away from the substrate; wherein the growth temperature of the superlattice structure is a second temperature, the first temperature being lower than the second temperature, and the superlattice structure includes periodically arranged AlN layers and AlGaN layers; the AlN layers and the AlGaN layers have the same thickness; An n-type cladding layer, an n-type waveguide layer, a quantum well, and a p-type electron blocking layer are grown sequentially on the side of the superlattice structure away from the nucleation layer. Multiple annular cavities are etched on the p-type electron blocking layer to form an annular photonic crystal; wherein the center of the annular cavity coincides with the center of the p-type electron blocking layer, and the etching direction of the annular cavity is opposite to the growth direction of the p-type electron blocking layer; the multiple annular cavities are spaced apart, and the depth of the multiple annular cavities is greater than zero and less than or equal to the sum of the thickness of the p-type electron blocking layer and the quantum well; A p-type extended contact layer is grown on the side of the p-type electron blocking layer opposite to the quantum well; Perform in-situ annealing.

2. The method for fabricating a chip based on a ring photonic crystal according to claim 1, characterized in that, The number of annular cavities is 5-10, and the thickness of the annular cavities is 50nm-120nm.

3. The method for fabricating a chip based on a ring photonic crystal according to claim 1, characterized in that, Multiple annular cavities are etched onto the p-type electron blocking layer to form an annular photonic crystal, including: A first mask layer is coated on the p-type electron blocking layer; The first mask layer is etched using electron beam lithography to form multiple annular grooves; wherein the etching depth of the annular grooves is the same as the coating thickness of the first mask layer. The p-type electron blocking layer is etched using inductively coupled plasma technology to form a ring photonic crystal; the ring photonic crystal includes multiple ring cavities, each corresponding to a ring groove. Remove the first mask layer that has not been etched.

4. The method for fabricating a chip based on a ring photonic crystal according to claim 1, characterized in that, The Al composition of the n-type coating layer gradually decreases from the side closer to the superlattice structure to the side farther away from the superlattice structure.

5. The method for fabricating a chip based on a ring photonic crystal according to claim 1, characterized in that, The quantum well has a period number of 3-8; the quantum well includes a well structure and a barrier structure; After the well structure is grown, it is flushed with NH3 atmosphere for a first preset time, and then the barrier structure is regrown. The Al content in the barrier structure is greater than that in the well structure.

6. The method for fabricating a chip based on a ring photonic crystal according to claim 1, characterized in that, The Al composition in the p-type extended contact layer gradually decreases from the side closer to the p-type electron blocking layer to the side farther away from the p-type electron blocking layer.

7. The method for fabricating a chip based on a ring photonic crystal according to claim 1, characterized in that, After in-situ annealing, the fabrication method of the chip based on the ring photonic crystal further includes: A patterned transparent conductive layer is grown on the p-type extended contact layer; wherein the center of the patterned transparent conductive layer coincides with the center of the p-type extended contact layer; along the etching direction of the annular cavity, the projection of the patterned transparent conductive layer on the p-type extended contact layer is located within the area enclosed by the plurality of annular cavities and does not overlap with the plurality of annular cavities; Electrodes are grown on the patterned transparent conductive layer.

8. A method for fabricating a chip based on a ring photonic crystal, characterized in that, include: A nucleation layer is grown on a substrate; the growth temperature of the nucleation layer is a first temperature. A superlattice structure is grown on the side of the nucleation layer away from the substrate; the growth temperature of the superlattice structure is a second temperature, and the first temperature is lower than the second temperature; the superlattice structure includes an AlN layer and an AlGaN layer arranged sequentially; the AlN layer and the AlGaN layer have the same thickness. On the side of the superlattice structure away from the nucleation layer, an n-type cladding layer, an n-type waveguide layer, a quantum well, a p-type electron blocking layer, and a p-type extended contact layer are grown sequentially. Multiple annular cavities are etched on the p-type extended contact layer to form an annular photonic crystal; wherein the center of the annular cavity coincides with the center of the p-type extended contact layer, and the etching direction of the annular cavity is opposite to the growth direction of the p-type extended contact layer; the multiple annular cavities are spaced apart, and the depth of the multiple annular cavities is greater than the thickness of the p-type extended contact layer, and less than or equal to the sum of the thicknesses of the p-type extended contact layer, the p-type electron blocking layer, and the quantum well; Perform in-situ annealing.

9. A chip based on a ring photonic crystal, characterized in that, The chip is fabricated using the method described in any one of claims 1 to 8, wherein the chip based on the ring photonic crystal comprises: Substrate; A nucleation layer is grown on the substrate; the growth temperature of the nucleation layer is a first temperature. A superlattice structure is grown on the side of the nucleation layer away from the substrate; the growth temperature of the superlattice structure is a second temperature, where the first temperature is lower than the second temperature; the superlattice structure includes an AlN layer and an AlGaN layer arranged sequentially; the AlN layer and the AlGaN layer have the same thickness. An n-type cladding layer is grown on the side of the superlattice structure away from the nucleation layer; An n-type waveguide layer is grown on the side of the n-type cladding layer that is away from the superlattice structure. A quantum well is grown on the side of the n-type waveguide layer away from the n-type cladding layer. A p-type electron blocking layer is grown on the side of the quantum well away from the n-type waveguide layer; A p-type extended contact layer is grown on the side of the p-type electron blocking layer opposite to the quantum well; A ring photonic crystal, comprising a plurality of ring cavities, wherein the plurality of ring cavities are at least disposed in the p-type electron blocking layer, the center of the ring cavity coincides with the center of the p-type electron blocking layer, and the etching direction of the ring cavity is opposite to the growth direction of the p-type electron blocking layer; the plurality of ring cavities are spaced apart.

10. The chip based on a ring photonic crystal according to claim 9, characterized in that, The annular cavity is disposed in the p-type electron blocking layer, and the depth of the annular cavity is greater than zero and less than or equal to the thickness of the p-type electron blocking layer. Alternatively, the annular cavity is disposed between the p-type electron blocking layer and the quantum well, wherein the depth of the annular cavity is greater than the thickness of the p-type electron blocking layer and less than or equal to the sum of the thicknesses of the p-type electron blocking layer and the quantum well; Alternatively, the annular cavity is disposed on the p-type extended contact layer and the p-type electron blocking layer, wherein the depth of the annular cavity is greater than the thickness of the p-type extended contact layer and less than or equal to the sum of the thicknesses of the p-type electron blocking layer and the p-type extended contact layer; Alternatively, the annular cavity is disposed in the p-type extended contact layer, the p-type electron blocking layer, and the quantum well, wherein the depth of the annular cavity is greater than the sum of the thicknesses of the p-type extended contact layer and the p-type electron blocking layer, and less than or equal to the sum of the thicknesses of the p-type extended contact layer, the p-type electron blocking layer, and the quantum well.

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