Memory bank ordering method, electronic device, and readable storage medium

Abstract

This application discloses a storage sorting method, an electronic device, and a readable storage medium, belonging to the field of computer science. The method includes: identifying sorting operators in a target object obtained from source code using a compiler; in response to the existence of a comparison-based sorting operator in the target object, obtaining a value of a target sorting dimension, wherein the target sorting dimension is at least one dimension used for sorting; in response to a value of the target sorting dimension being less than a sorting upper limit value, performing parallel sorting of multiple storage objects to be processed using a combination of sorting instructions and comparison instructions in a first sorting method; wherein the sorting upper limit value is related to the number of storage objects to be processed; in response to a value of the target sorting dimension being greater than the sorting upper limit value, performing parallel sorting of the multiple storage objects to be processed using a combination of the sorting instructions and the comparison instructions in a second sorting method; wherein the second sorting method is different from the first sorting method.

Description

Technical Field

[0001] This application belongs to the field of computer science, and specifically relates to a storage sorting method, an electronic device, and a readable storage medium. Background Technology

[0002] Sorting is a common fundamental computation in artificial intelligence computing, data preprocessing, and high-performance computing scenarios.

[0003] In the process of data sorting calculation, related technologies often use a fixed sorting method to sort data in all situations, which often results in low sorting efficiency. Summary of the Invention

[0004] This application provides a storage sorting method, an electronic device, and a readable storage medium, which can solve the problem of low sorting efficiency in related technologies.

[0005] Firstly, a storage sorting method is provided, including:

[0006] The compiler identifies sorting operators in target objects obtained from source code.

[0007] In response to the existence of a comparison-based sorting operator in the target object, the value of the target sorting dimension is obtained, wherein the target sorting dimension is at least one dimension used for sorting;

[0008] In response to the target sorting dimension being less than the upper limit of the sorting, multiple storage units to be processed are sorted in parallel using a first sorting method through a combination of sorting instructions and comparison instructions; the upper limit of the sorting is related to the number of storage units to be processed.

[0009] In response to the target sorting dimension being greater than the upper limit of the sorting, the plurality of storage units to be processed are sorted in parallel using the sorting instruction and the comparison instruction in a second sorting method; the second sorting method is different from the first sorting method.

[0010] Each of the storage units to be processed contains multiple elements. The sorting instruction is used to sort the multiple elements contained in the storage unit to be processed. The comparison instruction is used to compare the first element in the first storage unit to be processed with the second element in the second storage unit to be processed. The position of the first element in the first storage unit to be processed and the position of the second element in the second storage unit to be processed correspond to each other. The first element can be any element in the first storage unit to be processed, and the second element can be any element in the second storage unit to be processed. The larger of the first element and the second element is placed in either the first storage unit to be processed or the second storage unit to be processed. Both the first storage unit to be processed and the second storage unit to be processed are one of the multiple storage units to be processed.

[0011] Secondly, a storage sorting device is provided, comprising:

[0012] The identification module is used by the compiler to identify sorting operators in target objects obtained from source code.

[0013] The acquisition module is used to acquire the value of the target sorting dimension in response to the existence of a comparison-based sorting operator in the target object, wherein the target sorting dimension is at least one dimension used for sorting.

[0014] The processing module is configured to, in response to the target sorting dimension being less than the upper limit of sorting, perform parallel sorting of multiple storage entities to be processed in a first sorting manner using sorting instructions and comparison instructions; the upper limit of sorting is associated with the number of storage entities to be processed.

[0015] The processing module is further configured to, in response to the target sorting dimension being greater than the upper limit of the sorting value, perform parallel sorting of the plurality of storage units to be processed using the sorting instruction and the comparison instruction in a second sorting method; the second sorting method is different from the first sorting method;

[0016] Each of the storage units to be processed contains multiple elements. The sorting instruction is used to sort the multiple elements contained in the storage unit to be processed. The comparison instruction is used to compare the first element in the first storage unit to be processed with the second element in the second storage unit to be processed. The position of the first element in the first storage unit to be processed and the position of the second element in the second storage unit to be processed correspond to each other. The first element can be any element in the first storage unit to be processed, and the second element can be any element in the second storage unit to be processed. The larger of the first element and the second element is placed in either the first storage unit to be processed or the second storage unit to be processed. Both the first storage unit to be processed and the second storage unit to be processed are one of the multiple storage units to be processed.

[0017] Thirdly, an electronic device is provided, including a processor and a memory, the memory storing a program or instructions that, when executed by the processor, implement the method as described in the first aspect.

[0018] Fourthly, a readable storage medium is provided, on which a program or instructions are stored, which, when executed by a processor, implement the method described in the first aspect.

[0019] Fifthly, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the method described in the first aspect.

[0020] In this embodiment, different sorting methods are used for parallel sorting when the target sorting dimension is less than the upper limit and when the target sorting dimension is greater than the upper limit, which can improve sorting efficiency to a certain extent. Moreover, both sorting methods use a combination of sorting and comparison instructions for parallel sorting. Thus, by flexibly combining sorting and comparison instructions, various sorting scenarios can be addressed, further improving the sorting efficiency of sorting operations performed under different conditions. Attached Figure Description

[0021] Figure 1 This is a flowchart of a memory sorting method provided in an embodiment of this application;

[0022] Figure 2 This is a schematic diagram of the data sorting process in the case where the number of storage units for the sorting dimension is less than the upper limit of the sorting value in the embodiments of this application;

[0023] Figure 3 This is a schematic diagram of the data sorting process in an embodiment of this application where the number of storage units for the sorting dimension is equal to the upper limit of the sorting value;

[0024] Figure 4 This is a schematic diagram of the data sorting process in an embodiment of this application where the number of storage volumes for the sorting dimension is greater than the upper limit of the sorting value;

[0025] Figure 5 This is a structural block diagram of a storage sorting device provided in an embodiment of this application;

[0026] Figure 6 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0028] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0029] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0030] Bitonic sort serves as a bridge between classical algorithms and modern parallel hardware. In specific AI scenarios, especially when hardware acceleration, low latency, and deterministic sorting operations are required, bitonic sort remains an important tool. The core theorem of bitonic sort states that comparison-exchange operations can transform a bitonic sequence of arbitrary length into a monotonic sequence (completely increasing or decreasing), and this process is highly parallel.

[0031] Due to its regularized data access pattern and good parallelism, bitonic sorting is often used in parallel processing platforms such as graphics processing units (GPUs) and artificial intelligence (AI) accelerators.

[0032] AI accelerators' sorting modules may have the capability of "multi-threaded parallelism" and "independent sorting," but they also have "limits to the number of parallel operations" and "limits to sorting capacity." When the non-sorting dimensions are insufficient to meet the hardware's limit to the number of parallel operations, or when the sorting dimensions exceed the hardware's limit to sorting capacity, the following problems arise:

[0033] When the non-sorting dimension is insufficient to meet the hardware's maximum number of parallel operations, invalid values ​​will be added to this dimension to reach the required number of parallel operations for sorting, resulting in wasted hardware resources and low utilization.

[0034] When the sorting dimension is greater than the hardware's sorting capacity limit, this dimension will be split and sorted multiple times, resulting in low sorting efficiency and poor performance.

[0035] The memory sorting method provided in this application can be applied to the case of bitone sorting and can perform parallel sorting compilation efficiently.

[0036] The memory sorting method provided in this application uses two types of instructions: Sorting Redirect (SRT) and Comparison Directive (CMP). Both SRT and CMP instructions have the capability to process a specified number of memory banks in parallel, for example, up to 8. The maximum number of parallel operations is, for example, 8, and the maximum sorting capacity is, for example, 8 × memory banks. The SRT instruction independently sorts (ascending or descending) the elements within, for example, the 8 memory banks. The CMP instruction performs pairwise comparisons and swaps between, for example, the 8 memory banks. Elements in each pair of banks are compared at their corresponding positions, and their positions are swapped according to a minimum-to-maximum (min-max) or maximum-to-min (max-min) pattern. This application uses SRT and CMP instructions to implement parallel bitoneic sorting.

[0037] Taking the sorting instruction (SRT) and comparison instruction (CMP) as examples, both capable of parallel processing of 8 memory banks, with a maximum parallel processing limit of 8, the memory bank sorting method provided in this application can be applied to the compilation process. The overall technical approach is as follows:

[0038] During compilation, the compiler first identifies the sorting operator (SortOp) in the target object, such as the computation graph or intermediate representation (IR), and parses its sorted and unsorted dimensions. For the following cases, appropriate efficient compilation methods are employed:

[0039] The number of storage banks for sorted dimensions does not exceed 8 × storage banks, and the number of non-sorted dimensions is less than 8. A multi-dimensional joint parallel approach is used to fill the parallel number and achieve bitonic sorting.

[0040] The number of storage banks in the sorting dimension is equal to 8 × storage banks. Bitonic sort is achieved by a combination of sorting instructions (SRT) and comparison instructions (CMP).

[0041] The number of storage banks in the sorting dimension exceeds 8 banks, and a combination of multi-level, high-step sorting instructions (SRT) and comparison instructions (CMP) is used to implement bitone sorting.

[0042] The memory sorting method provided in this application embodiment can be executed by electronic components or electronic devices, which may include a processor (CPU) and memory. For example, the memory sorting method provided in this application embodiment can be executed by an AI accelerator card having memory and a processor. The memory can be a Graphics Layer Buffer (GLB), a high-performance, low-power on-chip static random access memory (SRAM) used for temporary storage of the most frequently accessed data. It can be understood as a "high-speed dedicated cache" or "sticky memory" next to the GPU core or AI accelerator. The design goal of the graphics layer cache is to minimize access to the system main memory (DRAM), because accessing main memory is power-intensive and has high latency.

[0043] This application does not limit the specific form of the electronic device. For example, the electronic device can be various terminal devices or various servers, such as servers in data centers, cloud servers, etc., and there is no limitation here.

[0044] The storage sorting method provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0045] Figure 1 This is a flowchart of a memory sorting method provided in an embodiment of this application. (Refer to...) Figure 1 The memory sorting method provided in this application embodiment may include:

[0046] Step 110: Identify sorting operators in the target object obtained from the source code using the compiler;

[0047] A compiler is a software program that completes the compilation process. It first performs lexical, syntactic, and semantic analysis on the source code, then performs multi-level optimization, and finally efficiently and correctly converts it into machine code or bytecode that a computer can directly execute or that can be executed by a virtual machine. The compilation process is carried out by the CPU executing the compiler software program.

[0048] In this embodiment, the target object obtained from the source code can be a computation graph or an intermediate representation. The intermediate representation (IR) is an intermediate form used by the compiler between the source code and machine code; it is the compiler's "universal language." Taking the target object as an intermediate representation as an example, the compiler can recognize all sorting operators in the IR.

[0049] In the embodiments of this application, the sorting operators in the target object may include comparison-based sorting operators or non-comparison sorting operators. The memory sorting method provided in the embodiments of this application can be applied to comparison-based sorting operators, including but not limited to bitonic sorting, odd-even sorting, etc.

[0050] Step 120: In response to the existence of a comparison-based sorting operator in the target object, obtain the value of the target sorting dimension, wherein the target sorting dimension is at least one dimension used for sorting.

[0051] The sorting dimensions in this application embodiment may include parallel processing unit (PE) dimension, width (W) dimension, channel group (Gc) dimension, and memory bank dimension. The target sorting dimension may be the channel group dimension and the memory bank dimension. This application embodiment may default to sorting by memory bank. When sorting by memory bank by default, the target sorting dimension may be the channel group dimension.

[0052] In the embodiments of this application, the sorting dimension can refer to sorting along one dimension or sorting along two combined dimensions. For example, in a layout of [N=2, W=4, Bank], sorting is performed along the innermost bank dimension, with the target sorting dimension referring to the bank dimension; or, in a layout of [N=4, Gc=2, W=2, Bank], sorting is performed along the combined Gc×Bank dimension, with the target sorting dimension referring to the Gc, Bank dimension.

[0053] Taking the layout [N=4,Gc=2,W=2,Bank] as an example, [N=4,Gc=2,W=2,Bank] is a block-based memory layout, often used for hardware optimization in parallel convolution computation or grouped matrix multiplication. The meaning of each dimension in this layout is analyzed below.

[0054] N=4 indicates 4 parallel processing units (PEs) or computational cores; Gc=2 indicates 2 channels per group (channel grouping) for grouped convolution; W=2 indicates that each PE processes 2 elements (vector width) at a time; this layout is particularly suitable for the parallelization of grouped convolution.

[0055] Here, channel grouping Gc is the "logical partition" of the algorithm, while width W is the "physical packaging" of the hardware. All channel data in the same group (Gc) must be stored contiguously in memory.

[0056] Width W refers to the number of elements in a single, consecutively loaded spatial dimension within the memory layout (e.g., the number of consecutive pixels along the width of an image). The size of W can be adjusted to accommodate different hardware (e.g., W=2 on a mobile ARM CPU, W=16 on a server CPU) element count.

[0057] Step 130: In response to the target sorting dimension being less than the upper limit of sorting, multiple storage units to be processed are sorted in parallel using a first sorting method through a combination of sorting instructions and comparison instructions; the upper limit of sorting is related to the number of storage units to be processed.

[0058] In this embodiment, the sorting upper limit can be set in units of memory blocks. For example, a sorting upper limit of 8 can represent 8 memory blocks to be processed. The target sorting dimension can be a channel grouping (Gc) dimension, and the value of the channel grouping (Gc) dimension can be 2, which represents 2 channels per group. In this case, the value of the target sorting dimension (i.e., 2) is less than the sorting upper limit (i.e., 8), and multiple memory blocks to be processed can be sorted in parallel using a first sorting method through a combination of sorting instructions and comparison instructions.

[0059] In the embodiments of this application, the combination of sorting instructions and comparison instructions can represent any number of sorting instructions and any number of comparison instructions. For example, one instruction combination method sequentially includes: one sorting instruction, one comparison instruction, and one sorting instruction. Another instruction combination method sequentially includes: one sorting instruction, one comparison instruction, one sorting instruction, two comparison instructions, one sorting instruction, three comparison instructions, and one sorting instruction. Thus, various different instruction combinations can be obtained through the combination of sorting instructions and comparison instructions, thereby being applicable to various different sorting situations. For example, the first instruction combination is used when the value of the target sorting dimension is less than the upper limit of the sorting value; the second instruction combination is used when the value of the target sorting dimension is greater than the upper limit of the sorting value; and the third instruction combination is used when the value of the target sorting dimension is equal to the upper limit of the sorting value.

[0060] Step 140: In response to the target sorting dimension value being greater than the sorting upper limit value, the plurality of storage units to be processed are sorted in parallel using a second sorting method through a combination of the sorting instruction and the comparison instruction; the second sorting method is different from the first sorting method.

[0061] Each of the storage units to be processed contains multiple elements. The sorting instruction is used to sort the multiple elements contained in the storage unit to be processed. The comparison instruction is used to compare the first element in the first storage unit to be processed with the second element in the second storage unit to be processed. The position of the first element in the first storage unit to be processed and the position of the second element in the second storage unit to be processed correspond to each other. The first element can be any element in the first storage unit to be processed, and the second element can be any element in the second storage unit to be processed. The larger of the first element and the second element is placed in either the first storage unit to be processed or the second storage unit to be processed. Both the first storage unit to be processed and the second storage unit to be processed are one of the multiple storage units to be processed.

[0062] In this embodiment, the elements can be numerical values. The number of elements in the first storage unit to be processed is the same as the number of elements in the second storage unit to be processed. Taking an example where both the first and second storage units to be processed contain 10 elements, and the larger of the first and second elements is placed in the second storage unit, comparing the first and second storage units to be processed using a comparison instruction can be represented as follows: comparing the first element in the first storage unit with the first element in the second storage unit, and placing the larger one in the second storage unit as the first element; comparing the second element in the first storage unit with the second element in the second storage unit, and placing the larger one in the second storage unit as the second element; and so on, comparing the tenth element in the first storage unit with the tenth element in the second storage unit, and placing the larger one in the second storage unit as the tenth element. During the comparison between the first and second storage blocks, the larger one is placed into the second storage block. After the comparison between the first and second storage blocks, the elements stored in the second storage block are all the larger ones obtained after the comparison at their respective positions.

[0063] In this embodiment, different sorting methods are used for parallel sorting when the target sorting dimension is less than the upper limit and when the target sorting dimension is greater than the upper limit, which can improve sorting efficiency to a certain extent. Moreover, both sorting methods use a combination of sorting and comparison instructions for parallel sorting. Thus, by flexibly combining sorting and comparison instructions, various sorting scenarios can be addressed, further improving the sorting efficiency of sorting operations performed under different conditions.

[0064] In some embodiments of this application, when the value of the target sorting dimension is less than the upper limit of the sorting, step 130, which involves parallel sorting of multiple memory banks to be processed using a combination of sorting and comparison instructions in a first sorting manner, includes: obtaining multiple target memory banks to be processed in parallel from the multiple memory banks to be processed; the number of the multiple target memory banks is equal to the upper limit of the sorting, and the multiple target memory banks are obtained using a multi-sorting dimension joint approach; and performing multiple rounds of parallel sorting of the multiple target memory banks using a combination of sorting and comparison instructions. This reduces the performance overhead of padding invalid values ​​and improves hardware utilization.

[0065] In some embodiments of this application, the target sorting dimension includes a channel grouping dimension, and the multiple sorting dimensions include a processing unit dimension and a width dimension. When the value of the target sorting dimension is less than the upper limit of the sorting value, the step of performing multiple rounds of parallel sorting on the multiple target memory banks using a combination of sorting instructions and comparison instructions includes:

[0066] The elements contained in each of the plurality of target storage entities are sorted in a first round using sorting instructions.

[0067] After the first round of parallel sorting, a second round of parallel sorting is performed on at least two target memory banks obtained according to the channel grouping dimension using comparison instructions.

[0068] After the second round of parallel sorting, the elements contained in each of the multiple target memory banks are sorted in a third round using the sorting instructions. Thus, by performing multiple rounds of parallel sorting on the multiple target memory banks through a specific combination of sorting and comparison instructions, hardware utilization can be improved while ensuring that all elements in the multiple target memory banks are monotonically increasing or monotonically decreasing in the channel grouping dimension.

[0069] The following reference Figure 2 The following details the case where the number of storage banks in the sorting dimension does not exceed 8 × storage banks, and the number of non-sorting dimensions is less than 8. Figure 2 In the example, taking the layout [N=4,Gc=2,W=2,Bank] as an example, the target sorting dimensions are Gc and Bank dimensions.

[0070] Traditional compilation methods pad invalid values ​​along the W dimension until W=4, and then perform parallel processing along the W dimension, resulting in a total sorting count of 8 × Bank. The optimized compilation method proposed in this application can perform parallel processing along a joint N×W dimension, with a parallel processing count of 4 per iteration, eliminating the need for padding invalid values. Figure 2As shown, parallel bitone sorting of [n0,w0], [n0,w1], [n1,w0], and [n1,w1] can be implemented in a single load / store operation.

[0071] In this application Figures 2-4 In the diagram, SRT performs an independent internal sorting of each bank. The symbol "↓" indicates ascending order, and the symbol "↑" indicates descending order. The arrows inside the boxes in the attached diagram all indicate the internal sorting performed according to the SRT instructions. CMP performs a pairwise comparison and swapping of banks. The symbol "↓" indicates swapping from smallest to largest (min-max), and the symbol "↑" indicates swapping from largest to smallest (max-min). The arrows outside the boxes all indicate sorting according to the CMP instructions. The bank indicated by the arrow is used to store the larger value obtained based on the comparison operation.

[0072] Reference Figure 2 The GLB is used to store multiple memory banks to be processed. Multiple target memory banks to be processed in parallel can be obtained from the GLB, sorted in the cache, and finally stored back into the GLB after processing. Figure 2 In this process, there are eight target memory banks to be processed in parallel. First, a first sorting instruction is used to perform a first round of parallel sorting on the elements contained in each target memory bank. After the first round of parallel sorting, a comparison instruction is used to compare at least two target memory banks obtained according to the channel grouping dimension. Figure 2 The second round of parallel sorting is performed on two target storage bodies. After the second round of parallel sorting, the elements contained in each target storage body are sorted in a third round of parallel sorting by a second sorting instruction.

[0073] by Figure 2 Taking two memory banks located in the range [n0, w0] as an example, Figure 2 The two memory banks are located in the upper left corner of a long box containing eight memory banks. These two memory banks are first sorted internally according to the CMP instruction; then they are sorted externally according to the CMP instruction. During the sorting process, the internal elements of each memory bank may change; finally, they are sorted internally again according to the CMP instruction, and the final processed memory bank is placed at the position [n0, w0] of GLB.

[0074] In terms of performance, compared to related technologies, it adopts Figure 2 The sorting method shown reduces the performance overhead of padding and improves hardware utilization.

[0075] In some embodiments of this application, the target sorting dimension may also be equal to the upper limit of sorting, and the target sorting dimension includes the channel grouping dimension. The memory sorting method provided in the embodiments of this application may further include:

[0076] In response to the target sorting dimension being equal to the sorting upper limit, a first number of first storage units to be processed in parallel are obtained from the plurality of storage units to be processed; the first number is equal to the sorting upper limit.

[0077] The first number of first storage blocks are sorted by a sorting instruction to obtain the first number of first processing storage blocks;

[0078] The first number of second processing memory blocks are obtained by comparing all memory blocks in the first number of first processing memory blocks by comparing them in groups of individual memory blocks using comparison instructions.

[0079] The first number of second processing memory blocks are sorted by a sorting instruction to obtain the first number of third processing memory blocks;

[0080] The first number of fourth processing memory blocks are obtained by comparing all memory blocks in the first number of third processing memory blocks by grouping them into pairs using comparison instructions.

[0081] The first number of fifth processing memory blocks are obtained by comparing two memory blocks within each group of the first number of fourth processing memory blocks using comparison instructions.

[0082] The first number of fifth processing memory blocks are sorted by a sorting instruction to obtain the first number of sixth processing memory blocks.

[0083] The first number of seventh processing memory blocks are obtained by comparing all memory blocks in the first number of sixth processing memory blocks in groups of four memory blocks by comparison instructions.

[0084] By comparing all the memory banks in the first number of seventh processing memory banks in pairs using comparison instructions, the first number of eighth processing memory banks are obtained.

[0085] The first number of ninth processing memory blocks are obtained by comparing all memory blocks in the first number of eighth processing memory blocks by grouping them into individual memory blocks using comparison instructions.

[0086] The first number of ninth processing storage units are sorted by sorting instructions to obtain the first number of first sorted storage units, wherein all elements in the first number of first sorted storage units are monotonically increasing or monotonically decreasing.

[0087] Thus, by performing multiple rounds of parallel sorting on the multiple target memory banks through a specific combination of sorting and comparison instructions, hardware utilization can be improved while ensuring that all elements in the multiple target memory banks are monotonically increasing or monotonically decreasing in the channel grouping dimension.

[0088] The following reference Figure 3 The case where the number of storage banks in the sorting dimension is equal to 8 × storage banks is explained in detail. Figure 3 In the example, taking the layout [N=2,Gc=8,Bank] as an example, the target sorting dimensions are Gc and Bank dimensions.

[0089] exist Figure 3 In this context, the GLB is used to store multiple memory banks to be processed. Memory banks to be processed in parallel can be obtained from the GLB, sorted in the cache, and finally stored back into the GLB after processing. Figure 3 In this process, the number of first memory banks to be processed in parallel is 8, that is, the first number is 8. After obtaining 8 first memory banks from the GLB, the first step is to sort the first number of first memory banks using the first sorting (SRT) instruction, that is... Figure 3 In the first step, the eight memory banks within the rectangle corresponding to the first SRT instruction are internally sorted to obtain the first number of first processing memory banks. In the second step, the first comparison (CMP) instruction is used to group and compare all memory banks in the first number of first processing memory banks, with each memory bank as a group, to obtain the first number of second processing memory banks. Figure 3 The eight memory blocks within the rectangle corresponding to the first CMP instruction are the eight second processing memory blocks. The third step involves sorting the first number of second processing memory blocks using a second sorting instruction to obtain the first number of third processing memory blocks. After the second sorting instruction is executed, Figure 3 The eight memory banks within the rectangle corresponding to the second SRT instruction are the eight third processing memory banks. In the fourth step, the second comparison instruction groups all memory banks in the first number of third processing memory banks for comparison, grouping them into pairs to obtain the first number of fourth processing memory banks. After the second comparison instruction completes execution, Figure 3 The eight memory banks within the rectangle corresponding to the second CMP instruction are the eight fourth processing memory banks. In the fifth step, a third comparison instruction compares the two memory banks within each group of the first number of fourth processing memory banks to obtain the first number of fifth processing memory banks. After the third comparison instruction completes execution, Figure 3The eight memory blocks within the rectangle corresponding to the third CMP instruction are the eight fifth processing memory blocks. The sixth step involves sorting the first number of fifth processing memory blocks using the third sorting instruction to obtain the first number of sixth processing memory blocks. After the third sorting instruction is executed, Figure 3 The eight memory banks within the rectangle corresponding to the third SRT instruction are the eight sixth processing memory banks. In the seventh step, the fourth comparison instruction groups all the memory banks in the first number of sixth processing memory banks for comparison, grouping them into sets of four, to obtain the first number of seventh processing memory banks. After the fourth comparison instruction is executed, Figure 3 The eight memory banks within the rectangle corresponding to the fourth CMP instruction are the eight seventh processing memory banks. The fifth comparison instruction groups all memory banks in the first number of seventh processing memory banks for comparison, grouping them into pairs, to obtain the first number of eighth processing memory banks. After the fifth comparison instruction completes execution, Figure 3 The eight memory banks within the rectangle corresponding to the fifth CMP instruction are the eight eighth processing memory banks. The sixth comparison instruction groups all memory banks in the first number of eighth processing memory banks for comparison, resulting in the first number of ninth processing memory banks. After the sixth comparison instruction completes execution, Figure 3 The eight memory blocks within the rectangle corresponding to the sixth CMP instruction are the eight ninth processing memory blocks. The first number of ninth processing memory blocks are sorted using the fourth sorting instruction to obtain the first number of first sorted memory blocks. After the fourth sorting instruction is executed, Figure 3 The eight memory blocks within the rectangle corresponding to the fourth SRT instruction are the eight first sorted memory blocks. All elements in these eight first sorted memory blocks are either monotonically increasing or monotonically decreasing.

[0090] In some embodiments of this application, when the value of the target sorting dimension is greater than the upper limit of the sorting value, step 140, which involves parallel sorting of the plurality of storage units to be processed using a second sorting method through a combination of the sorting instruction and the comparison instruction, includes:

[0091] Multiple target storage units to be processed in parallel are obtained from the multiple storage units to be processed. The multiple target storage units include a first number of first storage units and a first number of second storage units, wherein the first number is equal to the sorting upper limit value.

[0092] The first number of first storage units are sorted by sorting instructions and comparison instructions to obtain the first number of first sorted storage units; all elements in the first number of first sorted storage units are monotonically increasing or monotonically decreasing.

[0093] The first number of second storage units are sorted by the sorting instruction and the comparison instruction to obtain a second sorted storage unit; all elements in the first number of second sorted storage units are monotonically increasing or monotonically decreasing.

[0094] Based on the first number of first sorted storage units and the first number of second sorted storage units, multiple rounds of sorting are performed using the comparison instructions and the sorting instructions to obtain the first number of third sorted storage units and the first number of fourth sorted storage units. The multiple rounds of sorting include multiple rounds of comparison sorting according to the comparison instructions, and at least two rounds of comparison sorting with different storage unit numbers as granularity. All elements in the first number of third sorted storage units and all elements in the first number of fourth sorted storage units are monotonically increasing or monotonically decreasing. After obtaining the first number of third sorted storage units and the first number of fourth sorted storage units, they can be stored in the GLB.

[0095] In this way, there is no need to split the data into multiple tensors for sorting during the sorting process, thus avoiding redundant loading and storage overhead.

[0096] The following reference Figure 4 The case where the number of storage banks in the sorting dimension exceeds 8 × storage banks is explained in detail. Figure 4 In the example, taking the layout [N=2, Gc=16, Bank] as an example, the target sorting dimension is the Gc and Bank dimensions. Here, the first number of first storage cells and the first number of second storage cells can both be 8 storage cells obtained from the GLB, and the 8 first storage cells can be... Figure 4 The leftmost cache corresponds to the eight memory banks within the top rectangle; these eight secondary memory banks can be... Figure 4 The leftmost cache corresponds to the 8 memory blocks within the lower rectangle. The first number of first sorted memory blocks can be... Figure 4 The first number of the eight memory banks corresponding to the GLB in the middle, and the second sorted memory banks, can be... Figure 4 The GLB corresponds to the eight memory banks below it. The first number of third-ordered memory banks can be... Figure 4 The first number of fourth sorted memory cells obtained after the last SRT operation can be the top 8 memory cells. Figure 4 The following eight memory blocks are obtained after the last SRT operation. Figure 4 It can be seen that, Figure 4 After the last SRT operation, all elements in the eight memory banks above are either monotonically increasing or monotonically decreasing; similarly, Figure 4 After the last SRT operation, all elements in the following eight memory cells are either monotonically increasing or monotonically decreasing. Meanwhile, Figure 4 If all elements in the eight memory cells above are monotonically increasing after the last SRT operation, then... Figure 4 All elements in the eight memory blocks below, obtained after the last SRT operation, also monotonically increase. Figure 4 If all elements in the eight memory cells above are monotonically decreasing after the last SRT operation, then... Figure 4 After the last SRT operation, all elements in the eight memory blocks below also decrease monotonically.

[0097] In some embodiments of this application, based on the first number of first sorted storage units and the first number of second sorted storage units, multiple rounds of sorting are performed using the comparison instruction and the sorting instruction to obtain the first number of third sorted storage units and the first number of fourth sorted storage units, including:

[0098] Based on the first number of first sorted storage blocks and the first number of second sorted storage blocks, the first number of first comparison storage blocks and the first number of second comparison storage blocks are obtained; the first number of first comparison storage blocks include at least a portion of the first number of first sorted storage blocks and at least a portion of the first number of second sorted storage blocks; the first number of second comparison storage blocks include at least a portion of the first number of first sorted storage blocks and at least a portion of the first number of second sorted storage blocks.

[0099] The comparison instruction compares the elements in the first and second equal parts of the first number of first memory blocks to be compared, thereby obtaining the first number of third memory blocks to be compared; the first number of first memory blocks to be compared are divided into the first and second equal parts.

[0100] The comparison instruction is used to compare the elements in the third and fourth equal parts of the first number of second memory blocks to be compared, thereby obtaining the first number of fourth memory blocks to be compared; the first number of first memory blocks to be compared are divided into the third and fourth equal parts.

[0101] Based on the first number of third storage blocks to be compared and the first number of fourth storage blocks to be compared, the first number of fifth storage blocks to be compared and the first number of sixth storage blocks to be compared are obtained; the first number of fifth storage blocks to be compared include at least a portion of the first number of third sorted storage blocks and at least a portion of the first number of fourth sorted storage blocks; the first number of sixth storage blocks to be compared include at least a portion of the first number of third sorted storage blocks and at least a portion of the first number of fourth sorted storage blocks.

[0102] Based on the first number of fifth memory banks to be compared, the comparison instructions are used to perform multiple rounds of comparisons at different memory bank counts to obtain the first number of first target memory banks to be compared; the sorting instructions are used to sort the first number of first target memory banks to obtain the first number of third sorted memory banks.

[0103] Based on the first number of sixth memory blocks to be compared, the comparison instructions are used to perform multiple rounds of comparisons at different memory block counts to obtain the second target memory blocks; the sorting instructions are used to sort the first number of second target memory blocks to obtain the first number of fourth sorted memory blocks.

[0104] Figure 4 In the comparison, the first four memory blocks within the upper frame and the first four memory blocks within the lower frame of the GLB can be placed in the cache as eight first memory blocks to be compared. Similarly, the last four memory blocks within the upper frame and the last four memory blocks within the lower frame of the GLB can be placed in the cache as eight second memory blocks to be compared.

[0105] By comparing all elements in the first four memory cells and all elements in the last four memory cells of the eight first memory cells to be compared using comparison instructions, the first number of third memory cells to be compared are obtained. That is, the eight memory cells obtained after the comparison are the third memory cells to be compared. Similarly, by comparing all elements in the first four memory cells and all elements in the last four memory cells of the eight second memory cells to be compared using comparison instructions, the first number of fourth memory cells to be compared are obtained. That is, the eight memory cells obtained after the comparison are the fourth memory cells to be compared.

[0106] After obtaining eight third and eight fourth memory banks to be compared, the first four memory banks are selected from the eight third memory banks, and the first four memory banks are selected from the eight fourth memory banks to form eight fifth memory banks to be compared. Figure 4In the diagram, the top eight memory banks (without arrows within the small boxes) correspond to GLB. Similarly, after obtaining eight third and eight fourth memory banks to be compared, the last four memory banks are selected from the eight third memory banks, and the last four memory banks are selected from the eight fourth memory banks to form eight sixth memory banks to be compared. That is... Figure 4 In the middle, the 8 storage blocks below GLB that are in the small squares without arrows.

[0107] Subsequently, based on the first number of fifth memory blocks to be compared, multiple rounds of comparison can be performed using the comparison instruction at different memory block counts as granularity to obtain the first number of first target memory blocks to be compared; the first number of first target memory blocks to be compared can be sorted using the sorting instruction to obtain the first number of third sorted memory blocks. Figure 4 The algorithm performed three rounds of comparison and sorting at granularities of 4 memory banks, 2 memory banks, and 1 memory bank, respectively. Figure 4 The right side shows three consecutive CMP instructions. Figure 4 In this context, the first number of first target comparison memory banks are the eight memory banks obtained after the last CMP instruction is executed. Subsequently, SRT instructions can be executed on these eight memory banks to obtain eight third sorted memory banks. Similarly, based on the first number of sixth target comparison memory banks, multiple rounds of comparisons can be performed using the comparison instructions at different memory bank granularities to obtain the first number of second target comparison memory banks; the first number of second target comparison memory banks can then be sorted using the sorting instructions to obtain the first number of fourth sorted memory banks. Figure 4 The algorithm performed three rounds of comparison and sorting at granularities of 4 memory banks, 2 memory banks, and 1 memory bank, respectively. Figure 4 The right side shows three consecutive CMP instructions. Figure 4 In this context, the first number of second target comparison memory banks are the eight memory banks obtained after the last CMP instruction is executed. Subsequently, SRT instructions can be executed on these eight memory banks to obtain eight third sorted memory banks.

[0108] Related compilation methods split the data into two tensors [N=2, Gc=8, Bank] along the Gc dimension, and use multiple sorting operators (SortOp) and other operators, such as the comparison operator (CompareOp), to operate on these two tensors respectively to achieve sorting. The optimized compilation method provided in this application does not require splitting. In the compilation instructions of a single sorting operator (SortOp), a combination of multi-level SRT instructions and CMP instructions is used to achieve efficient sorting.

[0109] In some embodiments of this application, sorting the first number of first memory banks using sorting instructions and comparison instructions to obtain the first number of first sorted memory banks includes:

[0110] The first number of first storage blocks are sorted by a sorting instruction to obtain the first number of first processing storage blocks;

[0111] The first number of second processing memory blocks are obtained by comparing the memory blocks in the first number of first processing memory blocks using a comparison instruction;

[0112] The first number of second processing memory blocks are sorted by a sorting instruction to obtain the first number of third processing memory blocks;

[0113] The first number of fourth processing memory blocks are obtained by comparing all memory blocks in the first number of third processing memory blocks by grouping them into pairs using comparison instructions.

[0114] The first number of fifth processing memory blocks are obtained by comparing two memory blocks within each group of the first number of fourth processing memory blocks using comparison instructions.

[0115] The first number of fifth processing memory blocks are sorted by a sorting instruction to obtain the first number of sixth processing memory blocks.

[0116] The first number of seventh processing memory blocks are obtained by comparing all memory blocks in the first number of sixth processing memory blocks in groups of four memory blocks by comparison instructions.

[0117] By comparing all the memory banks in the first number of seventh processing memory banks in pairs using comparison instructions, the first number of eighth processing memory banks are obtained.

[0118] The first number of ninth processing memory blocks are obtained by comparing all memory blocks in the first number of eighth processing memory blocks by grouping them into individual memory blocks using comparison instructions.

[0119] The first number of ninth processing memory blocks are sorted by sorting instructions to obtain the first number of first sorted memory blocks.

[0120] The process executed above using sorting and comparison instructions is similar to... Figure 3 Similarly, the specific process can be found by referring to... Figure 3 The discussion on this topic will not be repeated here.

[0121] It should be understood that the storage sorting method provided in this application embodiment also has the following beneficial effects: first, it improves the parallelism rate and improves the hardware utilization rate; second, it reduces the startup overhead of sorting operations and the overhead of repeated load / store operations.

[0122] It should also be understood that, in the storage sorting method provided in this application embodiment, regardless of whether the first sorting method or the second sorting method is used, the final sorting result can be stored on memory, such as on a GLB. The sorting result can be used by a machine learning model. For example, the machine learning model uses the sorting result to perform probability prediction, obtains prediction results with various possibilities, and can select the result with a higher probability. The specific scenario for probability prediction is not limited, including but not limited to fault prediction in communication scenarios.

[0123] Figure 5 This is a structural block diagram of a storage sorting device provided in an embodiment of this application. (Refer to...) Figure 5 The storage sorting device 500 provided in this application embodiment includes: an identification module 510, an acquisition module 520, and a processing module 530. Wherein:

[0124] The identification module 510 is used to identify sorting operators in a target object obtained from source code by the compiler.

[0125] The acquisition module 520 is used to acquire the value of the target sorting dimension in response to the existence of a comparison-based sorting operator in the target object, wherein the target sorting dimension is at least one dimension used for sorting.

[0126] Processing module 530 is configured to, in response to the target sorting dimension being less than the upper limit of sorting, perform parallel sorting of multiple storage entities to be processed in a first sorting manner using sorting instructions and comparison instructions; the upper limit of sorting is associated with the number of storage entities to be processed.

[0127] The processing module 530 is further configured to, in response to the target sorting dimension being greater than the upper limit of the sorting value, perform parallel sorting of the plurality of storage units to be processed using the sorting instruction and the comparison instruction in a second sorting method; the second sorting method is different from the first sorting method.

[0128] Each of the storage units to be processed contains multiple elements. The sorting instruction is used to sort the multiple elements contained in the storage unit to be processed. The comparison instruction is used to compare the first element in the first storage unit to be processed with the second element in the second storage unit to be processed. The position of the first element in the first storage unit to be processed and the position of the second element in the second storage unit to be processed correspond to each other. The first element can be any element in the first storage unit to be processed, and the second element can be any element in the second storage unit to be processed. The larger of the first element and the second element is placed in either the first storage unit to be processed or the second storage unit to be processed. Both the first storage unit to be processed and the second storage unit to be processed are one of the multiple storage units to be processed.

[0129] In this embodiment, different sorting methods are used for parallel sorting when the target sorting dimension is less than the upper limit and when the target sorting dimension is greater than the upper limit, which can improve sorting efficiency to a certain extent. Moreover, both sorting methods use a combination of sorting and comparison instructions for parallel sorting. Thus, by flexibly combining sorting and comparison instructions, various sorting scenarios can be addressed, further improving the sorting efficiency of sorting operations performed under different conditions.

[0130] It should be understood that, since the storage sorting apparatus provided in this application corresponds to the storage sorting method described in the above embodiments, the relevant content of the storage sorting apparatus provided in this application can be referred to the above method embodiments, and will not be repeated here. For example, the specific processes of each step performed by each module in the identification module 510, the acquisition module 520, and the processing module 530 can all be referred to the above method embodiments.

[0131] Figure 6 This is a structural block diagram of an electronic device provided in an embodiment of this application. For example... Figure 6As shown, this application embodiment also provides an electronic device 600. The electronic device 600 includes a processor 610 and a memory 620. The memory 620 stores programs or instructions, which, when executed by the processor 610, implement the steps of any of the methods described above. For example, when the program is executed by the processor 610, it implements the following process: identifying sorting operators in a target object obtained based on source code through a compiler; in response to the existence of a comparison-based sorting operator in the target object, obtaining the value of a target sorting dimension, the target sorting dimension being at least one dimension used for sorting; in response to the value of the target sorting dimension being less than a sorting upper limit value, performing parallel sorting of multiple storage entities to be processed using a combination of sorting instructions and comparison instructions in a first sorting manner; the sorting upper limit value is associated with the number of storage entities to be processed; in response to the value of the target sorting dimension being greater than the sorting upper limit value, performing parallel sorting of the multiple storage entities to be processed using a combination of sorting instructions and comparison instructions in a second sorting manner; the second sorting manner is different from the first sorting manner; wherein, each Each of the aforementioned storage entities to be processed contains multiple elements. The sorting instruction is used to sort the multiple elements contained in the storage entity to be processed. The comparison instruction is used to compare a first element in a first storage entity to be processed with a second element in a second storage entity to be processed. The position of the first element in the first storage entity to be processed and the position of the second element in the second storage entity to be processed correspond to each other. The first element can be any element in the first storage entity to be processed, and the second element can be any element in the second storage entity to be processed. The larger of the first element and the second element is placed in either the first storage entity to be processed or the second storage entity to be processed. Both the first storage entity to be processed and the second storage entity to be processed are one of the multiple storage entities to be processed.

[0132] In this embodiment, different sorting methods are used for parallel sorting when the target sorting dimension is less than the upper limit and when the target sorting dimension is greater than the upper limit, which can improve sorting efficiency to a certain extent. Moreover, both sorting methods use a combination of sorting and comparison instructions for parallel sorting. Thus, by flexibly combining sorting and comparison instructions, various sorting scenarios can be addressed, further improving the sorting efficiency of sorting operations performed under different conditions.

[0133] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the steps of various embodiments of the storage sorting method and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0134] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0135] This application also provides a chip, which includes a processor and a communication interface. The communication interface and the processor are coupled. The processor is used to run programs or instructions to implement the various processes of the above method embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0136] This application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the various processes of the above method embodiments and achieve the same technical effects. To avoid repetition, it will not be described again here.

[0137] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0138] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0139] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A memory sorting method, characterized in that, include: The compiler identifies sorting operators in target objects obtained from source code. In response to the existence of a comparison-based sorting operator in the target object, the value of the target sorting dimension is obtained, wherein the target sorting dimension is at least one dimension used for sorting; In response to the target sorting dimension being less than the upper limit of the sorting, multiple storage units to be processed are sorted in parallel using a first sorting method through a combination of sorting instructions and comparison instructions; the upper limit of the sorting is related to the number of storage units to be processed. In response to the target sorting dimension being greater than the upper limit of the sorting, the plurality of storage units to be processed are sorted in parallel using a second sorting method through a combination of the sorting instruction and the comparison instruction; the second sorting method is different from the first sorting method. Each of the storage entities to be processed contains multiple elements. The sorting instruction is used to sort the multiple elements contained in the storage entity to be processed. The comparison instruction is used to compare a first element in a first storage entity to be processed with a second element in a second storage entity to be processed. The position of the first element in the first storage entity to be processed and the position of the second element in the second storage entity to be processed correspond to each other. The first element can be any element in the first storage entity to be processed, and the second element can be any element in the second storage entity to be processed. The larger of the first element and the second element is placed in either the first storage entity to be processed or the second storage entity to be processed. Both the first storage entity to be processed and the second storage entity to be processed are one of the multiple storage entities to be processed. The step of parallel sorting of multiple memory banks to be processed using a combination of sorting and comparison instructions in a first sorting manner includes: Multiple target storage units to be processed in parallel are obtained from the multiple storage units to be processed; the number of the multiple target storage units is equal to the sorting upper limit value, and the multiple target storage units are obtained by using a multi-sorting dimension joint method; The multiple target memory banks are sorted in multiple rounds in parallel by a combination of sorting and comparison instructions; The target sorting dimension includes the channel grouping dimension, and the multiple sorting dimensions include the processing unit dimension and the width dimension.

2. The method according to claim 1, characterized in that, The process of performing multiple rounds of parallel sorting on the multiple target memory banks using a combination of sorting and comparison instructions includes: The elements contained in each of the plurality of target storage entities are sorted in a first round using sorting instructions. After the first round of parallel sorting, a second round of parallel sorting is performed on at least two target memory banks obtained according to the channel grouping dimension using comparison instructions. After the second round of parallel sorting, the elements contained in each of the multiple target storage entities are sorted in a third round using the sorting instructions.

3. The method according to claim 1, characterized in that, The parallel sorting of the plurality of memory banks to be processed using a combination of the sorting instruction and the comparison instruction in a second sorting manner includes: Multiple target storage units to be processed in parallel are obtained from the multiple storage units to be processed. The multiple target storage units include a first number of first storage units and a first number of second storage units, wherein the first number is equal to the sorting upper limit value. The first number of first storage units are sorted by sorting instructions and comparison instructions to obtain the first number of first sorted storage units; all elements in the first number of first sorted storage units are monotonically increasing or monotonically decreasing. The first number of second storage units are sorted by the sorting instruction and the comparison instruction to obtain a second sorted storage unit; all elements in the first number of second sorted storage units are monotonically increasing or monotonically decreasing. Based on the first number of first sorted storage units and the first number of second sorted storage units, multiple rounds of sorting are performed through the comparison instruction and the sorting instruction to obtain the first number of third sorted storage units and the first number of fourth sorted storage units; The multi-round sorting includes multi-round comparison sorting performed according to the comparison instruction, and the multi-round comparison sorting includes at least two rounds of comparison sorting with the granularity of comparing different numbers of memory blocks; wherein all elements in the first number of third sorted memory blocks and all elements in the first number of fourth sorted memory blocks are monotonically increasing or monotonically decreasing.

4. The method according to claim 3, characterized in that, Based on the first number of first sorted storage units and the first number of second sorted storage units, multiple rounds of sorting are performed through the comparison instructions and the sorting instructions to obtain the first number of third sorted storage units and the first number of fourth sorted storage units, including: Based on the first number of first sorted storage blocks and the first number of second sorted storage blocks, the first number of first comparison storage blocks and the first number of second comparison storage blocks are obtained; the first number of first comparison storage blocks include at least a portion of the first number of first sorted storage blocks and at least a portion of the first number of second sorted storage blocks; the first number of second comparison storage blocks include at least a portion of the first number of first sorted storage blocks and at least a portion of the first number of second sorted storage blocks. The comparison instruction compares the elements in the first and second equal parts of the first number of first memory blocks to be compared, thereby obtaining the first number of third memory blocks to be compared; the first number of first memory blocks to be compared are divided into the first and second equal parts. The comparison instruction is used to compare the elements in the third and fourth equal parts of the first number of second memory blocks to be compared, thereby obtaining the first number of fourth memory blocks to be compared; the first number of first memory blocks to be compared are divided into the third and fourth equal parts. Based on the first number of third storage blocks to be compared and the first number of fourth storage blocks to be compared, the first number of fifth storage blocks to be compared and the first number of sixth storage blocks to be compared are obtained; the first number of fifth storage blocks to be compared include at least a portion of the first number of third sorted storage blocks and at least a portion of the first number of fourth sorted storage blocks; the first number of sixth storage blocks to be compared include at least a portion of the first number of third sorted storage blocks and at least a portion of the first number of fourth sorted storage blocks. Based on the first number of fifth memory banks to be compared, the comparison instructions are used to perform multiple rounds of comparisons at different memory bank counts to obtain the first number of first target memory banks to be compared; the sorting instructions are used to sort the first number of first target memory banks to obtain the first number of third sorted memory banks. Based on the first number of sixth memory blocks to be compared, the comparison instructions are used to perform multiple rounds of comparisons at different memory block counts to obtain the second target memory blocks; the sorting instructions are used to sort the first number of second target memory blocks to obtain the first number of fourth sorted memory blocks.

5. The method according to claim 3, characterized in that, The first number of first memory banks are sorted using sorting and comparison instructions to obtain the first number of sorted first memory banks, including: The sorting instructions are used to sort the first number of first storage units to obtain the first number of first processing storage units. The comparison instruction is used to compare the memory blocks in the first number of first processing memory blocks to obtain the first number of second processing memory blocks; The sorting instructions are used to sort the first number of second processing storage units to obtain the first number of third processing storage units. The comparison instruction is used to compare all the memory blocks in the first number of third processing memory blocks in pairs to obtain the first number of fourth processing memory blocks. The comparison instruction is used to compare two memory blocks within each group of the first number of fourth processing memory blocks to obtain the first number of fifth processing memory blocks. The sorting instructions are used to sort the first number of fifth processing memory blocks to obtain the first number of sixth processing memory blocks. The comparison instruction is used to compare all the memory blocks in the first number of sixth processing memory blocks in groups of four memory blocks to obtain the first number of seventh processing memory blocks. The comparison instruction is used to group all the memory cells in the first number of seventh processing memory cells into pairs for comparison, thereby obtaining the first number of eighth processing memory cells. The comparison instruction is used to group all the memory blocks of the first number of eighth processing memory blocks into groups of individual memory blocks for comparison, thereby obtaining the first number of ninth processing memory blocks. The sorting instructions are used to sort the first number of ninth processing memory blocks to obtain the first number of first sorted memory blocks.

6. The method according to claim 1, characterized in that, The target sorting dimension includes the channel grouping dimension; the method further includes: In response to the target sorting dimension being equal to the sorting upper limit, a first number of first storage units to be processed in parallel are obtained from the plurality of storage units to be processed, the first number being equal to the sorting upper limit. The sorting instructions are used to sort the first number of first storage units to obtain the first number of first processing storage units. The comparison instruction is used to group and compare all the memory blocks of the first number of first processing memory blocks as a group of individual memory blocks to obtain the first number of second processing memory blocks. The sorting instructions are used to sort the first number of second processing storage units to obtain the first number of third processing storage units. The comparison instruction is used to compare all the memory blocks in the first number of third processing memory blocks in pairs to obtain the first number of fourth processing memory blocks. The comparison instruction is used to compare two memory blocks within each group of the first number of fourth processing memory blocks to obtain the first number of fifth processing memory blocks. The sorting instructions are used to sort the first number of fifth processing memory blocks to obtain the first number of sixth processing memory blocks. The comparison instruction is used to compare all the memory blocks in the first number of sixth processing memory blocks in groups of four memory blocks to obtain the first number of seventh processing memory blocks. The comparison instruction is used to group all the memory cells in the first number of seventh processing memory cells into pairs for comparison, thereby obtaining the first number of eighth processing memory cells. The comparison instruction is used to group all the memory blocks of the first number of eighth processing memory blocks into groups of individual memory blocks for comparison, thereby obtaining the first number of ninth processing memory blocks. The sorting instruction is used to sort the first number of ninth processing storage units to obtain the first number of first sorted storage units, wherein all elements in the first number of first sorted storage units are monotonically increasing or monotonically decreasing.

7. An electronic device, characterized in that, It includes a processor and a memory, the memory storing a program or instructions that, when executed by the processor, implement the method as described in any one of claims 1 to 6.

8. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the method as described in any one of claims 1 to 6.

9. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 6.

Images