Multipurpose D2D transmitter and configuration method thereof

Abstract

The invention provides a multipurpose D2D transmitter, a configuration method thereof and a transmitter. The multipurpose D2D transmitter comprises a data loading module, a data detection module, a serializer module and an adjustment module, at least two delay units are arranged in the data loading module, the corresponding delay unit is selected according to the received mode control signal to delay the data signal and the indication signal, and the data detection module performs AND operation on the data signal and the indication signal after delay processing to obtain effective data. The serializer module obtains target data according to effective data, and the adjusting module performs logical operation on a target signal and a control signal and selects an SST driver according to a result so as to realize adjustment of impedance and balance. Therefore, according to the scheme, delay adjustability and bit width adjustability can be achieved, transmission requirements for different types of data can be met, adaptability to various application scenes is good, and flexible configuration of bit width, delay, impedance and balance of the transmitter by external signals can be supported.

Description

Technical Field

[0001] This invention relates to the field of chip-to-chip interconnect interface technology in integrated circuits, and specifically to a multi-purpose D2D transmitter and its configuration method. Background Technology

[0002] Interface circuit architectures used for chip interconnects can be divided into two types: serial architecture and parallel architecture. Serial architecture has high data transmission rates, high requirements for impedance equalization, and a complex circuit structure, consisting of modules such as serializers, pre-drivers, and drivers. Figure 1 As shown, the parallel architecture is relatively simple, but it has high requirements for data and clock latency. Furthermore, different types of data have different transmission requirements, and it is difficult to cover various data transmission application scenarios using only one of the above architectures.

[0003] Existing adjustable bit width technologies include using FIFO control to change the output bit width, or deserializing the data into a fixed bit width before serializing it (multi-protocol variable bit width 40-bit high-speed serial transmitter). However, both of these solutions occupy a large area and do not actually change the input data bit width of the serializer circuit.

[0004] Existing technologies achieve latency adjustment through configurable asynchronous FIFOs, such as... Figure 2 As shown, this method requires a certain amount of time for calculation and configuration, which will bring additional delays.

[0005] Existing SST driver structures for impedance adjustment require series resistors and lack independent tuning methods that balance impedance and equalization. Figure 3 As shown.

[0006] In summary, the existing technical solutions lack a multi-purpose transmitter that supports adjustable bit width, adjustable delay, and adjustable impedance and equalization, so as to flexibly adjust the impedance and equalization. Summary of the Invention

[0007] This invention provides a multi-purpose D2D transmitter and its configuration method to solve the technical problem that existing solutions lack a technical solution that allows for flexible adjustment of impedance and equalization.

[0008] In a first aspect, embodiments of the present invention provide a multi-purpose D2D transmitter circuit, characterized in that it includes:

[0009] The data loading module includes a low-latency unit and an asynchronous FIFO delay unit. It determines the delay unit to be called based on the received mode selection signal, delays the received data signal and indicator signal using the corresponding delay method, and merges the data signal and indicator signal processed by each delay unit to obtain a merged data signal.

[0010] The data detection module receives the merged data signal from the data loading module and performs an AND operation on the data signal and the corresponding indicator signal in the merged data signal to obtain valid data; wherein, the merged data signal includes the data signal and the corresponding indicator signal.

[0011] The serializer module consists of several serializer units and several MUX units. The MUX unit determines whether to select the data from the output terminal of the preceding N-stage serializer or the data from the target input terminal of the preceding M-stage serializer based on the received second control signal, thereby obtaining the target data with the target bit width; the control signals received by the several MUX units are the same;

[0012] The adjustment module includes a logic operation unit, a level conversion unit, and an SST driver unit. It performs logic operations on the control signals from the data loading module and the target data, and selects the SST driver chip based on the results of the logic operations, thereby achieving impedance and equalization adjustment.

[0013] Preferably, the data loading module includes:

[0014] The PBRS unit is used to generate a random code, which includes a data signal and a corresponding valid indication signal;

[0015] The receiving unit is used to receive data signals and corresponding valid indication signals from the outside.

[0016] The mode selection unit receives an external SEL control signal and is connected to the PBRS unit and the receiving unit. It is used to select the corresponding delay unit according to the SEL control signal and transmit the data signal from the PBRS or external source and the corresponding valid indication signal to the corresponding delay unit. The delay unit is a low-latency unit or an asynchronous FIFO delay unit.

[0017] The data merging unit, connected to the low-latency unit and the asynchronous FIFO unit, is used to merge the data signal output by the low-latency unit and the data signal output by the asynchronous FIFO unit to generate a merged data signal.

[0018] Preferably, the low-latency unit includes:

[0019] Two cascaded triggers.

[0020] Preferably, the asynchronous FIFO delay unit includes:

[0021] The counter receives a delay control signal DLY and determines the data reading time based on the delay control signal DLY.

[0022] The FIFO asynchronous module is also used to receive a depth control signal DEP to control the delay depth of the FIFO asynchronous module.

[0023] Preferably, the data detection module includes:

[0024] A number of AND gate logic units connected in parallel receive the merged data signal, and simultaneously perform preset delay processing on the data signal and the corresponding valid indication signal in the merged data signal, and perform AND operation on the delayed data signal and the valid indication signal to output valid data.

[0025] Preferably, the serializer module includes:

[0026] Several 8 / 4:1, 8:1, and 4:1 serializers are connected to the data detection module according to the target required bit width to convert the received parallel data into serial data;

[0027] Several MUX units receive external control signals to implement bit width configuration, and determine the data to be selected from the output terminal of the corresponding serializer or the target input terminal based on the external control signals.

[0028] The final stage serializer is connected to the MUX unit and performs serial processing on the output data of each MUX unit to obtain the target data.

[0029] Preferably, the adjustment module includes:

[0030] The logic operation unit is used to perform logic operations on the target data and the corresponding impedance configuration code value in the preset code pattern-impedance mapping table to obtain logic operation data.

[0031] The data is used to perform logical operations on the target data and the external control signals for selecting the number of pull-up, pull-down, and equalization slices to obtain logical operation data. The code value of the external control signals for selecting the number of pull-up, pull-down, and equalization slices is the preset impedance configuration code value of the impedance mapping table.

[0032] A level conversion unit, connected to a logic operation unit, converts the logic operation data into level data;

[0033] The SST driving unit, based on the level data, enables the selection and driving of the SST driving chip.

[0034] Preferably, the logic operation module includes: AND logic gate units and OR logic gate units connected in parallel, wherein the AND logic gate unit includes M AND logic gates connected in parallel, and the OR logic gate unit includes P OR logic gates connected in parallel.

[0035] The AND gate is used to perform an AND operation on the M data signals in the logic operation data and the pull-down impedance signal; Q of the P OR gates are used to perform an OR operation on the P second logic operation data (excluding the M first data signals) in the logic operation data and the pull-up impedance signal; PQ OR gates are used to perform an OR operation on the remaining PQ third logic operation data in the logic operation data and the equalization control signal.

[0036] Preferably, the SST driver module includes:

[0037] The pull-up impedance slice is composed of two PMOS transistors. The connection relationship between the two PMOS transistors is as follows: the source terminal of the first PMOS transistor is connected to the power supply level, the drain terminal is connected to the source terminal of the second PMOS transistor, and the gate terminal is connected to the level data from the control pull-up impedance level conversion unit; the source terminal of the second PMOS transistor is connected to the drain terminal of the first PMOS transistor, the drain terminal is connected to the circuit output terminal, and the gate terminal is connected to the pull-up impedance slice enable control signal.

[0038] The balanced slice consists of two PMOS transistors, and the connection relationship between the two PMOS transistors is as follows:

[0039] The source of the third PMOS transistor is connected to the power supply level, its drain is connected to the source of the fourth PMOS transistor, and its gate is connected to the level data from the control equalization level conversion unit; the source of the fourth PMOS transistor is connected to the drain of the third PMOS transistor, its drain is connected to the circuit output, and its gate is connected to the equalization slice enable control signal.

[0040] The pull-down impedance slice is composed of two NMOS transistors, and the connection relationship between the two NMOS transistors is as follows:

[0041] The source of the first NMOS transistor is connected to the drain of the second NMOS transistor. The drain is connected to the circuit output, and the gate is connected to the level data from the pull-down impedance level conversion unit. The drain of the second NMOS transistor is connected to the source of the first NMOS transistor. The source is connected to ground, and the gate is connected to the pull-down impedance slice enable control signal.

[0042] Secondly, embodiments of the present invention provide a configuration method based on a multi-purpose D2D transmitter circuit, comprising:

[0043] Based on the received mode selection signal, the delayed unit to be invoked is determined, the received data signal and indication signal are delayed using the corresponding delay method, and the data signal and indication signal obtained from each delayed unit are merged to obtain a merged data signal;

[0044] The system receives a merged data signal from the data loading module, performs an AND operation between the data signal in the merged data signal and the corresponding indicator signal to obtain valid data; the delay processing corresponds to the mode selection signal and control signal received by the data loading module; wherein, the merged data signal includes a data signal and a corresponding indicator signal;

[0045] Based on the received second control signal, a number of data that have passed through the previous stage serialization or have not passed through the previous stage serialization are selected to obtain the target data with the target bit width; the control signals received by the multiple MUX units are the same;

[0046] The control signal from the data loading module is used to perform logical operations on the target data. Based on the result of the logical operations, the SST driver chip is selected, thereby achieving impedance and equalization adjustment.

[0047] The multi-purpose D2D transmitter circuit and its configuration method provided in the embodiments of the present invention have at least the following technical effects:

[0048] The multi-purpose D2D transmitter and its configuration method provided in this invention include a data loading module with at least two types of delay units: a low-latency unit and an asynchronous FIFO delay unit. The data loading module selects the corresponding delay unit based on the received mode control signal to perform delay processing on the data signal and the indicator signal. The data detection module performs an AND operation on the delayed data signal and the indicator signal to obtain valid data. The serializer module obtains the target data based on the valid data. The adjustment module performs logical operations on the target signal and the control signal, and selects the SST driver chip based on the logical operation result to adjust the impedance and equalization. In this invention embodiment, the data loading module has two types of delay units, allowing selection of the corresponding delay unit according to actual needs, thereby achieving adjustable delay and adjustable bit width to adapt to various data transmission application scenarios.

[0049] The multi-purpose D2D transmitter provided in this solution can meet the transmission requirements of different types of data, has good adaptability to various application scenarios, and supports flexible configuration of the transmitter's bit width, delay, impedance, and equalization by external signals. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the constituent modules of a serial architecture in an existing technical solution;

[0051] Figure 2 This is a schematic diagram illustrating how delay adjustment is achieved through a configurable asynchronous FIFO in existing technologies.

[0052] Figure 3This is a schematic diagram illustrating the use of an SST driver structure to achieve impedance adjustment in existing technologies.

[0053] Figure 4 This is a schematic diagram of a multi-purpose D2D transmitter according to an embodiment of the present invention;

[0054] Figure 5 This is a schematic diagram of two delay units, a low-latency unit and an asynchronous FIFO delay unit, in an embodiment of the present invention.

[0055] Figure 6 This is a schematic diagram illustrating the configuration of the low-latency unit in an embodiment of the present invention;

[0056] Figure 7 This is a schematic diagram illustrating the structure of the asynchronous FIFO delay unit in an embodiment of the present invention;

[0057] Figure 8 This is a schematic diagram illustrating the structure of the data detection module in an embodiment of the present invention;

[0058] Figure 9 This is a schematic diagram of the variable bit-width 16:1 serializer module in an embodiment of the present invention.

[0059] Figure 10 This is a schematic diagram of a serializer configuration that can switch between 8:1 and 4:1 in an embodiment of the present invention;

[0060] Figure 11 This is a schematic diagram illustrating the structure of the level conversion module in an embodiment of the present invention;

[0061] Figure 12 This is a schematic diagram illustrating the structure of the adjustment module in an embodiment of the present invention;

[0062] Figure 13 This is a schematic diagram illustrating the structure of the logic operation unit in the adjustment module of this invention.

[0063] Figure 14 This is a schematic diagram of the SST drive module in the adjustment module of an embodiment of the present invention;

[0064] Figure 15 A flowchart illustrating a configuration method for a multi-purpose D2D transmitter circuit provided in an embodiment of the present invention. Detailed Implementation

[0065] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0066] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0067] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0068] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that the terms "first," "second," "third," "fourth," etc., used in the following description are for ease of description and do not constitute a specific limitation that the devices must be the same or different. The terms "bottom surface" and "top surface," "inner" and "outer" refer to directions toward or away from the geometric center of a specific component, respectively.

[0069] This invention provides a multi-purpose D2D transmitter, see [link / reference]. Figure 4-15 As shown, it includes:

[0070] Data loading module 11, see Figure 5 As shown, it includes a low-latency unit 111 and an asynchronous FIFO delay unit 112. Based on the received mode selection signal, the delay unit to be called is determined, the received data signal and indication signal are delayed using the corresponding delay method, and the data signal and indication signal processed by each delay unit are merged to obtain a merged data signal.

[0071] In embodiments of the present invention, the mode selection signal generally originates from outside the multi-purpose D2D transmitter circuitry, such as... Figure 5 The “SEL” signal in the circuit is used to select a specific delay mode, that is, the delay unit to be called. In this embodiment, the multi-purpose D2D transmitter circuit includes a low-delay unit 111 and an asynchronous FIFO delay unit 112. If the delay unit to be called is determined to be the low-delay unit 111 according to the mode selection signal, then the low-delay mode is used to delay the received data signal and indication signal. If the delay unit to be called is determined to be the asynchronous FIFO delay unit 112 according to the mode selection signal, then the asynchronous FIFO delay mode is used to delay the received data signal and indication signal.

[0072] In this embodiment of the invention, the data signal and the corresponding indication signal can be the data signal and the corresponding indication signal received by the data loading module 11 from an external source. The indication signal can be a valid indication signal with a data length of 1 bit.

[0073] As another optional embodiment of the present invention, a PRBS unit 113 can be set in the data loading module 11 to generate a random code including a data signal and an indication signal. As a preferred approach, the multi-purpose D2D transmitter circuit is first tested using externally input data signals and indication signals. After the test is completed, it is selected whether to use the random code generated by the PRBS unit 113 as the data signal and indication signal according to actual needs.

[0074] In this embodiment of the invention, after selecting the corresponding delay unit to delay the data signal and the indication signal, the selected low delay unit 111 or asynchronous FIFO delay unit 112 performs corresponding delay processing on the received data signal and indication signal, and then outputs the delayed data signal and the corresponding indication signal. It should be noted that since there are two delay units and the output signal is one data signal and one indication signal, the data signal and indication signal processed by the two delay units need to be merged before output to obtain a merged data signal and a merged indication signal, and then output. Note that the output data signal and indication signal of the delay unit that has not undergone the corresponding delay processing are all treated as "0".

[0075] The data detection module 12 receives the merged data signal from the data loading module and performs a logical AND operation on the data signal and the corresponding indicator signal in the merged data signal to obtain valid data.

[0076] In this embodiment of the invention, the indication signal can be a 1-bit signal representing data validity. For example, if the indication signal is "1", it indicates that the data signal is valid; otherwise, it indicates that the data signal is invalid. In this embodiment of the invention, a logical AND operation is performed on the indication signal and the data signal in the merged data signal to obtain valid data. That is, if the indication signal is "0", the valid data obtained by performing a logical AND operation between the delayed indication signal and the data signal is data consisting entirely of "0"s; while if the indication signal is "1", the valid data obtained by performing a logical AND operation between the delayed indication signal and the data signal is the data in the delayed data signal.

[0077] In this embodiment of the invention, if the asynchronous FIFO delay unit 112 is selected to perform delay processing on the data signal and the indication signal, the asynchronous FIFO delay unit 112 needs to determine the maximum depth of the asynchronous FIFO delay unit 112 according to the received depth delay signal DEP, and determine the reading time of the data signal according to the read delay signal DLY. The depth delay signal DEP and the read delay signal DLY are configured according to the serial interconnect data transmission requirements, and come from outside the D2D transmitter circuit. They are configured through external signals. The FIFO read enable signal is generated internally by the D2D transmitter circuit and does not require external control. The read delay signal DLY is made adjustable by controlling the time when the read enable signal is generated.

[0078] Serializer module 13, see Figure 9 As shown, it consists of several serializer units (8 / 4 to 1 unit 131, 8 to 1 unit 132, 2 to 1 unit 133, 2 to 1 unit 135 in the figure), D flip-flop 136 and several MUX units (MUX units 134, 137 and 138 in the figure). Each MUX unit 134 determines, according to the received second control signal ctrl, to select several data from the output terminals of the previous several serializer units or data from the target input terminals of the previous several serializer units, thereby obtaining the target data with the target bit width. Specifically, as shown in the figure, MUX unit 134 determines whether to select data from the output of 2to 1 unit 133 or its target input based on the second control signal Ctrl; MUX unit 137 determines whether to select data from the output of 8 / 4to 1 unit 131 or the target input from 2to 1 unit 135 based on the second control signal ctrl; MUX unit 138 determines whether to select data from the output of MUX unit 137 or the output of 2to 1 unit 135 based on the received second control signal; wherein, the control signal received by each MUX unit is the same;

[0079] In this embodiment of the invention, the MUX unit selects data from the output of the preceding serializer or data from the target input of the preceding serializer according to actual needs. Since the data bit width changes after being processed by the serializer, the selection of data processed by the preceding serializer can be determined based on the target bit width. It should be noted that within the same serializer module 13, each MUX unit receives the same control signal, meaning it either acquires all data processed by the serializer or all data before processing by the serializer, thereby obtaining the target data.

[0080] Adjust module 14, see Figure 11As shown, it includes a level conversion unit 141, a logic operation unit 142, and an SST drive unit 143, which performs logic operations on the control signals from the data loading module and the target data, and selects the SST driver chip, thereby achieving impedance and equalization adjustment.

[0081] In this embodiment of the invention, after the level conversion unit in the adjustment module converts the target data into a level signal, the logic operation unit performs a logic operation on the level signal and the external control signal that selects the number of pull-up, pull-down, and equalization slices to obtain the logic operation result. The result of the logic operation is used to select and control the driver chip in the SST driver unit. Since the driver chip carries a load, the appropriate number of SST driver chips can be selected according to the required load to achieve impedance and equalization adjustment.

[0082] In an embodiment of the present invention, see Figure 5 As shown, the data loading module 11 further includes at least:

[0083] PRBS unit 113 is used to generate random code, the random code including a data signal and a corresponding valid indication signal;

[0084] The receiving unit 114 is used to receive data signals and corresponding valid indication signals from the outside. Specifically, the receiving unit 114 can be an interface provided on the mode selection unit 115. As for the specific type of interface, it can be set according to actual needs.

[0085] The mode selection unit 115 receives an external SEL control signal, is linked to the PRBS unit 113 via a MUX unit, and is simultaneously connected to the receiving unit 114. It is used to select the corresponding delay unit according to the SEL control signal and transmit the data signal from the PRBS unit or the external source and the corresponding valid indication signal to the corresponding delay unit. The delay unit is a low-latency unit 111 or an asynchronous FIFO delay unit 112.

[0086] The data merging unit 116 is connected to the low-latency unit 111 and the asynchronous FIFO delay unit 112. It is used to merge the data signal output by the low-latency unit and the data signal output by the asynchronous FIFO delay unit, and at the same time merge the indicator signal output by the low-latency unit 111 and the indicator signal output by the asynchronous FIFO delay unit 112 to generate a merged data signal.

[0087] In this embodiment of the invention, during a single operation, a delay unit is selected, such as a low-latency unit 111 or an asynchronous FIFO delay unit 112. The data merging unit 116 needs to be connected to both delay units. To improve applicability, the selected delay unit can be flexibly changed according to actual needs. Therefore, the delayed data obtained after the delay processing of the two delay units (low-latency unit 111 and asynchronous FIFO delay unit 112) is finally merged and output, so as to avoid the need to set up multiple output interfaces.

[0088] In this embodiment of the invention, the low-latency unit 111 includes two cascaded flip-flops. See also Figure 6 As shown, the low-latency unit 111 includes a first flip-flop 1111 and a second flip-flop 1112. The input of the first flip-flop 1111 receives data (an externally input data signal and an indication signal, or a data signal and an indication signal generated by the PRBS unit). The output of the first flip-flop 1111 is connected to the input of the second flip-flop 1112. The output of the second flip-flop 1112 outputs the delayed data signal and the indication signal. It should be noted that both flip-flops use the same clock signal.

[0089] In an embodiment of the present invention, see Figure 7 As shown, the asynchronous FIFO delay unit 112 specifically includes: a counter, which receives a delay control signal DLY and determines the data reading time based on the delay control signal DLY;

[0090] See Figure 7 After the counter receives the delay control signal DLY, it calls the read enable signal Rd_en according to the delay control signal DLY, and then controls the time of the read enable signal Rd_en according to the specific delay value of the delay control signal DLY, and then reads the data in the corresponding data address (Data[0], Data[1], Data[2], Data[3]...Data[n]).

[0091] The asynchronous FIFO delay unit 112 is also used to receive a depth control signal DEP to control the maximum delay depth of the asynchronous FIFO delay unit 112.

[0092] In this embodiment of the invention, the asynchronous FIFO delay unit 112 receives a depth control signal DEP in addition to the delay control signal DLY. The depth control signal DEP is used to determine the maximum storage depth of the asynchronous FIFO delay unit.

[0093] It should be noted that the read enable signal Rd_en is generated internally by the asynchronous FIFO delay unit. After the counter receives the delay control signal DLY, it determines the data reading time by controlling the generation time of the read enable signal Rd_en. In this way, the data reading time can be adjusted according to the generation time of Rd_en, so as to realize the adjustable delay of the data signal.

[0094] In an embodiment of the present invention, see Figure 8 As shown, the data detection module 12 includes:

[0095] A number of AND gate logic units connected in parallel receive the merged data signal and perform an AND operation on the data signal and the corresponding valid indication signal in the merged data signal to output valid data.

[0096] In this embodiment of the invention, the data detection module 12 is composed of multiple AND gate logic units connected in parallel. As shown in the figure, the data detection module 12 includes a first AND gate logic unit 121, a second AND gate logic unit 122, a third AND gate logic unit 122, ..., an (N+1)th AND gate logic unit 12(N+1), wherein the first AND gate logic unit 121 is used to convert the first bit of data in the data signal into data. <0> The second AND gate logic unit 122 performs an AND operation with the valid indication signal to process the second bit of data in the data signal. <1> The third AND gate logic unit 123 performs an AND operation with the valid indication signal to process the third bit of the data signal. <2> The valid indication signal is ANDed, ..., the (N+1)th AND gate logic unit 12 (N+1) is used to perform an AND operation on the (N+1)th bit of data in the data signal. <n>The valid indication signal is ANDed with the original data signal. If the valid indication signal is "1", the original data signal is outputted, and if the valid indication signal is "0", all data bits of the data signal are "0". It is pointed out that the number of AND gate logic units is determined according to the number of data bits of the data signal, for example, in an optional embodiment, the number of AND gate logic units is the same as the number of data bits in the data signal.

[0097] In the embodiment of the present application, Figure 9 A structural diagram of a 16:1 serial module with variable bit width is shown in Fig. 1, which comprises: Figure 9 The 16:1 serial module with variable bit width comprises:

[0098] An 8:1 and 4:1 switchable serial module 131, an 8:1 serial module 132, a 2:1 serial module 133, a 2:1 serial module 135, a MUX unit 134, a MUX unit 137, a MUX unit 138, and a D flip-flop 136. The input ends of the 8:1 and 4:1 switchable serial module 131 and the 8:1 serial module 132 are connected with the output end of the data detection module, so as to convert the received parallel data into serial data.

[0099] When the control signal Width<0> is 0 and Width<1> is 0, the effective bit width of the 16:1 serial module with variable bit width 13 is 16 bits. The 8:1 and 4:1 switchable serial module 131 works as an 8:1 serial module. One input end of the 2:1 serial module 133 is connected with the output end of the 8:1 and 4:1 switchable serial module 131, and the other input end is connected with the output end of the 8:1 serial module 132. The MUX unit 134 selects the data input end connected with the output end of the 2:1 serial module 133, and the output end outputs the main tap signal. The 8 MUX unit 138 selects the input end connected with the output end of the 2:1 serial module 135, and does not select the input end connected with the output end of the MUX unit 137, so that the output value of the MUX unit 137 does not affect the final data result, and the output end outputs the rear tap signal.

[0100] When the control signal Width<0> is 0 and Width<1> is 1, the effective bit width of the variable bit width 16:1 serializer module 13 is 8 bits. The 8:1 and 4:1 switchable serializer 131 works as an 8:1 serializer. The MUX unit 134 selects the input terminal connected to the output terminal of the 8:1 and 4:1 switchable serializer 131, and the output terminal outputs the main tap signal. The D flip-flop 136 has its input terminal connected to the output terminal of the 8:1 and 4:1 switchable serializer 131, and its output terminal connected to one input terminal of the MUX unit 137. The MUX unit 137 selects the data input terminal connected to the output terminal of the D flip-flop 136. The MUX unit 138 selects the data input terminal connected to the MUX unit 137 without selecting the input terminal connected to the output terminal of the 2:1 serializer 135, and the output terminal outputs the post-tap signal. The output values of the 2:1 serializer 133 and the 2:1 serializer 135 and the 8:1 serializer 132 do not affect the final data result at this time.

[0101] When the control signal Width<0> is 1 and Width<1> is 1, the effective bit width of the variable bit width 16:1 serializer module 13 is 4 bits. The 8:1 and 4:1 switchable serializer 131 works as a 4:1 serializer. The MUX unit 134 selects the data input terminal connected to the output terminal of the 8:1 and 4:1 switchable serializer 131, and the output terminal outputs the main tap signal. The MUX unit 137 selects the input terminal connected to the output terminal of the 8:1 and 4:1 switchable serializer 131. The MUX unit 138 selects the data input terminal connected to the MUX unit 137 without selecting the input terminal connected to the output terminal of the 2:1 serializer 135, and the output terminal outputs the post-tap signal. The output values of all the 2:1 serializers 133 and the 8:1 serializer 132 do not affect the final data result at this time.

[0102] In the embodiment of the present application, further, referring to Figure 10 The 8:1 and 4:1 switchable serializer 131 includes:

[0103] The 4:1 serializer 1311 and the 4:1 serializer 1312 are connected to the output terminal of the data detection module, and convert the received parallel data into serial data;

[0104] The 2:1 serializer 1313 has its input terminal connected to the output terminals of the 4:1 serializer 1311 and the 4:1 serializer 1312, and is used to further serialize the received two-way data into one-way data;

[0105] MUX unit 1314, according to control signal Width <0> Choose one of the two input terminals, when Width <0> When the value is 1, the input terminal connected to the output of the 4:1 serializer 1311 is selected, and it functions as a 4:1 serializer module. When Width <0> When the value is 0, the input terminal connected to the output terminal of the 2:1 serializer 1313 is selected, and it works as an 8:1 serializer module.

[0106] In an embodiment of the present invention, see Figure 11 As shown, adjustment module 14 includes:

[0107] Level conversion unit 141 is connected to the serializer module and converts the data signal output by the serializer module into level data.

[0108] The logic operation unit 142 is used to perform a preset logic operation on the level data and the impedance configuration code value corresponding to the preset code pattern-impedance mapping table to obtain logic operation data;

[0109] SST drive unit 143, based on the logic operation data, realizes the selection and driving of SST drive chip.

[0110] Furthermore, in embodiments of the present invention, see... Figure 13 As shown, the logic operation unit 142 includes: AND logic gate subunits and OR logic gate subunits connected in parallel, wherein the AND logic gate subunit includes M AND logic gates connected in parallel, and the OR logic gate subunit includes P OR logic gates connected in parallel.

[0111] The AND logic gate sub-unit is used to perform a logical AND operation on the M first data signals in the logical operation data and the pull-down impedance signal; Q of the P OR logic gates are used to perform an OR logic operation on the P second logical operation data (excluding the M first data signals) in the logical operation data and the pull-up impedance signal; PQ OR logic gates are used to perform an OR logic operation on the remaining PQ third logical operation data in the logical operation data and the equalization control signal.

[0112] Further, see Figure 12 As shown, the level conversion unit 141 includes:

[0113] Several inverter units are shown in the figure, with two inverter units indicated by dashed boxes. Each inverter consists of a PMOS and an NMOS transistor. The PMOS transistor's source is connected to the power supply, its gate to the input data, and its drain to the output. The NMOS transistor's source is connected to ground, its gate to the input data, and its drain to the output. This configuration ensures a full-swing output of the data signal.

[0114] The cross-coupled level shifting circuit consists of four PMOS transistors (MP1, MP2, MP3, MP4) and two NMOS transistors (MN1, MN2). The connections are as follows: the source of MP3 is connected to the power supply, its gate is connected to the drain of MP2, and its drain is connected to the source of MP1. The gate of MP1 is connected to the input data, and its drain is connected to the gate of MP4. The gate of MN1 is connected to the input data, and its drain is connected to the gate of MP4. The source of MP4 is connected to the power supply, its gate is connected to the drain of MP1, and the drain of MP1 is connected to the source of MP2. The gate of MP2 is connected to the input data after passing through the inverter unit, and its drain is connected to the gate of MP3. The gate of MN2 is connected to the input data after passing through the inverter unit, and its drain is connected to the gate of MP3.

[0115] VDD is the low-voltage domain power supply, and VDDQ is the high-voltage domain voltage source. When the input data signal level changes from a logic level of "0" to a logic level of "1", MN1 turns on and enters the working state, acting as a discharge point. At this time, the gate voltage of MP4, connected to the drain of MN1, decreases, and MP4 turns on, causing the drain voltage of MP4 to rise. The signal received at the gate of MP2 changes in the opposite direction to the input signal level, changing from a logic level of "1" to a logic level of "0". MP2 turns on and enters the working state, ultimately outputting a high-level signal from the high-voltage domain VDDQ. When the input data signal level changes from a logic level of "0" to a logic level of "1", the operation is similar to the above: MP1, MP3, and MN2 turn on and enter the working state, ultimately outputting a low-level signal.

[0116] Further, see Figure 14 As shown, the SSI driver module 143 includes:

[0117] The pull-up impedance slice 1431 is composed of two PMOS transistors, and the connection relationship between the two PMOS transistors is as follows:

[0118] The source of PMOS transistor MP5 is connected to the power supply level, and the drain of PMOS transistor MP5 is connected to the source of PMOS transistor MP6. The gate of PMOS transistor MP5 is connected to the level data from the pull-up impedance level conversion unit. The source of PMOS transistor MP6 is connected to the drain of PMOS transistor MP5, and the drain of PMOS transistor MP5 is connected to the circuit output. The gate of PMOS transistor MP6 is connected to the pull-up impedance slice enable control signal.

[0119] The balanced slice 1432 consists of two PMOS transistors, and the connection relationship between the two PMOS transistors is as follows:

[0120] The source of PMOS transistor MP7 is connected to the power supply level, its drain is connected to the source of PMOS transistor MP8, and its gate is connected to the level data from the control equalization level conversion unit. The source of PMOS transistor MP8 is connected to the drain of PMOS transistor MP7, its drain is connected to the circuit output, and its gate is connected to the equalization slice enable control signal.

[0121] The pull-down impedance slice 1433 is composed of two NMOS transistors, MN3 and MN4. The connection relationship between the two NMOS transistors is as follows:

[0122] The source terminal of NMOS transistor MP3 is connected to the drain terminal of NMOS transistor MP4. The drain terminal is connected to the circuit output terminal, and the gate terminal is connected to the level data from the pull-down impedance level conversion unit. The drain terminal of NMOS transistor MP4 is connected to the source terminal of NMOS transistor MP3. The source terminal is connected to ground, and the gate terminal is connected to the pull-down impedance slice enable control signal.

[0123] The multi-purpose D2D transmitter circuit provided in this embodiment of the invention includes a data loading module with at least two types of delay units: a low-latency unit and an asynchronous FIFO delay unit. The data loading module selects the corresponding delay unit based on the received mode control signal to delay the data signal and the indicator signal. The data detection module performs an AND operation on the delayed data signal and the indicator signal to obtain valid data. The serializer module obtains the target data based on the valid data. The adjustment module performs logical operations on the target signal and the control signal, and selects the SST driver chip based on the logical operation result to adjust the impedance and equalization. In this embodiment of the invention, the data loading module is equipped with multiple types of delay units, allowing selection of the appropriate delay unit according to actual needs, thereby achieving adjustable delay and adjustable bit width to adapt to various data transmission application scenarios.

[0124] Example 2

[0125] This invention provides a configuration method based on a multi-purpose D2D transmitter circuit, see [link / reference]. Figure 15 As shown, it includes:

[0126] Step S2: Determine the delayed unit to be called based on the received mode selection signal, delay the received data signal and indication signal using the corresponding delay method, and merge the data signal and indication signal obtained by each delayed unit to obtain a merged data signal;

[0127] Step S4: Receive the merged data signal from the data loading module, and perform a logical AND operation on the data signal and the corresponding indicator signal in the merged data signal to obtain valid data;

[0128] Step S6: Based on the received second control signal, select several data from the target input terminal of the corresponding 2:1 serializer or the output terminal of the corresponding 2:1 serializer to obtain the target data with the target bit width; the control signals received by several MUX units are the same; Step S8: Perform logical operation between the external control signal for selecting the number of pull-up, pull-down, and equalization slices and the target data, and select the SST driver slice based on the result of the logical operation to achieve impedance and equalization adjustment.

[0129] The following is a specific example for illustration:

[0130] Based on the received mode selection signal, the asynchronous FIFO delay unit is invoked to delay the received data and indication signals. For example, if the delay control signal requires a 13-clock-cycle delay before the data signal enters the serializer, then the maximum FIFO depth can be configured to 16, and the delay control signal DLY can be configured to 13. Next, the bit width is configured. For instance, if the current serializer's maximum physical bit width is 16, and a 16-bit input width is required for data signal transmission, while an 8-bit input width is required for address signal transmission, then the data signal channel maintains the default 16-bit width configuration. However, for the address signal channel, the control signal of the serializer's internal data selector can be configured to bypass the previous stage serial signal (to the target input of the subsequent serializer) instead of outputting it from the subsequent serializer's output, thus changing the effective input bit width. Finally, the impedance and equalization are configured according to the channel transmission conditions. The configuration process is illustrated using an impedance of 50Ω and an equalization strength of -2dB as an example. Based on the impedance configuration code provided by the lookup table, the configuration code value of the 50Ω impedance in the impedance mapping table is logically operated on with the data signal through external register configuration to obtain logical operation data. This data is then input to the adjustment unit to select the impedance slice, completing the 50Ω impedance matching. Next, the -2dB equalization strength code pattern for the 50Ω impedance provided by the lookup table is configured to the adjustment module through external register configuration to complete the equalization strength configuration. This completes the configuration process for the IO unit in a serial interconnect application scenario. The IO configuration process for parallel interconnect applications is the same as the serial interconnect IO configuration process. Because parallel interconnects require low data latency into the serializer, and because the transmission distance in parallel interconnects is shorter, equalization is not required in most application scenarios, and the equalization adjustment module is disabled. Therefore, the delay and impedance configuration are not required in the parallel interconnect IO unit configuration process; the remaining procedures are the same as the serial interconnect IO configuration.

[0131] The configuration method based on a multi-purpose D2D transmitter circuit provided in this invention first selects a corresponding delay unit to delay the data signal and indication signal according to the received mode control signal; then, the delayed data signal and indication signal are ANDed to obtain valid data; next, the target data is obtained based on the valid data; finally, logical operations are performed on the target signal and control signal, and the SST driver chip is selected based on the logical operation result to achieve impedance and equalization adjustment. In this invention embodiment, the data loading module is equipped with various types of delay units, and the corresponding delay unit can be selected according to actual needs, thereby achieving adjustable delay and adjustable bit width to adapt to various data transmission application scenarios.< / n>

Claims

1. A multi-purpose D2D transmitter, characterized in that, include: The data loading module includes a low-latency unit and an asynchronous FIFO delay unit. It determines the delay unit to be called based on the received mode selection signal, delays the received data signal and indicator signal using the corresponding delay method, and merges the data signal and indicator signal processed by each delay unit to obtain a merged data signal. The data detection module receives the merged data signal from the data loading module and performs an AND operation on the data signal and the corresponding indicator signal in the merged data signal to obtain valid data; wherein, the merged data signal includes the data signal and the corresponding indicator signal. The serializer module consists of several serializer units and several MUX units. The MUX unit determines whether to select the data from the output terminal of the preceding N-stage serializer or the data from the target input terminal of the preceding M-stage serializer based on the received second control signal, thereby obtaining the target data with the target bit width; the control signals received by the several MUX units are the same; The adjustment module includes a logic operation unit, a level conversion unit, and an SST driver unit. It performs logic operations on the control signals from the data loading module and the target data, and selects the SST driver chip based on the result of the logic operation, thereby achieving impedance and equalization adjustment.

2. The multi-purpose D2D transmitter according to claim 1, characterized in that, The data loading module includes: The PBRS unit is used to generate a random code, which includes a data signal and a corresponding valid indication signal; The receiving unit is used to receive data signals and corresponding valid indication signals from the outside. The mode selection unit receives an external SEL control signal and is connected to the PBRS unit and the receiving unit. It is used to select the corresponding delay unit according to the SEL control signal and transmit the data signal from the PBRS or external source and the corresponding valid indication signal to the corresponding delay unit. The delay unit is a low-latency unit or an asynchronous FIFO delay unit. The data merging unit, connected to the low-latency unit and the asynchronous FIFO unit, is used to merge the data signal output by the low-latency unit and the data signal output by the asynchronous FIFO unit to generate a merged data signal.

3. The multi-purpose D2D transmitter according to claim 2, characterized in that, The low-latency unit includes: Two cascaded triggers.

4. The multi-purpose D2D transmitter according to claim 2, characterized in that, The asynchronous FIFO delay unit includes: The counter receives a delay control signal DLY and determines the data reading time based on the delay control signal DLY. The FIFO asynchronous module is also used to receive a depth control signal DEP to control the delay depth of the FIFO asynchronous module.

5. The multi-purpose D2D transmitter according to claim 1, characterized in that, The data detection module includes: A number of AND gate logic units connected in parallel receive the merged data signal, and simultaneously perform preset delay processing on the data signal and the corresponding valid indication signal in the merged data signal, and perform AND operation on the delayed data signal and the valid indication signal to output valid data.

6. The multi-purpose D2D transmitter according to claim 1, characterized in that, The serializer module includes: Several 2:1 and 4:1 serializers are connected to the data detection module according to the target required bit width to convert the received parallel data into serial data; Several MUX units receive external control signals and determine, based on the control signals, whether to select data from the output of the corresponding serializer or the target input. The final stage serializer is connected to the MUX unit and performs serial processing on the output data of each MUX unit to obtain the target data.

7. The multi-purpose D2D transmitter according to claim 1, characterized in that, The adjustment module includes: The logic operation unit is used to perform logic operations on the target data and the corresponding impedance configuration code value in the preset code pattern-impedance mapping table to obtain logic operation data. The data is used to perform logical operations on the target data and the external control signals for selecting the number of pull-up, pull-down, and equalization slices to obtain logical operation data. The code value of the external control signals for selecting the number of pull-up, pull-down, and equalization slices is the preset impedance configuration code value of the impedance mapping table. A level conversion unit, connected to a logic operation unit, converts the logic operation data into level data; The SST driving unit, based on the level data, enables the selection and driving of the SST driving chip.

8. The multi-purpose D2D transmitter according to claim 7, characterized in that, The logic operation module includes: AND logic gate units and OR logic gate units connected in parallel, wherein the AND logic gate unit includes M AND logic gates connected in parallel, and the OR logic gate unit includes P OR logic gates connected in parallel. The AND gate is used to perform an AND operation on the M data signals in the logic operation data and the pull-down impedance signal; Q of the P OR gates are used to perform an OR operation on the P second logic operation data (excluding the M first data signals) in the logic operation data and the pull-up impedance signal; PQ OR gates are used to perform an OR operation on the remaining PQ third logic operation data in the logic operation data and the equalization control signal.

9. The multi-purpose D2D transmitter according to claim 7, characterized in that, The SST driver module includes: The pull-up impedance slice is composed of two PMOS transistors. The connection relationship between the two PMOS transistors is as follows: the source terminal of the first PMOS transistor is connected to the power supply level, the drain terminal is connected to the source terminal of the second PMOS transistor, and the gate terminal is connected to the level data from the control pull-up impedance level conversion unit; the source terminal of the second PMOS transistor is connected to the drain terminal of the first PMOS transistor, the drain terminal is connected to the circuit output terminal, and the gate terminal is connected to the pull-up impedance slice enable control signal. The balanced slice consists of two PMOS transistors, and the connection relationship between the two PMOS transistors is as follows: The source of the third PMOS transistor is connected to the power supply level, its drain is connected to the source of the fourth PMOS transistor, and its gate is connected to the level data from the control equalization level conversion unit; the source of the fourth PMOS transistor is connected to the drain of the third PMOS transistor, its drain is connected to the circuit output, and its gate is connected to the equalization slice enable control signal. The pull-down impedance slice is composed of two NMOS transistors, and the connection relationship between the two NMOS transistors is as follows: The source of the first NMOS transistor is connected to the drain of the second NMOS transistor. The drain is connected to the circuit output, and the gate is connected to the level data from the pull-down impedance level conversion unit. The drain of the second NMOS transistor is connected to the source of the first NMOS transistor. The source is connected to ground, and the gate is connected to the pull-down impedance slice enable control signal.

10. A configuration method based on a multi-purpose D2D transmitter, characterized in that, include: Based on the received mode selection signal, the delayed unit to be invoked is determined, the received data signal and indication signal are delayed using the corresponding delay method, and the data signal and indication signal obtained from each delayed unit are merged to obtain a merged data signal; The system receives a merged data signal from the data loading module, performs an AND operation between the data signal in the merged data signal and the corresponding indicator signal to obtain valid data; the delay processing corresponds to the mode selection signal and control signal received by the data loading module; wherein, the merged data signal includes a data signal and a corresponding indicator signal; Based on the received second control signal, a number of data that have passed through the previous stage serialization or have not passed through the previous stage serialization are selected to obtain the target data with the target bit width; the control signals received by the multiple MUX units are the same; The control signal from the data loading module is used to perform logical operations on the target data. Based on the result of the logical operations, the SST driver chip is selected, thereby achieving impedance and equalization adjustment.

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