Square resistance prediction model training method and square resistance prediction method

Abstract

The application discloses a square resistance prediction model training method and a square resistance prediction method, and belongs to the technical field of semiconductors. The method comprises the following steps: obtaining a training set; determining a plurality of relative differences between an optimized process and a plurality of key parameters of each sample in the training set according to a design rule of the optimized process, wherein the optimized process is obtained by optimizing a source process; obtaining a square resistance prediction model, wherein the square resistance prediction model is constructed based on a physical relationship between square resistance and the plurality of key parameters; and training the square resistance prediction model by using a plurality of samples in the training set and the plurality of relative differences of each sample. The method can realize high-precision square resistance prediction.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for training a sheet resistance prediction model and a method for predicting sheet resistance. Background Technology

[0002] In 40nm and more advanced semiconductor nodes, accurate prediction of sheet resistance (Rs) of metal layers in BeoL (Back End of Line) is crucial for device performance, yield and reliability.

[0003] In advanced semiconductor manufacturing processes, the sheet resistance must be strictly controlled within 0.5–0.8 ohms. (or Fluctuations are allowed to be less than 5%, but due to variations in CMP process and uneven media thickness (such as...), Due to factors such as etching load, the actual deviation of sheet resistance often reaches 8–10%, which seriously affects the electrical properties of semiconductors.

[0004] In the current manufacturing environment, silicon wafer measurement data is characterized by its multi-dimensionality and high volume (TB / batch), making it difficult to achieve efficient and accurate sheet resistance prediction using traditional methods relying on manual experience. This problem is particularly prominent in new product development. The lack of accurate sheet resistance prediction leads to extended semiconductor development cycles, with a single BEoL process iteration requiring 6–12 weeks and engineering tape-out costs reaching millions of dollars. To approach the optimal process window, numerous parameter combinations (such as annealing temperature, deposition rate, CMP pressure, etc.) need to be validated, further increasing time and economic investment. This high-cost, long-cycle trial-and-error model significantly slows down technology maturity and product launch, hindering R&D investment returns and commercialization progress. Summary of the Invention

[0005] This invention provides a method for training a sheet resistance prediction model and a method for predicting sheet resistance, which can achieve high-precision sheet resistance prediction. The technical solution includes at least the following:

[0006] Firstly, a method for training a sheet resistance prediction model is provided, comprising: acquiring a training set, the training set including multiple samples, each sample including the sheet resistance of a k-th transistor in a source process, multiple key parameters associated with the sheet resistance, and the sheet resistance of the k-th transistor in an optimized process, the multiple key parameters including metal linewidth, metal line thickness, and metal material resistivity; determining multiple relative differences between the optimized process and multiple key parameters of each sample in the training set according to the design rules of the optimized process, the optimized process being optimized based on the source process; acquiring a sheet resistance prediction model, the sheet resistance prediction model being constructed based on the physical relationship between the sheet resistance and multiple key parameters; training the sheet resistance prediction model using multiple samples in the training set and multiple relative differences of each sample, wherein during the training of the sheet resistance prediction model, the parameters of the sheet resistance prediction model are optimized using a backpropagation gradient method.

[0007] Optionally, in the physical relationship between the sheet resistance and multiple key parameters, the sheet resistance is inversely proportional to the metal wire width and metal wire thickness, and directly proportional to the resistivity of the metal material; the sheet resistance prediction model is expressed by the following formula:

[0008]

[0009] in, Let be the sheet resistance of the i-th sample of the k-th transistor in the source process. The sheet resistance of the i-th sample of the k-th transistor predicted by the sheet resistance prediction model in the optimized process. , , The physical relationship coefficients in the sheet resistance prediction model are obtained using a neural network sub-model. This neural network sub-model is a sub-model within the sheet resistance prediction model. The input to the neural network sub-model is the plurality of relative differences, and the output of the neural network sub-model is the physical relationship coefficient. The relative difference in metal linewidth between the i-th sample of the k-th transistor in the optimized process and the source process. The relative difference in metal line thickness between the i-th sample of the k-th transistor in the optimized process and the source process. The relative difference in resistivity of the metal material between the i-th sample of the k-th transistor in the optimized process and the source process.

[0010] Optionally, the relative difference between the metal linewidths of the i-th sample of the k-th transistor in the optimized process and the source process is calculated using the following formula:

[0011]

[0012] in, The linewidth of the metal line indicated in the design rules of the optimized process for the k-th transistor. The linewidth of the metal line in the source process for the i-th sample of the k-th transistor;

[0013] The relative difference between the metal line thickness of the i-th sample of the k-th transistor in the optimized process and the source process is calculated using the following formula:

[0014]

[0015] in, The metal line thickness of the k-th transistor is indicated in the design rules of the optimized process. The metal line thickness of the i-th sample of the k-th transistor in the source process;

[0016] The relative difference between the resistivity of the metal material in the optimized process and the source process for the i-th sample of the k-th transistor is calculated using the following formula:

[0017]

[0018] in, Let the resistivity of the metal material be the value indicated by the design rules of the optimized process for the k-th transistor. The resistivity of the metal material in the source process is the i-th sample of the k-th transistor.

[0019] Optionally, during the training of the sheet resistance prediction model, the loss function is expressed by the following formula:

[0020]

[0021] in, Let be the loss function, representing the physical relationship coefficients predicted by the neural network sub-model in the sheet resistance prediction model. , , The loss, The sheet resistance prediction model is the predicted sheet resistance in the optimized process for the i-th sample corresponding to the k-th transistor. Let i be the label of the i-th sample corresponding to the k-th type of transistor, where i is a sample in the training set, and i is a positive integer ranging from 1 to 1. , The total number of samples corresponding to the k-th type of transistor in the training set.

[0022] Secondly, a method for training a sheet resistance prediction model is provided, comprising: acquiring multiple key parameters of a target transistor, wherein the target transistor is a transistor actually produced in an optimized process, the target transistor belongs to a k-th type of transistor, and the multiple key parameters include metal linewidth, metal line thickness, and metal material resistivity; acquiring a reference sample of the source process of the k-th type of transistor, and calculating multiple relative differences between the target transistor and the reference sample in multiple key parameters; inputting the multiple relative differences between the target transistor and the reference sample in multiple key parameters, and the reference sample of the source process of the k-th type of transistor into a sheet resistance prediction model to obtain the sheet resistance of the target transistor in the optimized process; wherein the sheet resistance prediction model is obtained using the aforementioned sheet resistance prediction model training method.

[0023] Thirdly, a sheet resistance prediction model training device is also provided, comprising: a first acquisition module for acquiring a training set, the training set including multiple samples, each sample including the sheet resistance of a k-th transistor in a source process, multiple key parameters associated with the sheet resistance, and the sheet resistance of the k-th transistor in an optimized process, the multiple key parameters including metal linewidth, metal line thickness, and metal material resistivity; a relative difference determination module for determining multiple relative differences between the optimized process and multiple key parameters of each sample in the training set according to the design rules of the optimized process, the optimized process being optimized based on the source process; a second acquisition module for acquiring a sheet resistance prediction model, the sheet resistance prediction model being constructed based on the physical relationship between the sheet resistance and multiple key parameters; and a training module for training the sheet resistance prediction model using multiple samples in the training set and multiple relative differences of each sample, wherein the parameters of the sheet resistance prediction model are optimized using a backpropagation gradient method during the training process.

[0024] Optionally, in the second acquisition module, in the physical relationship between the sheet resistance and multiple key parameters, the sheet resistance is inversely proportional to the metal wire width and the metal wire thickness, and the sheet resistance is directly proportional to the resistivity of the metal material.

[0025] The sheet resistance prediction model is expressed by the following formula:

[0026]

[0027] in, Let be the sheet resistance of the i-th sample of the k-th transistor in the source process. The sheet resistance of the i-th sample of the k-th transistor predicted by the sheet resistance prediction model in the optimized process. , , The physical relationship coefficients in the sheet resistance prediction model are obtained using a neural network sub-model. This neural network sub-model is a sub-model within the sheet resistance prediction model. The input to the neural network sub-model is the plurality of relative differences, and the output of the neural network sub-model is the physical relationship coefficient. The relative difference in metal linewidth between the i-th sample of the k-th transistor in the optimized process and the source process. The relative difference in metal line thickness between the i-th sample of the k-th transistor in the optimized process and the source process. The relative difference in resistivity of the metal material between the i-th sample of the k-th transistor in the optimized process and the source process.

[0028] Optionally, in the relative difference determination module, the relative difference between the metal linewidth of the i-th sample of the k-th transistor in the optimized process and the source process is calculated using the following formula:

[0029]

[0030] in, The linewidth of the metal line indicated in the design rules of the optimized process for the k-th transistor. The linewidth of the metal line in the source process for the i-th sample of the k-th transistor;

[0031] The relative difference between the metal line thickness of the i-th sample of the k-th transistor in the optimized process and the source process is calculated using the following formula:

[0032]

[0033] in, The metal line thickness of the k-th transistor is indicated in the design rules of the optimized process. The metal line thickness of the i-th sample of the k-th transistor in the source process;

[0034] The relative difference between the resistivity of the metal material in the optimized process and the source process for the i-th sample of the k-th transistor is calculated using the following formula:

[0035]

[0036] in, Let the resistivity of the metal material be the value indicated by the design rules of the optimized process for the k-th transistor. The resistivity of the metal material in the source process is the i-th sample of the k-th transistor.

[0037] Optionally, in the training module, during the training of the sheet resistance prediction model, the loss function is expressed by the following formula:

[0038]

[0039] in, Let be the loss function, representing the physical relationship coefficients predicted by the neural network sub-model in the sheet resistance prediction model. , , The loss, The sheet resistance prediction model is the predicted sheet resistance in the optimized process for the i-th sample corresponding to the k-th transistor. Let i be the label of the i-th sample corresponding to the k-th type of transistor, where i is a sample in the training set, and i is a positive integer ranging from 1 to 1. , The total number of samples corresponding to the k-th type of transistor in the training set.

[0040] Fourthly, a sheet resistance prediction device is also provided, comprising: a first acquisition module for acquiring multiple key parameters of a target transistor, wherein the target transistor is a transistor actually produced in an optimized process, the target transistor belongs to a k-th type of transistor, and the multiple key parameters include metal linewidth, metal line thickness, and metal material resistivity; a second acquisition module for acquiring a reference sample of the source process of the k-th type of transistor, and calculating multiple relative differences between the target transistor and the reference sample in multiple key parameters; and a sheet resistance prediction module for inputting the multiple relative differences between the target transistor and the reference sample in multiple key parameters, and the reference sample of the source process of the k-th type of transistor, into a sheet resistance prediction model to obtain the sheet resistance of the target transistor in the optimized process; wherein the sheet resistance prediction model is obtained using the sheet resistance prediction model training method described in the first aspect.

[0041] Fifthly, a computer device is also provided, comprising: a memory and a processor, wherein the memory stores at least one computer program, the at least one computer program being loaded and executed by the processor to perform the sheet resistance prediction model training method and the sheet resistance prediction method described in the above embodiments.

[0042] Sixthly, a computer-readable storage medium is also provided, wherein at least one computer program is stored in the computer-readable storage medium, the at least one computer program being loaded and executed by a processor to perform the sheet resistance prediction model training method and the sheet resistance prediction method described in the above embodiments.

[0043] In a seventh aspect, a computer program product is provided, comprising a computer program / instructions that, when executed by a processor, implement the method described in the first or second aspect.

[0044] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following:

[0045] The unexpected technical effect of this invention lies in the following: Since the optimized process is derived from the source process, there is a certain nonlinear correlation between the sheet resistance of the same transistor in the optimized process and that in the source process. Key parameters (metal linewidth, metal line thickness, and metal resistivity) are crucial factors affecting sheet resistance. Therefore, based on the relative differences in these key parameters between the source and optimized processes, the nonlinear correlation between the sheet resistance of the optimized and source processes can be fitted, thus creating a sheet resistance prediction model. This sheet resistance prediction model enables accurate and efficient sheet resistance prediction, thereby improving process controllability, shortening the development cycle, and reducing costs. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in this embodiment, the accompanying drawings used in the description of the embodiment will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 A flowchart of a sheet resistance prediction model training method provided by an exemplary embodiment of the present invention is shown;

[0048] Figure 2 This is a schematic diagram showing the relationship between sheet resistance and metal wire thickness;

[0049] Figure 3 This is a schematic diagram of the evaluation index of the sheet resistance prediction results of the trained sheet resistance prediction model on two different metal layer structures, 1XSD and 1XDD.

[0050] Figure 4 This is a schematic diagram of the sheet resistance prediction model on the N-nanometer optimized process, given that the training set is data from M-nanometer and N-nanometer process nodes.

[0051] Figure 5 A flowchart of a sheet resistance prediction method provided by an exemplary embodiment of the present invention is shown;

[0052] Figure 6 This diagram illustrates the structure of a sheet resistance prediction model training device provided in an exemplary embodiment of the present invention.

[0053] Figure 7 A schematic diagram of the sheet resistance prediction device provided in an exemplary embodiment of the present invention is shown.

[0054] Figure 8 This is a schematic diagram of the structure of a computer device provided in an exemplary embodiment of the present invention. Detailed Implementation

[0055] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, but do not exclude other elements or objects.

[0056] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0057] Figure 1 A flowchart illustrating a sheet resistance prediction model training method according to an exemplary embodiment of the present invention is shown, which can be executed by a computer device. See also Figure 1 The method includes:

[0058] In step 101, the training set is obtained.

[0059] The training set includes multiple samples, each of which includes the sheet resistance of the k-th transistor in the source process, several key parameters associated with the sheet resistance, and the sheet resistance of the k-th transistor in the optimized process.

[0060] Here, the sheet resistance of the k-th transistor in the optimized process is the label of this sample.

[0061] Here, the source process refers to a semiconductor process that has already been put into production and has accumulated multiple production experiences, while the optimized process is a process that is optimized based on the source process. For example, the source process can be represented as the N-process, indicating an N-nanometer process, while the optimized process can be represented as the N-EC process, indicating a process that is optimized based on the N-nanometer process. The N-nanometer process can be common nanometer processes such as 7 nanometers, 14 nanometers, 28 nanometers, 40 nanometers, 55 nanometers, and 90 nanometers.

[0062] Since the source process is a semiconductor process that has already been put into production and has accumulated extensive production experience, there are multiple production runs of sheet resistance during the manufacturing process using the source process. At this point, the key parameters of each transistor are known. Based on these key parameters and historical production data from the source process, multiple samples can be constructed for each transistor.

[0063] Optionally, several key parameters include: wire width, wire thickness, and resistivity of the metal material.

[0064] For the same type of transistor, there is a certain non-linear correlation between the sheet resistance of the source process and the sheet resistance of the optimized process.

[0065] For the same type of transistor, multiple samples of that transistor exist in the source process. Each sample is tagged with the sheet resistance of the transistor in the optimized process at the same key parameters as that sample. For example, the tag can be obtained by simulating the transistor in the optimized process or measuring the transistor in the actual device.

[0066] In step 102, based on the design rules of the optimized process, several relative differences between the optimized process and several key parameters of each sample in the training set are determined.

[0067] The design rules for optimizing the manufacturing process are known. These rules specify the metal linewidth, metal line thickness, and resistivity of the metal material, which can also be obtained through simulation.

[0068] Optionally, the relative difference between the metal linewidth of the i-th sample of the k-th transistor in the optimized process and the source process is calculated using the following formula (1).

[0069] (1)

[0070] In formula (1), Let represent the relative difference in metal linewidth between the i-th sample of the k-th transistor in the optimized process and the original process. Let be the metal linewidth indicated by the design rules for the k-th transistor in the optimized manufacturing process. Let be the metal linewidth of the i-th sample of the k-th transistor in the source process;

[0071] Optionally, the relative difference between the metal line thickness of the i-th sample of the k-th transistor in the optimized process and the source process is calculated using the following formula (2).

[0072] (2)

[0073] In formula (2), Let represent the relative difference in metal line thickness between the i-th sample of the k-th transistor and the source process. Let be the metal line thickness indicated in the design rules for the k-th transistor in the optimized manufacturing process. The metal line thickness of the i-th sample of the k-th transistor in the source process;

[0074] Optionally, the relative difference between the resistivity of the metal material in the optimized process and the source process for the i-th sample of the k-th transistor is calculated using the following formula (3).

[0075] (3)

[0076] In formula (3), Let be the relative difference in resistivity of the metal material between the i-th sample of the k-th transistor and the source process. Let be the resistivity of the metal material indicated in the design rules for the k-th transistor in the optimized manufacturing process. Let be the resistivity of the metal material in the source process for the i-th sample of the k-th transistor.

[0077] In the above formulas (1) to (3), , , It is a key parameter in the design rules of the k-th transistor in the optimized process, which is a constant value. , , Then it belongs to the actual production parameters of the i-th sample of the k-th type of transistor in the source process.

[0078] Typically, in real-world production data, the key parameters and sheet resistance of all k-th transistors are not exactly the same during production (i.e., there are slight fluctuations within the tolerance allowed by the design rules, but production is essentially based on the design rules). Furthermore, the actual production data for the k-th transistor is finite. If only real-world production data is used as samples for training, there may be insufficient sample size; therefore, the samples in the training set can be expanded.

[0079] The case of constructing the i-th sample of the k-th transistor based on historical production data is illustrated below. In this case, the virtual sample can be calculated using formulas (4) to (6), which is used to expand the training set.

[0080] (4)

[0081] (5)

[0082] (6)

[0083] In formulas (4) to (6), , , These are the key parameters of the j-th sample of the k-th transistor, representing the metal linewidth, metal line thickness, and resistivity of the metal material, respectively. The j-th sample of the k-th transistor is different from the i-th sample of the k-th transistor, and it is also obtained based on historical production data. , , These are the key parameters in the virtual sample constructed from the j-th sample of the k-th transistor, representing the linewidth, thickness, and resistivity of the metal line in the virtual sample constructed from the j-th sample of the k-th transistor. The meanings of the other parameters in formulas (4) to (6) are the same as those in formulas (1) to (6), and are omitted here.

[0084] The sheet resistance of the aforementioned virtual samples in the source process can be obtained by simulating the sheet resistance of the source process. For example, the sheet resistance of the source process can be simulated based on the key parameters of each virtual sample, thereby obtaining the sheet resistance of each virtual sample in the source process. Since the source process is a process that has already been put into production, the sheet resistance simulation model of the source process can be directly obtained (usually it has already been built during the production process).

[0085] Assuming that a total of I samples are constructed based on historical production data, then for any one of these I samples, I-1 virtual samples can be constructed using the above formulas (4) to (6). Therefore, a total of I-1 virtual samples can be constructed. There are 10 virtual samples, which, together with the original I samples constructed based on historical production data, total 100 virtual samples. This expands the training set by adding samples.

[0086] Multiple samples and virtual samples constructed based on historical production data only contain the key parameters and sheet resistance of each sample in the source process. The actual training set also needs to obtain the label for each sample. To obtain the label for each sample, a large-scale simulation model of the optimized process is required. This large-scale simulation model can simulate the entire production process of the optimized process, thus simulating the sheet resistance of the k-th transistor in the optimized process under the same key parameters, which is the label for each sample. For example, the label of the i-th sample of the k-th transistor is represented as... However, large-scale simulation models consume a lot of resources and take a long time to perform a single simulation. If only large-scale simulation models are used to obtain the sheet resistance in the optimized process, there will be problems of low efficiency and high cost. Therefore, large-scale simulation models can only be used to construct tags, and are not suitable for large-scale and efficient prediction of sheet resistance in the optimized process.

[0087] In summary, the i-th sample of the k-th transistor can be represented as ( , , , , ).in, It is the label of the i-th sample of the k-th transistor. It is the sheet resistance of the i-th sample of the k-th transistor in the source process. , , These are the key parameters of the i-th sample of the k-th transistor, namely the metal line width, metal line thickness, and metal material resistivity.

[0088] The process of obtaining the label for each sample requires a large-scale simulation model for optimized manufacturing processes. While this model can achieve high accuracy in simulating the sheet resistance of optimized processes, it suffers from long simulation times, low efficiency, and high costs per simulation, making it difficult to achieve end-to-end, efficient sheet resistance prediction for optimized processes. In this embodiment, the sheet resistance prediction model used in subsequent step 103 is a small-scale, high-efficiency prediction model that can achieve end-to-end, efficient, and accurate sheet resistance prediction for optimized processes.

[0089] In step 103, the sheet resistance prediction model is obtained.

[0090] The sheet resistance prediction model is constructed based on the physical relationship between sheet resistance and several key parameters.

[0091] In the physical relationship between sheet resistance and several key parameters, sheet resistance is inversely proportional to the wire width and wire thickness, and directly proportional to the resistivity of the metal material. This relationship can be expressed as: .in It is a sheet resistor. The resistivity of metallic materials. For metal wire width, The thickness is the metal wire thickness.

[0092] Figure 2 This is a schematic diagram showing the relationship between sheet resistance and metal wire thickness. Figure 2 In the diagram, the horizontal axis represents the metal wire thickness, and the vertical axis represents the sheet resistance predicted by the sheet resistance prediction model. For example... Figure 2 As shown, 1XSD stands for 1X Source / Drain, representing the front-end contact metal layer under 1x design rule; 1XDD stands for 1X Design-Dependent, representing the back-end interconnect metal layer under 1x design rule.

[0093] It can be seen that on both 1XSD and 1XDD metal layers, the sheet resistance of both Si (silicon) and Al (aluminum) is negatively correlated with the thickness of the metal line.

[0094] Based on the above physical relationships, the sheet resistance prediction model is expressed by the following formula (7).

[0095] (7)

[0096] In formula (7), Let be the sheet resistance of the i-th sample of the k-th transistor in the source process. The sheet resistance of the i-th sample of the k-th transistor predicted by the sheet resistance prediction model in the optimized process. , , The physical relationship coefficients in the sheet resistance prediction model are predicted using a neural network sub-model. The neural network sub-model is a sub-model in the sheet resistance prediction model. The input of the neural network sub-model is multiple relative differences, and the output of the neural network sub-model is the physical relationship coefficients. The meanings of the other parameters in formula (7) are the same as those in formulas (1) to (3), and are omitted here.

[0097] The aforementioned sheet resistance prediction model is essentially applicable when the linewidth, line thickness, and resistivity of the metal material in both the source and optimized processes are known, and it proposes a nonlinear relationship between the sheet resistance of a transistor in the source process and the sheet resistance in the optimized process.

[0098] Since the optimized process is derived from the source process, there is a certain non-linear correlation between the sheet resistance of the optimized process and that of the source process. Furthermore, the aforementioned key parameters (metal linewidth, metal line thickness, and metal material resistivity) are crucial factors affecting the sheet resistance. Therefore, by leveraging the relative differences in these key parameters between the source and optimized processes, a non-linear correlation between the sheet resistance of the optimized process and that of the source process can be established.

[0099] In the initial construction of the sheet resistance prediction model, physical relationship coefficients can be used. , , An initial value is set, and then the parameters of the sheet resistance prediction model are continuously iterated during training to update the physical relationship coefficients. , , The value of is then used to learn the nonlinear relationship between the sheet resistance of the source process and the sheet resistance of the optimized process.

[0100] For example, the sheet resistance prediction model is a machine learning model, such as a deep neural network (DNN).

[0101] For example, the sheet resistance prediction model includes, in sequence, an input layer, a first hidden layer, a second hidden layer, an output layer, and a physical formula layer. Here, the input layer, the first hidden layer, the second hidden layer, and the output layer are equivalent to a neural network sub-model, used to fit physical relationship coefficients based on relative differences. , , The input to this neural network sub-model is multiple relative differences. , , The output consists of three physical relationship coefficients. , , The physical formula layer is used to predict sheet resistance for process optimization.

[0102] Therefore, multiple relative differences , , The input is fed into the input layer, and then processed by the first hidden layer, the second hidden layer, and the output layer to obtain the physical relationship coefficients in the fitted formula (7). , , Then, multiple relative differences ( , , The sheet resistance of the i-th sample of the k-th transistor. Physical relationship coefficients fitted by the output layer , , The input is sent to the physical formula layer, and then the physical formula layer calculates the sheet resistance of the i-th sample of the k-th transistor in the optimized process using formula (7).

[0103] Suppose the first hidden layer has 4 neurons, and the parameter matrix is... The bias vector is The second hidden layer has 3 neurons, and the parameter matrix is... The bias vector is The output layer has 3 neurons, and the parameter matrix is... The bias vector is .

[0104] Multiple relative differences After input to the input layer, The processing in the first hidden layer can be represented as ,in This is the output of the first hidden layer. This represents the ReLU activation function. Similarly, the output of the first hidden layer... After inputting into the second hidden layer, The processing in the second hidden layer can be represented as .in This is the output of the second hidden layer. The output layer is a linear layer and can output physical relationship coefficients without an activation function. , , The output of the second hidden layer The processing in the output layer can be represented as follows: .

[0105] Therefore, the process of optimizing the parameters of the sheet resistance prediction model during subsequent training is essentially an optimization of the parameter matrix based on the total loss. , , and bias vector , , The process of optimizing the parameters of a neural network sub-model is essentially the process of optimizing the parameter matrix. This can be achieved using common neural network parameter optimization methods (such as backpropagation gradient methods). , , and bias vector , , In order to optimize the parameters of the sheet resistance prediction model. , , The purpose.

[0106] In this embodiment, the physical relationship coefficients of the sheet resistance prediction model , , Composed of multiple relative differences and parameter matrix , , and bias vector , , Decision. After the sheet resistance prediction model is trained, the parameter matrix... , , and bias vector , , This solidifies the multiple relative differences in the process to be predicted and optimized. Since these differences are known, we can now predict and optimize multiple relative differences in the process. The input is fed into the input layer, and the current physical relationship coefficients are then obtained from the output layer. , , (Physical relationship coefficients at this time) , , (It is accurate and reliable). Then, the current physical relationship coefficients are... , , The current sample's source process sheet resistance Multiple relative differences After being input into the physical formula layer, the output of the physical formula layer is used as the sheet resistance of the currently predicted optimized process.

[0107] In step 104, the sheet resistance prediction model is trained using multiple samples from the training set and multiple relative differences for each sample.

[0108] During the training of the sheet resistance prediction model, the total loss of the current training round is calculated based on the loss function, and the parameters of the sheet resistance prediction model are optimized using the backpropagation gradient method based on the total loss of the current training round, thereby completing the training of the current round and entering the next round of training.

[0109] Optionally, the loss function is expressed by formula (8).

[0110] (8)

[0111] In formula (8), Let be the loss function, representing the physical relationship coefficients predicted by the neural network sub-model in the sheet resistance prediction model. , , The loss, This represents the sheet resistance predicted by the sheet resistance prediction model on the i-th sample corresponding to the k-th transistor in the optimized process. Let be the label of the i-th sample corresponding to the k-th transistor. The i-th sample corresponding to the k-th transistor is a sample in the training set, where i is a positive integer ranging from 1 to 1. , This represents the total number of samples corresponding to the k-th type of transistor in the training set.

[0112] There are many existing technologies regarding the implementation of the backpropagation gradient method, so we will omit the details here.

[0113] Table 1: Three sample instances in the training set.

[0114]

[0115] As shown in Table 1 above, a total of 3 different samples belonging to the k-th transistor are included. In sample 1, the relative difference between the optimized process and the metal linewidth of sample 1 is discussed. The relative difference between the optimized process and the metal line thickness of Sample 1 is 1.2. The relative difference between the resistivity of the optimized process and the metallic material in Sample 1 is 0.8. The sheet resistance of sample 1 in the source process is 10.0 Ω, which is 1.5 Ω. The label for sample 1 is 5.0. The meanings of the parameters in Sample 2 and Sample 3 are similar to those in Sample 1, and will not be detailed here.

[0116] Let the physical relationship coefficients be initially set. , , The values ​​are all 0.5. Substituting samples 1 to 3 into formula (7), the predicted values ​​of samples 1, 2, and 3 output by the sheet resistance prediction model are 12.50, ... 6.88 12.00 .

[0117] Substituting the predicted values ​​of samples 1 to 3 and the labels into formula (8), the total loss can be calculated as 100.54.

[0118] Then, backpropagation gradient calculation is performed and parameters are updated. , , The value of this parameter can be used to obtain the parameters in the next round (the second round of training). , , The values ​​were 0.79, 0.16, and -0.18, respectively.

[0119] Based on the parameters in the second round of training , , Substituting the value into formula (7), the predicted value for sample 1 is calculated to be 8.40. As can be seen, compared with the first round, the predicted value of sample 1 in the second round is closer to the label of sample 1 (the difference between the predicted value of sample 1 and the label in the first round is 7.5, and the difference between the predicted value of sample 1 and the label in the second round is 3.4). Therefore, the loss calculated in the second round will decrease significantly, indicating that the parameter update direction of the sheet resistance prediction model is correct.

[0120] In this embodiment, for transistors other than the k-th type, the corresponding sheet resistance prediction model can be trained in the same way as steps 101 to 104, thereby enabling the prediction of the sheet resistance of each type of transistor in the optimized process.

[0121] Figure 3 This is a schematic diagram of the evaluation index of the sheet resistance prediction results of the trained sheet resistance prediction model on two different metal layer structures, 1XSD and 1XDD.

[0122] The trained sheet resistance prediction model was used to predict sheet resistance on two different metal layer structures, 1XSD and 1XDD, with optimized processes. Evaluation metrics for the prediction results were calculated, including Mean Absolute Percentage Error (MAPE) and the coefficient of determination. .like Figure 3 As shown in the figure. It can be seen that the sheet resistance prediction model exhibits excellent performance in sheet resistance prediction. Although the sheet resistance changes differently between 1XSD and 1XDD due to differences in process structure, the model can still accurately capture and predict its characteristics, demonstrating strong adaptability and high prediction accuracy to diverse metal layer structures.

[0123] Figure 4 This diagram illustrates the sheet resistance prediction results of the model on an optimized N-nanometer process, given that the training set consists of data from M-nanometer and N-nanometer process nodes. Here, both M-nanometer and N-nanometer processes can be common nanometer processes such as 7nm, 14nm, 28nm, 40nm, 55nm, and 90nm, and they are distinct processes. The optimized N-nanometer process is a process optimized based on the N-nanometer process.

[0124] Figure 4 In the diagram, the horizontal axis represents different process nodes (Mnm process, Nnm process, and Nnm optimized process), and the vertical axis represents sheet resistance. The blue markers represent the sheet resistance predicted by the sheet resistance prediction model for the Nnm optimized process, the red markers represent the sheet resistance for the Nnm process in the training set, and the green markers represent the sheet resistance for the Mnm process in the training set. It can be seen that there is indeed a non-linear relationship between the sheet resistance of the Mnm and Nnm processes and the sheet resistance of the Nnm optimized process (i.e.,...). Figure 4 (The blue arc in the middle).

[0125] exist Figure 4 In this case, the MAPE of the sheet resistance prediction model is approximately 3%. The value is approximately 0.93. This result verifies the model's good generalization ability across process nodes, highlighting its scalability and application potential in advanced process development.

[0126] In this embodiment, since the optimized process is obtained by optimizing the source process, there is a certain nonlinear correlation between the sheet resistance of the optimized process and the sheet resistance of the source process. Key parameters (metal linewidth, metal line thickness, and metal material resistivity) are crucial parameters affecting the sheet resistance. Therefore, based on the relative differences in key parameters between the source and optimized processes, the nonlinear correlation between the sheet resistance of the optimized process and the sheet resistance of the source process can be fitted, thereby modeling a sheet resistance prediction model. The sheet resistance prediction model is then trained using the methods described in steps 101 to 104. This sheet resistance prediction model can achieve accurate and efficient sheet resistance prediction, thereby improving process controllability, shortening the R&D cycle, and reducing costs.

[0127] The sheet resistance prediction method in this embodiment is widely applicable to single-damascus and double-damascus processes, and can accurately and efficiently predict the sheet resistance of various transistors.

[0128] Figure 5 A flowchart illustrating a sheet resistance prediction method provided by an exemplary embodiment of the present invention is shown, the method being executable by a computer device. See also Figure 5 The method includes:

[0129] In step 501, several key parameters of the target transistor are obtained.

[0130] The target transistor is a transistor that is actually produced in the optimized process. The target transistor belongs to the k-th type of transistor, and several key parameters include the metal line width, metal line thickness, and metal material resistivity.

[0131] Here, the design rules for the k-th transistor in the optimized process were used when constructing the training set. However, in actual production, the key parameters of the k-th transistor produced in the optimized process are not necessarily exactly the same as the design rules of the optimized process. Therefore, for the target transistor actually produced in the optimized process, it is necessary to obtain its actual key parameters rather than the design rules of the optimized process.

[0132] In step 502, a reference sample of the source process of the k-th transistor is obtained, and several relative differences between the target transistor and the reference sample are calculated.

[0133] According to the contents recorded in formulas (1) to (3) and formula (7), when calculating multiple relative differences, a sample from a source process (including) is required. , , , During the training phase of the sheet resistance prediction model, , , , It is known, but after the sheet resistance prediction model is trained, when using the sheet resistance prediction model to predict the sheet resistance in the actual optimized process, the required selection is... , , , The value of the sheet resistance is unknown. Therefore, it is necessary to construct a reference sample of the source process and use the metal line width, metal line thickness, metal material resistivity, and source process sheet resistance of the reference sample in the trained sheet resistance prediction model to achieve optimized sheet resistance prediction in the process.

[0134] For example, a reference sample can be constructed by averaging the parameters of multiple samples in the training set. For instance, the metal linewidth of the reference sample can be obtained by averaging the metal linewidth of multiple samples in the training set; the metal line thickness of the reference sample can be obtained by averaging the metal material resistivity of multiple samples in the training set; and the source process sheet resistance of the reference sample can be obtained by averaging the source process sheet resistance of multiple samples in the training set. Thus, a reference sample for the source process can be obtained.

[0135] Once the reference sample is obtained, the metal linewidth of the reference sample can be considered as... The metal linewidth of the target transistor is considered as Substitute into formula (1) to calculate the relative difference between the metal linewidths of the target transistor and the reference sample; consider the metal line thickness of the reference sample as... The thickness of the metal line of the target transistor is considered as Substitute into formula (2) to calculate the relative difference between the metal line thickness of the target transistor and the reference sample; consider the resistivity of the metal material of the reference sample as... The resistivity of the metal material of the target transistor is considered as Substitute these values ​​into Equation (2) to calculate the relative difference in resistivity of the metal material between the target transistor and the reference sample. This allows for the calculation of multiple relative differences between several key parameters of the target transistor and the reference sample.

[0136] In step 503, the relative differences between multiple key parameters of the target transistor and the reference sample, and the reference sample of the source process of the k-th transistor are input into the sheet resistance prediction model to obtain the sheet resistance of the target transistor in the optimized process.

[0137] Among them, the sheet resistance prediction model is constructed based on the physical relationship between sheet resistance and several key parameters.

[0138] In this embodiment, the sheet resistance prediction model is a pre-trained sheet resistance prediction model, so the parameters of the neural network sub-model are fixed. At this point, following the method in step 103, the relative differences between multiple key parameters of the target transistor and the reference sample, and the sheet resistance of the reference sample for the k-th transistor source process are input into the sheet resistance prediction model to obtain the sheet resistance of the target transistor in the optimized process. The training method of the sheet resistance prediction model is described in steps 101 to 104 above, and details are omitted here.

[0139] For example, if we need to obtain the sheet resistance d1 of a target transistor (actually produced in an optimized process), where the target transistor belongs to the k-th type of transistor, let the metal linewidth of the target transistor in the optimized process be a1, the metal line thickness be b1, and the resistivity of the metal material be c1. Let the metal linewidth of the reference sample of the k-th type of transistor in the source process be a2, the metal line thickness be b2, and the resistivity of the metal material be c2. The sheet resistance in the source process is d2. Then, we consider the metal linewidth a1 of the target transistor as... The thickness of the metal wire b1 is considered as The resistivity c1 of metallic materials is considered as ; and the metal linewidth a2 of the reference sample is considered as The thickness of the metal wire b2 is considered as The resistivity c2 of metallic materials is considered as The sheet resistance in the source process is considered as d2. Then, the sheet resistance d1 of the target transistor is predicted using the methods described in steps 101 to 104 above.

[0140] In this embodiment, since the optimized process is derived from the source process, there is a certain nonlinear correlation between the sheet resistance of the same transistor in the optimized process and that in the source process. Key parameters (metal linewidth, metal line thickness, and metal resistivity) are crucial influencing the sheet resistance. Therefore, based on the relative differences in these key parameters between the source and optimized processes, the nonlinear correlation between the sheet resistance of the optimized and source processes can be fitted, thus creating a sheet resistance prediction model. This sheet resistance prediction model enables accurate and efficient sheet resistance prediction, thereby improving process controllability, shortening the development cycle, and reducing costs.

[0141] The following are device embodiments of this application. For details not described in detail in the device embodiments, please refer to the above method embodiments.

[0142] Figure 6 A schematic diagram of a sheet resistance prediction model training device provided in an exemplary embodiment of the present invention is shown. See also Figure 6 The sheet resistance prediction model training device 600 includes: a first acquisition module 601, a relative difference determination module 602, a second acquisition module 603, and a training module 604.

[0143] The first acquisition module 601 is used to acquire a training set, which includes multiple samples. Each sample includes the sheet resistance of the k-th transistor in the source process, multiple key parameters associated with the sheet resistance, and the sheet resistance of the k-th transistor in the optimized process. The multiple key parameters include the metal line width, the metal line thickness, and the resistivity of the metal material.

[0144] The relative difference determination module 602 is used to determine multiple relative differences between the optimized process and multiple key parameters of each sample in the training set according to the design rules of the optimized process. The optimized process is obtained by optimizing the source process.

[0145] The second acquisition module 603 is used to acquire the sheet resistance prediction model, which is constructed based on the physical relationship between the sheet resistance and multiple key parameters.

[0146] The training module 604 is used to train the sheet resistance prediction model using multiple samples in the training set and multiple relative differences of each sample. During the training of the sheet resistance prediction model, the backpropagation gradient method is used to optimize the parameters of the sheet resistance prediction model.

[0147] Optionally, in the second acquisition module 603, in the physical relationship between sheet resistance and multiple key parameters, sheet resistance is inversely proportional to the metal wire width and metal wire thickness, and sheet resistance is directly proportional to the resistivity of the metal material.

[0148] The sheet resistance prediction model is expressed by the following formula:

[0149]

[0150] in, Let be the sheet resistance of the i-th sample of the k-th transistor in the source process. The sheet resistance of the i-th sample of the k-th transistor predicted by the sheet resistance prediction model in the optimized process. , , The physical relationship coefficients in the sheet resistance prediction model are obtained using a neural network sub-model. The neural network sub-model is a sub-model within the sheet resistance prediction model; its input consists of multiple relative differences, and its output is the physical relationship coefficient. Let represent the relative difference in metal linewidth between the i-th sample of the k-th transistor in the optimized process and the original process. Let represent the relative difference in metal line thickness between the i-th sample of the k-th transistor and the source process. Let be the relative difference in resistivity of the metal material between the i-th sample of the k-th transistor in the optimized process and the original process.

[0151] Optionally, in the relative difference determination module 602, the relative difference between the metal linewidth of the i-th sample of the k-th transistor in the optimized process and the source process is calculated using the following formula:

[0152]

[0153] in, The linewidth of the metal line indicated in the design rules of the optimized process for the k-th transistor. The linewidth of the metal line in the source process for the i-th sample of the k-th transistor;

[0154] The relative difference between the metal line thickness of the i-th sample of the k-th transistor in the optimized process and the source process is calculated using the following formula:

[0155]

[0156] in, The metal line thickness of the k-th transistor is indicated in the design rules of the optimized process. The metal line thickness of the i-th sample of the k-th transistor in the source process;

[0157] The relative difference between the resistivity of the metal material in the optimized process and the source process for the i-th sample of the k-th transistor is calculated using the following formula:

[0158]

[0159] in, Let the resistivity of the metal material be the value indicated by the design rules of the optimized process for the k-th transistor. The resistivity of the metal material in the source process is the i-th sample of the k-th transistor.

[0160] Optionally, in training module 604, during the training of the sheet resistance prediction model, the loss function is expressed by the following formula:

[0161]

[0162] in, Let be the loss function, representing the physical relationship coefficients predicted by the neural network sub-model in the sheet resistance prediction model. , , The loss, This represents the sheet resistance predicted by the sheet resistance prediction model on the i-th sample corresponding to the k-th transistor in the optimized process. Let be the label of the i-th sample corresponding to the k-th transistor. The i-th sample corresponding to the k-th transistor is a sample in the training set, where i is a positive integer ranging from 1 to 1. , This represents the total number of samples corresponding to the k-th type of transistor in the training set.

[0163] Figure 7 A schematic diagram of the sheet resistance prediction device provided in an exemplary embodiment of the present invention is shown. See also Figure 7 The sheet resistance prediction device 700 includes: a first acquisition module 701, a second acquisition module 702, and a sheet resistance prediction module 703.

[0164] The first acquisition module 701 is used to acquire multiple key parameters of the target transistor, which is a transistor actually produced in the optimized process. The target transistor belongs to the k-th type of transistor. The multiple key parameters include the metal line width, metal line thickness and metal material resistivity.

[0165] The second acquisition module 702 is used to acquire a reference sample of the source process of the k-th transistor, and calculate multiple relative differences of multiple key parameters between the target transistor and the reference sample.

[0166] The sheet resistance prediction module 703 is used to input multiple relative differences of multiple key parameters between the target transistor and the reference sample, and the reference sample of the source process of the k-th transistor into the sheet resistance prediction model to obtain the sheet resistance of the target transistor in the optimized process.

[0167] The sheet resistance prediction model is obtained using the sheet resistance prediction model training method described in steps 101 to 104.

[0168] It should be noted that the sheet resistance prediction device provided in the above embodiments, when performing sheet resistance prediction, or the sheet resistance prediction model training device provided in the above embodiments, when performing sheet resistance prediction model training, is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the sheet resistance prediction device and the sheet resistance prediction method embodiments provided in the above embodiments belong to the same concept, and the sheet resistance prediction model training device and the sheet resistance prediction model training method embodiments provided in the above embodiments belong to the same concept. The specific implementation process is detailed in the method embodiments and will not be repeated here.

[0169] The module division in this embodiment of the invention is illustrative and represents only one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in each embodiment of the invention can be integrated into a single processor, exist as separate physical entities, or consist of two or more modules integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0170] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a terminal device (which may be a personal computer, mobile phone, or communication device, etc.) or processor to execute all or part of the steps of the method of the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0171] Figure 8This is a schematic diagram of the structure of a computer device provided in an exemplary embodiment of the present invention. For example... Figure 8 As shown, the computer device 800 includes a processor 801 and a memory 802.

[0172] Processor 801 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 801 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 801 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 801 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 801 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0173] The memory 802 may include one or more computer-readable storage media, which may be non-transitory. The memory 802 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 802 is used to store at least one instruction, which is executed by the processor 801 to implement the sheet resistance prediction method and the sheet resistance prediction model training method provided in the embodiments of the present invention.

[0174] Those skilled in the art will understand that Figure 8 The structure shown does not constitute a limitation on the computer device 800, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0175] This invention also provides a non-transitory computer-readable storage medium, which, when the instructions in the storage medium are executed by the processor of a computer device, enables the computer device to execute the sheet resistance prediction method and the sheet resistance prediction model training method provided in this invention.

[0176] This invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the sheet resistance prediction method and the sheet resistance prediction model training method provided in this invention.

[0177] The above description is merely an optional embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for training a sheet resistance prediction model, characterized in that, The training method for the sheet resistance prediction model includes: Obtain a training set, which includes multiple samples. Each sample includes the sheet resistance of the k-th transistor in the source process, multiple key parameters associated with the sheet resistance, and the sheet resistance of the k-th transistor in the optimized process. The multiple key parameters include the metal line width, metal line thickness, and metal material resistivity. Based on the design rules of the optimized process, the relative differences of multiple key parameters between the optimized process and each sample in the training set are determined. The optimized process is obtained by optimizing the source process. Obtain a sheet resistance prediction model, which is constructed based on the physical relationship between sheet resistance and multiple key parameters; The sheet resistance prediction model is trained using multiple samples from the training set and multiple relative differences for each sample. During the training process, the parameters of the sheet resistance prediction model are optimized using the backpropagation gradient method.

2. The method for training a sheet resistance prediction model according to claim 1, characterized in that, In the physical relationship between the sheet resistance and several key parameters, the sheet resistance is inversely proportional to the metal wire width and metal wire thickness, and directly proportional to the resistivity of the metal material. The sheet resistance prediction model includes a neural network sub-model and a physical formula layer connected in sequence. The neural network sub-model includes an input layer, a first hidden layer, a second hidden layer, and an output layer connected in sequence. The physical formula layer of the sheet resistance prediction model is expressed by the following formula: in, Let be the sheet resistance of the i-th sample of the k-th transistor in the source process. The sheet resistance of the i-th sample of the k-th transistor predicted by the sheet resistance prediction model in the optimized process. , , The physical relationship coefficients in the sheet resistance prediction model are predicted using the neural network sub-model. The input of the neural network sub-model is the plurality of relative differences, and the output of the neural network sub-model is the physical relationship coefficient. The relative difference in metal linewidth between the i-th sample of the k-th transistor in the optimized process and the source process. The relative difference in metal line thickness between the i-th sample of the k-th transistor in the optimized process and the source process. The relative difference in resistivity of the metal material between the i-th sample of the k-th transistor in the optimized process and the source process.

3. The method for training a sheet resistance prediction model according to claim 2, characterized in that, The relative difference between the metal linewidth of the i-th sample of the k-th transistor in the optimized process and the source process is calculated using the following formula: in, The linewidth of the metal line indicated in the design rules of the optimized process for the k-th transistor. The linewidth of the metal line in the source process for the i-th sample of the k-th transistor; The relative difference between the metal line thickness of the i-th sample of the k-th transistor in the optimized process and the source process is calculated using the following formula: in, The metal line thickness of the k-th transistor is indicated in the design rules of the optimized process. The metal line thickness of the i-th sample of the k-th transistor in the source process; The relative difference between the resistivity of the metal material in the optimized process and the source process for the i-th sample of the k-th transistor is calculated using the following formula: in, Let the resistivity of the metal material be the value indicated by the design rules of the optimized process for the k-th transistor. The resistivity of the metal material in the source process is the i-th sample of the k-th transistor.

4. The method for training a sheet resistance prediction model according to any one of claims 1 to 3, characterized in that, During the training of the sheet resistance prediction model, the loss function is expressed by the following formula: in, Let be the loss function, representing the physical relationship coefficients predicted by the neural network sub-model in the sheet resistance prediction model. , , The loss, The sheet resistance prediction model is the predicted sheet resistance in the optimized process for the i-th sample corresponding to the k-th transistor. Let i be the label of the i-th sample corresponding to the k-th type of transistor, where i is a sample in the training set, and i is a positive integer ranging from 1 to 1. , The total number of samples corresponding to the k-th type of transistor in the training set.

5. A method for predicting sheet resistance, characterized in that, The sheet resistance prediction method includes: The target transistor is a transistor actually produced in the optimized process. The target transistor belongs to the k-th type of transistor. The multiple key parameters include metal line width, metal line thickness and metal material resistivity. Obtain a reference sample of the source process of the k-th transistor, and calculate multiple relative differences of multiple key parameters between the target transistor and the reference sample; The relative differences of several key parameters between the target transistor and the reference sample, and the reference sample of the source process of the k-th transistor are input into the sheet resistance prediction model to obtain the sheet resistance of the target transistor in the optimized process. The sheet resistance prediction model is obtained using the sheet resistance prediction model training method described in any one of claims 1 to 4.

6. A sheet resistance prediction model training device, characterized in that, The sheet resistance prediction model training device includes: The first acquisition module is used to acquire a training set, which includes multiple samples. Each sample includes the sheet resistance of the k-th transistor in the source process, multiple key parameters associated with the sheet resistance, and the sheet resistance of the k-th transistor in the optimized process. The multiple key parameters include the metal line width, metal line thickness, and metal material resistivity. The relative difference determination module is used to determine multiple relative differences between the optimized process and multiple key parameters of each sample in the training set according to the design rules of the optimized process, wherein the optimized process is obtained by optimization based on the source process; The second acquisition module is used to acquire the sheet resistance prediction model, which is constructed based on the physical relationship between the sheet resistance and multiple key parameters. The training module is used to train the sheet resistance prediction model using multiple samples in the training set and multiple relative differences of each sample. During the training of the sheet resistance prediction model, the parameters of the sheet resistance prediction model are optimized using the backpropagation gradient method.

7. A sheet resistance prediction device, characterized in that, The sheet resistance prediction device includes: The first acquisition module is used to acquire multiple key parameters of the target transistor, which is a transistor actually produced in the optimized process. The target transistor belongs to the k-th type of transistor. The multiple key parameters include metal line width, metal line thickness and metal material resistivity. The second acquisition module is used to acquire a reference sample of the source process of the k-th transistor and calculate multiple relative differences of multiple key parameters between the target transistor and the reference sample. The sheet resistance prediction module is used to input multiple relative differences of multiple key parameters between the target transistor and the reference sample, and the reference sample of the source process of the k-th transistor into the sheet resistance prediction model to obtain the sheet resistance of the target transistor in the optimized process. The sheet resistance prediction model is obtained using the sheet resistance prediction model training method described in any one of claims 1 to 4.

8. A computer device, characterized in that, The computer device includes a memory and a processor, wherein the memory stores at least one computer program, which is loaded and executed by the processor to implement the sheet resistance prediction model training method according to any one of claims 1 to 4 or the sheet resistance prediction method according to claim 5.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one computer program, which is loaded and executed by a processor to implement the sheet resistance prediction model training method of any one of claims 1 to 4 or the sheet resistance prediction method of claim 5.

10. A computer program product comprising a computer program / instructions, characterized in that, When the computer program / instruction is executed by the processor, it implements the sheet resistance prediction model training method of any one of claims 1 to 4 or the sheet resistance prediction method of claim 5.

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