Memory and read circuit therein

Abstract

The present disclosure relates to a read circuit for a memory, comprising: a sensing module comprising a first capacitor, a second capacitor, and a discharge switch wherein an upper pole plate of the first capacitor is coupled to a first end of the discharge switch, an upper pole plate of the second capacitor is coupled to a second end of the discharge switch, the sensing module is configured to couple an upper polar plate of the first capacitor to a memory cell to be read in a sensing process; the discharge switch is configured to be not conducted under the condition that the to-be-read storage unit is in a first state and to be conducted under the condition that the to-be-read storage unit is in a second state in the sensing process; the sensitive amplification module is configured to read data corresponding to the state of the storage unit to be read according to the voltage of the upper electrode plate of the second capacitor after the sensing process; wherein the capacitance value of the second capacitor is smaller than that of the first capacitor. Therefore, the reading precision can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of storage, and more particularly to a memory and a read circuit therein. Background Technology

[0002] Currently, with the continuous development of consumption levels, higher and higher requirements are being placed on electronic devices, and memory technology is also developing rapidly, especially NAND flash memory, which has many advantages over traditional memory, such as faster performance and lower power consumption, but there is still a desire to further improve its read accuracy. Summary of the Invention

[0003] One technical problem this disclosure aims to solve is to provide an improved read circuit for a memory that can improve read accuracy.

[0004] According to a first aspect of this disclosure, a read circuit for a memory is provided, comprising: a sensing module including a first capacitor, a second capacitor, and a discharge switch, wherein the upper plate of the first capacitor is coupled to a first terminal of the discharge switch, the upper plate of the second capacitor is coupled to a second terminal of the discharge switch, the sensing module being configured to couple the upper plate of the first capacitor to a memory cell to be read during sensing, and the discharge switch being configured to be non-conductive when the memory cell to be read is in a first state and conductive when the memory cell to be read is in a second state during sensing; and a sensitive amplification module configured to read data corresponding to the state of the memory cell to be read based on the voltage of the upper plate of the second capacitor after the sensing process; wherein the capacitance value of the second capacitor is less than the capacitance value of the first capacitor.

[0005] Optionally, the first capacitor is configured to discharge the voltage of its upper plate from a first pre-charge voltage to a first level when the memory cell to be read is in the first state during the sensing process, and to discharge the voltage of its upper plate from the first pre-charge voltage to a second level lower than the first level when the memory cell to be read is in the second state; and the discharge switch is configured to not conduct when the voltage of the upper plate of the first capacitor is discharged to the first level, and to conduct when the voltage of the upper plate of the first capacitor is discharged to the second level.

[0006] Optionally, the sensing module is further configured to adjust the voltage of the upper plate of the second capacitor during the sensing process, such that the voltage of the upper plate of the second capacitor is raised by a first value at the beginning of the sensing process and lowered by a second value at the end of the sensing process.

[0007] Optionally, adjusting the voltage of the upper plate of the second capacitor during the sensing process includes: applying a first signal to the lower plate of the second capacitor, the first signal changing from a third level to a fourth level at the start of the sensing process and changing from the fourth level to a fifth level at the end of the sensing process, wherein the fourth level is higher than the third level and the fifth level is lower than the fourth level.

[0008] Optionally, the sensing module further includes a first switch, wherein a first end of the first switch is coupled to a bit line coupled to the memory cell to be read, a second end is coupled to the upper plate of the first capacitor, a control terminal receives a first control signal, and a control terminal of the discharge switch receives a second control signal. The first control signal has a sixth level during the sensing process to enable the first switch to conduct, and the second control signal has a seventh level during the sensing process to enable the discharge switch to not conduct when the memory cell to be read is in the first state, and to conduct when the memory cell to be read is in the second state.

[0009] Optionally, the first switch is an NMOS transistor.

[0010] Optionally, the discharge switch is an NMOS transistor.

[0011] Optionally, the sensitive amplification module includes a detection unit and a data latch, wherein after the sensing process, the detection unit receives the voltage of the upper plate of the second capacitor, is coupled to the control terminal of the data latch, and causes the signal level at the control terminal to flip when the state of the memory cell to be read is detected to be the first state based on the voltage of the upper plate of the second capacitor. The data latch is configured to output a data signal with an eighth level at its output terminal, and flips the level of the data signal to a ninth level when the signal level at the control terminal flips.

[0012] Optionally, the detection unit includes a first NMOS transistor, wherein a first terminal of the first NMOS transistor is coupled to the control terminal of the data latch, a second terminal is coupled to a negative power supply voltage or ground, and the gate is coupled to the upper plate of the second capacitor.

[0013] Optionally, the sum of the threshold voltage of the first NMOS transistor and the voltage at the second terminal of the first NMOS transistor is located between a first voltage value and a second voltage value, wherein the first voltage value is the amplitude of the voltage at the upper plate of the second capacitor after the sensing process when the memory cell to be read is in the first state, the second voltage value is the amplitude of the voltage at the upper plate of the second capacitor after the sensing process when the memory cell to be read is in the second state, and the first voltage value is greater than the second voltage value.

[0014] Optionally, the sensitive amplification module further includes a mismatch sampling unit, and a mismatch sampling process is included before the sensing process. At the beginning of the mismatch sampling process, the upper plate of the second capacitor has been charged to a second pre-charge voltage and the first NMOS transistor is turned on. During the mismatch sampling process, the mismatch sampling unit discharges the upper plate of the second capacitor until the first NMOS transistor becomes non-conductive. The mismatch sampling process is part of the pre-charge process before the sensing process, or between the pre-charge process and the sensing process.

[0015] Optionally, the mismatch sampling unit includes a second NMOS transistor, wherein a first terminal of the second NMOS transistor is coupled to a first terminal of the first NMOS transistor, a second terminal is coupled to the gate of the first NMOS transistor, and the gate receives a third control signal, the third control signal having a tenth level during the mismatch sampling process to enable the second NMOS transistor to be turned on.

[0016] Optionally, the data latch includes a first inverter, a second inverter, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The input terminal of the first inverter is coupled to the output terminal of the second inverter, and the output terminal of the first inverter is coupled to the input terminal of the second inverter. One of the input and output terminals of the first inverter serves as the output terminal of the data latch. The first terminal of the third NMOS transistor is coupled to the input terminal of the first inverter, and the second terminal is coupled to the first terminal of the fifth NMOS transistor. Its gate receives a reset signal. The first terminal of the fourth NMOS transistor is coupled to the output terminal of the first inverter, and the second terminal is coupled to the first terminal of the fifth NMOS transistor and serves as the control terminal of the data latch, coupled to the detection unit. Its gate receives a set signal. The second terminal of the fifth NMOS transistor is coupled to a negative power supply voltage or ground, and its gate receives a fourth control signal.

[0017] Optionally, the data latch includes a first inverter, a second inverter, a third NMOS transistor, and a fourth NMOS transistor. The input terminal of the first inverter is coupled to the output terminal of the second inverter, and the output terminal of the first inverter is coupled to the input terminal of the second inverter. One of the input and output terminals of the first inverter serves as the output terminal of the data latch. The first terminal of the third NMOS transistor is coupled to the output terminal of the first inverter, and the second terminal is coupled to a negative power supply voltage or ground. Its gate receives a reset signal. The first terminal of the fourth NMOS transistor is coupled to the input terminal of the first inverter, and the second terminal serves as the control terminal of the data latch, coupled to the detection unit. Its gate receives a set signal.

[0018] Optionally, the capacitance value of the second capacitor is equal to or less than one-tenth of the capacitance value of the first capacitor.

[0019] Optionally, the first state is a programming state, and the second state is an erasure state.

[0020] According to a second aspect of this disclosure, a memory is provided that includes a read circuitry according to any of the schemes described in the first aspect of this disclosure.

[0021] Therefore, some embodiments of this disclosure employ a large sensing capacitor, a small sensing capacitor, and a discharge switch coupled between the two capacitors, thereby enabling a two-step capacitance sensing scheme and thus expanding the read flip window to improve read accuracy. Attached Figure Description

[0022] The above and other objects, features and advantages of this disclosure will become more apparent from the more detailed description of exemplary embodiments thereof taken in conjunction with the accompanying drawings, wherein like reference numerals generally denote like parts.

[0023] Figure 1 An exemplary structure of a flash memory cell according to some embodiments of the present disclosure is shown.

[0024] Figure 2 A read scheme for NAND flash memory according to some embodiments of the present disclosure is illustrated.

[0025] Figures 3A to 3D Some exemplary structures of the read circuitry for NAND flash memory are shown.

[0026] Figures 4A to 4D The operation of the NAND flash memory read circuit is shown.

[0027] Figure 5 It shows in Figures 4B to 4DThe waveform of the voltage change of the sensing node over time during the reading process is shown, as well as the jitter of the flip point.

[0028] Figure 6A An exemplary schematic diagram of a read circuit for a memory according to some embodiments of the present disclosure is shown. Figure 6B An exemplary schematic diagram of the sensitive amplification module in the readout circuit is shown.

[0029] Figures 7 to 9 Exemplary circuit diagrams for a memory read circuit according to some embodiments of the present disclosure are shown.

[0030] Figure 10 It shows in Figure 9 The waveforms of voltage changes over time at three different nodes during the reading process of the reading circuit. Detailed Implementation

[0031] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0032] It should be understood that terms such as "first," "second," etc., used herein are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or similar may explicitly or implicitly include one or more of the stated features. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0033] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, terms such as "installation," "connection," "linking," and "coupling" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0034] Furthermore, it should be understood that techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where applicable, such techniques, methods, and apparatus should be considered part of this specification.

[0035] Furthermore, it should be understood that in the various figures of this disclosure, if there are the same reference numerals, they indicate devices or units with the same function, but their device parameters or unit structure / parameters, etc., can be changed according to the actual circuit requirements; and in some cases, different reference numerals can be used in different figures to indicate devices or units with the same function, and their device parameters or unit structure / parameters, etc., can be the same or different from each other as needed.

[0036] Figure 1 An exemplary structure of a flash memory cell is shown, which can be used to construct various types of flash memory, such as NAND or NOR flash memory. It should be understood that... Figure 1 The descriptions are merely illustrative examples for the purpose of facilitating understanding of the solutions disclosed herein and are not intended to limit the scope of this disclosure.

[0037] like Figure 1 As shown, this flash memory cell includes a control gate (CG), an insulating dielectric layer, a floating gate (FG), a tunnel oxide (TOX) layer, a source, a drain, and a substrate. The control gate and the floating gate are typically made of polysilicon. The dielectric layer located between the control gate and the floating gate is called the insulating dielectric layer, which is usually composed of a three-layer structure of silicon oxide / silicon nitride / silicon oxide (ONO) and is used to block the flow of electrons from the floating gate to the control gate.

[0038] The tunneling oxide layer is typically made of silicon dioxide. When the voltage difference between the control gate and the substrate is high, the tunneling oxide layer allows electrons to flow from the substrate to the floating gate through the hot electron injection effect, or to draw electrons out of the floating gate through Fowler-Nordheim (FN) tunneling. When not in operation, the tunneling oxide layer exhibits an insulating state.

[0039] The state of a flash memory cell (also known as a floating-gate transistor) can be changed using programming or erasing operations. During programming, electrons are injected from the substrate through a tunneling oxide layer into the floating gate for storage. During erasing, the electrons in the floating gate return to the substrate through the tunneling oxide layer. The threshold voltage of the flash memory cell is controlled by the number of electrons in the floating gate. The electrons in the floating gate are electrically isolated in the absence of an external voltage, making the flash memory cell non-volatile. The number of electrons stored in the floating gate affects the threshold voltage of the floating-gate transistor; therefore, to read the stored state of the flash memory cell, the desired result can be obtained by applying a voltage to the gate of the floating-gate transistor to detect its conduction state.

[0040] Based on the different electronic storage states in the floating gate, the states of flash memory cells can be divided into programming state and erase state: Applying a voltage to the control gate of the flash memory cell causes electrons to tunnel from the channel into the floating gate, increasing the threshold voltage of the flash memory cell and making the turn-on voltage required for the transistor to conduct higher. Flash memory cells in this state can be called programming cells (offcell) or 0 cells (i.e., cells storing data "0"). This state is called programming state. Applying a voltage to the control gate causes electrons in the floating gate layer to tunnel out of the floating gate layer, decreasing the threshold voltage of the flash memory cell and making the turn-on voltage lower. Flash memory cells in this state can be called erase cells (oncell) or 1 cells (i.e., cells storing data "1"). This state is called erase state.

[0041] The following is combined Figure 2 The simplified diagram uses NAND flash memory as an example to discuss memory read schemes.

[0042] like Figure 2 As shown, the NAND flash memory's sense amplifier (SA) is positioned along the BL direction of the array, where BL connects to a series of memory cells (also known as a string). During a read operation, the selected cell (sel cell, indicated by the "?" in the diagram, also referred to as the cell to be read below) in the string is given a read voltage Vread, while the unselected cells are given a pass voltage Vpass. Applying a voltage difference along the BL to CSL (Common Source Line) direction generates a current. By sensing the magnitude of this current through the SA, the state of the memory cell can be determined. This read method has become an exemplary read scheme for NAND flash memory.

[0043] Figures 3A to 3D Exemplary structures of NAND flash memory read circuits and some variations thereof are shown. Figures 4A to 4D by Figure 3A The working process of the reading circuit is illustrated by taking the reading circuit structure as an example.

[0044] like Figure 3A As shown, the read circuit may include a bit line selection transistor BL_Sel for selecting the currently read bit line (BL), one end of which is coupled to BL, and the other end of which is coupled to one end of a charging transistor BL_C for pre-charging the BL. The other end of the charging transistor BL_C is coupled to the positive power supply voltage VDD. Although not shown in the figure, it should be understood that the BL can be as follows: Figure 2 The ground is coupled to the storage unit to be read.

[0045] The readout circuit may also include a charging transistor Sen_C for pre-charging the sensing node Sen_Node, one end of which is coupled to the sensing node Sen_Node and the other end of which is coupled to the positive power supply voltage VDD. One end of the sensing control transistor Sen and the upper plate of the sensing capacitor C_Sen are also coupled at the sensing node Sen_Node. The other end of the sensing control transistor Sen is coupled to the other end of the bit line selection transistor BL_Sel.

[0046] The read circuit may also include a circuit section for reading and latching data corresponding to the state of the memory cell coupled to BL based on the voltage at the sensing node Sen_Node. Figure 3A The circuit located to the right of the sensing node Sen_Node includes transistors Sen_Tr, RST, SET, and T1, and two inverters Inv1 and Inv2. The input of inverter Inv1 is coupled to the output of inverter Inv2, and the output is coupled to the input of inverter Inv2, so both can be used to latch data. Transistors Sen_Tr, RST, SET, and T1 can be used to control the latched data, i.e., determine whether the data latched at both ends of the inverter is 0 or 1. For example, one end of transistor Sen_Tr is coupled to one end of transistors RST, SET, and T1, and the other end is coupled to a negative power supply voltage or ground (represented by VSS in the figure, which can be selected as a negative power supply voltage or ground as needed; VSS will be used directly to represent the negative power supply voltage or ground in the following text). The control terminal (i.e., the gate) of this transistor is coupled to the sensing node Sen_Node. The other end of transistor RST is coupled to the input of inverter Inv1, the other end of transistor SET is coupled to the output of inverter Inv1, and the other end of transistor T1 is coupled to VSS. The control terminals of transistors RST, SET, and T1 can receive appropriate control signals for data latching. Inverters Inv1 and Inv2, as well as transistors RST, SET, and T1, can be collectively referred to as a data latch, while transistor Sen_Tr can be referred to as the grounding transistor used for this data latch.

[0047] Figure 3A The diagram shows that after a reset, the data latched at the left and right ends of the inverter are 0 and 1, respectively. As will be explained in detail later, during subsequent readings, the data latched at the left and right ends of the inverter may be changed to 1 and 0 depending on the state of the memory cell to be read.

[0048] This can be achieved by appropriately applying the above. Figure 3A The gate voltage of each transistor is used to control the on-state of each transistor, so as to achieve the following, combined with Figures 4A to 4DThe corresponding operations required for reading are detailed below. Furthermore, the terms "one end," "other end," "first end," or "second end," etc., used to describe each transistor herein refer to either the source or drain terminal, but are not limited to either. Those skilled in the art will understand that the source and drain terminals of a transistor are typically structurally indistinguishable and are determined by the voltage applied across them during operation.

[0049] In addition, such as Figure 3A As shown, the bit line selection transistor BL_Sel, the charging transistor BL_C, the sensing control transistor Sen, the transistor Sen_Tr, RST, SET, and T1 are all NMOS transistors, while the charging transistor Sen_C is a PMOS transistor. However, it should be understood that the readout circuit is not limited to this; the type of one or more transistors can be changed as needed (e.g., from NMOS to PMOS or vice versa), and their connection method and / or gate voltage setting can be adaptively changed.

[0050] Additionally, the following will be combined. Figures 4A to 4D With the detailed reading working principle being basically the same, it is possible to... Figure 3A Various suitable modifications can be made to the circuit structure, for example Figures 3B to 3D shown.

[0051] Compared to Figure 3A ,exist Figure 3B In the circuit structure, the control transistors and their connections in the data latch have changed. For example, such as... Figure 3B As shown, the following has been removed. Figure 3A Transistor T1 is used in the inverter, and one end of transistor Sen_Tr is coupled only to one end of transistor SET, while the other end of transistor SET is coupled to the input of inverter Inv1. One end of transistor RST is coupled to the output of inverter Inv1, and the other end is coupled to VSS. The control terminals of transistors RST and SET can receive appropriate control signals for data latching. Inverters Inv1 and Inv2, as well as transistors RST and SET, can be collectively referred to as a data latch. Figure 3B As shown in the figure, after the reset, the data latched at the left and right ends of the inverter are 1 and 0 respectively, which may change according to the state of the memory cell to be read during subsequent reading. Figure 3B The control principle of the data latch in Figure 3A Basically the same.

[0052] Compared to Figure 3A ,exist Figure 3C In the circuit structure, in addition to the above-mentioned Figure 3B In addition to the data latch structure shown, the circuit structure of the pre-charge section has also been changed. For example, as... Figure 3C As shown, the following has been removed. Figure 3A The charging transistor BL_C is used only to charge both BL and the sensing node Sen_Node. For example, turning on transistors Sen_C, Sen, and BL_Sel simultaneously can precharge both BL and the sensing node Sen_Node at the same time.

[0053] and Figure 3C Similarly, in Figure 3D In the circuit structure, it can be changed to remove Figure 3A The charging transistor Sen_C is used instead of BL_C. Only the charging transistor BL_C is used to charge both BL and the sensing node Sen_Node. For example, turning on transistors BL_C, Sen, and BL_Sel simultaneously can precharge both BL and the sensing node Sen_Node at the same time.

[0054] The following is combined Figures 4A to 4D by Figure 3A The reading process will be described in detail using the circuit as an example.

[0055] In such Figure 4A In the first stage of the reading process shown, the BL precharge process and the data latch data reset process are performed.

[0056] For example, such as Figure 4A As shown by the red arrow on the left, the charging transistor BL_C and the bit line selection transistor BL_Sel are turned on (for example, by applying a high voltage to the gates of both transistors), thus forming a current path from the power supply voltage VDD to BL, raising the voltage of BL, i.e., pre-charging BL. In subsequent operations, BL_Sel can remain on to ensure the voltage of BL is stable. By controlling the gate voltage of BL_Sel, the voltage of BL can be clamped to a stable value. However, if the voltage of BL is unstable during subsequent reading, it will cause the coupling capacitors between different BLs to charge and discharge, which will affect the reading accuracy. The selected memory cell (also called the memory cell to be read) in the memory cell string connected to BL has two possible conduction states: the memory cell to be read that is currently in the erase state (also called "oncell") will be turned on, so that there is DC current on BL, and the BL voltage is clamped at a stable low value (this low clamping voltage value is lower than the gate voltage value that turns on the transistor Sen_Tr); while the memory cell to be read that is currently in the programming state (also called "off cell") will not be turned on, so that the charging on BL is completed and the charging stops. At this time, the BL voltage is high, at least higher than the gate voltage value that turns on the transistor Sen_Tr.

[0057] In addition, such as Figure 4AAs shown by the blue arrow on the right, transistors RST and T1 are turned on, thus forming a path from the input of inverter Inv1 to VSS, pulling it to the level corresponding to data 0. This can also be considered as resetting the data latched in the data latch to 0. Correspondingly, the data at the output of inverter Inv1 is 1.

[0058] While the data reset process for the data latch is exemplarily given here in the first stage, it should be understood that this data reset process can also be performed in subsequent stages, as long as... Figure 4D Complete the steps shown in the diagram.

[0059] Next, in such Figure 4B In the second stage of the reading process shown, the charging transistor Sen_C is turned on (for example, a low voltage is applied to its gate), thereby forming a current path from the power supply voltage VDD to the sensing node Sen_Node as shown by the red arrow in the figure. The sensing capacitor C_Sen, that is, the sensing node Sen_Node, is pre-charged, and the voltage of the sensing node Sen_Node is raised to VDD in preparation for subsequent sensing processing.

[0060] It should be understood that Figure 4B The operation can also be with Figure 4A The operations can be performed simultaneously or before it. For example, when transistor Sen is off, it can be... Figure 4A The charging of BL in the middle Figure 4B The charging of the Sen_Nodes in the system can be carried out simultaneously without interference.

[0061] Next, in such Figure 4C In the third stage of the read process shown, the charging transistor Sen_C is turned off, and the sensing control transistor Sen is turned on, thus forming a path from the sensing node Sen_Node to BL as shown by the blue arrow in the figure. That is, the sensing capacitor C_Sen at the sensing node Sen_Node will discharge. The discharge phenomenon of the sensing capacitor C_Sen will vary depending on the state of the memory cell to be read: if the memory cell to be read is on cell, the sensing capacitor C_Sen will discharge to a lower voltage value clamped by BL, that is, the voltage value at the sensing node Sen_Node is lower than the gate voltage value that turns on the transistor Sen_Tr; if the memory cell to be read is off cell, the discharge phenomenon of the sensing capacitor C_Sen is not very obvious, and the voltage change is small. That is, the voltage at the sensing node Sen_Node may only be slightly lower than VDD, but it must be higher than the gate voltage value that turns on the transistor Sen_Tr.

[0062] Next, in such Figure 4DIn the fourth stage of the read process, transistor SET is turned on. The state of the grounding transistor Sen_Tr used for the data latch depends on the voltage at the sensing node Sen_Node. As shown by the two blue arrows in the figure, when the memory cell to be read is on cell, the voltage at the sensing node Sen_Node cannot turn on transistor Sen_Tr. Therefore, the value "1" at the input of the previously reset inverter Inv2 will not flip, meaning the data value latched in the data latch remains unchanged. When the memory cell to be read is off cell, the voltage at the sensing node Sen_Node turns on transistor Sen_Tr, forming a path from the input of inverter Inv2 to VSS. This pulls the value "1" at the input of the previously reset inverter Inv2 low to "0", causing the data value latched in the data latch to flip. Therefore, the read result of the memory cell to be read is stored in the data latch, and the state of the memory cell to be read can be obtained by subsequently reading the value of the data latch. Although not shown in the diagram, it should be understood that the circuit for reading the data latch can be connected from either end of the data latch (such as the input or output of the inverter Inv1).

[0063] Those skilled in the art can readily understand from the above description. Figure 3A Various variations (such as those mentioned above) Figures 3B to 3D The similar reading process of the circuit is not described in detail here.

[0064] Figure 5 It shows in Figures 4B to 4D The waveform diagram shown illustrates the change of the voltage Vsen of the sensing node Sen_Node over time during the reading process.

[0065] like Figure 5 As shown, initially, due to... Figure 4B In the second stage of the reading process shown, the sensing node Sen_Node is pre-charged, so the voltage Vsen of the sensing node Sen_Node gradually increases over time until it reaches a final stable pre-charge voltage; then, due to... Figure 4C In the third stage of the reading process shown, the sensing node Sen_Node discharges to varying degrees depending on the state of the memory cell being read; therefore, the waveform of its voltage Vsen has… Figure 5 The two different curves shown are: the upper one is the Vsen waveform curve when the storage cell to be read is off cell, and the lower one is the Vsen waveform curve when the storage cell to be read is on cell. The two eventually reach different stable values ​​Vsen_off and Vsen_on.

[0066] As mentioned above Figure 4DAs described above, in the final read stage, Vsen, as the gate voltage of the grounding transistor Sen_Tr in the data latch, determines the on-state of Sen_Tr and thus the final latched value. The gate voltage that enables Sen_Tr to turn on and pulls down the data latch voltage to a certain value, causing the latched value to flip, is called the flip point Vtrigger. Vtrigger must not only enable Sen_Tr to conduct (i.e., >VSS + Vts (the threshold voltage of Sen_Tr)), but is also affected by the driving capability of the transistors in the inverters of the data latch and the pull-down capabilities of transistors SET and RST. To ensure read accuracy, the flip window of the read value is usually designed to be as large as possible, i.e., ... Figure 5 As shown by the black dashed line, the theoretical Vtrigger value is designed to be the middle value between Vsen_off and Vsen_on, i.e., = (Vsen_off + Vsen_on) / 2.

[0067] However, in actual circuits, due to the different positions of each transistor in the layout and various non-ideal effects during manufacturing, transistor mismatch is introduced. Even if the MOSFETs use the same width-to-length ratio in the design, their driving capabilities will differ after manufacturing. Therefore, during the sensing and reading process, the size of Vtrigger will fluctuate due to the transistor mismatch in the data latch (i.e., Vtrigger shake), which makes the flip window for reading the value smaller, affecting the reading accuracy, and sometimes even causing the data latch to read the wrong value. Figure 5 The red and blue dashed lines in the diagram schematically represent the jitter of the flip point Vtrigger caused by mismatch. That is, Vtrigger deviates from the ideal median value (black dashed line) and becomes smaller or larger. It can be seen that the vertical jitter of Vtrigger makes the flip window smaller, which affects the reading accuracy.

[0068] In addition, as mentioned earlier, the voltage value discharged by the Sen_Node is affected by the voltage at the other end of the transistor Sen. The voltage at the other end of the transistor Sen is the voltage value held by BL, not 0. The Sen_Node can only discharge to the voltage at the other end of the transistor Sen, which is the BL potential. Therefore, the voltage Vsen of the discharged Sen_Node may not be able to completely turn off or on the transistor Sen_Tr, which may reduce the sensor's ability to distinguish voltages and affect the reading accuracy.

[0069] In addition, the discharge time of the Sen_Node is affected by the magnitude of the BL current. With the increasing demand for sensing speed, a faster sensing speed is needed to improve the working efficiency of the device.

[0070] Therefore, some embodiments of this disclosure propose a read circuit for a memory that employs a large sensing capacitor, a small sensing capacitor, and a discharge switch coupled between the two capacitors, thereby enabling a two-step capacitance sensing scheme. This expands the read flip window to improve read accuracy. Furthermore, in some cases, the small sensing capacitor can also reduce sensing time and increase sensing speed, i.e., increase read speed.

[0071] In some embodiments, the read circuit according to this disclosure includes a sensing module comprising a first capacitor, a second capacitor, and a discharge switch, wherein the upper plate of the first capacitor is coupled to a first terminal of the discharge switch, the upper plate of the second capacitor is coupled to a second terminal of the discharge switch, and the capacitance value of the second capacitor is less than the capacitance value of the first capacitor. The sensing module is configured to couple the upper plate of the first capacitor to the memory cell to be read during sensing, and the discharge switch is configured to be non-conductive when the memory cell to be read is in a first state but conductive when the memory cell to be read is in a second state during sensing.

[0072] The read circuit also includes a sensitive amplification module, which is configured to read data corresponding to the state of the memory cell to be read based on the voltage of the upper plate of the second capacitor after the sensing process.

[0073] For example, Figure 6A An exemplary schematic diagram of an exemplary implementation of the reading circuit of the above embodiments is provided, and Figure 6B Given Figure 6A An exemplary schematic diagram of the sensitive amplification module in the image is shown. It should be understood that... Figure 6A The memory cell 601 shown is the object to be read by the read circuit, not part of the read circuit, and is shown here only for the sake of completeness of the description.

[0074] like Figure 6A As shown, the readout circuit includes a sensing module 610 and a sensitive amplification module 620. Additionally, in some cases, similar to the combination described above... Figures 3A to 3D The read circuit may further include a precharge module 630 for precharging and a bit line selection transistor BL_Sel.

[0075] For example, the sensing module 610 includes a first capacitor C1, a second capacitor C2, and an NMOS transistor SO acting as a discharge switch. The upper plate Node1 of the first capacitor C1 is coupled to the first terminal of the transistor SO, and the upper plate Node2 of the second capacitor C2 is coupled to the second terminal of the transistor SO. The capacitance of the second capacitor C2 is less than the capacitance of the first capacitor C1. For example, the capacitance of the second capacitor C2 is equal to or less than one-tenth of the capacitance of the first capacitor C1. Hereinafter, the first capacitor C1 may be referred to as the large capacitor, and the second capacitor C2 as the small capacitor. Therefore, when the discharge switch (transistor SO) is turned on, node Node2 is connected to node Node1, and as will be described in detail later, node Node2 discharges to node Node1.

[0076] It should be understood that the capacitance values ​​of the large and small capacitors can be designed separately according to the needs of the read circuit. For example, the capacitance value of the large capacitor can be designed according to the need to sense the voltage on BL, while the capacitance value of the small capacitor can be designed to be below a certain threshold, i.e., a small charge that allows it to discharge to the voltage of Node1 during the conduction period of transistor SO without significantly increasing the voltage of Node1. However, the capacitance value of the small capacitor cannot be too small to avoid crosstalk noise. The appropriate ratio of the capacitance values ​​of the small and large capacitors can be designed according to the characteristics of the actual read circuit and the memory cell to be read (such as the BL read current).

[0077] Additionally, in some cases, the sensing module 610 can use an NMOS transistor S1 as a first switch to couple the upper plate of the first capacitor C1 to the memory cell 601 to be read during the sensing process. For example, the first terminal of transistor S1 is coupled to the bit line BL coupled to the memory cell 601 to be read; although Figure 6A The diagram shows that the first terminal of transistor S1 is directly coupled to one terminal of transistor BL_Sel. However, it should be understood that since transistor BL_Sel is always on during reading to select the bit line BL, the first terminal of transistor S1 can also be considered to be coupled to the bit line BL via transistor BL_Sel. The second terminal of transistor S1 is coupled to the upper plate Node1 of the first capacitor C1. The control terminal of transistor S1 can receive a high-level gate voltage during sensing to turn on transistor S1, thereby coupling the upper plate Node1 of the first capacitor C1 to the memory cell 601 to be read via transistor S1, transistor BL_Sel, and bit line BL, thus enabling the sensing of the state of the memory cell 601 to be read.

[0078] Transistor SO is configured to not conduct during sensing when the memory cell 601 to be read is in a first state, but to conduct when the memory cell 601 to be read is in a second state. For example, the first state and the second state can be the aforementioned programming state (corresponding to off cell) and erase state (corresponding to on cell), respectively.

[0079] For example, transistor SO can be configured so that its conduction is determined by the voltage of the upper plate Node1 of the first capacitor C1. Similar to the sensing capacitor C_Sen described earlier, the upper plate Node1 of the first capacitor C1 discharges to different degrees during sensing depending on the state of the memory cell 601 to be read. Specifically, in the first state (e.g., corresponding to off cell), the voltage of the upper plate Node1 discharges from the first pre-charge voltage to a first level, while in the second state (e.g., corresponding to on cell), the voltage of the upper plate Node1 discharges from the first pre-charge voltage to a second level lower than the first level. The first pre-charge voltage is obtained by the pre-charge module 630 charging the upper plate Node1 during the previous pre-charge phase. The gate voltage, threshold voltage, etc., of transistor SO can be configured so that transistor SO does not conduct when the voltage of the upper plate Node1 of the first capacitor discharges to the first level, and conducts when the voltage of the upper plate Node1 of the first capacitor discharges to the second level.

[0080] Therefore, when the memory cell 601 to be read is in the first state (such as the corresponding off cell), the transistor SO is not turned on, and the upper plate Node2 of the second capacitor C2 will not discharge, maintaining the previous higher level. When the memory cell 601 to be read is in the second state (such as the corresponding on cell), the transistor SO is turned on, and the upper plate Node2 of the second capacitor C2 is connected to the upper plate Node1 of the first capacitor C1, thereby quickly discharging to the lower level at the upper plate Node1 of the first capacitor C1.

[0081] Then, after the sensing process (e.g., during the comparison reading process), the sensitive amplification module 620 reads the data corresponding to the state of the memory cell 601 to be read based on the voltage of the upper plate Node2 of the second capacitor C2. For example, it obtains the data corresponding to the first state based on the higher level at Node2 corresponding to the first state, and obtains the data corresponding to the second state based on the lower level at Node2 corresponding to the second state.

[0082] Therefore, compared to the previous combination Figures 3A to 5The scheme using a single sensing capacitor, according to the two-step capacitance sensing scheme of this disclosure, can, through appropriate design, allow the voltage received by the subsequent sensitive amplification module 620 (i.e., the voltage of Node 2) to generate a larger distinguishing window (i.e., a larger difference) in the first state (e.g., corresponding to off cell) and the second state (e.g., corresponding to on cell). In other words, it expands the readout flip window, thereby improving readout accuracy. Furthermore, since the second capacitor C2 has a smaller capacitance value and a faster discharge rate, it can also accelerate the sensing speed, thereby improving the readout speed.

[0083] For example, the sensing module 610 can be configured to adjust the voltage of the upper plate Node2 of the second capacitor C2 during the sensing process. This raises the voltage of Node2 by a first value at the start of the sensing process. Therefore, during the sensing process, the higher level of Node2 in the first state (before discharge) increases by the first value, while in the second state, it can still discharge to the lower level of Node1 of the first capacitor C1, thus widening the level difference between the two states. Alternatively, the sensing module 610 can also be configured to adjust the voltage of Node2 during the sensing process, lowering it by a second value at the end of the sensing process. This pulls down the read-flip window to an appropriate position, increasing the difference between the Node2 voltage level in both states and the flip point Vtrigger, thereby widening the read-flip window.

[0084] For example, the voltage of the upper plate of the second capacitor C2 can be adjusted by applying a coupling signal to the lower plate of the second capacitor C2. For instance, a first signal is applied to the lower plate of the second capacitor C2. This first signal changes from a third level to a fourth level at the start of the sensing process and from a fourth level to a fifth level at the end of the sensing process, where the fourth level is higher than the third level and the fifth level is lower than the fourth level. Due to the coupling effect, at the start of the sensing process, the increase in the voltage of the lower plate of the second capacitor C2 causes the voltage of its upper plate Node2 to also increase, and at the end of the sensing process, the decrease in the voltage of the lower plate of the second capacitor C2 causes the voltage of its upper plate Node2 to also decrease, thereby expanding the flip window.

[0085] The following is combined Figure 6B describe Figure 6A This is an exemplary implementation of the sensitive amplification module 620. For clarity and ease of description, Figure 6B The diagram also shows a second capacitor C2 coupled to the sensitive amplification module. It should be understood that, as Figure 6A As shown, it is a component of the sensing module, not part of the sensitive amplification module.

[0086] like Figure 6B As shown, the sensitive amplification module 620' includes a detection unit 621 and a data latch 622.

[0087] The detection unit 621 receives the voltage of the upper plate Node2 of the second capacitor C2. Additionally, the detection unit 621 is coupled to the control terminal CTR of the data latch 622, and when it detects that the state of the memory cell 601 to be read is in the first state (e.g., corresponding to off cell) based on the voltage of the upper plate Node2 of the second capacitor C2 (e.g., the aforementioned undischarged higher level), it causes the signal Vctr level at the control terminal CTR to flip.

[0088] The data latch 622 is configured to output a data signal with an eighth level at its output terminal OUT after the sensing process, initially (e.g., at the start of the comparison reading process), and to flip the level of the data signal Vdata to a ninth level if the level of the signal Vctr at its control terminal CTR flips, for example, the output data flips from 0 to 1 or from 1 to 0.

[0089] Therefore, the sensitive amplification module 620' reads the data corresponding to the state of the memory unit 601 based on the voltage of the upper plate Node2 of the second capacitor C2. Specifically, the higher voltage level at Node2 corresponds to the data corresponding to the first state (the data output after the data latch 622 flips), and the lower voltage level at Node2 corresponds to the data corresponding to the second state (the data output when the data latch 622 is not flipped). Various principles and methods can be used to implement the detection unit 621 and the data latch 622 as needed.

[0090] It should be understood that this disclosure does not limit [the scope of the disclosure]. Figure 6A The above describes an exemplary implementation of the sensitive amplification module 620 and the pre-charge module 630. Various principles and methods can be used to implement the sensitive amplification module 620 and the pre-charge module 630 as needed.

[0091] In some embodiments, Figure 6A The pre-charge module 630 and sensitive amplification module 620 in the above-mentioned modules can adopt the same characteristics as those described above. Figures 3A to 3D The corresponding parts in the previous section have the same or similar implementation methods. For example, they can be combined with the previous ones. Figures 3A to 3D Based on the various readout circuits and their variations discussed, a second capacitor and a discharge switch are added to obtain the readout circuit employing a dual capacitor according to embodiments of this disclosure, such as... Figure 7 and Figure 8 exemplified.

[0092] For example, such as Figure 7 As shown above, in the aforementioned Figure 3AThe illustrated readout circuit adds a second capacitor C2 and an NMOS transistor SO as a discharge switch. Additionally, a new charging transistor SO_C is added to pre-charge the newly added second capacitor C2. It should be understood that... Figure 7 The capacitor C1 and NMOS transistor S1 in the sensing module 710 correspond to respectively Figure 3A The capacitor C_Sen and the NMOS transistor Sen in the figure are used interchangeably for ease of understanding. Figure 6A Same label.

[0093] For example, Figure 7 The circuit structure of the sensing module 710 in the middle and Figure 6A The sensing module 610 is the same as that in the previous one, so it will not be described again here.

[0094] Figure 7 The sensitive amplification module 720 in the middle is Figure 6B An exemplary implementation circuit of the structure shown includes a data latch 722 and an NMOS transistor Sen_Tr as a detection unit.

[0095] The first terminal of transistor Sen_Tr is coupled to the control terminal of data latch 722 (in Figure 7 The transistor Sen_Tr is exemplarily represented by one end of a transistor SET, with the second end coupled to VSS (negative power supply voltage or ground), and the gate coupled to the upper plate Node2 of the second capacitor C2. The transistor Sen_Tr is designed to distinguish between the first and second states of the memory cell to be read based on the magnitude of the voltage at the upper plate Node2 of the second capacitor C2. Thus, the transistor Sen_Tr can be designed such that the sum of its threshold voltage and the voltage VSS at its second end lies between a first voltage value and a second voltage value, wherein the first voltage value is the magnitude of the voltage at the upper plate Node2 of the second capacitor C2 after the sensing process when the memory cell to be read is in the first state, and the second voltage value is the magnitude of the voltage at the upper plate Node2 of the second capacitor C2 after the sensing process when the memory cell to be read is in the second state, and the first voltage value is greater than the second voltage value.

[0096] and Figure 3ASimilar to the data latch in the original, data latch 722 also includes inverters Inv1 and Inv2, and NMOS transistors RST, SET, and T1. The input terminal of inverter Inv1 is coupled to the output terminal of inverter Inv2, and the output terminal of inverter Inv1 is coupled to the input terminal of inverter Inv2. One of the input and output terminals of inverter Inv1 can also serve as the output terminal of data latch 722. The first terminal of transistor RST is coupled to the input terminal of inverter Inv1, and the second terminal is coupled to the first terminal of transistor T1. Its gate receives a reset signal. The first terminal of transistor SET is coupled to the output terminal of inverter Inv1, and the second terminal is coupled to the first terminal of transistor T1 and serves as the control terminal of data latch 722, coupled to the detection unit (i.e., the first terminal of transistor Sen_Tr). Its gate receives a set signal. The second terminal of transistor T1 is coupled to VSS, and its gate receives a fourth control signal.

[0097] Figure 7 The pre-charge module 730 includes charging transistors BL_C, Sen_C, and SO_C, one end of which is coupled to the power supply voltage VDD, and the other end of which is coupled to one end of transistor BL_Sel, the upper plate Node1 of the first capacitor C1, and the upper plate Node2 of the second capacitor C2, respectively, for charging BL, the upper plate Node1 of the first capacitor C1, and the upper plate Node2 of the second capacitor C2. Although Figure 7 The charging transistors BL_C and SO_C are shown to be NMOS transistors, and the charging transistor Sen_C is a PMOS transistor. However, it should be understood that this disclosure is not limited thereto, and the type of one or more of the transistors can be changed as needed (e.g., from NMOS to PMOS or vice versa) and their gate voltage settings can be adaptively changed.

[0098] The following describes some embodiments of this disclosure. Figure 7 An exemplary operation flow of the circuit.

[0099] During the pre-charging process, the pre-charging module 730 charges the upper plate Node1 of the first capacitor C1 and the upper plate Node2 of the second capacitor C2 to the first pre-charging voltage and the second pre-charging voltage, respectively. The two voltages can be the same (such as VDD) or different.

[0100] Then, an SAC signal is applied to the lower plate of the second capacitor C2 to increase the potential of the lower plate, thereby using capacitive coupling to raise the voltage of the upper plate Node2 of the second capacitor C2 (i.e., voltage = second pre-charge voltage + first value, which can exceed VDD).

[0101] During the sensing process, the gate of the transistor S1, which serves as the first switch, receives a high-level first control signal Vctr1 to turn on the transistor S1. At this time, the upper plate Node1 of the first capacitor C1 discharges to different voltages due to different BL states. For example, it discharges to Figure 5 the Vsen_off and Vsen_on shown.

[0102] During the discharge process of Node1, the gate of the transistor SO, which serves as the discharge switch, receives a high-level second control signal Vctr2. The level of Vctr2 is designed such that the transistor SO is not turned on in the first state (such as off cell) and the transistor SO is turned on in the second state (such as on cell). That is to say, in the second state, Vnode1 can reach the conduction condition (Vnode1 < Vctr2 - Vto (the threshold voltage of the transistor SO)), the transistor SO is turned on, and the small capacitor C2 quickly discharges to the target value (i.e., the current Vnode1 value during the sensing process); while in the first state, Vnode1 can never reach this conduction condition, the transistor SO is not turned on, the small capacitor C2 does not discharge, and Node2 will maintain the previously lifted high voltage unchanged. After that, a lower-level SAC signal is applied to the lower plate of the second capacitor C2 to reduce the potential of the lower plate, so as to use the capacitance coupling effect to make the voltage of the upper plate Node2 of the second capacitor C2 drop by a second value, in order to move the flip window to a suitable position so that the flip point is located at the midpoint of the flip window. The subsequent sense amplifier module 720's comparison and reading operation of the voltage of the upper plate Node2 of the second capacitor C2 can refer to the relevant content described above in combination with Figures 4A to 4D and will not be elaborated here.

[0103] Therefore, by using Figure 7 the sensing module 710 shown, it is possible to make the voltage of Node2 generate a larger discrimination window (i.e., a larger difference) in two different cases of the first state (such as corresponding to offcell) and the second state (such as corresponding to on cell), which is beneficial for subsequent comparison and reading. That is to say, the read flip window is expanded, thereby improving the read accuracy. In addition, since the capacitance value of the second capacitor C2 is small, the discharge speed is faster, so the sensing speed can also be increased, thereby improving the read speed. In addition, since the capacitance value of the second capacitor C2 is small, the power consumption consumed by the operation of adjusting the voltage of the upper plate of the second capacitor C2 to expand the flip window is less, so that higher read accuracy can be achieved with lower power consumption.

[0104] In addition, Figure 8 shows Figure 7 a variant of the read circuit of Figure 3BThe read circuit shown is based on the addition of a second capacitor C2 and an NMOS transistor SO as a discharge switch, thus... Figure 7 The difference lies in the use of Figure 3B The structure of the data latch shown is used to replace Figure 3A The structure of the data latch shown is illustrated.

[0105] For example, such as Figure 8 As shown, with Figure 3B Similar to the data latch in [the original text], data latch 722' also includes inverters Inv1 and Inv2, and NMOS transistors RST and SET. The input terminal of inverter Inv1 is coupled to the output terminal of inverter Inv2, and the output terminal of inverter Inv1 is coupled to the input terminal of inverter Inv2. One of the input and output terminals of inverter Inv1 can also serve as the output terminal of data latch 722'. The first terminal of transistor RST is coupled to the output terminal of inverter Inv1, and the second terminal is coupled to VSS; its gate receives a reset signal. The first terminal of transistor SET is coupled to the input terminal of inverter Inv1, and the second terminal serves as the control terminal of data latch 722', coupled to the detection unit (i.e., the first terminal of transistor Sen_Tr); its gate receives a set signal. The operating principle of this data latch 722' is similar to [the original text]. Figure 7 The data latch 722 in the middle is basically the same, therefore Figure 8 The working principle of the entire reading circuit and Figure 7 They are basically the same, so I won't go into details here.

[0106] It should be understood that Figure 7 and Figure 8 The read circuit shown is merely an example and not a limitation; for example, it can also be used in... Figure 3C to Figure 3D A second capacitor and a discharge switch are similarly added to the read circuit and other variant circuits, respectively. Furthermore, since the key point of this disclosure is the sensing module, which employs a two-step capacitance sensing method, the remaining implementation parts of the read circuit to which this disclosure applies are not limited. Additionally, although the read circuit has been described using NAND flash memory as an example, this disclosure is not limited to this and can be applied to read circuits of other types of memory, as long as they also require similar capacitance sensing operations. In other words, the basic principle and implementation method of the read circuit to which the sensing module of this disclosure can be applied are not limited to the aforementioned combination... Figures 3A to 8 Discussed.

[0107] In addition, in some embodiments, the problem of reduced reading window caused by Vtrigger jitter due to mismatch can be further solved by adding a mismatch sampling unit to the reading circuit.

[0108] For example, it can be Figure 7A mismatch sampling unit is added to the sensitive amplification module, and a mismatch sampling process is defined before the sensing process during the operation of the readout circuit. This mismatch sampling process can be part of the pre-charging process before the sensing process, or between the pre-charging process and the sensing process.

[0109] At the start of the mismatch sampling process, the upper plate Node2 of the second capacitor C2 is charged to the second pre-charge voltage, turning on the transistor Sen_Tr, which serves as the detection unit. During the mismatch sampling process, the mismatch sampling unit discharges the upper plate Node2 of the second capacitor C2 until the transistor Sen_Tr becomes non-conductive. Therefore, the voltage of Node2 is ultimately discharged to the flip point Vtrigger of its connected sensitive amplification module, incorporating the effect of the mismatch, thus achieving mismatch sampling. Correspondingly, during subsequent sensing, the voltage value of Node2 moves up and down with the fluctuations of the flip point Vtrigger, effectively compensating for the mismatch effect and preventing it from affecting the size of the read flip window.

[0110] Figure 9 An example of a readout circuit using a mismatch sampling unit is shown, which is in Figure 7 An NMOS transistor OC was added as a mismatch sampling unit to the existing readout circuit.

[0111] like Figure 9 As shown, the sensitive amplification module 720" also includes an NMOS transistor OC as a mismatch sampling unit. Its first terminal is coupled to the first terminal of the transistor Sen_Tr, and its second terminal is coupled to the gate of the transistor Sen_Tr. The gate receives a third control signal Vctr3. The third control signal Vctr3 can have a level that turns on the transistor OC during the mismatch sampling process. Figure 9 The rest of the reading circuit can be referred to in conjunction with the previous sections. Figure 7 The details described will not be repeated here.

[0112] The following is combined Figure 10 To describe in some embodiments of this disclosure Figure 9 An exemplary operation flow of the circuit.

[0113] Figure 10 Examples are shown in Figure 9 The waveforms of the voltage at nodes Node1 and Node2 and the voltage at the lower plate of the second capacitor C2 (i.e., the SAC signal) during the reading process of the reading circuit are shown as changes over time.

[0114] Figure 10 The operational timing is shown, which is divided into four processes: pre-charging of Node2, mismatch sampling, sensing, and comparison. Additionally, Figure 10The two jitter scenarios of the Vtrigger flip point are also illustrated using red and blue dashed lines, which deviate vertically from the theoretical Vtrigger point of the design shown by the black dashed line. Because this jitter is sampled during the mismatch sampling process, the voltage waveform of Node2 varies depending on the Vtrigger flip point jitter. Therefore, the voltage waveforms of Node2 under the two Vtrigger jitter scenarios shown by the red and blue dashed lines are represented by solid red and blue lines, respectively.

[0115] like Figure 10 As shown, during the pre-charging process of Node2, Node2 is fully charged, reaching the second pre-charging voltage, and then enters the mismatch sampling process. During both the pre-charging and mismatch sampling processes, Node1 is simultaneously pre-charged to reach the first pre-charging voltage. Because the capacitance of the first capacitor C1 is greater than that of the second capacitor C2, the first capacitor C1 requires a longer pre-charging time. In other words, it can be... Figure 10 The pre-charging process plus the mismatch sampling process are considered together as the complete pre-charging process required by the read circuit. Since the second capacitor C2 is a small capacitor, it can finish the pre-charging process and start sampling faster. That is, it uses part of the time in the original pre-charging process to perform mismatch sampling, and does not waste the overall timing time due to mismatch sampling.

[0116] Then, during the mismatch sampling process, transistors OC and Sen_Tr are simultaneously turned on, and the upper plate Node2 of the second capacitor C2 discharges. The voltage of Node2 drops until it reaches near Vtrigger, at which point the voltage of Node2 is insufficient to keep Sen_Tr on. In other words, the voltage of Node2 is eventually discharged to the Vtrigger of its connected sensitive amplifier module, incorporating the effects of the mismatch. For example... Figure 10 The solid red and blue lines represent the different Vtrigger values ​​they correspond to.

[0117] When the mismatch sampling process ends and the sensing process begins (which can be after the Node2 voltage stabilizes, or after a fixed period of time following the start of mismatch sampling), the lower plate of the second capacitor C2 begins to receive a high-level SAC signal. This signal, through capacitive coupling, raises the voltage value of the upper plate Node2, for example, by increasing the amplitude Vso_sac1. Figure 10 As shown, the boosted Node2 voltage can be greater than the second pre-charge voltage. When the voltage is boosted using the SAC signal, both transistors OC and SET are off.

[0118] Subsequently, during the sensing process, higher voltage levels can be applied to the gates of transistors S1 and SO, respectively, causing transistor S1 to conduct and node Node1 to discharge, resulting in a voltage drop, similar to... Figure 5 as shown. Although Figure 10 it is shown in [reference] that Node1 is discharged at the beginning of the sensing process, the timing of the present disclosure is not limited thereto. For example, it can also be set to discharge Node1 after a fixed time when the SAC signal becomes high. As described above, for the case of an off cell, the transistor SO is always non-conductive, Node2 is not discharged, and the high voltage remains unchanged. For the case of an on cell, when the voltage of Node1 drops to <Vctr2 - Vto>, the transistor SO starts to conduct, and Node2 starts to discharge. As Figure 10 shown, in the case of different Vtrigger jitters shown in red and blue, the discharge speed of Node2 is basically the same, so the voltage after discharge still maintains the difference in the mismatch voltage sampled before. Moreover, in the case of an on cell, Node2 can enter the final comparison stage in advance without waiting for Node1 to complete the discharge (i.e., its voltage is stabilized to the corresponding BL voltage), thus improving the sensing speed. The time point when the sensing process ends can be determined based on experience or experiments, etc., to ensure that both the flip window is expanded and the sensing speed is increased.

[0119] At the end of the sensing process, the level of the SAC signal on the lower plate of the second capacitor C2 is reduced, thereby reducing the voltage value of the lower plate Node2 through capacitive coupling. For example, the amplitude Vso_sac2 is reduced, so that the voltage of Node2 is within a suitable range for the subsequent comparison and reading operations of the sense amplifier module.

[0120] After that, during the comparison process, the transistor SET is turned on. If the voltage value of Node2 is higher than the flip point Vtrigger, the value of the data latch will flip. If the voltage of Node2 is lower than the flip point Vtrigger, the value of the data latch will not flip. At this time, since the voltage of Node2 always maintains the mismatch voltage sampled before, its value fluctuates with the jitter of Vtrigger in the subsequent circuit, thus compensating for the influence of the mismatch and solving the problem of the reduction of the reading window caused by the jitter of Vtrigger. In addition, from Figure 10 it can also be seen that compared with the reserved window between the Vsen voltage and Vtrigger shown in, for example Figure 5 shown, the reserved window between the Node2 voltage and Vtrigger is increased, that is, the reading window is further expanded.

[0121] In summary, Figure 9 the reading circuit of [circuit name] can further expand the reading window, further improve the reading accuracy of the reading circuit, and improve the reading speed.

[0122] Furthermore, the read circuits according to the embodiments of this disclosure described above can be applied to various memories, including but not limited to NAND flash memory. Additionally, memories using the read circuits of the embodiments of this disclosure can be applied to various electronic devices with storage needs, such as computers, smartphones and their peripheral electronic devices (e.g., Bluetooth headsets and wearable devices), electronic devices using the Internet of Things, and automotive electronic devices.

[0123] Those skilled in the art will understand that appropriate modifications can be made to the various circuit structures of this disclosure as needed, and all such modifications are within the scope of protection of this disclosure.

[0124] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A read circuit for a memory, comprising: A sensing module includes a first capacitor, a second capacitor, and a discharge switch, wherein the upper plate of the first capacitor is coupled to a first terminal of the discharge switch, the upper plate of the second capacitor is coupled to a second terminal of the discharge switch, the sensing module is configured to couple the upper plate of the first capacitor to the memory cell to be read during sensing, and the discharge switch is configured to not conduct during sensing when the memory cell to be read is in a first state but conduct when the memory cell to be read is in a second state; as well as A sensitive amplification module is configured to read data corresponding to the state of the memory cell to be read based on the voltage of the upper plate of the second capacitor after the sensing process. The capacitance value of the second capacitor is less than the capacitance value of the first capacitor.

2. The reading circuit according to claim 1, wherein, The first capacitor is configured to discharge the voltage of the upper plate of the first capacitor from the first pre-charge voltage to the first level when the memory cell to be read is in the first state during the sensing process, and to discharge the voltage of the upper plate of the first capacitor from the first pre-charge voltage to the second level when the memory cell to be read is in the second state. as well as The discharge switch is configured to not conduct when the voltage of the upper plate of the first capacitor discharges to the first level, and to conduct when the voltage of the upper plate of the first capacitor discharges to the second level.

3. The reading circuit according to claim 1, wherein, The sensing module is further configured to adjust the voltage of the upper plate of the second capacitor during the sensing process, such that the voltage of the upper plate of the second capacitor is raised by a first value at the beginning of the sensing process and lowered by a second value at the end of the sensing process.

4. The reading circuit according to claim 3, wherein, Adjusting the voltage of the upper plate of the second capacitor during the sensing process includes: A first signal is applied to the lower plate of the second capacitor. The first signal changes from a third level to a fourth level at the start of the sensing process and changes from the fourth level to a fifth level at the end of the sensing process, wherein the fourth level is higher than the third level and the fifth level is lower than the fourth level.

5. The reading circuit according to claim 1, wherein, The sensing module also includes a first switch. In this configuration, the first terminal of the first switch is coupled to the bit line of the memory cell to be read, the second terminal is coupled to the upper plate of the first capacitor, and the control terminal receives a first control signal. The control terminal of the discharge switch receives a second control signal. The first control signal has a sixth level during the sensing process to turn on the first switch. The second control signal has a seventh level during the sensing process such that the discharge switch is not turned on when the memory cell to be read is in the first state, and the discharge switch is turned on when the memory cell to be read is in the second state.

6. The reading circuit according to claim 5, wherein, The first switch is an NMOS transistor; and / or The discharge switch is an NMOS transistor.

7. The reading circuit according to claim 1, wherein, The sensitive amplification module includes a detection unit and a data latch. Specifically, after the sensing process, the detection unit receives the voltage of the upper plate of the second capacitor, which is coupled to the control terminal of the data latch. Furthermore, if the voltage of the upper plate of the second capacitor indicates that the state of the memory cell to be read is the first state, the detection unit causes the signal level at the control terminal to flip. The data latch is configured to output a data signal with an eighth level at its output terminal, and to flip the level of the data signal to a ninth level when the signal level at the control terminal flips.

8. The reading circuit according to claim 7, wherein, The detection unit includes a first NMOS transistor. The first terminal of the first NMOS transistor is coupled to the control terminal of the data latch, the second terminal is coupled to the negative power supply voltage or ground, and the gate is coupled to the upper plate of the second capacitor.

9. The reading circuit according to claim 8, wherein, The sum of the threshold voltage of the first NMOS transistor and the voltage at the second terminal of the first NMOS transistor lies between the first voltage value and the second voltage value. Wherein, the first voltage value is the amplitude of the voltage on the upper plate of the second capacitor after the sensing process when the memory cell to be read is in the first state, the second voltage value is the amplitude of the voltage on the upper plate of the second capacitor after the sensing process when the memory cell to be read is in the second state, and the first voltage value is greater than the second voltage value.

10. The reading circuit according to claim 8, wherein, The sensitive amplification module also includes a mismatch sampling unit. Prior to the sensing process, a mismatch sampling process is also included. At the start of the mismatch sampling process, the upper plate of the second capacitor has been charged to a second pre-charge voltage, causing the first NMOS transistor to turn on. During the mismatch sampling process, the mismatch sampling unit discharges the upper plate of the second capacitor until the first NMOS transistor becomes non-conductive. The mismatch sampling process is either part of a pre-charging process prior to the sensing process or between the pre-charging process and the sensing process.

11. The reading circuit according to claim 10, wherein, The mismatch sampling unit includes a second NMOS transistor. In this configuration, the first terminal of the second NMOS transistor is coupled to the first terminal of the first NMOS transistor, and the second terminal is coupled to the gate of the first NMOS transistor. The gate receives a third control signal. The third control signal has a tenth level during the mismatch sampling process to turn on the second NMOS transistor.

12. The reading circuit according to claim 7, wherein, The data latch includes a first inverter, a second inverter, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. In this configuration, the input terminal of the first inverter is coupled to the output terminal of the second inverter, the output terminal of the first inverter is coupled to the input terminal of the second inverter, and one of the input and output terminals of the first inverter serves as the output terminal of the data latch. The first terminal of the third NMOS transistor is coupled to the input terminal of the first inverter, and the second terminal is coupled to the first terminal of the fifth NMOS transistor. The gate receives a reset signal. The first terminal of the fourth NMOS transistor is coupled to the output terminal of the first inverter, and the second terminal is coupled to the first terminal of the fifth NMOS transistor and serves as the control terminal of the data latch, coupled to the detection unit. The gate receives a set signal. The second terminal of the fifth NMOS transistor is coupled to a negative power supply voltage or ground, and the gate receives a fourth control signal.

13. The reading circuit according to claim 7, wherein, The data latch includes a first inverter, a second inverter, a third NMOS transistor, and a fourth NMOS transistor. In this configuration, the input terminal of the first inverter is coupled to the output terminal of the second inverter, the output terminal of the first inverter is coupled to the input terminal of the second inverter, and one of the input and output terminals of the first inverter serves as the output terminal of the data latch. The first terminal of the third NMOS transistor is coupled to the output terminal of the first inverter, the second terminal is coupled to the negative power supply voltage or ground, and the gate receives a reset signal. The first terminal of the fourth NMOS transistor is coupled to the input terminal of the first inverter, and the second terminal, as the control terminal of the data latch, is coupled to the detection unit, with the gate receiving a set signal.

14. The reading circuit according to claim 1, wherein, The capacitance value of the second capacitor is equal to or less than one-tenth of the capacitance value of the first capacitor.

15. The readout circuit according to any one of claims 1-14, wherein, The first state is the programming state, and the second state is the erasure state.

16. A memory comprising a read circuit according to any one of claims 1-15.

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