Balanced bridge circuit control method, balanced bridge circuit and three-level converter device

Abstract

The invention discloses a control method of a balance bridge circuit, the balance bridge circuit and three-level conversion equipment, and belongs to the field of electric energy conversion. When the voltages of two direct-current bus capacitors are not equal, according to the voltage difference value of the upper half bus capacitor and the lower half bus capacitor of a direct-current bus, the voltage of the two direct-current bus capacitors can be adjusted; the duty ratio of the pulse width modulation signal is determined, then the non-target switch group is controlled to be switched off, and the controllable switches in the target switch group are controlled according to the pulse width modulation signal, so that electric energy migration is carried out through the inductor to realize DC bus voltage balance, and only one PWM signal for the target switch group needs to be generated; and the control complexity is reduced.

Description

Technical Field

[0001] This invention relates to the field of power conversion, and in particular to a balanced bridge circuit and a three-level converter. Background Technology

[0002] For three-level converter equipment (such as inverters or converters), in order to achieve voltage balance between the upper and lower half of the bus under three-phase unbalanced load conditions, a balancing bridge circuit can be connected in parallel on the DC bus of the three-level converter equipment. However, there is a lack of a mature control method for the balancing bridge circuit in related technologies, resulting in high control complexity.

[0003] Therefore, how to provide a solution to the above-mentioned technical problems is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a balanced bridge circuit and a three-level converter. When the voltages of the two DC bus capacitors are unequal, this invention can determine the duty cycle of the pulse width modulation signal based on the voltage difference between the upper and lower half of the DC bus capacitors. Then, it controls the non-target switch group to open and controls the controllable switch in the target switch group according to the pulse width modulation signal, so as to achieve DC bus voltage balance through inductor-based power transfer. Moreover, it only needs to generate one PWM signal for the target switch group, reducing control complexity.

[0005] To solve the above-mentioned technical problems, the present invention provides a balanced bridge circuit, which includes a power transfer circuit and an inductor. The power transfer circuit includes a first switch group, a second switch group, a first unidirectional conducting device, and a second unidirectional conducting device. Both the first and second switch groups are composed of an even number of controllable switches with body diodes connected in series. The body diodes of each controllable switch are arranged from the low potential end to the high potential end. The first terminal of the first switch group is connected to the positive terminal of the DC bus, and the second terminal of the first switch group is connected to the first terminal of the second switch group. The common point of the second switch group is used as the first circuit point, and the second terminal of the second switch group is connected to the negative terminal of the DC bus. An inductor is connected between the first circuit point and the midpoint of the DC bus. The common point formed by connecting the anode of the first unidirectional conducting device and the cathode of the second unidirectional conducting device is used as the second circuit point. The cathode of the first unidirectional conducting device is connected to the third circuit point, and the anode of the second unidirectional conducting device is connected to the fourth circuit point. The second circuit point is connected to the midpoint of the DC bus, the third circuit point is the midpoint of the first switch group, and the fourth circuit point is the midpoint of the second switch group. The control method of the balanced bridge circuit includes:

[0006] When the voltages of the two DC bus capacitors are not equal, the duty cycle of the pulse width modulation signal is determined based on the voltage difference between the upper and lower half of the DC bus capacitor.

[0007] The non-target switch group is controlled to disconnect, and the controllable switch in the target switch group is controlled according to the pulse width modulation signal in order to balance the voltage of the two DC bus capacitors;

[0008] The target switch group is a switch group connected in parallel with the DC bus capacitor with a higher voltage, while the non-target switch group is a switch group connected in parallel with the DC bus capacitor with a lower voltage.

[0009] On the other hand, when the voltages of the two DC bus capacitors are unequal, determining the duty cycle of the pulse width modulation signal based on the voltage difference between the upper and lower half of the DC bus capacitors includes:

[0010] When the voltages of the two DC bus capacitors are not equal, the inductor current reference value is determined by a closed-loop control algorithm based on the voltage difference between the upper and lower half of the DC bus capacitor.

[0011] The duty cycle of the pulse width modulation signal is determined by a closed-loop control algorithm based on the current difference between the inductor current reference value and the actual inductor current value.

[0012] On the other hand, controlling the controllable switches in the target switch group according to the pulse width modulation signal includes:

[0013] Dead time processing is performed on the pulse width modulation signal;

[0014] The pulse width modulation signal without dead time processing is applied to one half of the controllable switches in the target switch group closest to the inductor;

[0015] The pulse width modulation signal, after dead time processing, is applied to the half of the controllable switches in the target switch group that is furthest from the inductor, so that the half of the controllable switches furthest from the inductor in the target switch group is turned off and then turned on relative to the other half of the controllable switches closest to the inductor.

[0016] On the other hand, the first switch group includes a first controllable switch and a second controllable switch, and the second switch group includes a third controllable switch and a fourth controllable switch;

[0017] The cathode of the body diode of the first controllable switch serves as the first terminal of the first switch group, the anode of the body diode of the second controllable switch serves as the second terminal of the first switch group, the cathode of the body diode of the third controllable switch serves as the first terminal of the second switch group, and the anode of the body diode of the fourth controllable switch serves as the second terminal of the second switch group.

[0018] On the other hand, the closed-loop control algorithm includes a proportional-integral (PI) regulation algorithm.

[0019] On the other hand, the DC bus includes the DC bus of a photovoltaic power generation system.

[0020] On the other hand, the balanced bridge circuit also includes a fifth controllable switch and a sixth controllable switch;

[0021] The body diode of the fifth controllable switch serves as the first unidirectional conduction device, and the body diode of the sixth controllable switch serves as the second unidirectional conduction device.

[0022] The control of the non-target switch group to disconnect and the controllable switch in the target switch group to control the pulse width modulation signal include:

[0023] Control the non-target switch group and the non-target switch to disconnect, and control the target switch group and the target switch according to the pulse width modulation signal;

[0024] Among them, the non-target switch is one of the fifth and sixth controllable switches that is directly connected to the target switch group, and the target switch is one of the fifth and sixth controllable switches that is directly connected to the non-target switch group.

[0025] To address the aforementioned technical problems, the present invention also provides a balanced bridge circuit, including a power transfer circuit and an inductor;

[0026] The power transfer circuit includes a first switch group, a second switch group, a first unidirectional conducting device, and a second unidirectional conducting device. Both the first and second switch groups are composed of an even number of controllable switches with body diodes connected in series. The body diodes of each controllable switch are arranged from the low-potential end to the high-potential end. The first terminal of the first switch group is connected to the positive terminal of the DC bus. The common point formed by connecting the second terminals of the first and second switch groups is the first circuit point. The second terminal of the second switch group is connected to the negative terminal of the DC bus. An inductor is connected between the first circuit point and the midpoint of the DC bus. The common point formed by connecting the anode of the first unidirectional conducting device and the cathode of the second unidirectional conducting device is the second circuit point. The cathode of the first unidirectional conducting device is connected to the third circuit point, and the anode of the second unidirectional conducting device is connected to the fourth circuit point. The second circuit point is connected to the midpoint of the DC bus. The third circuit point is the midpoint of the first switch group, and the fourth circuit point is the midpoint of the second switch group.

[0027] The balanced bridge circuit uses the control method described above.

[0028] To solve the above-mentioned technical problems, the present invention also provides a three-level converter device, including a three-level converter device body, a controller, and a balanced bridge circuit as described above connected to the three-level converter device body;

[0029] The three-level converter body is used to perform power conversion between the DC bus and the three-phase power grid under the control of the controller.

[0030] On the other hand, the three-level converter also includes a switching switch that is connected to the midpoint of the three-phase power grid and the midpoint of the DC bus respectively;

[0031] The controller is also used to: when the load of the three-level converter is a three-phase unbalanced load, control the switching switch to close, and control the three-level converter body to perform power conversion between the DC bus and the three-phase power grid through sinusoidal pulse width modulation; when the load of the three-level converter is a three-phase balanced load, control the switching switch to open, and control the three-level converter body to perform power conversion between the DC bus and the three-phase power grid through space vector pulse width modulation or discontinuous pulse width modulation.

[0032] Beneficial Effects: This invention provides a balanced bridge circuit. Considering that by controlling the target switch group (the switch group connected in parallel with the higher voltage DC bus capacitor) in the power transfer circuit of the balanced bridge circuit with PWM, a low-impedance path can be established for the first half of the bus capacitor (the higher voltage DC bus capacitor) to charge the inductor during the conduction period of the target switch group. When the target switch group is turned off, a freewheeling path is established for the inductor to discharge to the "lower voltage DC bus capacitor" through the body diode of the controllable switch in the non-target switch group (the switch group connected in parallel with the lower voltage DC bus capacitor), so as to achieve bus voltage balance. Therefore, when the voltages of the two DC bus capacitors are not equal, this invention can determine the duty cycle of the pulse width modulation signal according to the voltage difference between the upper and lower half of the DC bus capacitor, then control the non-target switch group to turn off, and control the controllable switch in the target switch group according to the pulse width modulation signal, so as to achieve DC bus voltage balance through power transfer via the inductor. Moreover, only one PWM signal needs to be generated for the target switch group, reducing the control complexity.

[0033] The present invention also provides a three-level converter device, which has the same beneficial effects as the above balanced bridge circuit. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the relevant technologies and the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A flowchart illustrating a control method for a balanced bridge circuit provided by the present invention;

[0036] Figure 2 This is a schematic diagram of the structure of the first balanced bridge circuit provided by the present invention;

[0037] Figure 3 A schematic diagram of a process for determining the duty cycle provided by the present invention;

[0038] Figure 4 The signal waveform diagram of the controlled switch and inductor in the first type of balanced bridge circuit is shown.

[0039] Figure 5 This is a schematic diagram of the first state of the first type of balanced bridge circuit.

[0040] Figure 6 This is a schematic diagram of the second state of the first type of balanced bridge circuit;

[0041] Figure 7 This is a schematic diagram of the third state of the first type of balanced bridge circuit;

[0042] Figure 8 This is a schematic diagram of the structure of the second type of balanced bridge circuit provided by the present invention;

[0043] Figure 9 This is a schematic diagram of the first state of the second type of balanced bridge circuit.

[0044] Figure 10 This is a schematic diagram of the second state of the second type of balanced bridge circuit;

[0045] Figure 11 This is a schematic diagram of the third state of the second type of balanced bridge circuit;

[0046] Figure 12 The signal waveform diagram of the controlled switch and inductor in the second type of balanced bridge circuit is shown.

[0047] Figure 13 This is a schematic diagram of the structure of a three-level converter provided by the present invention. Detailed Implementation

[0048] The core of this invention is to provide a balanced bridge circuit and a three-level converter. When the voltages of the two DC bus capacitors are not equal, this invention can determine the duty cycle of the pulse width modulation signal based on the voltage difference between the upper and lower half of the DC bus capacitors. Then, it controls the non-target switch group to open and controls the controllable switch in the target switch group according to the pulse width modulation signal, so as to achieve DC bus voltage balance through inductor-based power transfer. Moreover, only one PWM signal needs to be generated for the target switch group, reducing the control complexity.

[0049] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating a control method for a balanced bridge circuit provided by the present invention. The balanced bridge circuit includes a power transfer circuit and an inductor. The power transfer circuit includes a first switch group, a second switch group, a first unidirectional conducting device, and a second unidirectional conducting device. Both the first and second switch groups are composed of an even number of controllable switches with body diodes connected in series. The body diodes of each controllable switch are arranged from the low potential end to the high potential end. The first terminal of the first switch group is connected to the positive terminal of the DC bus, and the second terminal of the first switch group is connected to the first terminal of the second switch group. The common point of the second switch group is used as the first circuit point, and the second terminal of the second switch group is connected to the negative terminal of the DC bus. An inductor is connected between the first circuit point and the midpoint of the DC bus. The common point formed by connecting the anode of the first unidirectional conducting device and the cathode of the second unidirectional conducting device is used as the second circuit point. The cathode of the first unidirectional conducting device is connected to the third circuit point, and the anode of the second unidirectional conducting device is connected to the fourth circuit point. The second circuit point is connected to the midpoint of the DC bus, the third circuit point is the midpoint of the first switch group, and the fourth circuit point is the midpoint of the second switch group. The control method of the balanced bridge circuit includes:

[0051] S101: When the voltages of the two DC bus capacitors are not equal, the duty cycle of the pulse width modulation signal is determined based on the voltage difference between the upper and lower half of the DC bus capacitors.

[0052] Specifically, considering the technical problems mentioned above, and taking into account that by controlling the target switch group (the switch group connected in parallel with the higher voltage DC bus capacitor) in the power transfer circuit of the balanced bridge circuit with PWM, a low-impedance path can be established for the first half-bus capacitor (the higher voltage DC bus capacitor) to charge the inductor during the conduction period of the target switch group, and when the target switch group is turned off, a freewheeling path is established for the inductor to discharge to the "lower voltage DC bus capacitor" through the body diode of the controllable switch in the non-target switch group (the switch group connected in parallel with the lower voltage DC bus capacitor) in order to achieve bus voltage balance, in this embodiment of the invention, when the voltages of the two DC bus capacitors are not equal, the target switch group in the power transfer circuit of the balanced bridge circuit is controlled to achieve bus voltage balance.

[0053] In this step, considering that the duty cycle of the PWM signal for the target switch group can be determined based on the voltage difference between the upper and lower half of the DC bus capacitor, the duty cycle of the pulse width modulation signal can be determined first when the voltages of the two DC bus capacitors are not equal, based on the voltage difference between the upper and lower half of the DC bus capacitor, so as to serve as the data basis for subsequent steps.

[0054] S102: Controls the non-target switch group to disconnect and controls the controllable switch in the target switch group according to the pulse width modulation signal in order to balance the voltage of the two DC bus capacitors;

[0055] The target switch group is a switch group connected in parallel with the DC bus capacitor with a higher voltage, while the non-target switch group is a switch group connected in parallel with the DC bus capacitor with a lower voltage.

[0056] Specifically, after obtaining the duty cycle of the pulse width modulation signal, the controllable switches in the target switch group can be controlled according to the pulse width modulation signal. At the same time, the non-target switch group can be controlled to turn off, thereby establishing a low-impedance path for the "high-voltage DC bus capacitor" to charge the inductor during the conduction period of the target switch group. When the target switch group turns off the device, a freewheeling path for the inductor to discharge to the "low-voltage DC bus capacitor" is established through the body diode of the controllable switch in the non-target switch group (the switch group connected in parallel with the low-voltage DC bus capacitor), so as to achieve bus voltage balance.

[0057] Specifically, for a better explanation of the embodiments of the present invention, please refer to... Figure 2 , Figure 2 This is a schematic diagram of the structure of the first balanced bridge circuit provided by the present invention. Figure 2The first controllable switch Q1 and the second controllable switch Q2 form the first switch group, and the third controllable switch Q3 and the fourth controllable switch Q4 form the second switch group. L is an inductor, D5 is the first unidirectional conducting device, and D6 is the second unidirectional conducting device.

[0058] This invention provides a balanced bridge circuit. Considering that by controlling the PWM of the target switch group (a switch group connected in parallel with the higher-voltage DC bus capacitor) in the power transfer circuit of the balanced bridge circuit, a low-impedance path can be established during the conduction period of the target switch group to charge the inductor from the "higher-voltage DC bus capacitor". When the target switch group is turned off, a freewheeling path is established through the body diode of the controllable switch in the non-target switch group (a switch group connected in parallel with the lower-voltage DC bus capacitor) to discharge the inductor to the "lower-voltage DC bus capacitor", thus achieving bus voltage balance. Therefore, when the voltages of the two DC bus capacitors are unequal, this invention can determine the duty cycle of the pulse width modulation signal based on the voltage difference between the upper and lower half of the DC bus capacitor, then control the non-target switch group to turn off, and control the controllable switch in the target switch group according to the pulse width modulation signal to achieve DC bus voltage balance through power transfer via the inductor. Furthermore, only one PWM signal needs to be generated for the target switch group, reducing control complexity.

[0059] Based on the above embodiments:

[0060] As an optional embodiment, when the voltages of the two DC bus capacitors are unequal, determining the duty cycle of the pulse width modulation signal based on the voltage difference between the upper and lower half of the DC bus capacitors includes:

[0061] When the voltages of the two DC bus capacitors are not equal, the inductor current reference value is determined by a closed-loop control algorithm based on the voltage difference between the upper and lower half of the DC bus capacitor.

[0062] The duty cycle of the pulse width modulation signal is determined by a closed-loop control algorithm based on the current difference between the inductor current reference value and the actual inductor current value.

[0063] Specifically, considering the need for precise control of the charging and discharging current of inductor L during power migration to avoid insufficient voltage balance accuracy or device damage due to excessive or insufficient current, this embodiment of the invention can set the controller to determine the duty cycle of the pulse width modulation (PWM) signal through a closed-loop control algorithm. First, the reference value of the inductor L current is determined based on the voltage difference between the two DC bus capacitors, and then the duty cycle is adjusted based on the current difference to achieve precise control of the conduction time of the target switch group. The closed-loop control algorithm improves the current control accuracy, ensuring that the inductor L current stably tracks the reference value, thereby improving the voltage balance accuracy of the two DC bus capacitors. At the same time, it avoids excessive current fluctuations from impacting circuit devices and extends the service life of the devices.

[0064] Specifically, for a better explanation of the embodiments of the present invention, please refer to... Figure 3 , Figure 3 This invention provides a flowchart for determining the duty cycle. First, the voltage VP of the upper bus capacitor C1 and the voltage VN of the lower bus capacitor C2 are acquired, and the voltage difference ΔV = VN - VP is calculated. ΔV is multiplied by a coefficient K and then input to a proportional-integral regulator (PI). The regulator outputs a reference value Iref for the inductor current L (K is -1 if VP > VN; K is 1 if VN > VP). The actual value Iref of the inductor current L is then acquired. L Calculate the current difference ΔI = Iref - I L The input ΔI is fed into another PI regulator, which outputs a modulation signal MOD. MOD is compared with a triangular carrier wave to generate the duty cycle of the PWM signal. When the target switch group is the first switch group (Q1 and Q2), the controller controls the on and off of Q2 through this PWM signal. The duty cycle determines the on-time of Q2 in one switching cycle (e.g., when duty=50%, Q2 is on for half a cycle). When the target switch group is the second switch group (Q3 and Q4), the controller controls the on and off of Q3 through this PWM signal, thereby achieving precise control of the charging and discharging current of inductor L and ensuring that ΔV gradually decreases to zero.

[0065] Of course, in addition to this specific form, "when the voltages of the two DC bus capacitors are not equal, the duty cycle of the pulse width modulation signal is determined based on the voltage difference between the upper half of the DC bus capacitor and the lower half of the DC bus capacitor" can also be in other forms, and the embodiments of the present invention are not limited here.

[0066] As an optional embodiment, controlling the controllable switches in the target switch group according to the pulse width modulation signal includes:

[0067] Dead time processing is applied to pulse width modulation signals;

[0068] Apply a pulse width modulation signal without dead time processing to one half of the controllable switches in the target switch group closest to the inductor;

[0069] A pulse width modulation signal, processed with dead time, is applied to the half of the controllable switches in the target switch group that is furthest from the inductor, so that the half of the controllable switches furthest from the inductor in the target switch group is turned off first and then turned on relative to the other half of the controllable switches closest to the inductor.

[0070] Specifically, to prevent the upper and lower bridge arms of the controllable switches in the switch group from being directly connected, the pulse width modulation signal can be subjected to dead time processing in this embodiment of the invention. The pulse width modulation signal without dead time processing is applied to the half of the controllable switches in the target switch group that is closer to the inductor, and the pulse width modulation signal with dead time processing is applied to the half of the controllable switches in the target switch group that is farther from the inductor, so that the half of the controllable switches in the target switch group that is farther from the inductor is turned off and then turned on relative to the other half of the controllable switches that is closer to the inductor.

[0071] As an optional embodiment, the first switch group includes a first controllable switch and a second controllable switch, and the second switch group includes a third controllable switch and a fourth controllable switch;

[0072] The cathode of the body diode of the first controllable switch serves as the first terminal of the first switch group, the anode of the body diode of the second controllable switch serves as the second terminal of the first switch group, the cathode of the body diode of the third controllable switch serves as the first terminal of the second switch group, and the anode of the body diode of the fourth controllable switch serves as the second terminal of the second switch group.

[0073] The first to the fourth controllable switches are all of the same type;

[0074] The first to the fourth controllable switches are all N-channel metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors.

[0075] Specifically, considering that both the first switch group and the second switch group can be implemented by connecting at least two controllable switches in series, the first switch group in this embodiment of the invention includes a first controllable switch and a second controllable switch, and the second switch group includes a third controllable switch and a fourth controllable switch. The connection relationship of the body diodes of each controllable switch is clearly defined, which helps to simplify the circuit structure and reduce costs.

[0076] Specifically, considering that each controllable switch in the circuit needs to have consistent electrical characteristics (such as on-state voltage drop and switching speed) to ensure the matching of control timing and avoid control delays or current imbalances caused by differences in device types, this embodiment of the invention specifies that the first to fourth controllable switches are of the same type and are limited to N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs). The consistent electrical characteristics of devices of the same type improve the synchronization of control timing and reduce current fluctuations. The selection of MOSFETs and IGBTs covers the needs of medium and high voltage scenarios, taking into account both switching speed and withstand voltage, and improving the applicability of the circuit.

[0077] Of course, in addition to this specific form, there can be different selection methods, and the embodiments of the present invention are not limited here.

[0078] Specifically, for a better explanation of the embodiments of the present invention, please refer to... Figures 4 to 7 , Figure 4 The signal waveforms of the controlled switch and inductor L in the first type of balanced bridge circuit are shown. Figure 5 This is a schematic diagram of the first state of the first type of balanced bridge circuit. Figure 6 This is a schematic diagram of the second state of the first type of balanced bridge circuit; Figure 7 This is a schematic diagram of the third state of the first type of balanced bridge circuit; in this embodiment, the premise is that the voltage of the lower half bus capacitor is higher than the voltage of the upper half bus capacitor, the target switch group is the second switch group, that is, the controlled switches are the third controllable switches Q3 and Q4 in the second switch group, Vg3 is the control signal of Q3, Vg4 is the control signal of Q4, and I L Let L be the current value of the inductor. Figure 5 The current paths from t0 to t1 and from t2 to t3 are illustrated. Figure 6 The current path from stage t1 to t2 is illustrated. Figure 7 The current path from t3 to t4 is illustrated.

[0079] Mode 1: From t0 to t1, transistor Q3 is turned on (transistors Q1, Q2, and Q4 are off). Before this, inductor L continues to flow in the same direction as the previous state. Figure 5 As shown. When Q3 is on, the current in inductor L flows in the following direction: BUSN → inductor L → Q3 → D6 → BUSN. Due to the low line impedance, the current in inductor L remains almost unchanged.

[0080] Module 2: During the stage from t1 to t2, at the moment of t1, Q4 is turned on. During this stage, Q3 remains conducting continuously, and Q4 is conducting (Q1 and Q2 are still in the off state). At this time, the lower half bus capacitor charges the inductor L, the lower half bus discharges, the voltage of VN drops, the inductor L stores energy, and the magnitude of the current in the inductor L increases. The direction of the current in the inductor L is: BUSN → inductor L → Q3 → Q4 → BUS-.

[0081] Mode 3: During the stage from t2 to t3, at the moment of t2, Q4 is turned off (Q3 maintains conduction, and Q1 and Q2 are still in the off state). This is the dead time period when Q4 is turned off. The current in the inductor L is the same as that in Mode 1.

[0082] Mode 4: During the stage from t3 to t4, at the moment of t3, Q3 is turned off (Q3 and Q4 maintain the off state, and Q1 and Q2 are still in the off state). At this time, the current in the inductor L continues to freewheel. The path is: BUSN → L → D2 → D1 → BUS+ → C1, charging the upper half bus capacitor C1. The voltage of VP rises, the lower half bus capacitor C2 in Mode 2 discharges, and the voltage of VN drops. In such a working cycle, the voltage difference between VP and VN becomes smaller and smaller, achieving the voltage balance between the upper and lower half buses. Similarly, when VN < VP, there are similar modes, which will not be elaborated here.

[0083] Specifically, this balanced bridge circuit is applicable to the application scenarios of three-phase unbalanced loads or half-wave loads. In the case of three-phase unbalanced loads or half-wave loads, the balanced bridge circuit is enabled to control the half bus voltage to achieve the balance of the half bus voltage. The working voltage of each switching tube is the half bus voltage, which is suitable for the scenario with a relatively high bus voltage. Therefore, it facilitates the selection of switching tubes in the balanced bridge circuit and reduces the design cost. The working voltage of the inductor L is the voltage difference from -0.5Vbus to 0.5Vbus. For the traditional two-level balanced bridge, the working voltage of the inductor L changes from -Vbus to Vbus. According to the volt-second balance, at the same bus voltage and switching frequency, the three-level balanced bridge circuit is beneficial to reducing the inductance value of the inductor L and the cost of the inductor L.

[0084] Of course, in addition to this specific form, the number of controllable switches in the first switch group and the second switch group can also be other specific even values, which are not limited in the embodiments of the present invention.

[0085] As an optional embodiment, the closed-loop control algorithm includes a proportional-integral regulation algorithm.

[0086] Specifically, considering that the proportional-integral (PI, Proportional-Integral Regulator) regulation algorithm has the advantages of simplicity, high efficiency, and precise control, the closed-loop control calculation method in the embodiments of the present invention can adopt the proportional-integral regulation algorithm.

[0087] Of course, in addition to the proportional-integral control algorithm, the closed-loop control algorithm can be of many other types, and the embodiments of the present invention are not limited to these types.

[0088] As an optional embodiment, the DC bus includes the DC bus of a photovoltaic power generation system.

[0089] Specifically, considering that the DC bus of a photovoltaic power generation system often faces high-voltage scenarios such as 1500V and 2000V, and is prone to voltage imbalance between the upper and lower half of the bus due to three-phase unbalanced loads, there is an urgent need for an appropriate balancing bridge circuit to solve the voltage balance problem. Therefore, in this embodiment of the invention, the DC bus is explicitly included in the DC bus of the photovoltaic power generation system, which specifically meets the needs of this scenario.

[0090] Of course, besides this specific form, the DC bus can also be a DC bus in other scenarios, and the embodiments of the present invention are not limited here.

[0091] As an optional embodiment, the balanced bridge circuit also includes a fifth controllable switch and a sixth controllable switch;

[0092] The body diode of the fifth controllable switch serves as the first unidirectional conduction device, and the body diode of the sixth controllable switch serves as the second unidirectional conduction device.

[0093] Controlling the non-target switch group to disconnect and controlling the controllable switches in the target switch group according to the pulse width modulation signal includes:

[0094] Control the non-target switch group and the non-target switch to disconnect, and control the target switch group and the target switch according to the pulse width modulation signal;

[0095] Among them, the non-target switch is one of the fifth and sixth controllable switches that is directly connected to the target switch group, and the target switch is one of the fifth and sixth controllable switches that is directly connected to the non-target switch group.

[0096] Specifically, considering that the body diode of the controllable switch can realize the function of a unidirectional conducting device and can unify the devices of the power transfer circuit, making it easier to select and lay out, the balanced bridge circuit in this embodiment of the invention also includes a fifth controllable switch and a sixth controllable switch; the body diode of the fifth controllable switch serves as the first unidirectional conducting device, and the body diode of the sixth controllable switch serves as the second unidirectional conducting device; thereby simplifying the circuit structure and facilitating the selection and layout of devices in the power transfer circuit.

[0097] Specifically, for a better explanation of the embodiments of the present invention, please refer to... Figures 8 to 12 , Figure 8 This is a schematic diagram of the structure of the second type of balanced bridge circuit provided by the present invention; Figure 9 This is a schematic diagram of the first state of the second type of balanced bridge circuit. Figure 10 This is a schematic diagram of the second state of the second type of balanced bridge circuit; Figure 11 This is a schematic diagram of the third state of the second type of balanced bridge circuit; Figure 12 The signal waveform diagram of the controlled switch and inductor L in the second type of balanced bridge circuit is shown. Figure 12 Vg5 is the control signal for the fifth controllable switch, Q5 is the fifth controllable switch, and Q6 is the sixth controllable switch.

[0098] Specifically, in a concrete example, where the voltage VN of the lower half-bus capacitor C2 is higher than the voltage VP of the upper half-bus capacitor C1, the target switch group is the second switch group, the target switch is Q5, and the control process includes the following four modes, among which... Figure 9 Corresponding to stages t0 to t1 and t2 to t3, Figure 10 Corresponding to stages t2 to t3, Figure 11 This corresponds to stages t3 to t4.

[0099] Mode 1: From t0 to t1, at time t0, Q5 and Q3 are turned on, and at time t1, Q4 is turned on. The current in inductor L freewheels along the paths BUSN→L→D2→Q5→BUSN and BUSN→L→Q3→D6→BUSN. The current in inductor L is approximately horizontal.

[0100] Mode 2: From t1 to t2, at time t1, Q4 is turned on, and at time t2, Q4 is turned off; Q3 remains on. During this stage, the lower half of the bus applies voltage to the two ends of inductor L, and inductor L stores energy. The current path of inductor L is BUSN→L→Q3→Q4→BUS-. As inductor L stores energy, the voltage of the lower half of the bus decreases.

[0101] Mode 3: From t2 to t3, at time t3, Q3 and Q5 are disconnected, and the current paths are BUSN→L→D2→Q5→BUSN and BUSN→L→Q3→D6→BUSN. The current in inductor L is approximately horizontal.

[0102] Mode 4: From t3 to t4, at time t4+, Q3 and Q5 are turned on. During this stage, the current path of inductor L is: BUSN→L→D2→D1→BUS+. The current of inductor L is released, and the energy stored in inductor L charges the upper half bus capacitor C1, causing the upper half bus voltage to rise.

[0103] When the voltage of the upper half bus is greater than that of the lower half bus, there are also four modes similar to those in the above embodiments, which realize the voltage of the upper half bus decreases and the voltage of the lower half bus increases, thus achieving the balance of the half bus voltage. The embodiments of the present invention will not be described in detail here.

[0104] Of course, in addition to this specific form, the first unidirectional conducting device and the second unidirectional conducting device can also be of other types, and the embodiments of the present invention are not limited here.

[0105] The present invention also provides a balanced bridge circuit, including a power transfer circuit and an inductor;

[0106] The power transfer circuit includes a first switch group, a second switch group, a first unidirectional conducting device, and a second unidirectional conducting device. Both the first and second switch groups are composed of an even number of controllable switches with body diodes connected in series. The body diodes of each controllable switch are arranged from the low-potential end to the high-potential end. The first terminal of the first switch group is connected to the positive terminal of the DC bus. The common point formed by connecting the second terminals of the first and second switch groups is the first circuit point. The second terminal of the second switch group is connected to the negative terminal of the DC bus. An inductor is connected between the first circuit point and the midpoint of the DC bus. The common point formed by connecting the anode of the first unidirectional conducting device and the cathode of the second unidirectional conducting device is the second circuit point. The cathode of the first unidirectional conducting device is connected to the third circuit point, and the anode of the second unidirectional conducting device is connected to the fourth circuit point. The second circuit point is connected to the midpoint of the DC bus. The third circuit point is the midpoint of the first switch group, and the fourth circuit point is the midpoint of the second switch group.

[0107] The balanced bridge circuit uses the control method of the balanced bridge circuit in the aforementioned embodiments.

[0108] For a description of the control method for the balanced bridge circuit provided in the embodiments of the present invention, please refer to the aforementioned embodiments of the control method for the balanced bridge circuit. The embodiments of the present invention are not limited here.

[0109] The present invention also provides a three-level converter device, including a three-level converter device body, a controller, and a balanced bridge circuit as described in the foregoing embodiments connected to the three-level converter device body;

[0110] The three-level converter body is used to perform power conversion between the DC bus and the three-phase power grid under the control of the controller.

[0111] The three-level converter equipment can be of various types, such as a three-phase ANPC topology photovoltaic inverter, like... Figure 13 As shown, Figure 13This is a schematic diagram of a three-level converter device provided by the present invention. The three-level converter device is a three-phase ANPC topology circuit (including six main power switches (Q1 to Q6), six freewheeling diodes (body diodes of Q1 to Q6), and an LC filter circuit). The balance bridge circuit is connected in parallel to the DC bus of the device body. The controller simultaneously collects the DC bus voltage (VP, VN) and the three-phase grid voltage and current signals. When the device body needs to invert the DC power of the photovoltaic system into three-phase AC power and connect it to the grid, the controller controls the main power switches of the device body to operate according to a preset modulation mode to realize DC-AC conversion; at the same time, it monitors VP and VN. If the two are not equal, the controller controls the power transfer circuit of the balance bridge circuit to establish a charging and discharging path, and synchronously realizes voltage balance during the power conversion process.

[0112] For a description of the three-level converter device provided in the embodiments of the present invention, please refer to the aforementioned embodiment of the balanced bridge circuit. The embodiments of the present invention will not be repeated here.

[0113] As an optional embodiment, the three-level converter also includes a switching switch connected to the neutral point of the three-phase power grid and the neutral point of the DC bus, respectively;

[0114] The controller is also used to control the switching switch to close when the load of the three-level converter is a three-phase unbalanced load, and to control the three-level converter body to perform power conversion between the DC bus and the three-phase power grid through sinusoidal pulse width modulation; when the load of the three-level converter is a three-phase balanced load, the switching switch to open, and to control the three-level converter body to perform power conversion between the DC bus and the three-phase power grid through space vector pulse width modulation or discontinuous pulse width modulation.

[0115] in, Figure 13 The "S" in the diagram represents the toggle switch.

[0116] Specifically, considering that three-level converter equipment can optimize efficiency by using different modulation methods under different load types (three-phase balanced load or three-phase unbalanced load) (e.g., SVPWM and DPWM are more efficient under three-phase balanced load, while SPWM control is more precise under unbalanced load), and that the switching between the DC bus midpoint and the three-phase grid midpoint can be achieved through a switching switch to adapt to the needs of different modulation methods, this embodiment of the invention sets a switching switch to connect the three-phase grid midpoint and the DC bus midpoint, and the controller controls the switching on and off and the modulation method switching according to the load type. Thus, the modulation method can be adaptively selected according to the load type, reducing switching losses and improving equipment efficiency under three-phase balanced load, and ensuring output power quality under three-phase unbalanced load; the switching control of the switching switch provides hardware support for different modulation methods and improves the load adaptability of the equipment.

[0117] The switching device can be of various types of bidirectional conducting devices, such as NMOS, relays, or circuit breakers, etc., and the embodiments of the present invention are not limited thereto.

[0118] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. It should also be noted that in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0119] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A control method for a balanced bridge circuit, characterized in that, The balanced bridge circuit includes a power transfer circuit and an inductor. The power transfer circuit includes a first switch group, a second switch group, a first unidirectional conducting device, and a second unidirectional conducting device. Both the first and second switch groups are composed of an even number of controllable switches with body diodes connected in series. The body diodes of each controllable switch are arranged from the low-potential end to the high-potential end. The first terminal of the first switch group is connected to the positive terminal of the DC bus. The common point formed by connecting the second terminals of the first and second switch groups is the first circuit point. The second terminal of the second switch group is connected to the negative terminal of the DC bus. The inductor is connected between the first circuit point and the midpoint of the DC bus. The common point formed by connecting the anode of the first unidirectional conducting device and the cathode of the second unidirectional conducting device is the second circuit point. The cathode of the first unidirectional conducting device is connected to the third circuit point, and the anode of the second unidirectional conducting device is connected to the fourth circuit point. The second circuit point is connected to the midpoint of the DC bus. The third circuit point is the midpoint of the first switch group, and the fourth circuit point is the midpoint of the second switch group. The control method of the balanced bridge circuit includes: When the voltages of the two DC bus capacitors are not equal, the duty cycle of the pulse width modulation signal is determined based on the voltage difference between the upper and lower half of the DC bus capacitors. The non-target switch group is controlled to disconnect, and the controllable switch in the target switch group is controlled according to the pulse width modulation signal in order to balance the voltage of the two DC bus capacitors; The target switch group is a switch group connected in parallel with the DC bus capacitor with a higher voltage, while the non-target switch group is a switch group connected in parallel with the DC bus capacitor with a lower voltage.

2. The control method for the balanced bridge circuit according to claim 1, characterized in that, When the voltages of the two DC bus capacitors are unequal, determining the duty cycle of the pulse width modulation signal based on the voltage difference between the upper and lower half of the DC bus capacitors includes: When the voltages of the two DC bus capacitors are not equal, the inductor current reference value is determined by a closed-loop control algorithm based on the voltage difference between the upper and lower half of the DC bus capacitor. The duty cycle of the pulse width modulation signal is determined by a closed-loop control algorithm based on the current difference between the reference value and the actual value of the inductor current.

3. The control method for the balanced bridge circuit according to claim 2, characterized in that, The controllability of the controllable switches in the target switch group according to the pulse width modulation signal includes: Dead time processing is performed on the pulse width modulation signal; The pulse width modulation signal without dead time processing is applied to one half of the controllable switches in the target switch group closest to the inductor; The pulse width modulation signal, after dead time processing, is applied to the half of the controllable switches in the target switch group that is furthest from the inductor, so that the half of the controllable switches furthest from the inductor in the target switch group is turned off and then turned on relative to the other half of the controllable switches closest to the inductor.

4. The control method for the balanced bridge circuit according to claim 1, characterized in that, The first switch group includes a first controllable switch and a second controllable switch, and the second switch group includes a third controllable switch and a fourth controllable switch; The cathode of the body diode of the first controllable switch serves as the first terminal of the first switch group, the anode of the body diode of the second controllable switch serves as the second terminal of the first switch group, the cathode of the body diode of the third controllable switch serves as the first terminal of the second switch group, and the anode of the body diode of the fourth controllable switch serves as the second terminal of the second switch group.

5. The control method for the balanced bridge circuit according to claim 2, characterized in that, The closed-loop control algorithm includes a proportional-integral (PI) regulation algorithm.

6. The control method for the balanced bridge circuit according to claim 1, characterized in that, The DC bus includes the DC bus of the photovoltaic power generation system.

7. The control method for the balanced bridge circuit according to any one of claims 1 to 6, characterized in that, The balanced bridge circuit also includes a fifth controllable switch and a sixth controllable switch; The body diode of the fifth controllable switch serves as the first unidirectional conduction device, and the body diode of the sixth controllable switch serves as the second unidirectional conduction device. The control of the non-target switch group to disconnect and the controllable switch in the target switch group to control the pulse width modulation signal include: Control the non-target switch group and the non-target switch to disconnect, and control the target switch group and the target switch according to the pulse width modulation signal; Among them, the non-target switch is one of the fifth and sixth controllable switches that is directly connected to the target switch group, and the target switch is one of the fifth and sixth controllable switches that is directly connected to the non-target switch group.

8. A balanced bridge circuit, characterized in that, This includes power transfer circuits and inductors; The power transfer circuit includes a first switch group, a second switch group, a first unidirectional conducting device, and a second unidirectional conducting device. Both the first and second switch groups are composed of an even number of controllable switches with body diodes connected in series. The body diodes of each controllable switch are arranged from the low-potential end to the high-potential end. The first terminal of the first switch group is connected to the positive terminal of the DC bus. The common point formed by connecting the second terminals of the first and second switch groups is the first circuit point. The second terminal of the second switch group is connected to the negative terminal of the DC bus. An inductor is connected between the first circuit point and the midpoint of the DC bus. The common point formed by connecting the anode of the first unidirectional conducting device and the cathode of the second unidirectional conducting device is the second circuit point. The cathode of the first unidirectional conducting device is connected to the third circuit point, and the anode of the second unidirectional conducting device is connected to the fourth circuit point. The second circuit point is connected to the midpoint of the DC bus. The third circuit point is the midpoint of the first switch group, and the fourth circuit point is the midpoint of the second switch group. The balanced bridge circuit is controlled by the balanced bridge circuit control method as described in any one of claims 1 to 7.

9. A three-level converter device, characterized in that, It includes a three-level converter body, a controller, and a balanced bridge circuit as described in claim 8 connected to the three-level converter body; The three-level converter body is used to perform power conversion between the DC bus and the three-phase power grid under the control of the controller.

10. The three-level converter according to claim 9, characterized in that, The three-level converter also includes a switching switch that is connected to the midpoint of the three-phase power grid and the midpoint of the DC bus, respectively; The controller is also used to: when the load of the three-level converter is a three-phase unbalanced load, control the switching switch to close, and control the three-level converter body to perform power conversion between the DC bus and the three-phase power grid through sinusoidal pulse width modulation; when the load of the three-level converter is a three-phase balanced load, control the switching switch to open, and control the three-level converter body to perform power conversion between the DC bus and the three-phase power grid through space vector pulse width modulation or discontinuous pulse width modulation.

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