Semiconductor die and semiconductor wafer

Abstract

A semiconductor die and a semiconductor wafer are provided. The first semiconductor die, the second semiconductor die, and the detector are configured to determine alignment accuracy if the first semiconductor die is bonded to the second semiconductor die. The first test pads of each of the first test pad groups of the first semiconductor die are electrically connected to each other through lines extending in a first direction, and the second test pads of each of the second test pad groups of the second semiconductor die are electrically connected to each other through lines extending in a third direction transverse to the first direction. A detector detects a misalignment between the first semiconductor die and the second semiconductor die based on a current flowing between the first test pads of each first test pad group and the second test pads of each second test pad group.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0127545, filed on September 20, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] In general, the present disclosure relates to semiconductor dies and semiconductor wafers. BACKGROUND

[0003] As semiconductor manufacturing technology has advanced, various processes for manufacturing semiconductor devices have been developed. One of the processes includes a process of implementing one semiconductor device by bonding two or more semiconductor dies or implementing a plurality of semiconductor devices by bonding two or more semiconductor wafers. When two or more semiconductor dies or semiconductor wafers are bonded, the alignment of the semiconductor dies or semiconductor wafers can be a factor for determining yield.

[0004] When the semiconductor dies or semiconductor wafers are not successfully aligned, communication between the semiconductor dies or semiconductor wafers can not be successfully performed. When the communication is not successfully performed, one or more semiconductor devices implemented via the bonding can have a defect, and the yield of the one or more semiconductor devices can decrease.

[0005] Accordingly, a method of determining the accuracy of the alignment of semiconductor dies or semiconductor wafers is desired. Furthermore, when the bonding of the semiconductor dies or semiconductor wafers can be adjusted according to the determined degree of misalignment, the yield of one or more semiconductor devices can be improved. SUMMARY

[0006] According to some embodiments, the present disclosure relates to a semiconductor die including: a first semiconductor die including first test pads, wherein the first test pads are grouped into a plurality of first test pad groups, and the first test pads of each of the plurality of first test pad groups are electrically connected to each other by a line in a first direction; a second semiconductor die including second test pads, wherein the second test pads are grouped into a plurality of second test pad groups, the plurality of second test pad groups are arranged at positions respectively corresponding to positions of the plurality of first test pad groups, and the second test pads of each of the plurality of second test pad groups are electrically connected to each other by a line in a third direction intersecting the first direction; and a detector configured to, when the first semiconductor die and the second semiconductor die are bonded to each other, determine the accuracy of the alignment between the first semiconductor die and the second semiconductor die based on a current flowing between the first test pads of each of the plurality of first test pad groups and the second test pads of each of the plurality of second test pad groups.

[0007] According to some embodiments, the disclosure relates to a semiconductor wafer including: a first semiconductor wafer including a first bonding metal pad and a first test pad, wherein the first bonding metal pad is connected to a cell array structure including a plurality of memory blocks, the first test pad is grouped into a plurality of first test pad groups, and the first test pads of each of the plurality of first test pad groups are electrically connected to each other by a line in a first direction; a second semiconductor wafer including a second bonding metal pad and a second test pad, the second bonding metal pad being in contact with the first bonding metal pad, respectively, wherein the second bonding metal pad is connected to a core peripheral circuit structure including a circuit connected to the plurality of memory blocks, respectively, the second test pad is grouped into a plurality of second test pad groups, the plurality of second test pad groups are arranged at positions corresponding to positions of the plurality of first test pad groups, respectively, and the second test pads of each of the plurality of second test pad groups are electrically connected to each other by a line in a third direction intersecting the first direction; and a detector configured to determine accuracy of alignment between the first semiconductor wafer and the second semiconductor wafer based on a current flowing between the first test pad of each of the plurality of first test pad groups and the second test pad of each of the plurality of second test pad groups when the first semiconductor wafer and the second semiconductor wafer are bonded to each other.

[0008] According to some embodiments, the disclosure relates to a semiconductor wafer including: a first semiconductor wafer including a first bonding metal pad and a first test pad, wherein the first bonding metal pad is connected to a cell array structure including a plurality of memory blocks, the first test pad is grouped into a plurality of first test pad groups, and the first test pads of each of the plurality of first test pad groups are electrically connected to each other by a line in a first direction; a second semiconductor wafer including a second bonding metal pad and a second test pad, the second bonding metal pad being in contact with the first bonding metal pad, respectively, wherein the second bonding metal pad is connected to a core peripheral circuit structure including a circuit connected to the plurality of memory blocks, respectively, the second test pad is grouped into a plurality of second test pad groups, the plurality of second test pad groups are arranged at positions corresponding to positions of the plurality of first test pad groups, respectively, and the second test pads of each of the plurality of second test pad groups are electrically connected to each other by a line in a third direction intersecting the first direction; and a detector configured to determine accuracy of alignment between the first semiconductor wafer and the second semiconductor wafer based on a current flowing between the first test pad of each of the plurality of first test pad groups and the second test pad of each of the plurality of second test pad groups when the first semiconductor wafer and the second semiconductor wafer are bonded to each other.

[0009] According to some embodiments, the disclosure relates to a semiconductor wafer including: a first semiconductor wafer including first semiconductor dies arranged in a first direction and a third direction intersecting the first direction, wherein each of the first semiconductor dies includes a first bonding metal pad connected to a cell array structure including a plurality of memory blocks and a first test pad, the first test pads are grouped into a plurality of first test pad groups, and the first test pads of each of the plurality of first test pad groups are electrically connected to each other by a line in the first direction; a second semiconductor wafer including second semiconductor dies arranged in the first direction and the third direction, wherein each of the second semiconductor dies includes a second bonding metal pad in contact with the first bonding metal pad and a second test pad, respectively, the second bonding metal pad is connected to a core-peripheral circuit structure including a circuit connected to the plurality of memory blocks, respectively, the second test pads are grouped into a plurality of second test pad groups, the plurality of second test pad groups are arranged in positions corresponding to positions of the plurality of first test pad groups, respectively, and the second test pads of each of the plurality of second test pad groups are electrically connected to each other by a line in the third direction intersecting the first direction; and a detector configured to determine accuracy of alignment between the first semiconductor wafer and the second semiconductor wafer when the first semiconductor wafer and the second semiconductor wafer are bonded to each other, based on a current flowing between the first test pads of each of the plurality of first test pad groups and the second test pads of each of the plurality of second test pad groups. BRIEF DESCRIPTION OF DRAWINGS

[0010] Example embodiments will become more fully understood from the detailed description given herein below, and the accompanying drawings, which are given by way of illustration only and thus are not limitative of the present application, and wherein:

[0011] Figure 1 An example of a first semiconductor wafer and a second semiconductor wafer according to some embodiments is illustrated.

[0012] Figure 2 An example of a first die of Figure 1 bonded to a second die according to some embodiments is illustrated.

[0013] Figure 3A An example of a first die of Figure 3B and a second die according to some embodiments is illustrated. Figure 2 An example of an assembly of a first die and a second die of

[0014] Figures 4A to 4C is a view illustrating an example of a state in which a first die of Figure 3A is bonded to a second die according to some embodiments.

[0015] Figures 5A to 5D is a view illustrating an example of a test pad pattern according to some embodiments.

[0016] Figures 6 to 9 This is a view illustrating an example of a semiconductor device according to some embodiments.

[0017] Figure 10 This is a block diagram illustrating an example of a system comprising an electronic device, according to some embodiments. Detailed Implementation

[0018] In the following text, exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0019] In some implementations, semiconductor devices may utilize three-dimensional (3D) stacking technology. 3D stacking technology has been proposed as a solution to overcome scaling limitations by providing numerous advantages, including high capacity, high bandwidth, low power consumption, and low form factor. 3D semiconductor devices may utilize through-silicon vias (TSVs), in which silicon vias pass through each semiconductor die to electrically connect the semiconductor chip. A first and second die may be arranged stacked vertically (see [link to documentation]). Figure 2 A first TSV (Transient Voltage Slab) can be formed through the first die, a first pad (or solder pad) can be formed below the first TSV, and the first pad can be formed on the surface of the substrate of the first die adjacent to the second die. A second TSV can be formed through the second die, a second pad can be formed above the second TSV, and the second pad can be formed on the surface of the substrate of the second die adjacent to the first die. When the first die and the second die are bonded together, the first pad and the second pad can bond together. The bonding of the first die and the second die can be successful when the positions of the first pad and the second pad are accurately aligned (e.g., aligned within an acceptable tolerance range). The bonding of the first die and the second die can fail when the positions of the first pad and the second pad are not accurately aligned (e.g., the positions of the first pad and the second pad are aligned outside an acceptable tolerance range). Hereinafter, a semiconductor wafer is provided for supporting test operations to determine the accuracy of the alignment of the first pad and the second pad, and to adjust the bonding of the first die and the second die based on the determined degree of misalignment.

[0020] Figure 1 Examples of a first semiconductor wafer and a second semiconductor wafer according to some embodiments are shown. Figure 1In particular embodiments, the first semiconductor dies DIE1 can be fabricated on a first semiconductor wafer WAF1 corresponding to the fifth direction within a first boundary line BDL1. The first semiconductor dies DIE1 can be singulated from the first semiconductor wafer WAF1 by cutting the first semiconductor wafer WAF1 along a first horizontal cut line CLH1 corresponding to the first and second directions and a first vertical cut line CLV1 corresponding to the third and fourth directions. The second semiconductor dies DIE2 can be fabricated on a second semiconductor wafer WAF2 corresponding to the fifth direction within a second boundary line BDL2. The second semiconductor dies DIE2 can be singulated from the second semiconductor wafer WAF2 by cutting the second semiconductor wafer WAF2 along a second horizontal cut line CLH2 corresponding to the first and second directions and a second vertical cut line CLV2 corresponding to the third and fourth directions.

[0021] As indicated by the cross CRS in Figure 1 The first semiconductor wafer WAF1 and the second semiconductor wafer WAF2 can be bonded to each other to realize a plurality of semiconductor devices as indicated by the cross CRS in

[0022] According to some embodiments, the plurality of semiconductor devices can include memory devices and / or logic semiconductor devices. For example, the memory devices can include volatile memory devices such as dynamic random access memory (DRAM), static random access memory (SRAM), mobile DRAM, double data rate (DDR) synchronous DRAM (SDRAM), low power DDR (LPDDR) SDRAM, graphics DDR (GDDR) SDRAM, rambus DRAM (RDRAM), and high bandwidth memory (HBM) devices. In some embodiments, the memory devices can include non-volatile memory devices such as electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), nanoscale floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), and the like. The logic semiconductor devices can include central processing units (CPUs), graphics processing units (GPUs), neural processing units (NPUs), application processors (APs), system on chips (SoCs), and the like. The logic semiconductor devices can be realized as application specific integrated circuits (ASICs), SoCs, and the like.

[0023] Figure 2 An example of a first die being bonded to a second die according to some embodiments is shown. Figure 1 An example of a first die being bonded to a second die according to some embodiments is shown. Figure 1 In Figure 2 In order to be bonded to the second die DIE2, the first die DIE1 can be rotated 180 degrees with respect to the first direction and the second direction. Accordingly, the coordinate system of the first die DIE1 and the coordinate system of the second die DIE2 can be indicated separately from each other. The first die DIE1 can include first pads PAD1 arranged on the upper surface in the fifth direction. The first pads PAD1 can be arranged in the first direction and the third direction at equal intervals. The second die DIE2 can include second pads PAD2 arranged on the upper surface in the fifth direction. The second pads PAD2 can also be arranged in the first direction and the third direction at equal intervals.

[0024] When the first semiconductor wafer WAF1 is bonded to the second semiconductor wafer WAF2, the first pads PAD1 of the first die DIE1 can be bonded (sometimes referred to as bonded) to the second pads PAD2 of the second die DIE2. When the positions of the first pads PAD1 are accurately aligned (e.g., aligned within a tolerance range) with the positions of the second pads PAD2, the bonding can be successful. When the positions of the first pads PAD1 are not accurately aligned (e.g., the positions of the first pads PAD1 are aligned outside the tolerance range from the positions of the second pads PAD2), the bonding can be unsuccessful.

[0025] The semiconductor dies and the semiconductor wafer can support a test operation for determining alignment accuracy. The semiconductor dies and the semiconductor wafer can provide test pads for the alignment test operation. By performing the alignment test operation, the semiconductor dies and the semiconductor wafer can be easily and accurately aligned and bonded.

[0026] Figure 3A In Figure 3B An example of a first die being bonded to a second die according to some embodiments is shown. Figure 2 An example of an assembly of a first die DIE1 and a second die DIE2 according to some embodiments is shown. Figure 3A Test pads (i.e., first to sixth test pads 411, 412, 421, 422, 441, 442, 461, 462, 481, 482, 491, 492, 511, 512, 521, 522, 541, 542, 561, 562, 581, 582, 591, and 592) for determining alignment accuracy when the first pads PAD1 of the first die DIE1 are bonded to the second pads PAD2 of the second die DIE2 are shown. Figure 3B An example of a first die being bonded to a second die according to some embodiments is shown. Figure 3Athe first to sixth test pads 411, 412, 421, 422, 441, 442, 461, 462, 481, 482, 491, 492, 511, 512, 521, 522, 541, 542, 561, 562, 581, 582, 591, and 592 of the first to sixth test pad groups 410, 420, 440, 460, 480, and 490 of the first test pad pattern 400.

[0027] In Figure 3A the first die DIE1 can include a first test pad pattern 400, and the second die DIE2 can include a second test pad pattern 500. The first test pad pattern 400 can include a plurality of test pad groups (i.e., first to sixth test pad groups 410, 420, 440, 460, 480, and 490), and the first to sixth test pads 411, 412, 421, 422, 441, 442, 461, 462, 481, 482, 491, and 492 are grouped into the plurality of test pad groups. The second test pad pattern 500 can include a plurality of test pad groups (i.e., first to sixth test pad groups 510, 520, 540, 560, 580, and 590), and the first to sixth test pads 511, 512, 521, 522, 541, 542, 561, 562, 581, 582, 591, and 592 are grouped into the plurality of test pad groups. The first to sixth test pad groups 410, 420, 440, 460, 480, and 490 of the first test pad pattern 400 can be respectively arranged at positions respectively corresponding to positions of the first to sixth test pad groups 510, 520, 540, 560, 580, and 590 of the second test pad pattern 500.

[0028] The first test pad group 410 of the first test pad pattern 400 can include the first and second test pads 411 and 412, and the first and second test pads 411 and 412 can be electrically connected to each other by a wire 413. The first test pad group 510 of the second test pad pattern 500 can include the first and second test pads 511 and 512, and the first test pad 511 can be electrically connected to each other by a wire 513, and the second test pad 512 can be electrically connected to each other by a wire 514. The first and second test pads 411 and 412 of the first die DIE1 can be bonded to the first and second test pads 511 and 512 of the second die DIE2. The first test pad groups 410 and 510 can be provided to have a shape having no misalignment (i.e., a 0% misalignment shape) between the first and second test pads 411 and 412 of the first die DIE1 and the first and second test pads 511 and 512 of the second die DIE2. Accordingly, in Figure 3B when the first die DIE1 is bonded to the second die DIE2, the first and second test pads 411 and 412 can be bonded to the first and second test pads 511 and 512, respectively, with a 100% bonding area.

[0029] The second test pad group 420 of the first test pad pattern 400 may include second test pads 421 and 422, and the second test pads 421 and 422 may be electrically connected to each other via line 423. The second test pad group 520 of the second test pad pattern 500 may include second test pads 521 and 522, and the second test pads 521 may be electrically connected to each other via line 523, and the second test pads 522 may be electrically connected to each other via line 524. The second test pads 421 and 422 of the first die DIE1 may be coupled to the second test pads 521 and 522 of the second die DIE2. The second test pad groups 420 and 520 may be configured to have a 20% misalignment between the second test pads 421 and 422 of the first die DIE1 and the second test pads 521 and 522 of the second die DIE2. Therefore, in Figure 3B In the process, when the first die DIE1 is bonded to the second die DIE2, the second test pads 421 and 422 can be bonded to the second test pads 521 and 522 with 80% of the bonding area, respectively.

[0030] The third test pad group 440 of the first test pad pattern 400 may include third test pads 441 and 442, and the third test pads 441 and 442 may be electrically connected to each other via line 443. The third test pad group 540 of the second test pad pattern 500 may include third test pads 541 and 542, and the third test pads 541 may be electrically connected to each other via line 543, and the third test pads 542 may be electrically connected to each other via line 544. The third test pads 441 and 442 of the first die DIE1 may be coupled to the third test pads 541 and 542 of the second die DIE2. The third test pad groups 440 and 540 may be configured to have a 40% misalignment between the third test pads 441 and 442 of the first die DIE1 and the third test pads 541 and 542 of the second die DIE2. Therefore, in Figure 3B In the process, when the first die DIE1 is bonded to the second die DIE2, the third test pads 441 and 442 can be bonded to the third test pads 541 and 542 with 60% of the bonding area, respectively.

[0031] The fourth test pad group 460 of the first test pad pattern 400 may include fourth test pads 461 and 462, and the fourth test pads 461 and 462 are electrically connected to each other via line 463. The fourth test pad group 560 of the second test pad pattern 500 may include fourth test pads 561 and 562, and the fourth test pads 561 are electrically connected to each other via line 563, and the fourth test pads 562 are electrically connected to each other via line 564. The fourth test pads 461 and 462 of the first die DIE1 may be coupled to the fourth test pads 561 and 562 of the second die DIE2. The fourth test pad groups 460 and 560 may be configured to have a 60% misalignment between the fourth test pads 461 and 462 of the first die DIE1 and the fourth test pads 561 and 562 of the second die DIE2. Therefore, in Figure 3B In the process, when the first die DIE1 is bonded to the second die DIE2, the fourth test pads 461 and 462 can be bonded to the fourth test pads 561 and 562 with 40% of the bonding area, respectively.

[0032] The fifth test pad group 480 of the first test pad pattern 400 may include fifth test pads 481 and 482, and the fifth test pads 481 and 482 are electrically connected to each other via line 483. The fifth test pad group 580 of the second test pad pattern 500 may include fifth test pads 581 and 582, and the fifth test pads 581 are electrically connected to each other via line 583, and the fifth test pads 582 are electrically connected to each other via line 584. The fifth test pads 481 and 482 of the first die DIE1 may be coupled to the fifth test pads 581 and 582 of the second die DIE2. The fifth test pad groups 480 and 580 may be configured to have an 80% misalignment between the fifth test pads 481 and 482 of the first die DIE1 and the fifth test pads 581 and 582 of the second die DIE2. Therefore, in Figure 3B In the process, when the first die DIE1 is bonded to the second die DIE2, the fifth test pads 481 and 482 can be bonded to the fifth test pads 581 and 582 respectively with 20% of the bonding area.

[0033] The sixth test pad group 490 of the first test pad pattern 400 may include sixth test pads 491 and 492, and the sixth test pads 491 and 492 are electrically connected to each other via line 493. The sixth test pad group 590 of the second test pad pattern 500 may include sixth test pads 591 and 592, and the sixth test pads 591 are electrically connected to each other via line 593, and the sixth test pads 592 are electrically connected to each other via line 594. The sixth test pads 491 and 492 of the first die DIE1 may be coupled to the sixth test pads 591 and 592 of the second die DIE2. The sixth test pad groups 490 and 590 may be configured to have a 100% misaligned shape between the sixth test pads 491 and 492 of the first die DIE1 and the sixth test pads 591 and 592 of the second die DIE2. Therefore, in Figure 3B In the process, when the first die DIE1 is bonded to the second die DIE2, the sixth test pads 491 and 492 can be bonded to the sixth test pads 591 and 592 with 0% bonding area respectively. That is to say, the sixth test pads 491, 492, 591 and 592 can be in a disconnected state.

[0034] Regarding the first test pad pattern 400 and the second test pad pattern 500, an example is described as follows: In this example, the first to sixth test pad groups 410 and 510, 420 and 520, 440 and 540, 460 and 560, 480 and 580, and 490 and 590 are designed to have misaligned shapes of 0%, 20%, 40%, 60%, 80%, and 100% respectively (that is, the corresponding two of the misaligned shapes are misaligned). The difference between them is 20%, so that the bonding areas of the first test pad to the sixth test pads 411, 412, 511 and 512, 421, 422, 521 and 522, 441, 442, 541 and 542, 461, 462, 561 and 562, 481, 482, 581 and 582, and 491, 492, 591 and 592 can be 100%, 80%, 60%, 40%, 20% and 0%, respectively. However, the examples are given only to aid in understanding this disclosure and are not intended to limit this disclosure. According to some embodiments, the first test pad pattern 400 and the second test pad pattern 500 may be designed to have misaligned shapes, wherein the difference between corresponding two misaligned shapes is further reduced (e.g., 1%, 5%, or 10%), such that the mating areas of the first to sixth test pads 411, 412, 511 and 512, 421, 422, 521 and 522, 441, 442, 541 and 542, 461, 462, 561 and 562, 481, 482, 581 and 582, and 491, 492, 591 and 592 can be further specified. This indicates that the accuracy of alignment can be increased according to the accurate misaligned shapes. According to some embodiments, the difference between corresponding two misaligned shapes is not limited to the differences exemplified above, and may be any other difference.

[0035] Figures 4A to 4C It is used to describe according to some implementation methods Figure 3A A view of the state of the first die DIE1 combined with the second die DIE2. Figure 4A This shows the state in which the fifth test pads 481, 482, 581, and 582 of the fifth test pad groups 480 and 580 are accurately aligned when the first die DIE1 is bonded to the second die DIE2. Figure 4B The fifth test pads 481, 482, 581, and 582 of the fifth test pad groups 480 and 580 are shown to be misaligned. Figure 4C This is the circuit diagram of detector 585, which is configured to detect whether the fifth test pads 481, 482, 581 and 582 of the fifth test pad groups 480 and 580 are misaligned.

[0036] exist Figure 3A and Figure 4AIn this configuration, the fifth test pads 481 and 482 of the fifth test pad group 480 of the first die DIE1 can be bonded to the fifth test pads 581 and 582 of the fifth test pad group 580 of the second die DIE2 with an 80% misalignment. Therefore, the fifth test pads 481, 482, 581, and 582 can be bonded to each other with a 20% bonding area and can be electrically connected to each other (i.e., short-circuited) via wires 483, 583, and 584.

[0037] exist Figure 4B In, with Figure 4A In contrast, the fifth test pads 481 and 482 of the fifth test pad group 480 of the first die DIE1 may not be coupled to the fifth test pads 581 and 582 of the fifth test pad group 580 of the second die DIE2. This indicates that the positions of the fifth test pads 481 and 482 of the first die DIE1 are misaligned with the positions of the fifth test pads 581 and 582 of the second die DIE2 by 20% or more, thus resulting in a 100% misalignment and an electrically disconnected state.

[0038] exist Figure 4C In this configuration, detector 585 may be disposed in the second die DIE2 and electrically connected to the fifth test pad 581 of the second die DIE2. Detector 585 may include inverter 501 and transmission gate (sometimes referred to as switch) 502. Inverter 501 is configured to receive a select signal SELECT#, and transmission gate 502 is configured to supply a power supply voltage VEXT_P to the fifth test pad 581 of the fifth test pad group 580 in response to the select signal SELECT# and an output signal from inverter 501. The select signal SELECT# may command the detection of misalignment with respect to each of the first to sixth test pad groups 410 and 510, 420 and 520, 440 and 540, 460 and 560, 480 and 580, and 490 and 590. Figure 4C The select signal SELECT# can be configured to command the detection of misalignment of the fifth test pads 481, 482, 581, and 582 in the fifth test pad groups 480 and 580. The power supply voltage VEXT_P can be the power supply voltage of the second die DIE2.

[0039] exist Figure 4A In this configuration, detector 585 can be electrically connected to the fifth test pad 581 in the fifth test pad group 580, and the ground voltage line can be connected to the fifth test pad 582. When the select signal SELECT# is activated to a logic high level, detector 585 can provide the power supply voltage VEXT_P to the fifth test pad 581. Figure 4AThe fifth test pads 481, 482, 581, and 582 can be connected to each other and electrically connected (i.e., short-circuited) via lines 483, 583, and 584, and therefore, detector 585 can detect the current flowing from the power supply voltage VEXT_P to the ground voltage VSS. Thus, detector 585 can determine that the fifth test pads 481, 482, 581, and 582 of the fifth test pad groups 480 and 580 can be aligned with the originally designed 80% misaligned shape.

[0040] exist Figure 4B In the fifth test pad groups 480 and 580, the fifth test pads 481, 482, 581, and 582 may be 100% misaligned (i.e., electrically disconnected), and the detector 585 may be unable to detect the current flowing from the power supply voltage VEXT_P to the ground voltage VSS. Therefore, the detector 585 can determine that the fifth test pads 481, 482, 581, and 582 of the fifth test pad groups 480 and 580 may be further misaligned by 20% or more from the initially designed 80% misaligned shape, so that the misalignment is 100% and the device is electrically disconnected. Here, the detector 585 can determine that the bonding of the first die DIE1 and the second die DIE2 may have about 20% misalignment, and can correct about 20% of the misalignment for the first die DIE1 to be bonded to the second die DIE2.

[0041] Figures 5A to 5D These are views used to describe first test pad patterns 400a to 400d and second test pad patterns 500a to 500d according to some embodiments. In the following, subscripts attached to the same reference numerals in different figures (e.g., a in 400a and b in 400b) are used to distinguish multiple components having substantially the same or identical functions from one another. Descriptions of... Figure 3A The aspects of the first test pad pattern 400 and the second test pad pattern 500 are the same as those of the first test pad pattern 400a to 400d and the second test pad pattern 500a to 500d.

[0042] exist Figure 5A In China, combined Figure 3AThe first test pad pattern 400a of the first die DIE1 may include a first test pad group to a sixth test pad group 610, 620, 640, 660, 680 and 690, and the second test pad pattern 500a of the second die DIE2 may include a first test pad group to a sixth test pad group 610a, 620a, 640a, 660a, 680a and 690a. In the first test pad pattern 400a and the second test pad pattern 500a, the first test pad groups 610 and 610a, the second test pad groups 620 and 620a, the third test pad groups 640 and 640a, the fourth test pad groups 660 and 660a, the fifth test pad groups 680 and 680a, and the sixth test pad groups 690 and 690a can be designed to have misaligned shapes of 0%, 20%, 40%, 60%, 80%, and 100% respectively relative to the origin in a first direction (that is, the difference between the corresponding two misaligned shapes is 20%). In one example, the size of the misaligned pattern corresponding to the misaligned shape can be increased in one direction (e.g., by way of example only, one of the first, second, third, and fourth directions), and the bonding area between the test pads of the first test pad pattern 400a and the corresponding test pads of the second test pad pattern 500a can be reduced. The first test pad pattern 400a and the second test pad pattern 500a can be referred to as the first test pattern TP1.

[0043] The first test pad group 610 of the first test pad pattern 400a may include first test pads 611 and 612, and the first test pads 611 and 612 may be electrically connected to each other via line 613. The first test pad group 610a of the second test pad pattern 500a may include first test pads 611a and 612a, and the first test pads 611a may be electrically connected to each other via line 613a, and the first test pads 612a may be electrically connected to each other via line 614a. The first test pad groups 610 and 610a may be configured to have a non-misaligned shape (i.e., a 0% misaligned shape) in a first direction relative to the origin between the first test pads 611 and 612 of the first die DIE1 and the first test pads 611a and 612a of the second die DIE2. Detector 601 may be electrically connected to the first test pad 611a of the first test pads 611a and 612a of the second die DIE2, and ground voltage line may be connected to the first test pad 612a. The detector 601 can detect whether the first test pads 611 and 612 of the first test pad group 610 are misaligned with the first test pads 611a and 612a of the first test pad group 610a.

[0044] The second test pad group 620 of the first test pad pattern 400a may include second test pads 621 and 622, and the second test pads 621 and 622 may be electrically connected to each other via line 623. The second test pad group 620a of the second test pad pattern 500a may include second test pads 621a and 622a, and the second test pads 621a may be electrically connected to each other via line 623a, and the second test pads 622a may be electrically connected to each other via line 624a. The second test pad groups 620 and 620a may be configured to have a 20% misalignment in a first direction relative to the origin between the second test pads 621 and 622 of the first die DIE1 and the second test pads 621a and 622a of the second die DIE2. Detector 602 may be electrically connected to the second test pad 621a of the second test pads 621a and 622a of the second die DIE2, and a ground voltage line may be connected to the second test pad 622a. Detector 602 can detect whether the second test pads 621 and 622 of the second test pad group 620 are misaligned with the second test pads 621a and 622a of the second test pad group 620a.

[0045] The third test pad group 640 of the first test pad pattern 400a may include third test pads 641 and 642, and the third test pads 641 and 642 may be electrically connected to each other via line 643. The third test pad group 640a of the second test pad pattern 500a may include third test pads 641a and 642a, and the third test pads 641a may be electrically connected to each other via line 643a, and the third test pads 642a may be electrically connected to each other via line 644a. The third test pad groups 640 and 640a may be configured to have a 40% misalignment in a first direction relative to the origin between the third test pads 641 and 642 of the first die DIE1 and the third test pads 641a and 642a of the second die DIE2. A detector 604 may be electrically connected to the third test pad 641a of the third test pads 641a and 642a of the second die DIE2, and a ground voltage line may be connected to the third test pad 642a. The detector 604 can detect whether the third test pads 641 and 642 of the first test pad group 640 are misaligned with the third test pads 641a and 642a of the first test pad group 640a.

[0046] The fourth test pad group 660 of the first test pad pattern 400a may include fourth test pads 661 and 662, and the fourth test pads 661 and 662 may be electrically connected to each other via line 663. The fourth test pad group 660a of the second test pad pattern 500a may include fourth test pads 661a and 662a, and the fourth test pads 661a may be electrically connected to each other via line 663a, and the fourth test pads 662a may be electrically connected to each other via line 664a. The fourth test pad groups 660 and 660a may be configured to have a 60% misalignment in a first direction relative to the origin between the fourth test pads 661 and 662 of the first die DIE1 and the fourth test pads 661a and 662a of the second die DIE2. A detector 606 may be electrically connected to the fourth test pad 661a of the fourth test pads 661a and 662a of the second die DIE2, and a ground voltage line may be connected to the fourth test pad 662a. Detector 606 can detect whether the fourth test pads 661 and 662 of the fourth test pad group 660 are misaligned with the fourth test pads 661a and 662a of the fourth test pad group 660a.

[0047] The fifth test pad group 680 of the first test pad pattern 400a may include fifth test pads 681 and 682, and the fifth test pads 681 and 682 may be electrically connected to each other via line 683. The fifth test pad group 680a of the second test pad pattern 500a may include fifth test pads 681a and 682a, and the fifth test pads 681a may be electrically connected to each other via line 683a, and the fifth test pads 682a may be electrically connected to each other via line 684a. The fifth test pad groups 680 and 680a may be configured to have an 80% misalignment in a first direction relative to the origin between the fifth test pads 681 and 682 of the first die DIE1 and the fifth test pads 681a and 682a of the second die DIE2. A detector 608 may be electrically connected to the fifth test pad 681a of the fifth test pads 681a and 682a of the second die DIE2, and a ground voltage line may be connected to the fifth test pad 682a. Detector 608 can detect whether the fifth test pads 681 and 682 of the fifth test pad group 680 are misaligned with the fifth test pads 681a and 682a of the fifth test pad group 680a.

[0048] The sixth test pad group 690 of the first test pad pattern 400a may include sixth test pads 691 and 692, and the sixth test pads 691 and 692 may be electrically connected to each other via line 693. The sixth test pad group 690a of the second test pad pattern 500a may include sixth test pads 691a and 692a, and the sixth test pads 691a may be electrically connected to each other via line 693a, and the sixth test pads 692a may be electrically connected to each other via line 694a. The sixth test pad groups 690 and 690a may be configured to have a 100% misalignment shape between the sixth test pads 691 and 692 of the first die DIE1 and the sixth test pads 691a and 692a of the second die DIE2 in a first direction relative to the origin. Detector 609 may be electrically connected to the sixth test pad 691a of the sixth test pads 691a and 692a of the second die DIE2, and ground voltage line may be connected to the sixth test pad 692a. Detector 609 can detect whether the sixth test pads 691 and 692 of the sixth test pad group 690 are misaligned with the sixth test pads 691a and 692a of the sixth test pad group 690a.

[0049] exist Figure 5B The second test pattern TP2, including the first test pad pattern 400b of the first die DIE1 and the second test pad pattern 500b of the second die DIE2, is... Figure 5A The difference in the first test pattern TP1 may be that the first test pad group 610 and 610b, the second test pad group 620 and 620b, the third test pad group 640 and 640b, the fourth test pad group 660 and 660b, the fifth test pad group 680 and 680b, and the sixth test pad group 690 and 690b may be designed to have misaligned shapes of 0%, 20%, 40%, 60%, 80%, and 100% respectively in the second direction relative to the origin (that is, the difference between the corresponding two misaligned shapes is 20%).

[0050] exist Figure 5C The third test pattern TP3, including the first test pad pattern 400c of the first die DIE1 and the second test pad pattern 500c of the second die DIE2, is... Figure 5A The first test pattern TP1 may differ in that: the first test pad group 610 and 610c, the second test pad group 620 and 620c, the third test pad group 640 and 640c, the fourth test pad group 660 and 660c, the fifth test pad group 680 and 680c, and the sixth test pad group 690 and 690c may be designed to have misaligned shapes of 0%, 20%, 40%, 60%, 80%, and 100% respectively in the third direction relative to the origin (that is, the difference between the corresponding two misaligned shapes is 20%).

[0051] exist Figure 5DThe fourth test pattern TP4, including the first test pad pattern 400d of the first die DIE1 and the second test pad pattern 500d of the second die DIE2, is... Figure 5A The difference in the first test pattern TP1 may be that the first test pad group 610 and 610d, the second test pad group 620 and 620d, the third test pad group 640 and 640d, the fourth test pad group 660 and 660d, the fifth test pad group 680 and 680d, and the sixth test pad group 690 and 690d may be designed to have misaligned shapes of 0%, 20%, 40%, 60%, 80%, and 100% respectively in the fourth direction relative to the origin (that is, the difference between the corresponding two misaligned shapes is 20%).

[0052] Figures 6 to 9 This is a view used to describe examples of semiconductor devices according to some implementation methods. Figure 6 , Figure 7 and Figure 9 Depicting it Figure 2 The structure of the memory device 10 in which the first die DIE1 and the second die DIE2 are combined with each other. Figure 8 It is along Figure 7 The image shows a cross-sectional view of the memory device 10 taken along lines X1-X2. The memory device 10 may include a DRAM, which includes a plurality of memory cells, each memory cell including a vertical channel transistor and a capacitor. For ease of understanding, elements described as upper / lower surfaces, upper / lower portions, above / below, right / left, etc., are based on the orientation shown in the referenced figures. Thus, depending on the orientation shown in the figures, the same surface may be referred to as either the upper surface or the lower surface.

[0053] exist Figure 6 In this memory device 10, a cell array structure (CAS) and a core peripheral circuit structure (CPS) stacked on top of each other in a vertical direction (fifth direction) may be included. The cell array structure (CAS) may include a core peripheral circuit structure (CPS) formed on an upper substrate (e.g., Figure 8 The memory cell array 22 on the 320) and the core peripheral circuit structure CPS may include a memory cell array 22 formed on the lower substrate (e.g., Figure 8 The core peripheral circuitry on the 310) is described. The CAS cell array structure can include multiple memory blocks (i.e., memory blocks BLK1, BLK2, ..., and BLKi, where i is a positive integer). The multiple memory blocks BLK1, BLK2, ..., and BLKi can include multiple memory cells, each including a vertical channel transistor and a capacitor. Each memory cell can be composed of a cell transistor and a cell capacitor, and the cell transistor can be implemented as a cell structure CS and the cell capacitor can be implemented as a reference. Figure 8The capacitor structure DSP described. The core peripheral circuit of the core peripheral circuit structure CPS can be formed by including semiconductor devices (such as transistors) and patterns for interconnecting semiconductor devices on a lower substrate. The core peripheral circuit may include peripheral circuitry, including a row decoder and a sense amplifier. The row decoder may include word line driver circuitry configured to decode a row address and select a word line WL corresponding to the row address and apply a word line drive voltage having a high voltage level to the selected word line WL. The sense amplifier may be configured to sense the voltage level of the bit line BL corresponding to the column address in the bit line BL of the memory cell connected to the selected word line WL. Patterns for electrically connecting the word lines WL and bit lines BL of the memory cell array 22 to the core peripheral circuitry formed in the core peripheral circuit structure CPS (e.g., Figure 8 (The bonding metal pads 301 and 302).

[0054] exist Figure 7 In the CAS cell array structure, the first memory block BLK1 and the second memory block BLK2 may be included, and refer to Figures 5A to 5D The described first test pad patterns 400a, 400b, 400c, and 400d can be arranged between the first memory block BLK1 and the second memory block BLK2. The core peripheral circuit structure CPS can include a first word line driver circuit SWD1 and a first bit line sense amplifier circuit BLSA1, respectively connected to the word line WL and bit line BL of the first memory block BLK1, in the region superimposed with the first memory block BLK1; and can include a second word line driver circuit SWD2 and a second bit line sense amplifier circuit BLSA2, respectively connected to the word line WL and bit line BL of the second memory block BLK2, in the region superimposed with the second memory block BLK2. (Refer to...) Figures 5A to 5D The second test pad patterns 500a, 500b, 500c and 500d described herein may be arranged between the first word line driver circuit SWD1 and the first bit line sense amplifier circuit BLSA1 and the second word line driver circuit SWD2 and the second bit line sense amplifier circuit BLSA2.

[0055] exist Figure 8In this configuration, the core peripheral circuit structure (CPS) may include a lower substrate 310, an interlayer insulating layer 315, a plurality of circuit elements (i.e., first circuit element 312a and second circuit element 312b) formed on the lower substrate 310, first metal layers 314a and 314b respectively connected to the plurality of circuit elements (i.e., first circuit element 312a and second circuit element 312b), second metal layers 316a and 316b formed on the first metal layers 314a and 314b, and a bonding metal pad 301 formed on the uppermost metal layer of the core peripheral circuit structure (CPS). According to some embodiments, the first metal layers 314a and 314b may include tungsten (W) with relatively high resistance, the second metal layers 316a and 316b may include copper (Cu) with relatively low resistance, and the bonding metal pad 301 may include Cu. According to some embodiments, the bonding metal pad 301 may include aluminum (Al) or W.

[0056] In this disclosure, only the first metal layers 314a and 314b and the second metal layers 316a and 316b are shown and described. However, this disclosure is not limited thereto, and one or more metal layers may be further formed on the second metal layers 316a and 316b. At least one of the one or more metal layers formed over the second metal layers 316a and 316b may include aluminum or the like, which has a lower resistance than Cu included in the second metal layers 316a and 316b. An interlayer insulating layer 315 may be disposed on the lower substrate 310 to cover a plurality of circuit elements (i.e., the first circuit element 312a and the second circuit element 312b), the first metal layers 314a and 314b, and the second metal layers 316a and 316b, and may include an insulating material (such as silicon oxide, silicon nitride, etc.).

[0057] Multiple circuit elements (i.e., first circuit element 312a and second circuit element 312b) may be connected to at least one of the circuit elements included in the peripheral circuitry. For ease of explanation, first circuit element 312a may indicate a transistor included in the first word line driver circuit SWD1, and second circuit element 312b may indicate a transistor included in the first word line sense amplifier circuit BLSA1.

[0058] In memory device 10, bit lines BL may be arranged on an upper substrate 320 and separated from each other in a first direction. In one example, layer 325 may be located between the bit lines BL and the upper substrate 320. The upper substrate 320 may refer to an element corresponding to the lower substrate 310. According to some embodiments, the upper substrate 320 may be referred to as a plate or conductive plate. The bit lines BL may be separated from each other in the first direction and may extend upward in a third direction intersecting (crossing) the first direction. Active patterns AP may be alternately arranged on each of the bit lines BL in the third direction. The active patterns AP may be separated from each other by a certain distance in the first direction. That is, the active patterns AP may be arranged in two dimensions in the intersecting first direction and the third direction. According to some embodiments, multiple word lines WL, multiple bit lines BL, and multiple active patterns AP may form multiple vertical channel transistors.

[0059] Each of the active patterned APs may have a length in a first direction, a width in a third direction, and a height in a fifth direction perpendicular to the upper substrate 320. Each of the active patterned APs may have substantially the same width. Each of the active patterned APs may have an upper surface and a lower surface opposite to each other in the fifth direction. For example, the lower surface of the active patterned AP may contact the bit line BL. Each of the active patterned APs may include a source region adjacent to the bit line BL, a drain region adjacent to the contact pattern BC, and a channel region between the source region and the drain region. During operation of the memory device 10, the channel region of the active patterned AP may be controlled by the word line WL and the back gate electrode BG. The active patterned AP may include, for example, single-crystal silicon (Si) to improve leakage current characteristics during operation of the memory device 10.

[0060] The back gate electrodes BG can be arranged on the bit line BL and separated from each other by a specific distance in the third direction. The back gate electrodes BG can extend across the bit line BL in a first direction. Each of the back gate electrodes BG can be arranged between active patterns AP that are adjacent to each other in the third direction. A first active pattern 191 can be arranged on one side of each of the back gate electrodes BG, and a second active pattern 192 can be arranged on the other side. The back gate electrodes BG can have a smaller height than the active patterns AP in the vertical direction (i.e., the fifth direction). The back gate electrodes BG can receive a negative voltage during operation of the memory device 10 and can increase the threshold voltage of the vertical channel transistor. Therefore, according to the fine structure of the vertical channel transistor, the degradation of leakage current characteristics due to the reduction of the threshold voltage can be prevented.

[0061] A first insulating pattern 111 may be disposed between active patterns AP that are adjacent to each other in a third direction. The first insulating pattern 111 may extend parallel to the back gate electrode BG in a first direction. A back gate insulating layer 113 may be disposed between each back gate electrode BG and each active pattern AP, and between the back gate electrode BG and the first insulating pattern 111. The back gate insulating layer 113 may include a vertical portion covering two side surfaces of the back gate electrode BG and a horizontal portion connecting the vertical portions. The horizontal portion of the back gate insulating layer 113 may contact the pattern BC closer to the bit line BL, and may cover the upper surface of the back gate electrode BG. A back gate cover pattern 115 may be disposed between the bit line BL and the back gate electrode BG. The back gate cover pattern 115 may include an insulating material, and the lower surface of the back gate cover pattern 115 may contact the bit line BL. The back gate cover pattern 115 may be disposed between the vertical portions of the back gate insulating layer 113.

[0062] Word lines WL may extend on bit lines BL in a first direction and may be arranged alternately in a third direction. A first word line 181 within the word lines WL may be arranged on one side of a first active pattern 191, and a second word line 182 within the word lines WL may be arranged on the other side of a second active pattern 192. A portion of the first word line 181 may be arranged between adjacent first active patterns 191 in the first direction, and a portion of the second word line 182 may be arranged between adjacent second active patterns 192 in the first direction.

[0063] The word line WL can be vertically separated from the bit line BL and the contact pattern BC. From a vertical perspective, the word line WL can be positioned between the bit line BL and the contact pattern BC. Adjacent word lines WL can have sidewalls facing each other. The word line WL can have a lower height in the vertical direction than the active pattern AP. The height of the word line WL can be the same as or greater than the height of the back gate electrode BG in the third direction.

[0064] A gate insulating layer 160 may be disposed between a word line WL and an active pattern AP. The gate insulating layer 160 may extend parallel to the word line WL in a first direction. The gate insulating layer 160 may cover a side surface of the first active pattern 191 and another surface (e.g., the other side surface) of the second active pattern 192. The gate insulating layer 160 may have substantially the same thickness. A second insulating pattern 141 may be disposed between the gate insulating layer 160 and a contact pattern BC. For example, the second insulating pattern 141 may comprise silicon oxide. A first etch stop layer 131 and a second etch stop layer 133 may be disposed between the active pattern AP and the second insulating pattern 141.

[0065] The word lines WL can be separated from each other by a third insulating pattern 151 on the bit line BL. The third insulating pattern 151 can extend between the word lines WL in a first direction. A first cover layer 153 can be disposed between the third insulating pattern 151 and the word lines WL. The first cover layer 153 can have substantially the same thickness. The third insulating pattern 151 may include a third vertical pattern 151A and a third horizontal pattern 151B.

[0066] The contact pattern BC can penetrate the third etch stop layer 210 and the interlayer insulating layer 220, and can contact the active pattern AP respectively. In other words, the contact pattern BC can contact the drain region of the active pattern AP respectively. The lower width of the contact pattern BC can be greater than the upper width of the contact pattern BC. Adjacent contact patterns BC can be separated from each other by the insulating pattern 230. Each of the contact patterns BC can have various shapes (such as circular, elliptical, rectangular, square, rhomboid, hexagonal, etc. in planar view). A landing pad (or mating pad) LP can be arranged on the contact pattern BC.

[0067] The insulating pattern 230 can be arranged between the landing pads LP. In a planar view, the landing pads LP can be arranged in a matrix shape in a first direction and a third direction. The upper surface of the landing pads LP can be substantially coplanar with the upper surface of the insulating pattern 230. A fourth etch stop layer 240 can be formed on the insulating pattern 230.

[0068] Data storage pattern DSPs can be arranged on the landing pad LP. The data storage pattern DSPs can be electrically connected to the active pattern APs. The data storage pattern DSPs can be arranged in a matrix shape in a first direction and a third direction. The data storage pattern DSPs can be fully or partially stacked with the landing pad LP. The data storage pattern DSPs can contact the entire upper surface or part of the upper surface of the landing pad LP. An upper insulating layer 260 can be arranged on the data storage pattern DSPs, and the cell contact plug PLG can contact the plate electrode 255 through the upper insulating layer 260.

[0069] According to some embodiments, the data storage pattern DSP may correspond to a unit capacitor and may include a capacitor dielectric layer 253 disposed between the storage electrode 251 and the plate electrode 255. In this case, the storage electrode 251 may be in direct contact with the landing pad LP, and the storage electrode 251 may have various shapes (such as circular, elliptical, rectangular, square, rhomboid, hexagonal, etc. in a planar view).

[0070] According to some embodiments, the data storage pattern DSP can be a variable resistance pattern that switches between two resistance states based on an electrical pulse applied to the memory element. For example, the data storage pattern DSP may include, but is not limited to, phase change materials, perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, antiferromagnetic materials, etc., having a crystallization state that changes according to the amount of current. Depending on the material layer of the data storage pattern DSP, the memory device 10 may be implemented as a resistive memory (such as PRAM, MRAM, RRAM, etc.).

[0071] The through-electrode (THV) 322 can contact the metal layer 318b by passing through the upper substrate 320 and can extend longitudinally in the fifth direction to the bonding metal pad 302 formed on the uppermost metal layer of the core peripheral circuit structure CPS. According to some embodiments, only metal layers 318a and 318b are shown and described. However, this disclosure is not limited thereto, and one or more metal layers may further be formed on metal layers 318a and 318b. The bit line BL can be electrically connected to the second circuit element 312b of the first bit sense amplifier circuit BLSA1 via the bonding metal pad 302 of the cell array structure CAS and the bonding metal pad 301 of the core peripheral circuit structure CPS.

[0072] According to some embodiments, the bonding metal pad 302 of the core array structure CAS and the bonding metal pad 301 of the core peripheral circuit structure CPS can be connected to each other by an electrical bonding method or a physical bonding method. When the bonding metal pads 301 and 302 include Cu, the bonding method can be a Cu-Cu bonding method. As another example, the bonding metal pads 301 and 302 may also include Al or W.

[0073] Each word line WL is electrically or physically connected to the metal layer 318a of the CAS (Cell Array Structure), and the metal layer 318a of the CAS can contact the bonding metal pad 301. Each word line WL can be electrically connected to the first circuit element 312a of the first word line driver circuit SWD1 via the bonding metal pad 302 of the CAS and the bonding metal pad 301 of the CPS (Core Peripheral Circuit Structure). Each bit line BL is electrically or physically connected to the metal layer 318b of the CAS, and the metal layer 318a of the CAS can contact the bonding metal pad 301. Each bit line BL can be electrically connected to the second circuit element 312b of the first bit line sense amplifier circuit BLSA1 via the bonding metal pad 302 of the CAS and the bonding metal pad 301 of the CPS.

[0074] exist Figure 9In the memory device 10, memory cells including a data storage pattern DSP, a word line WL, a back gate electrode BG, an active pattern AP, and a bit line BL can be arranged in each of the regions of the first memory block BLK1 and the second memory block BLK2 of the cell array structure CAS. The word line WL, the active pattern AP, and the bit line BL can form a vertical channel transistor VCT. In the process of forming the bonding metal pad 302 of the cell array structure CAS, a reference can be formed. Figures 5A to 5D The first test pad patterns 400a, 400b, 400c, and 400d are described as the first test pattern TP1 to the fourth test pattern TP4. In the process of forming the bonding metal pad 301 of the core peripheral circuit structure CPS, a reference can be formed. Figures 5A to 5D The description includes second test pad patterns 500a, 500b, 500c, and 500d, representing the first test pattern TP1 to the fourth test pattern TP4. Each of the second test pad patterns 500a to 500d is connectable to a detector 901, and the detector 901 is capable of detecting whether the test pads in the first to sixth test pad groups 610 and 610b, 620 and 620b, 640 and 640b, 660 and 660b, 680 and 680b, and 690 and 690b are misaligned.

[0075] Figure 10 This is a block diagram illustrating an example of an electronic device system including a semiconductor device according to some embodiments. Figure 10 System 2000 may include a camera 2100, a display 2200, an audio processor 2300, a modem 2400, dynamic random access memory (DRAM) 2500a and 2500b, flash memory 2600a and 2600b, input / output (I / O) devices 2700a and 2700b, and an application processor (AP) 2800. System 2000 may be implemented by a laptop computer, mobile terminal, smartphone, desktop personal computer (PC), wearable device, healthcare device, or Internet of Things (IoT) device. Furthermore, system 2000 may be implemented by a server or PC.

[0076] Camera 2100 can capture still images or videos under user control, store the captured image / video data, or send the captured image / video data to display 2200. Audio processor 2300 can process audio data included in flash memory 2600a and 2600b or network content. Modem 2400 can modulate and transmit signals for wired / wireless data transmission and reception, and the receiving end can demodulate the signals to recover the original signals. I / O devices 2700a and 2700b may include devices for providing digital input and / or output functions (such as Universal Serial Bus (USB), storage devices, digital cameras, Secure Digital (SD) cards, Digital Universal Optical Disc (DVD), network adapters, touch screens, etc.).

[0077] AP 2800 can control the general operation of system 2000. AP 2800 may include controller 2810, accelerator or accelerator chip 2820, and interface 2830. AP 2800 can control display 2200 to display a portion of the contents stored in flash memory 2600a and 2600b. When user input is received through I / O devices 2700a and 2700b, AP 2800 can perform control operations corresponding to the user input. AP 2800 may include accelerator blocks, which are dedicated circuits for artificial intelligence (AI) data computation, or accelerator chip 2820 may be provided separately from AP 2800. DRAM 2500b may be additionally mounted in the accelerator or accelerator chip 2820. The accelerator may be a function block dedicated to specific functions of AP 2800, and may include a GPU as a function block dedicated to graphics data processing, a neural processor (NPU) as a block dedicated to AI computation and inference, and a data processor (DPU) as a block dedicated to data transmission. According to some implementations, images captured by a user using camera 2100 can be signal processed and stored in DRAM 2500b, and accelerator or accelerator chip 2820 can perform AI data calculations for identifying data by using the data stored in DRAM 2500b and functions for inference.

[0078] System 2000 may include multiple DRAMs 2500a and 2500b. AP 2800 can control DRAMs 2500a and 2500b according to JEDEC-compliant commands and MRS, or it can perform communication by setting DRAM interface specifications for using service-specific functions related to low voltage / high speed / reliability and Cyclic Redundancy Check (CRC) / Error Correction Code (ECC) functions. For example, AP 2800 can communicate with DRAM 2500a using an interface according to JEDEC standards (such as LPDDR4, LPDDR5, etc.), and can communicate with DRAM 2500b by setting new DRAM interface specifications for controlling DRAM 2500b, which has a larger bandwidth than DRAM 2500a.

[0079] Figure 10 Only DRAMs 2500a and 2500b are depicted. However, this disclosure is not limited thereto, and any memory (such as PRAM, SRAM, MRAM, RRAM, FRAM, and hybrid random access memory (RAM)) that meets the conditions related to the bandwidth, response rate, and voltage of AP 2800 or accelerator chip 2820 may be used. DRAMs 2500a and 2500b may have relatively less latency and relatively less bandwidth than I / O devices 2700a and 2700b or flash memory 2600a and 2600b. DRAMs 2500a and 2500b may be initialized at the power-on time of system 2000 and loaded with operating system and application data, and may be used as temporary storage devices for operating system and application data or as execution space for various software codes.

[0080] In DRAM 2500a and 2500b, the four basic arithmetic operations (addition / subtraction / multiplication / division), vector operations, address operations, or Fast Fourier Transform (FET) operations can be performed. Furthermore, in DRAM 2500a and 2500b, functions for inference can be performed. Inference can be performed using deep learning algorithms based on artificial neural networks. Deep learning algorithms can include training operations that train a model using various data and inference operations that allow the trained model to recognize data.

[0081] System 2000 may include multiple storage devices or multiple flash memory devices 2600a and 2600b having a capacity larger than DRAM 2500a and 2500b. An accelerator or accelerator chip 2820 may perform training operations and AI data computations using flash memory devices 2600a and 2600b. According to some embodiments, flash memory devices 2600a and 2600b may include a memory controller 2610 and flash memory devices 2620, and operating means disposed in the memory controller 2610 may be used to perform training operations and inference AI data computations performed by AP 2800 and / or accelerator chip 2820 with relatively increased efficiency. Flash memory devices 2600a and 2600b may store photographs captured by camera 2100 or data transmitted from a data network. For example, augmented reality (AR) / virtual reality (VR) content, high-definition (HD) content, or ultra-high-definition (UHD) content may be stored.

[0082] Components of System 2000 may include references Figures 1 to 9 The description describes test pad patterns configured to detect misalignment of die bonding pads. A first test pad pattern, including a first test pad, may be included in a first semiconductor die, and a second test pad pattern, including a second test pad, may be included in a second semiconductor die. First test pads in each of the first test pad groups of the first semiconductor die are electrically connected to each other via lines extending in a first direction, and second test pads in each of the second test pad groups of the second semiconductor die are electrically connected to each other via lines extending upward in a third direction intersecting the first direction. Various misalignment patterns may be arranged between the first and second test pads in each of the first and second test pad groups. A detector configured to determine alignment accuracy when the first semiconductor die is bonded to the second semiconductor die may include a switch configured to apply a power supply voltage of the second semiconductor die to the second test pads electrically connected to each other via the first line extending upward in a third direction, and to apply a ground voltage to the second test pads electrically connected to each other via the second line extending upward in a third direction. The detector can detect misalignment between a first semiconductor die and a second semiconductor die based on the current flowing between the first test pad in each of the first test pad groups and the second test pad in each of the second test pad groups. Based on the detected misalignment, the detector can be configured to correct the misalignment during the bonding of the first and second semiconductor dies.

[0083] While this disclosure contains numerous details of specific implementations, these details should not be construed as limiting the scope of the claims, their equivalents, and the appended claims. Specific features described in the context of individual embodiments in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a specific combination, in some cases, one or more features from the combination may be excluded from the combination, and the combination may be for sub-combinations or variations of sub-combinations.

Claims

1. A semiconductor die, comprising: A first semiconductor die includes a plurality of first test pad groups, each of the plurality of first test pad groups including a first test pad, wherein the first test pads of each of the plurality of first test pad groups are electrically connected to each other by a line extending in a first direction. A second semiconductor die includes a plurality of second test pad groups, each of the plurality of second test pad groups including a second test pad, wherein the plurality of second test pad groups are arranged at positions corresponding to the positions of the plurality of first test pad groups, and the second test pad of each of the plurality of second test pad groups is electrically connected to each other via a line extending upward in a third direction transverse to a first direction; and The detector is configured to determine the alignment accuracy between the first semiconductor die and the second semiconductor die, based on the current flowing between the first test pad in each of the plurality of first test pad groups and the second test pad in each of the plurality of second test pad groups, when the first semiconductor die and the second semiconductor die are coupled together.

2. The semiconductor die as claimed in claim 1, wherein, Each of the plurality of first test pad groups and each of the plurality of second test pad groups is provided with a misaligned pattern, the misaligned pattern being disposed between the first test pad and the second test pad.

3. The semiconductor die as described in claim 2, wherein, The size of the misaligned pattern increases in the first direction, and the bonding area between the first test pad and the second test pad decreases.

4. The semiconductor die as claimed in claim 2, wherein, The size of the misaligned pattern increases in a second direction opposite to the first direction, and the bonding area between the first test pad and the second test pad decreases.

5. The semiconductor die as claimed in claim 2, wherein, The size of the misaligned pattern increases upwards on the third side, and the bonding area between the first test pad and the second test pad decreases.

6. The semiconductor die as claimed in claim 2, wherein, The size of the misaligned pattern increases in a fourth direction opposite to the third direction, and the bonding area between the first test pad and the second test pad decreases.

7. The semiconductor die as described in claim 1, in, The detector is included in the second semiconductor die, and The detector includes a switch configured to apply a power supply voltage of the second semiconductor die to each of the plurality of second test pad groups, which are electrically connected to each other via a first line extending upward from a third party, and to apply a ground voltage to the second test pads electrically connected to each other via a second line extending upward from a third party.

8. The semiconductor die as claimed in claim 1, wherein, The detector is configured to adjust for misalignment based on a determined alignment accuracy when the first semiconductor die and the second semiconductor die are coupled together.

9. A semiconductor die, comprising: A first semiconductor die includes a first bonding metal pad and a plurality of first test pad groups, each of the plurality of first test pad groups including a first test pad, wherein the first bonding metal pad is connected to a cell array structure including a plurality of memory blocks, and the first test pads of each of the plurality of first test pad groups are electrically connected to each other via lines extending in a first direction. A second semiconductor die includes a second bonding metal pad and a plurality of second test pad groups. The second bonding metal pads are respectively in contact with first bonding metal pads. Each of the plurality of second test pad groups includes a second test pad. The second bonding metal pads are connected to a core peripheral circuit structure, which includes circuitry respectively connected to the plurality of memory blocks. The plurality of second test pad groups are arranged at positions corresponding to the positions of the plurality of first test pad groups. The second test pads of each of the plurality of second test pad groups are electrically connected to each other via lines extending upwards in a third direction transverse to a first direction. The detector is configured to determine the alignment accuracy between the first semiconductor die and the second semiconductor die, based on the current flowing between the first test pad in each of the plurality of first test pad groups and the second test pad in each of the plurality of second test pad groups, when the first semiconductor die and the second semiconductor die are coupled together.

10. The semiconductor die as claimed in claim 9, in, Each of the plurality of first test pad groups is arranged between the plurality of memory blocks, and Each of the plurality of second test pad groups is arranged between word line driver circuits of the second semiconductor die, and the word line driver circuits are respectively connected to multiple word lines of each of the plurality of memory blocks.

11. The semiconductor die as described in claim 9, in, The second bonding metal pad is connected to the bit line sensing amplifier circuit of the second semiconductor die, and the bit line sensing amplifier circuit is respectively connected to multiple bit lines of each of the plurality of memory blocks, and Each of the plurality of second test pad groups is arranged between bit line sense amplifier circuits corresponding to the plurality of memory blocks, respectively.

12. The semiconductor die as claimed in claim 9, wherein, Each of the plurality of first test pad groups and each of the plurality of second test pad groups is provided with a misaligned pattern, the misaligned pattern being disposed between the first test pad and the second test pad.

13. The semiconductor die as claimed in claim 12, wherein, The size of the misaligned pattern increases in the first direction, and the bonding area between the first test pad and the second test pad decreases.

14. The semiconductor die as claimed in claim 12, wherein, The size of the misaligned pattern increases in a second direction opposite to the first direction, and the bonding area between the first test pad and the second test pad decreases.

15. The semiconductor die as claimed in claim 12, wherein, The size of the misaligned pattern increases upwards on the third side, and the bonding area between the first test pad and the second test pad decreases.

16. The semiconductor die of claim 12, wherein, The size of the misaligned pattern increases in a fourth direction opposite to the third direction, and the bonding area between the first test pad and the second test pad decreases.

17. The semiconductor die as claimed in claim 9, in, The detector is included in the second semiconductor die, and The detector includes a switch configured to apply a power supply voltage of the second semiconductor die to each of the plurality of second test pad groups, which are electrically connected to each other via a first line extending upward from a third party, and to apply a ground voltage to the second test pads electrically connected to each other via a second line extending upward from a third party.

18. The semiconductor die as claimed in claim 9, wherein, The detector is configured to adjust for misalignment based on a determined alignment accuracy when the first semiconductor die and the second semiconductor die are coupled together.

19. A semiconductor wafer comprising: A first semiconductor wafer includes a first semiconductor die disposed in a third direction and a direction tangential to the first direction, wherein each of the first semiconductor dies includes a plurality of first test pad groups, each of the plurality of first test pad groups including a first test pad, and the first test pads of each of the plurality of first test pad groups are electrically connected to each other by a line extending in the first direction. A second semiconductor wafer includes a second semiconductor die disposed in a first direction and a third direction, wherein each of the second semiconductor dies includes a plurality of second test pad groups, each of the plurality of second test pad groups including a second test pad, the plurality of second test pad groups being disposed at positions corresponding to the positions of the plurality of first test pad groups, and the second test pads of each of the plurality of second test pad groups being electrically connected to each other via lines extending in the third direction; and The detector is configured to determine the alignment accuracy between the first semiconductor wafer and the second semiconductor wafer, based on the current flowing between the first test pad in each of the plurality of first test pad groups and the second test pad in each of the plurality of second test pad groups, when the first semiconductor wafer and the second semiconductor wafer are coupled together.

20. The semiconductor wafer of claim 19, wherein, Each of the plurality of first test pad groups and each of the plurality of second test pad groups is provided with a misaligned pattern, the misaligned pattern being disposed between the first test pad and the second test pad.

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