A method for fabricating a semiconductor structure and the semiconductor structure.

Abstract

This invention provides a method for fabricating a semiconductor structure and the semiconductor structure itself, relating to the field of semiconductor technology. The method for fabricating the semiconductor structure includes the following steps: providing a substrate, the substrate comprising a substrate, a pad oxide layer, a pad nitride layer, and at least one trench, wherein the pad oxide layer is formed on the surface of the substrate, the pad nitride layer is formed on the surface of the pad oxide layer, and the trench is disposed within the substrate, with an opening extending through the pad oxide layer and the pad nitride layer at its upper part; forming a piezoelectric material layer at the bottom of the trench; filling the trench with an isolation oxide until the isolation oxide covers the trench and the pad nitride layer; applying an electric field to the substrate in a direction perpendicular to the upper surface of the substrate, and planarizing the isolation oxide under the action of the electric field until the isolation oxide on the surface of the pad nitride layer is removed, and then removing the electric field to obtain a shallow trench isolation structure. The method for fabricating the semiconductor structure of this invention can improve the dish-shaped depressions on the surface of the shallow trench isolation structure and improve the yield of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Technology

[0002] In integrated circuit manufacturing, shallow trench isolation (STI) is often used to isolate individual devices fabricated on a substrate, such as different memory cells. In existing technologies, the fabrication method for shallow trench isolation structures involves sequentially forming a pad nitride layer and a pad oxide layer on a substrate, then sequentially etching the pad nitride layer, pad oxide layer, and substrate in a selected area to form a shallow trench. Further, an isolation oxide layer is filled into the trench until it covers the pad nitride layer. The filled isolation oxide is then chemically and mechanically polished until flush with the pad nitride layer, thus forming the shallow trench isolation structure. During the formation of the shallow trench isolation structure, dish-shaped depressions easily form on the surface, narrowing the process window for subsequent processes (such as photolithography and deposition), leading to a decrease in semiconductor yield and increased difficulty in process control. Summary of the Invention

[0003] This invention provides a method for fabricating a semiconductor structure and a semiconductor structure to improve the dish-shaped depressions on the surface of a shallow trench isolation structure and increase the yield of the semiconductor structure.

[0004] This invention provides a method for fabricating a semiconductor structure, the method comprising the following steps:

[0005] A substrate is provided, the substrate including a substrate, a pad oxide layer, a pad nitride layer and at least one trench, the pad oxide layer being formed on the surface of the substrate, the pad nitride layer being formed on the surface of the pad oxide layer, the trench being disposed in the substrate and penetrating through the pad oxide layer at the top, and the pad nitride layer forming an opening;

[0006] A piezoelectric material layer is formed at the bottom of the trench;

[0007] Fill the trench with an insulating oxide until the insulating oxide covers the trench and the pad nitride layer;

[0008] An electric field is applied to the substrate in a direction perpendicular to the upper surface of the substrate, and the isolation oxide is planarized under the action of the electric field until the isolation oxide on the surface of the pad nitride layer is removed, and the electric field is then removed to obtain a shallow trench isolation structure.

[0009] In one embodiment of the present invention, the thickness of the piezoelectric material layer is 200~1000 Å.

[0010] In one embodiment of the present invention, the strength of the electric field is 10~30V / m.

[0011] In one embodiment of the present invention, the material of the piezoelectric material layer includes either barium titanate or lead zirconate titanate.

[0012] In one embodiment of the present invention, the piezoelectric coefficient of the piezoelectric material layer is 30~150 pC / N.

[0013] In one embodiment of the present invention, a piezoelectric material layer is formed at the bottom of the trench, comprising the following steps:

[0014] Fill the trench with piezoelectric material until the piezoelectric material covers the trench and the pad nitride layer;

[0015] The piezoelectric material is planarized until the piezoelectric material on the surface of the pad nitride layer is removed;

[0016] The piezoelectric material within the trench is etched to form a piezoelectric material layer at the bottom of the trench.

[0017] In one embodiment of the present invention, when etching the piezoelectric material, a fluorine-containing etching medium is selected to perform wet etching or dry etching on the piezoelectric material.

[0018] In one embodiment of the present invention, after the isolation oxide is planarized under the action of the electric field, the preparation method further includes the process of removing the pad nitride layer and the pad oxide layer.

[0019] In one embodiment of the present invention, the substrate preparation process includes:

[0020] Provide the substrate;

[0021] The pad oxide layer is deposited on the substrate;

[0022] Deposit the pad nitride layer on the surface of the pad oxide layer;

[0023] Using patterned photoresist as a mask, the pad nitride layer, the pad oxide layer, and the substrate are etched to form trenches on the substrate.

[0024] The present invention also provides a semiconductor structure, which is prepared according to the above-described method for preparing a semiconductor structure.

[0025] The beneficial effects of this invention are as follows: This invention proposes a method for fabricating a semiconductor structure. A piezoelectric material layer is formed at the bottom of a trench. An isolation oxide layer is filled onto the surface of the piezoelectric material layer until it covers the trench and the pad nitride layer. An electric field is applied to the substrate during planarization of the isolation oxide layer, and the electric field is removed after the isolation oxide on the surface of the pad nitride layer is removed. An unexpected result of this application is that a piezoelectric material layer is filled beneath the oxide isolation layer. When an electric field is applied to the piezoelectric material layer during the planarization of the isolation oxide, the piezoelectric material layer deforms and sinks downwards under the action of the electric field. After the planarization of the isolation oxide is completed, the electric field is removed, and the piezoelectric material layer returns to its shape, simultaneously pushing the isolation oxide to deform upwards. This reduces the dish-shaped depression on the surface of the shallow trench isolation structure and improves the yield of the semiconductor structure. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0027] In the attached diagram:

[0028] Figure 1 This is a microscopic schematic diagram of a shallow trench isolation structure fabricated in the prior art;

[0029] Figure 2 This is a flowchart illustrating the fabrication process of a semiconductor structure provided in one embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of forming a pad oxide layer and a pad nitride layer on a substrate according to an embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of the formation of a photoresist layer provided in one embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of the formation of a trench according to one embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of removing the photoresist layer according to an embodiment of the present invention;

[0034] Figure 7 This is a schematic diagram of a piezoelectric material provided in one embodiment of the present invention;

[0035] Figure 8 This is a schematic diagram of the planarization treatment of piezoelectric materials provided in one embodiment of the present invention;

[0036] Figure 9 This is a schematic diagram of the formation of a piezoelectric material layer provided in one embodiment of the present invention;

[0037] Figure 10 This is a schematic diagram of a filling isolation oxide provided in one embodiment of the present invention;

[0038] Figure 11 This is a schematic diagram of the formation of an initial shallow trench isolation structure provided in one embodiment of the present invention;

[0039] Figure 12 This is a schematic diagram of a shallow trench isolation structure provided in one embodiment of the present invention;

[0040] Figure 13 This is a schematic diagram of removing the pad nitriding layer and the pad oxide layer according to an embodiment of the present invention.

[0041] The attached figures are labeled as follows:

[0042] 10. Substrate; 100. Substrate; 200. Pad oxide layer; 300. Pad nitride layer; 400. Photoresist layer; 410. Trench region; 500. Trench; 510. Isolation oxide; 520. Initial shallow trench isolation structure; 530. Shallow trench isolation structure; 600. Piezoelectric material; 610. Piezoelectric material layer. Detailed Implementation

[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0044] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0045] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0046] In this document, when referring to numerical ranges, unless otherwise specified, the distribution of selectable values ​​within a numerical range is considered continuous, including the two endpoints of the range (i.e., the minimum and maximum values), and every value between these two endpoints. When multiple numerical ranges are provided to describe a feature or property, these numerical ranges can be combined.

[0047] Based on the problems existing in the background technology, the inventors discovered through extensive experiments that, due to limitations in the manufacturing process, when filling the trench with isolating oxide, the filling height of the isolating oxide in the trench is less than the height of the isolating oxide on the surface of the nitride layer on both sides. Furthermore, during the subsequent planarization treatment of the isolating oxide, the difference in hardness between the isolating oxide and the pad oxide layer easily leads to dish-shaped depressions (such as...) on the surface of the resulting shallow trench isolation structure. Figure 1 (As shown in the green box in the image), the depth of the dish-shaped recess is approximately 40~100 Å, and the value in each green box corresponds to the depth of the dish-shaped recess. Therefore, this application provides a method for fabricating a semiconductor structure to improve the dish-shaped recess on the surface of a shallow trench isolation structure and increase the yield of the semiconductor structure.

[0048] Please see Figures 2 to 12 The present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0049] S1, providing such Figure 6 The substrate 10 shown includes a substrate 100, a pad oxide layer 200, a pad nitride layer 300, and at least one trench 500. The pad oxide layer 200 is formed on the surface of the substrate 100, the pad nitride layer 300 is formed on the surface of the pad oxide layer 200, and the trench 500 is disposed in the substrate 100, with its upper part penetrating through the pad oxide layer 200 and the pad nitride layer 300 to form an opening.

[0050] S2, please refer to Figure 9 As shown, a piezoelectric material layer 610 is formed at the bottom of the trench 500.

[0051] S3, please refer to Figure 10 As shown, the trench 500 is filled with isolation oxide 510 until the isolation oxide 510 covers the trench 500 and the pad nitride layer 300.

[0052] S4, please refer to Figure 11 and Figure 12 As shown, an electric field is applied to the substrate 10 in a direction perpendicular to the upper surface of the substrate 10, and the isolation oxide 510 is planarized under the action of the electric field until the isolation oxide 510 on the surface of the pad nitride layer 300 is removed, and then the electric field is removed to obtain the desired result. Figure 12 The shallow trench isolation structure 530 shown is illustrated.

[0053] Please see Figure 6 As shown, in step S1 of this invention, the substrate 100 can be any material suitable for forming a semiconductor structure, such as undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). This invention does not limit the specific material and thickness of the substrate 100, and the substrate 100 can be a P-doped semiconductor substrate or an N-doped semiconductor substrate. The doping type of the impurities can be flexibly set according to the desired semiconductor structure. In this embodiment, the substrate 100 is, for example, a silicon substrate.

[0054] It should be noted that the substrate 10 can be a purchased semi-finished product or it can be prepared in-house. In one embodiment, the substrate 10 is prepared in-house based on the substrate 100. Please refer to [link / reference]. Figures 3 to 6 As shown, the preparation method of substrate 10 is as follows:

[0055] Please see Figure 3 As shown, in one embodiment of the present invention, a pad oxide layer 200 is formed on the surface of the substrate 100. The pad oxide layer 200 can serve as a protective layer for the substrate 100, protecting the substrate 100 it covers in subsequent processes and preventing unnecessary damage to the substrate 100. Furthermore, since the subsequently formed pad nitride layer 300 has high stress, dislocations are easily generated on the surface of the substrate 100 during its formation. The pad oxide layer 200 can provide a buffer during the formation of the pad nitride layer 300, preventing dislocations from being generated on the substrate 100. The material of the pad oxide layer 200 can be silicon dioxide or similar materials, and the pad oxide layer 200 can be formed by any one of the following methods: dry oxidation, wet oxidation, or in-situ steam generation (ISSG). In this embodiment, the pad oxide layer 200 is formed, for example, by a dry oxygen oxidation method. Exemplarily, the substrate 100 is placed in a furnace tube, oxygen is introduced, and the surface of the substrate 100 reacts with the oxygen at a high temperature to generate a dense pad oxide layer 200. The fabrication process of the substrate 10 may also include cleaning the substrate 100 before forming the pad oxide layer 200. By cleaning the substrate 100, impurities present on the surface of the substrate 100 can be removed, preventing impurities from affecting subsequent processes and thus ensuring device performance. For example, a cleaning solution can be used to clean the substrate 100, or a gas such as nitrogen can be used to purge the substrate 100 to achieve cleaning.

[0056] Please see Figure 3As shown, in one embodiment of the present invention, after forming the pad oxide layer 200, a pad nitride layer 300 is formed on the pad oxide layer 200. The material of the pad nitride layer 300 can be silicon nitride or oxynitride; in this embodiment, the pad nitride layer 300 is, for example, silicon nitride. The pad nitride layer 300 can be prepared by any one of the following processes: low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma chemical vapor deposition. Exemplarily, when preparing the pad nitride layer 300 using a low-pressure chemical vapor deposition process, silicon nitride can be generated by reacting ammonia and dichlorosilane. By setting the pad nitride layer 300, it can not only serve as a mask during the subsequent formation of the trench 500 and protect the substrate 100 from damage during etching, but also protect the substrate 100 from planarization processes such as chemical mechanical polishing (CMP) involved in the fabrication of the piezoelectric material layer 610 and the initial shallow trench isolation structure 520.

[0057] Please see Figures 4 to 6 As shown, in one embodiment of the present invention, after forming the pad nitride layer 300, photoresist is coated on the pad nitride layer 300 to form a photoresist layer 400. The type of photoresist material is not limited; it can be a common positive photoresist material or a negative photoresist material. After coating the photoresist, photolithography processes such as mask exposure and development are used to pattern the coated photoresist, exposing the trench region 410. Using the patterned photoresist layer 400 as a mask layer, the pad nitride layer 300, the pad oxide layer 200, and the substrate 100 are etched sequentially to form trenches 500. The number, position, depth, and width of the trenches 500 are set according to actual needs and are not limited here. The number of trenches 500 can be one or more; exemplarily, the number of trenches 500 is multiple. In this embodiment, the shape of the trench 500 is an inverted trapezoidal cross-section that is wider at the top and narrower at the bottom, that is, the width of the top of the trench 500 is greater than the width of the bottom of the trench 500. Of course, in some embodiments, the trench 500 can also be rectangular. In this embodiment, the trench 500 can be formed by sequentially removing the pad nitride layer 300, the pad oxide layer 200, and part of the substrate 100 by dry etching. The etching gas includes, for example, one or a mixture of several of chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), or hydrogen bromide (HBr), or a combination of them and oxygen (O2). After etching, the photoresist layer 400 is removed by wet cleaning or ashing treatment.

[0058] Please see Figure 7As shown, in step S2 of this invention, after forming the trench 500, a piezoelectric material 600 is filled into the trench 500 until the piezoelectric material 600 covers the trench 500 and the pad nitride layer 300. This invention does not limit the deposition method of the piezoelectric material 600; for example, it can be deposited using high-density plasma chemical vapor deposition (HDP-CVD) or high-aspect-ratio process chemical vapor deposition (HARP-CVD). Exemplarily, the piezoelectric coefficient of the piezoelectric material 600 is 30~150 pC / N, such as any value from 30 to 150 pC / N, including 30 pC / N, 60 pC / N, 90 pC / N, 120 pC / N, and 150 pC / N. In this application, the piezoelectric material 600 is, for example, a perovskite structure material, or, for example, barium titanate (BaTiO3) or lead zirconate titanate (PbZrTiO3). In other embodiments, the piezoelectric material 600 may also be other materials capable of producing a piezoelectric effect.

[0059] In some embodiments, before filling the trench 500 with the piezoelectric material 600, the semiconductor structure fabrication method further includes pulling back the pad nitride layer 300 and the pad oxide layer 200 to expose the edges and corners of the substrate 100. For example, the pad nitride layer 300 can be etched back with phosphoric acid first, followed by the pad oxide layer 200 with hydrofluoric acid; or the pad oxide layer 200 can be etched back with hydrofluoric acid first, followed by the pad nitride layer 300 with phosphoric acid. Specifically, taking the etching of the pad nitride layer 300 followed by the etching of the pad oxide layer 200 as an example, the substrate 10 can be immersed in a phosphoric acid bath first, and then immersed in a hydrofluoric acid bath. The phosphoric acid and hydrofluoric acid solutions hardly corrode the substrate 100. Alternatively, a dry etching method can be used to sequentially etch back the pad nitride layer 300 and the pad oxide layer 200. Dry etching includes physical etching, chemical etching, and physicochemical etching. Physical etching utilizes the sputtering effect generated by ion collisions on the surface of the etched structure to achieve etching. Chemical etching achieves etching through the chemical interaction between activated etching gas and the etched structure, producing volatile compounds. Physicochemical etching achieves etching through the physical and chemical interactions between ions or active groups in plasma and the etched structure. The etch-back process can enlarge the sidewalls of the pad nitride layer 300 and the pad oxide layer 200 along the direction of the enlarged trench 500 opening, thus improving the filling quality of the subsequent isolation oxide 510. In some embodiments, after the etch-back process of the pad nitride layer 300 and the pad oxide layer 200, the substrate 10 is further cleaned to prevent byproducts generated during the etch-back process from falling into the trench 500 and affecting the subsequent deposition of the piezoelectric material 600 and the isolation oxide 510. The cleaning process can be performed using, for example, hydrofluoric acid or HPM solution (a mixed solution of hydrochloric acid, hydrogen peroxide, and deionized water), or using, for example, APM solution (a mixed solution of ammonium hydroxide, hydrogen peroxide, and deionized water). Since the edges formed during the etching process are typically sharp, in one embodiment of the invention, after cleaning the substrate 10, the edge corners 110 are rounded. Exemplarily, the rounding of the edge corners is performed by wet etching with an APM solution to roughen the edge corners and obtain rounded corners. Different degrees of rounding can be obtained by adjusting the concentration of the APM solution, the temperature of the mixed solution, and the etching time. After roughening the corners to obtain rounded corners, when current is applied to the semiconductor device, the high electric field will not concentrate at the rounded corner location, thereby reducing leakage current.

[0060] Please see Figure 8As shown, in one embodiment of the present invention, after filling the piezoelectric material 600, the piezoelectric material 600 is planarized. Planarization can be performed, for example, by chemical mechanical polishing to planarize the insulating medium. After planarization, the piezoelectric material 600 is at least partially exposed on the substrate 100. The present invention does not limit the planarization of the piezoelectric material 600 to a specific location; it can be placed at any location according to the semiconductor device design requirements. For example, part of the piezoelectric material 600 can be removed by polishing, with the pad nitride layer 300 serving as the polishing stop layer. That is, the planarization of the piezoelectric material 600 stops when the piezoelectric material 600 on the surface of the pad nitride layer 300 is removed and exposed.

[0061] Please see Figure 9 As shown, in one embodiment of the present invention, after planarization of the piezoelectric material 600, the piezoelectric material 600 within the trench 500 is etched to obtain a piezoelectric material layer 610. The present invention does not limit the etching method of the piezoelectric material 600; for example, a fluorinated etching medium can be used to perform wet etching or dry etching of the piezoelectric material 600. Exemplarily, wet etching can use a hydrofluoric acid (HF) solution or a mixed solution of hydrofluoric acid (HF) and nitric acid (HNO3), etc. Dry etching can use a fluorine-based gas, such as carbon tetrafluoride (CF4) or sulfur hexafluoride (SF6), etc. Both the dissociation of the fluorinated etching solution and the fluorinated etching gas in the plasma state can generate fluorine (F). - Ions can effectively etch piezoelectric materials. The thickness of the piezoelectric material layer 610 can be adjusted according to the height of the isolation structure of the trench 500, for example, the thickness of the piezoelectric material layer 610 is less than 40% of the height of the trench 500. For example, the thickness of the piezoelectric material layer 610 is 200~1000 Å, such as any value in the range of 200 Å, 400 Å, 600 Å, 800 Å or 1000 Å.

[0062] Please see Figure 10As shown, in step S3 of this invention, after forming the piezoelectric material layer 610, the isolation oxide 510 is filled into the trench 500 until the isolation oxide 510 covers the trench 500 and the pad nitride layer 300. This invention does not limit the deposition method of the isolation oxide; for example, it can be deposited by chemical vapor deposition or high aspect ratio chemical vapor deposition. In this embodiment, the isolation oxide 510 is obtained, for example, by depositing tetraethyl orthosilicate (TEOS). Specifically, tetraethyl orthosilicate and an oxygen-containing precursor are introduced, the oxygen-containing precursor including, for example, one of O2 or O3, and the deposition time is controlled to obtain the isolation oxide 510. Chemical vapor deposition is fast and can be deposited at low temperatures, resulting in a good filling ability of the deposited isolation oxide 510 and reducing the likelihood of voids. After depositing the isolation oxide 510, a high-temperature tempering process can be performed to increase the density and stress characteristics of the isolation oxide 510. In this embodiment, the insulating medium is, for example, silicon oxide. In other embodiments, the insulating oxide layer may be other insulating materials suitable for isolation.

[0063] Please see Figure 11 and Figure 12 As shown, in step S4 of the present invention, an electric field is applied to the substrate 10 in a direction perpendicular to the upper surface of the substrate 10 (the direction of the electric field is...). Figure 11 The isolation oxide 510 is planarized under the action of an electric field (in the direction of the arrow in the diagram) to obtain an initial shallow trench isolation structure 520. For example, the strength of the electric field is 10~30V / m, such as any value among 10~30V / m, 20V / m, or 30V / m. The planarization of the isolation oxide 510 is performed, for example, by chemical mechanical polishing, and the initial shallow trench isolation structure 520 is at least partially exposed on the substrate 100. This invention does not limit the planarization of the isolation oxide 510 to a specific location; it can be placed at any location according to the semiconductor device design requirements. For example, part of the isolation oxide 510 can be removed by polishing, with the pad nitride layer 300 serving as a polishing stop layer, until the isolation oxide 510 on the surface of the pad nitride layer 300 is removed, thus obtaining the initial shallow trench isolation structure 520. During the planarization process of the isolation oxide 510, the piezoelectric material layer 610 deforms downwards along the height direction of the trench 500 under the action of an electric field. After the electric field is removed, the piezoelectric material layer 610 recovers its shape upwards along the height direction of the trench 500, simultaneously pushing the initial isolation oxide 510 to deform upwards, thus obtaining a shallow trench isolation structure 530. This improves the dish-shaped depressions on the surface of the shallow trench isolation structure 530 and increases the yield of semiconductor structures. The formula for calculating the deformation of the piezoelectric material layer 610 is as follows: L=d E L0, L represents the deformation of the piezoelectric material layer 610, d represents the piezoelectric coefficient of the piezoelectric material 600, E represents the applied electric field strength, and L0 represents the length of the electric field applied to the piezoelectric material layer 610. In this application, the length of the electric field applied to the piezoelectric material layer 610 is equal to the thickness of the piezoelectric material layer 610. Therefore, when the piezoelectric material 600 and the electric field strength are fixed, the deformation of the piezoelectric material layer 610 is directly proportional to its thickness. Appropriate piezoelectric material 600 and electric field strength can be selected as needed, and a piezoelectric material layer 610 of appropriate thickness can be provided.

[0064] Please see Figure 13 As shown, in one embodiment of the present invention, after planarizing the isolation oxide 510, the method for fabricating the semiconductor structure further includes removing the pad oxide layer 200 and the pad nitride layer 300 from the surface of the substrate 100. The present invention does not limit the method for removing the pad oxide layer 200 and the pad nitride layer 300; for example, dry etching, wet etching, or a combination of dry and wet etching may be used. In this embodiment, for example, phosphoric acid is used to etch the pad nitride layer 300, and hydrofluoric acid is used to remove the pad oxide layer 200.

[0065] This invention also provides a semiconductor structure fabricated using the method described above. The semiconductor structure of this invention effectively improves the dish-shaped depressions on the surface of the shallow trench isolation structure, thereby improving the quality of subsequent manufacturing processes and ultimately enhancing the quality and yield of the semiconductor structure.

[0066] In summary, the semiconductor structure fabrication method proposed in this invention involves forming a piezoelectric material layer at the bottom of a trench, filling the surface of the piezoelectric material layer with an isolation oxide layer until the isolation oxide covers the trench and the pad nitride layer, applying an electric field to the substrate during the planarization process of the isolation oxide, and removing the electric field after the isolation oxide on the surface of the pad nitride layer is removed. An unexpected result of this application is that by filling the piezoelectric material layer beneath the oxide isolation layer, and applying an electric field to the piezoelectric material layer during the planarization process of the isolation oxide, the piezoelectric material layer deforms and sinks downwards under the action of the electric field. After the planarization process of the isolation oxide is completed and the electric field is removed, the piezoelectric material layer returns to its shape, simultaneously pushing the isolation oxide to deform upwards, reducing the dish-shaped depression on the surface of the shallow trench isolation structure, and improving the yield of the semiconductor structure.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, the substrate including a substrate, a pad oxide layer, a pad nitride layer and at least one trench, the pad oxide layer being formed on the surface of the substrate, the pad nitride layer being formed on the surface of the pad oxide layer, the trench being disposed in the substrate and penetrating through the pad oxide layer at the top, and the pad nitride layer forming an opening; A piezoelectric material layer is formed at the bottom of the trench; Fill the trench with an isolation oxide until the isolation oxide covers the trench and the pad nitride layer; An electric field is applied to the substrate in a direction perpendicular to the upper surface of the substrate, and the isolation oxide is planarized under the action of the electric field until the isolation oxide on the surface of the pad nitride layer is removed, and the electric field is then removed to obtain a shallow trench isolation structure.

2. The preparation method according to claim 1, characterized in that, The thickness of the piezoelectric material layer is 200~1000 Å.

3. The preparation method according to claim 1, characterized in that, The strength of the electric field is 10~30V / m.

4. The preparation method according to claim 1, characterized in that, The material of the piezoelectric material layer includes either barium titanate or lead zirconate titanate.

5. The preparation method according to claim 1, characterized in that, The piezoelectric coefficient of the piezoelectric material layer is 30~150 pC / N.

6. The preparation method according to claim 1, characterized in that, Forming a piezoelectric material layer at the bottom of the trench includes the following steps: Fill the trench with piezoelectric material until the piezoelectric material covers the trench and the pad nitride layer; The piezoelectric material is planarized until the piezoelectric material on the surface of the pad nitride layer is removed; The piezoelectric material within the trench is etched to form a piezoelectric material layer at the bottom of the trench.

7. The preparation method according to claim 6, characterized in that, When etching the piezoelectric material, a fluorine-containing etching medium is selected to perform wet etching or dry etching on the piezoelectric material.

8. The preparation method according to claim 1, characterized in that, After planarizing the isolation oxide under the action of the electric field, the preparation method further includes the process of removing the pad nitride layer and the pad oxide layer.

9. The preparation method according to claim 1, characterized in that, The substrate preparation process includes: Provide the substrate; The pad oxide layer is deposited on the substrate; Deposit the pad nitride layer on the surface of the pad oxide layer; Using patterned photoresist as a mask, the pad nitride layer, the pad oxide layer, and the substrate are etched to form trenches on the substrate.

10. A semiconductor structure, characterized in that, It is prepared according to the method for preparing the semiconductor structure according to any one of claims 1 to 9.

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