Adjustable positive and negative high voltage generator suspended on high voltage and working method thereof

Abstract

The invention discloses an adjustable positive and negative high voltage generator suspended on high voltage and a working method thereof, and belongs to the field of electron gun driving and acceleration control in an electron optical system. The master control MCU is connected with the isolation drive DAC I, the isolation drive DAC II, the isolation drive DAC III and the voltage monitoring module, the isolation drive DAC is connected with the operational amplifier, the operational amplifier is connected with the inverter circuits, the inverter circuit I, the inverter circuit II and the inverter circuit III are connected with the operational amplifier processing module, the inverter circuit I is connected with the voltage doubling circuit with the output being HVout-, and the inverter circuit II is connected with the voltage doubling circuit with the output being HVout-. The inverter circuit I is connected with the inverter circuit I, the inverter circuit II is connected with the voltage doubling circuit with the output being HVout, the inverter circuit III is connected with the voltage doubling circuit with the output being HVout +, the voltage doubling circuit with the output being HVout-is connected with the voltage doubling circuit with the output being HVout, the voltage doubling circuit with the output being HVout + and the sampling voltage module, and the sampling voltage module is further connected with the operational amplifier processing module and the voltage monitoring module. The high-voltage power supply is also used for solving the problem that a common high-voltage power supply cannot adjust positive and negative high-voltage generators suspended on high voltage at a low-voltage end.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electron gun driving and acceleration control in electron optical systems, and particularly relates to a positive and negative adjustable high-voltage generator suspended on high voltage and a working method thereof. BACKGROUND

[0002] In modern electron optical equipment, the electron gun is one of the core components, and its performance directly determines the beam quality, system stability and final imaging or processing quality. Especially in field emission electron guns (including hot field emission and cold field emission), the generation, extraction, acceleration and purification process of the electron beam depends on the precise voltage cooperation between multiple electrodes, mainly including: 1. Extraction electrode voltage: used to generate a strong electric field at the cathode tip to extract electrons; 2. Suppressor electrode voltage: used to suppress the parasitic electron emission of non-emission areas and prevent scattered electrons from interfering; 3. Acceleration voltage: provides initial kinetic energy for the electron beam to control its penetration depth and imaging characteristics.

[0003] These voltages must be coordinated and highly stable, and their reference potential must be suspended on a high-voltage platform to adapt to the multi-stage electrode structure inside the electron gun.

[0004] Currently, ordinary high-voltage power supplies on the market mostly use an inverter circuit combined with a voltage doubler rectifier to achieve voltage boosting, and their output reference ground is generally the earth, and the output voltage is usually single polarity, with limited adjustment range and stability. This type of power supply is widely used in electrostatic spraying, electrostatic adsorption, high-voltage generation and other occasions, but it cannot meet the coordinated control requirements of the electron gun for multiple suspended high voltages, mainly in: Lack of potential suspension capability: the output reference ground of ordinary high-voltage power supplies is a fixed ground potential, which cannot realize potential isolation and coordination between multiple electrodes; Poor coordination of multiple outputs: the electron gun requires three voltages of extraction, suppression and acceleration to cooperate with each other, and ordinary power supplies cannot achieve synchronous adjustment and stable coordination; Single function: unable to provide positive and negative adjustable high voltage at the same time, making it difficult to meet the coexistence requirements of the extraction electrode (positive voltage) and the suppression electrode (negative voltage).

[0005] Therefore, there is still a lack of an integrated power supply system in the prior art that can provide multiple suspended high voltages for the electron gun, with high stability, independent adjustment and coordinated work. Especially in high-end equipment such as high-resolution scanning electron microscopes and electron beam lithography, the quality of the electron beam directly depends on the performance of the high-voltage power supply, and the traditional power supply has become a bottleneck restricting the performance improvement of the system. SUMMARY

[0006] The application provides a positive and negative high-voltage generator suspended on high voltage and a working method thereof, which aims at solving the problem that the common high-voltage power supply cannot adjust the positive and negative high-voltage generator suspended on high voltage at the low-voltage end, and the voltage of the reference high voltage (suspension) of the common high-voltage power supply cannot be adjusted.

[0007] The application is realized by the following technical scheme: The application provides a positive and negative high-voltage generator suspended on high voltage, which comprises a master control MCU, an isolation driving DAC I, an isolation driving DAC II, an isolation driving DAC III, an operational amplifier I, an operational amplifier II, an operational amplifier III, an inverter circuit I, an inverter circuit II, an inverter circuit III, a voltage doubler circuit with an output of H_Vout-, a voltage doubler circuit with an output of H_Vout, a voltage doubler circuit with an output of H_Vout+, a sampling voltage module, an operational amplifier processing module and a voltage monitoring module. The master control MCU is connected with the isolation driving DAC I, the isolation driving DAC II, the isolation driving DAC III and the voltage monitoring module respectively, the isolation driving DAC I is connected with the operational amplifier I, the isolation driving DAC II is connected with the operational amplifier II, the isolation driving DAC III is connected with the operational amplifier III, the operational amplifier I is connected with the inverter circuit I, the operational amplifier II is connected with the inverter circuit II, the operational amplifier III is connected with the inverter circuit III, the inverter circuit I is further connected with the inverter circuit II, the inverter circuit III and the operational amplifier processing module, the inverter circuit I is connected with the voltage doubler circuit with an output of H_Vout-, the inverter circuit II is connected with the voltage doubler circuit with an output of H_Vout, the inverter circuit III is connected with the voltage doubler circuit with an output of H_Vout+, the voltage doubler circuit with an output of H_Vout- is connected with the voltage doubler circuit with an output of H_Vout, the voltage doubler circuit with an output of H_Vout+ and the sampling voltage module respectively, and the sampling voltage module is further connected with the operational amplifier processing module and the voltage monitoring module.

[0008] 2. The adjustable positive and negative high voltage generator according to claim 1, wherein the main control MCU sends signals to the isolation driving DAC I, the isolation driving DAC II and the isolation driving DAC III, the isolation driving DAC I sends signals to the operational amplifier I, the isolation driving DAC II sends signals to the operational amplifier II, the isolation driving DAC III sends signals to the operational amplifier III, the operational amplifier I sends signals to the inverter circuit I, the operational amplifier II sends signals to the inverter circuit II, the operational amplifier III sends signals to the inverter circuit III, the inverter circuit I sends signals to the voltage doubler circuit outputting H_Vout-, the inverter circuit II sends signals to the voltage doubler circuit outputting H_Vout, the inverter circuit III sends signals to the voltage doubler circuit outputting H_Vout+, the voltage doubler circuit outputting H_Vout- and the voltage doubler circuit outputting H_Vout+ both send signals to the voltage doubler circuit outputting H_Vout and the sampling voltage module, the voltage doubler circuit outputting H_Vout also sends signals to the sampling voltage module, the sampling voltage module sends signals to the operational amplifier processing module and the voltage monitoring module, and the voltage monitoring module sends the monitored information to the main control MCU.

[0009] Further, the isolation driving DAC specifically comprises a chip U3, the No. 1 terminal of the chip U3 is connected with the No. 1 terminal of a chip U5 and a working voltage 3V3_ISO respectively, the No. 2 terminal of the chip U3 is connected with the No. 8 terminal of the chip U3 and one end of a resistor R12, one end of a resistor R11, one end of a resistor R10, one end of a resistor R9 respectively after being connected with an isolation ground, the other end of the resistor R12 is connected with the No. 3 terminal of the chip U3 and the main control MCU respectively, the other end of the resistor R11 is connected with the No. 4 terminal of the chip U3 and the main control MCU respectively, the other end of the resistor R10 is connected with the No. 5 terminal of the chip U3 and the main control MCU respectively, the other end of the resistor R9 is connected with the No. 6 terminal of the chip U3 and the main control MCU respectively, the No. 10 terminal of the chip U3 is connected with one end of a resistor R5, the No. 11 terminal of the chip U3 is connected with the No. 4 terminal of a chip U4, the No. 12 terminal of the chip U3 is connected with the No. 4 terminal of a chip U1, the No. 13 terminal of the chip U3 is connected with the No. 5 terminal of the chip U1, the No. 5 terminal of the chip U4 and the No. 5 terminal of a chip U7 respectively, the No. 14 terminal of the chip U3 is connected with the No. 6 terminal of the chip U1, the No. 6 terminal of the chip U4 and the No. 6 terminal of the chip U7 respectively, and the No. 16 terminal of the chip U3 is connected with the other end of the resistor R5, a working voltage VCC, the No. 8 terminal of the chip U1, the No. 8 terminal of the chip U4 and the No. 8 terminal of the chip U7 respectively. The No. 9 terminal of the chip U3 is connected with the No. 15 terminal of the chip U3 and then connected with the ground. The 2nd end of the chip U5 is connected with one end of the resistor R19, the 3rd end of the chip U5 is connected with one end of the resistor R20 and the master control MCU respectively, the 4th end of the chip U5 is connected with the other end of the resistor R19 and the other end of the resistor R20 respectively and then connected with the isolation ground, the 8th end of the chip U5 is connected with the working voltage VCC, the 6th end of the chip U5 is connected with the 4th end of the chip U7, the 7th end of the chip U5 is connected with one end of the resistor R18, the 5th end of the chip U5 is connected with the other end of the resistor R18 and then connected with the ground; The 7th end of the chip U1 is connected with the 7th end of the chip U4 and the 7th end of the chip U7 respectively, the 2nd end of the chip U1 is connected with the 2nd end of the chip U4 and the 2nd end of the chip U7 respectively and then connected with the ground, the 3rd end of the chip U1 is connected with the working voltage VDD, the 3rd end of the chip U4 and the 3rd end of the chip U7 respectively; The 1st end of the chip U1 is connected with one end of the resistor R4, the other end of the resistor R4 is connected with the 5th end of the operational amplifier U2B, the 6th end of the operational amplifier U2B is connected with one end of the resistor R1 and one end of the resistor R2 respectively, the other end of the resistor R1 is connected with the ground, the other end of the resistor R2 is connected with one end of the resistor R3 and the 7th end of the operational amplifier U2B respectively, the other end of the resistor R3 is connected with one end of the capacitor C1 and the Vout_- end respectively, the other end of the capacitor C1 is connected with the ground; The 1st end of the chip U4 is connected with one end of the resistor R13, the other end of the resistor R13 is connected with the 3rd end of the operational amplifier U2A, the 2nd end of the operational amplifier U2A is connected with one end of the resistor R6 and one end of the resistor R7 respectively, the other end of the resistor R6 is connected with the ground, the other end of the resistor R7 is connected with one end of the resistor R8 and the 1st end of the operational amplifier U2A respectively, the other end of the resistor R8 is connected with one end of the capacitor C2 and the Vout_F end respectively, the other end of the capacitor C2 is connected with the ground; The 1st end of the chip U7 is connected with one end of the resistor R16, the other end of the resistor R16 is connected with the 3rd end of the operational amplifier U6, the 4th end of the operational amplifier U6 is connected with one end of the resistor R14 and one end of the resistor R15 respectively, the other end of the resistor R14 is connected with the ground, the other end of the resistor R15 is connected with one end of the resistor R17 and the 1st end of the operational amplifier U6 respectively, the other end of the resistor R17 is connected with one end of the capacitor C3 and the Vout_+ end respectively, the other end of the capacitor C3 is connected with the ground.

[0010] Furthermore, the Vout_- terminal is connected to one end of capacitor C6 and one side of the same-name terminal of the first group of transformer T1, respectively. The other end of capacitor C6 is connected to the collector of transistor Q1 and one side of the opposite-name terminal of the first group of transformer T1, respectively. The emitter of transistor Q1 is connected to ground. The base of transistor Q1 is connected to the same-name terminal of the second group of transformer T1, respectively. The opposite-name terminal of the second group of transformer T1 is connected to one end of resistor R25, and the other end of resistor R25 is connected to the collector of transistor Q2 and one end of capacitor C9, respectively. The other end of capacitor C9 is connected to ground. The base of transistor Q2 is connected to ground after being connected in series with resistor R21. The other side of the same-name terminal of the first group of transformer T1 is connected to one end of capacitor C4. The other end of capacitor C4 is connected to the anode of diode D1, the cathode of diode D2, and one end of capacitor C5. The other side of the opposite-name terminal of the first group of transformer T1 is connected to one end of resistor R22, terminal 5 of operational amplifier U19B, the cathode of diode D1, one end of capacitor C7, and the output terminal H_Vout. The other end of capacitor C5 is connected to the anode of diode D3 and the cathode of diode D4. The other end of capacitor C7 is connected to... The anode of diode D2 and the cathode of diode D3 are connected to one end of capacitor C8. The other end of capacitor C8 is connected to the anode of diode D4, one end of resistor R24, and the output terminal H_Vout-. The other end of resistor R22 is connected to one end of resistor R23 and one end of resistor R73. The other end of resistor R23 is connected to the other end of resistor R24. The other end of resistor R73 is connected to terminal 6 of operational amplifier U19B and one end of resistor R78. The other end of resistor R78 is connected to terminal 7 of operational amplifier U19B. One end of resistor R49 is connected to the other end of resistor R49, which is connected to one end of resistor R71, one end of capacitor C28, and terminal 2 of chip U18. Terminal 1 of chip U18 is connected to the operating voltage H_VCC for floating power supply. Terminal 3 of chip U18 is connected to terminal 4 of chip U18, the other end of resistor R71, the other end of capacitor C28, and the output terminal H_Vout. Terminal 5 of chip U18 is connected to one end of resistor R72 and then to ground. Terminal 6 of chip U18 is connected to resistor R71... One end of the chip U18 is connected to the terminal of the IC U18. The 7th terminal of the IC U18 is connected to one end of the resistor R50. The other end of the resistor R70, one end of the resistor R72, and one end of the resistor R74 are connected to the 6th terminal of the op-amp U21B. The 7th terminal of the op-amp U21B is connected to the other end of the resistor R74 and one end of the resistor R69. The other end of the resistor R69 is connected to one end of the capacitor C29 and the output terminal Vout_fb-. The other end of the capacitor C29 is connected to ground. The 8th terminal of the chip U18 is connected to the operating voltage VCC.

[0011] Furthermore, the Vout_F terminal is connected to one end of capacitor C13 and one side of the same-name terminal of the first group of transformer T2, respectively. The other end of capacitor C13 is connected to the collector of transistor Q3 and one side of the opposite-name terminal of the first group of transformer T2, respectively. The emitter of transistor Q3 is connected to ground, the base of transistor Q3 is connected to the same-name terminal of the second group of transformer T2, the opposite-name terminal of the second group of transformer T2 is connected to one end of resistor R37, the other end of resistor R37 is connected to the collector of transistor Q4 and one end of capacitor C17, the other end of capacitor C17 is connected to ground, the base of transistor Q4 is connected to ground after series with resistor R26, and the emitter of transistor Q4 is connected to the emitter of transistor Q2, the emitter of transistor Q6, one end of resistor R35, and one end of capacitor C18, respectively. The other end of capacitor C18 is connected to ground. The other end of resistor R35 is connected to one end of resistor R27 and terminal 7 of operational amplifier U8B. The other end of resistor R27 is connected to terminal 6 of operational amplifier U8B and one end of resistor R34. Terminal 5 of operational amplifier U8B is connected to ground. The other end of resistor R34 is connected to one end of resistor R29 and terminal 1 of operational amplifier U8A. The other end of resistor R29 is connected to terminal 2 of operational amplifier U8A, one end of resistor R28, and one end of resistor R36. Terminal 3 of operational amplifier U8A is connected to ground. The other end of resistor R28 is connected to the output terminal Vout_fb. The other end of resistor R36 is connected to the output terminal Refer_volt. The other side of the same-name terminal of the first group of transformer T2 is connected to one end of capacitor C10. The other end of capacitor C10 is connected to the negative terminal of diode D5, the positive terminal of diode D6, and one end of capacitor C11. The other side of the opposite-name terminal of the first group of transformer T2 is connected to one end of resistor R30, the positive terminal of diode D5, and one end of capacitor C14, and then connected to ground. The other end of resistor R30 is connected to one end of resistor R31 and the output terminal Vout_fb. The other end of resistor R31 is connected to one end of resistor R32. The other end of resistor R32 is connected to... One end of R33 is connected, the other end of resistor R33 is connected to one end of resistor R51, the other end of resistor R51 is connected to one end of resistor R52, the other end of resistor R52 is connected to the cathode of diode D9, one end of capacitor C16, and the output terminal H_Vout, the other end of capacitor C16 is connected to the anode of diode D8, the cathode of diode D7, and one end of capacitor C15, the anode of diode D7 is connected to one end of capacitor C12, and the other end of capacitor C12 is connected to the cathode of diode D8 and the anode of diode D9.

[0012] Furthermore, the Vout_+ terminal is connected to one end of capacitor C21 and one side of the same-name terminal of the first group of transformer T3, respectively. The other end of capacitor C21 is connected to the collector of transistor Q5 and one side of the opposite-name terminal of the first group of transformer T3, respectively. The emitter of transistor Q5 is connected to ground. The base of transistor Q5 is connected to the same-name terminal of the second group of transformer T3, respectively. The opposite-name terminal of the second group of transformer T3 is connected to one end of resistor R42, respectively. The other end of resistor R42 is connected to the collector of transistor Q6 and one end of capacitor C24, respectively. The other end of capacitor C24 is connected to ground. The base of transistor Q6 is connected to ground after being connected in series with resistor R38. The other side of the same-name terminal of the first group of transformer T3 is connected to one end of capacitor C19. The other end of capacitor C19 is connected to the negative terminal of diode D10, the positive terminal of diode D11, and one end of capacitor C20. The other side of the opposite-name terminal of the first group of transformer T3 is connected to one end of resistor R39, the positive terminal of diode D10, one end of capacitor C22, and the output terminal H_Vout. The other end of capacitor C20 is connected to the negative terminal of diode D12 and the positive terminal of diode D13. The other end of capacitor C22 is connected to the negative terminal of diode D11, the positive terminal of diode D12, and one end of capacitor C23. The other end of capacitor C23 is connected to the negative terminal of diode D13, one end of resistor R41, and the output terminal H_Vout+. The other end of resistor R39 is connected to one end of resistor R40 and terminal 3 of operational amplifier U19A. The other end of resistor R40 is connected to the other end of resistor R41. Terminal 2 of operational amplifier U19A is connected to terminal 1 of operational amplifier U19A and one end of resistor R77. The other end of resistor R77 is connected to one end of resistor R56, one end of capacitor C30, and terminal 2 of chip U20. Terminal 1 of chip U20 is connected to the floating power supply of operating voltage H_VCC. Terminal 3 of chip U20 is connected to terminal 4 of chip U20, the other end of resistor R56, the other end of capacitor C30, and the output terminal H_Vout. Terminal 5 of chip U20 is connected to one end of resistor R75 and then grounded. Terminal 6 of chip U20 is connected to one end of resistor R55. The following connections are made: terminal 7 of chip U20 is connected to one end of resistor R53; the other end of resistor R53 is connected to terminal 3 of operational amplifier U21A; the other end of resistor R55 is connected to the other end of resistor R75, one end of resistor R76, and terminal 2 of operational amplifier U21A; terminal 1 of operational amplifier U21A is connected to the other end of resistor R76 and one end of resistor R54; the other end of resistor R54 is connected to one end of capacitor C31 and the output terminal Vout_fb+; the other end of capacitor C31 is grounded; and terminal 8 of chip U20 is connected to the operating voltage VCC.

[0013] Furthermore, the output terminal Vout_fb is connected to one end of resistor R48, the other end of resistor R48 is connected to terminal 3 of integrated operational amplifier U11, terminal 4 of integrated operational amplifier U11 is connected to terminal 1 of integrated operational amplifier U11 and one end of resistor R47, the other end of resistor R47 is connected to one end of capacitor C25 and terminal 1 of chip U9, terminal 3 of chip U9 is connected to one end of resistor R43 and terminal 6 of chip U10, terminal 2 of chip U9 is connected to terminal 6 and then grounded, terminal 5 of chip U9 is connected to the other end of resistor R43, one end of resistor R44, terminal 8 of chip U10 and the operating voltage VCC, terminal 4 of chip U9 is connected to the other end of resistor R44 and terminal 7 of chip U10, and terminal 5 of chip U10 is grounded; Terminal 1 of chip U10 is connected to one end of resistor R45, the operating voltage 3V3_ISO, and one end of resistor R46. The other end of resistor R45 is connected to terminal 2 of chip U10 and the main control MCU. Terminal 3 of chip U10 is connected to the other end of resistor R46 and the main control MCU. Terminal 4 of chip U10 is connected to isolation ground.

[0014] Furthermore, the output terminal Vout_fb- is also connected to one end of resistor R62, the other end of resistor R62 is connected to terminal 3 of integrated operational amplifier U14, terminal 4 of integrated operational amplifier U14 is connected to terminal 1 of integrated operational amplifier U14 and one end of resistor R61, the other end of resistor R61 is connected to one end of capacitor C26 and terminal 1 of chip U12, terminal 3 of chip U12 is connected to one end of resistor R57 and terminal 6 of chip U13, terminal 2 of chip U12 is connected to terminal 6 and then grounded, terminal 5 of chip U12 is connected to the other end of resistor R57, one end of resistor R58, terminal 8 of chip U13 and the operating voltage VCC, terminal 4 of chip U12 is connected to the other end of resistor R58 and terminal 7 of chip U13, and terminal 5 of chip U13 is grounded; Terminal 1 of chip U13 is connected to one end of resistor R59, the operating voltage 3V3_ISO, and one end of resistor R60. The other end of resistor R59 is connected to terminal 2 of chip U13 and the main control MCU. Terminal 3 of chip U13 is connected to the other end of resistor R60 and the main control MCU. Terminal 4 of chip U13 is connected to isolation ground.

[0015] Furthermore, the output terminal Vout_fb+ is also connected to one end of resistor R68. The other end of resistor R68 is connected to terminal 3 of integrated operational amplifier U17. Terminal 4 of integrated operational amplifier U17 is connected to terminal 1 of integrated operational amplifier U17 and one end of resistor R67. The other end of resistor R67 is connected to one end of capacitor C27 and terminal 1 of chip U15. Terminal 3 of chip U15 is connected to one end of resistor R63 and terminal 6 of chip U16. Terminals 2 and 6 of chip U15 are connected to ground. Terminal 5 of chip U15 is connected to the other end of resistor R63, one end of resistor R64, terminal 8 of chip U16, and the operating voltage VCC. Terminal 4 of chip U15 is connected to the other end of resistor R64 and terminal 7 of chip U16. Terminal 5 of chip U16 is connected to ground. Terminal 1 of chip U16 is connected to one end of resistor R65, the operating voltage 3V3_ISO, and one end of resistor R66. The other end of resistor R65 is connected to terminal 2 of chip U16 and the main control MCU. Terminal 3 of chip U16 is connected to the other end of resistor R66 and the main control MCU. Terminal 4 of chip U16 is connected to isolation ground.

[0016] A method for operating an adjustable positive and negative high-voltage generator suspended above high voltage is disclosed. The method utilizes the aforementioned adjustable positive and negative high-voltage generator suspended above high voltage. Specifically, an MCU connected to an isolation chip controls three DACs: isolation driver DACⅠ, isolation driver DACⅡ, and isolation driver DACⅢ, which output three voltages respectively. These three voltages are amplified by operational amplifiers Ⅰ, Ⅱ, and Ⅲ, respectively, and then used to control the output voltages of three inverter circuits. The three inverter circuits are connected to voltage multiplier circuits with outputs H_Vout-, H_Vout, and H_Vout+ respectively for voltage multiplication. After voltage multiplication, the three voltage multiplier circuits output H_Vout-, H_Vout, and H_Vout+ respectively. The three high-voltage circuits then pass through a sampling voltage module. The sampled voltage Vout_fb at the output H_Vout voltage is processed by an operational amplifier and then sent to inverter circuit I, inverter circuit II, and inverter circuit III respectively to operate the inverter circuits. At the same time, the sampled voltage Vout_fb at the output H_Vout- and the sampled voltage Vout_fb+ at the output H_Vout+ are sent to the MCU for voltage monitoring to monitor the output voltage in real time.

[0017] The beneficial effects of this invention are: This invention is not an ordinary high-voltage power supply, but uses very few electronic components, and can adjust the positive and negative high-voltage generators suspended on the high voltage at the low-voltage end, and can also adjust the voltage of the reference high voltage (suspended).

[0018] This invention can realize multiple independent adjustable high voltage outputs, corresponding to extraction electrode, suppression electrode and acceleration electrode respectively; In this invention, all output reference potentials are suspended on a high-voltage platform to meet the potential coordination requirements between the electrodes inside the electron gun. This invention supports both positive and negative high voltage outputs to adapt to the polarity requirements of different electrodes; This invention has coordinated control capabilities, ensuring that multiple voltages remain synchronized and stable during dynamic adjustment.

[0019] The implementation of this invention will significantly improve the beam quality, system stability, and imaging resolution of the electron gun, and is applicable to fields such as electron microscopes, electron beam processing equipment, and surface analysis instruments, and has important scientific value and engineering application prospects. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of the present invention.

[0021] Figure 2 This is a schematic diagram of the DAC voltage output principle of the present invention.

[0022] Figure 3 This is a schematic diagram of the inverter circuit, voltage multiplier circuit, and sampling voltage of the present invention.

[0023] Figure 4 This is a schematic diagram of the voltage monitoring principle of the present invention. Detailed Implementation

[0024] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of this application with unnecessary detail.

[0025] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0026] It should also be understood that the terminology used in this application specification is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this application specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0027] The following is in conjunction with the appendix to this application specification. Figures 1-4 The technical solutions in the embodiments of this application are clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0028] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0029] Implementation Method 1 This embodiment provides an adjustable positive and negative high-voltage generator suspended above high voltage, such as... Figure 1As shown, the generator includes a main control MCU, isolation driver DACⅠ, isolation driver DACⅡ, isolation driver DACⅢ, operational amplifier Ⅰ, operational amplifier Ⅱ, operational amplifier Ⅲ, inverter circuit Ⅰ, inverter circuit Ⅱ, inverter circuit Ⅲ, voltage doubler circuit with output H_Vout-, voltage doubler circuit with output H_Vout, voltage doubler circuit with output H_Vout+, sampling voltage module, operational amplifier processing module, and voltage monitoring module; The main control MCU is connected to the isolation driver DACⅠ, isolation driver DACⅡ, isolation driver DACⅢ, and voltage monitoring module. The isolation driver DACⅠ is connected to operational amplifier Ⅰ, the isolation driver DACⅡ is connected to operational amplifier Ⅱ, and the isolation driver DACⅢ is connected to operational amplifier Ⅲ. Operational amplifier Ⅰ is connected to inverter circuit Ⅰ, operational amplifier Ⅱ is connected to inverter circuit Ⅱ, and operational amplifier Ⅲ is connected to inverter circuit Ⅲ. Inverter circuit Ⅰ is also connected to inverter circuit Ⅱ, inverter circuit Ⅲ, and operational amplifier processing module. Inverter circuit Ⅰ is connected to a voltage multiplier circuit with output H_Vout-. Inverter circuit Ⅱ is connected to a voltage multiplier circuit with output H_Vout. Inverter circuit Ⅲ is connected to a voltage multiplier circuit with output H_Vout+. The voltage multiplier circuit with output H_Vout- is connected to the voltage multiplier circuit with output H_Vout, the voltage multiplier circuit with output H_Vout+, and sampling voltage module. The sampling voltage module is also connected to operational amplifier processing module and voltage monitoring module.

[0030] Furthermore, such as Figure 1 As shown, the main control MCU sends signals to isolated driver DACⅠ, isolated driver DACⅡ, and isolated driver DACⅢ. Isolated driver DACⅠ sends a signal to operational amplifier Ⅰ, isolated driver DACⅡ sends a signal to operational amplifier Ⅱ, and isolated driver DACⅢ sends a signal to operational amplifier Ⅲ. Operational amplifier Ⅰ sends a signal to inverter circuit Ⅰ, operational amplifier Ⅱ sends a signal to inverter circuit Ⅱ, and operational amplifier Ⅲ sends a signal to inverter circuit Ⅲ. Inverter circuit Ⅰ sends a signal to a voltage doubler circuit with output H_Vout-, and inverter circuit Ⅱ sends a signal to the output... The inverter circuit III sends a signal to the voltage doubler circuit with output H_Vout+. Both the voltage doubler circuit with output H_Vout- and the voltage doubler circuit with output H_Vout+ send signals to the voltage doubler circuit with output H_Vout and the sampling voltage module. The voltage doubler circuit with output H_Vout also sends a signal to the sampling voltage module. The sampling voltage module sends a signal to the operational amplifier processing module and the voltage monitoring module. The voltage monitoring module sends the monitored information to the main control MCU.

[0031] Furthermore, such as Figure 2As shown, the isolated driver DAC specifically includes chip U3. Terminal 1 of chip U3 is connected to terminal 1 of chip U5 and the operating voltage 3V3_ISO. Terminal 2 of chip U3 is connected to terminal 8 of chip U3 and one end of resistors R12, R11, R10, and R9, then connected to isolation ground. The other end of resistor R12 is connected to terminal 3 of chip U3 and the main control MCU. The other end of resistor R11 is connected to terminal 4 of chip U3 and the main control MCU. The other end of resistor R10 is connected to terminal 5 of chip U3 and the main control MCU. The other end of resistor R9 is connected to... Pin 6 of chip U3 is connected to the main control MCU. Pin 10 of chip U3 is connected to one end of resistor R5. Pin 11 of chip U3 is connected to pin 4 of chip U4. Pin 12 of chip U3 is connected to pin 4 of chip U1. Pin 13 of chip U3 is connected to pins 5 of chip U1, 5 of chip U4, and 5 of chip U7. Pin 14 of chip U3 is connected to pins 6 of chip U1, 6 of chip U4, and 6 of chip U7. Pin 16 of chip U3 is connected to the other end of resistor R5, the operating voltage VCC, pin 8 of chip U1, pin 8 of chip U4, and pin 8 of chip U7. The 9th terminal of the chip U3 is connected to the 15th terminal of the chip U3 and then connected to ground. Terminal 2 of chip U5 is connected to one end of resistor R19. Terminal 3 of chip U5 is connected to one end of resistor R20 and the main control MCU. Terminal 4 of chip U5 is connected to the other ends of resistor R19 and resistor R20, and then connected to isolation ground. Terminal 8 of chip U5 is connected to the operating voltage VCC. Terminal 6 of chip U5 is connected to terminal 4 of chip U7. Terminal 7 of chip U5 is connected to one end of resistor R18. Terminal 5 of chip U5 is connected to the other end of resistor R18 and then connected to ground. Terminal 7 of chip U1 is connected to terminal 7 of chip U4 and terminal 7 of chip U7 respectively. Terminal 2 of chip U1 is connected to terminal 2 of chip U4 and terminal 2 of chip U7 respectively and then connected to ground. Terminal 3 of chip U1 is connected to the working voltage VDD, terminal 3 of chip U4 and terminal 3 of chip U7 respectively. Terminal 1 of chip U1 is connected to one end of resistor R4, and the other end of resistor R4 is connected to terminal 5 of operational amplifier U2B. Terminal 6 of operational amplifier U2B is connected to one end of resistor R1 and one end of resistor R2. The other end of resistor R1 is connected to ground. The other end of resistor R2 is connected to one end of resistor R3 and terminal 7 of operational amplifier U2B. The other end of resistor R3 is connected to one end of capacitor C1 and the Vout_- terminal. The other end of capacitor C1 is connected to ground. Terminal 1 of chip U4 is connected to one end of resistor R13, and the other end of resistor R13 is connected to terminal 3 of operational amplifier U2A. Terminal 2 of operational amplifier U2A is connected to one end of resistor R6 and one end of resistor R7, and the other end of resistor R6 is connected to ground. The other end of resistor R7 is connected to one end of resistor R8 and one end of operational amplifier U2A, and the other end of resistor R8 is connected to one end of capacitor C2 and the Vout_F terminal, and the other end of capacitor C2 is connected to ground. Terminal 1 of chip U7 is connected to one end of resistor R16. The other end of resistor R16 is connected to terminal 3 of operational amplifier U6. Terminal 4 of operational amplifier U6 is connected to one end of resistor R14 and one end of resistor R15. The other end of resistor R14 is connected to ground. The other end of resistor R15 is connected to one end of resistor R17 and terminal 1 of operational amplifier U6. The other end of resistor R17 is connected to one end of capacitor C3 and the Vout_+ terminal. The other end of capacitor C3 is connected to ground.

[0032] Furthermore, such as Figure 3 As shown, the Vout_- terminal is connected to one end of capacitor C6 and one side of the same-name terminal of the first group of transformer T1. The other end of capacitor C6 is connected to the collector of transistor Q1 and one side of the opposite-name terminal of the first group of transformer T1. The emitter of transistor Q1 is grounded. The base of transistor Q1 is connected to the same-name terminal of the second group of transformer T1. The opposite-name terminal of the second group of transformer T1 is connected to one end of resistor R25. The other end of resistor R25 is connected to the collector of transistor Q2 and one end of capacitor C9. The other end of capacitor C9 is connected to ground. The base of transistor Q2 is connected to ground after being connected in series with resistor R21. The other side of the same-name terminal of the first group of transformer T1 is connected to one end of capacitor C4. The other end of capacitor C4 is connected to the anode of diode D1, the cathode of diode D2, and one end of capacitor C5. The other side of the opposite-name terminal of the first group of transformer T1 is connected to one end of resistor R22, terminal 5 of operational amplifier U19B, the cathode of diode D1, one end of capacitor C7, and the output terminal H_Vout. The other end of capacitor C5 is connected to the anode of diode D3 and the cathode of diode D4. The other end of capacitor C7 is connected to... The diode D2 is connected to the anode of the diode D2, the cathode of the diode D3, and one end of the capacitor C8. The other end of the capacitor C8 is connected to the anode of the diode D4, one end of the resistor R24, and the output terminal H_Vout-. The other end of the resistor R22 is connected to one end of the resistor R23 and one end of the resistor R73. The other end of the resistor R23 is connected to the other end of the resistor R24. The other end of the resistor R73 is connected to one end of the resistor R78 and terminal 6 of the operational amplifier U19B. The other end of the resistor R78 is connected to terminal 7 of the operational amplifier U19B. One end of the first terminal is connected to one end of resistor R49. The other end of resistor R49 is connected to one end of resistor R71, one end of capacitor C28, and terminal 2 of chip U18. Terminal 1 of chip U18 is connected to the operating voltage H_VCC. Terminal 3 of chip U18 is connected to terminal 4 of chip U18, the other end of resistor R71, the other end of capacitor C28, and the output terminal H_Vout. Terminal 5 of chip U18 is connected to one end of resistor R72 and then grounded. Terminal 6 of chip U18 is connected to one end of resistor R70. The terminals are connected as follows: terminal 7 of chip U18 is connected to one end of resistor R50; the other end of resistor R70 is connected to the other end of resistor R72, one end of resistor R74, and terminal 6 of operational amplifier U21B; terminal 7 of operational amplifier U21B is connected to the other end of resistor R74 and one end of resistor R69; the other end of resistor R69 is connected to one end of capacitor C29 and the output terminal Vout_fb-; the other end of capacitor C29 is connected to ground; and terminal 8 of chip U18 is connected to the operating voltage VCC.

[0033] Furthermore, such as Figure 3As shown, the Vout_F terminal is connected to one end of capacitor C13 and one side of the same-name terminal of the first group of transformer T2. The other end of capacitor C13 is connected to the collector of transistor Q3 and one side of the opposite-name terminal of the first group of transformer T2. The emitter of transistor Q3 is connected to ground. The base of transistor Q3 is connected to the same-name terminal of the second group of transformer T2. The opposite-name terminal of the second group of transformer T2 is connected to one end of resistor R37. The other end of resistor R37 is connected to the collector of transistor Q4 and one end of capacitor C17. The other end of capacitor C17 is connected to ground. The base of transistor Q4 is connected to ground after series with resistor R26. The emitter of transistor Q4 is connected to the emitters of transistors Q2 and Q6, one end of resistor R35, and one end of capacitor C18. The other end of capacitor C18 is connected to ground. The other end of resistor R35 is connected to one end of resistor R27 and terminal 7 of operational amplifier U8B. The other end of resistor R27 is connected to terminal 6 of operational amplifier U8B and one end of resistor R34. Terminal 5 of operational amplifier U8B is connected to ground. The other end of resistor R34 is connected to one end of resistor R29 and terminal 1 of operational amplifier U8A. The other end of resistor R29 is connected to terminal 2 of operational amplifier U8A, one end of resistor R28, and one end of resistor R36. Terminal 3 of operational amplifier U8A is connected to ground. The other end of resistor R28 is connected to the output terminal Vout_fb. The other end of resistor R36 is connected to the output terminal Refer_volt. The other side of the same-name terminal of the first group of transformer T2 is connected to one end of capacitor C10. The other end of capacitor C10 is connected to the negative terminal of diode D5, the positive terminal of diode D6, and one end of capacitor C11. The other side of the opposite-name terminal of the first group of transformer T2 is connected to one end of resistor R30, the positive terminal of diode D5, and one end of capacitor C14, and then connected to ground. The other end of resistor R30 is connected to one end of resistor R31 and the output terminal Vout_fb. The other end of resistor R31 is connected to one end of resistor R32. The other end of resistor R32 is connected to... One end of R33 is connected, the other end of resistor R33 is connected to one end of resistor R51, the other end of resistor R51 is connected to one end of resistor R52, the other end of resistor R52 is connected to the cathode of diode D9, one end of capacitor C16, and the output terminal H_Vout, the other end of capacitor C16 is connected to the anode of diode D8, the cathode of diode D7, and one end of capacitor C15, the anode of diode D7 is connected to one end of capacitor C12, and the other end of capacitor C12 is connected to the cathode of diode D8 and the anode of diode D9.

[0034] Furthermore, such asFigure 3 As shown, the Vout_+ terminal is connected to one end of capacitor C21 and one side of the same-name terminal of the first group of transformer T3, respectively. The other end of capacitor C21 is connected to the collector of transistor Q5 and one side of the opposite-name terminal of the first group of transformer T3, respectively. The emitter of transistor Q5 is grounded. The base of transistor Q5 is connected to the same-name terminal of the second group of transformer T3, respectively. The opposite-name terminal of the second group of transformer T3 is connected to one end of resistor R42, respectively. The other end of resistor R42 is connected to the collector of transistor Q6 and one end of capacitor C24, respectively. The other end of capacitor C24 is connected to ground, and the base of transistor Q6 is connected to ground after being connected in series with resistor R38. The other side of the same-name terminal of the first group of transformer T3 is connected to one end of capacitor C19. The other end of capacitor C19 is connected to the cathode of diode D10, the anode of diode D11, and one end of capacitor C20. The other side of the opposite-name terminal of the first group of transformer T3 is connected to one end of resistor R39, the anode of diode D10, one end of capacitor C22, and the output terminal H_Vout. The other end of capacitor C20 is connected to the cathode of diode D12 and the anode of diode D13. The other end of capacitor C22 is connected to the cathode of diode D11, the anode of diode D12, and one end of capacitor C23. The other end of capacitor C23 is connected to the cathode of diode D13, one end of resistor R41, and the output terminal H_Vout+. The other end of resistor R39 is connected to one end of resistor R40 and terminal 3 of operational amplifier U19A. The other end of resistor R40 is connected to the other end of resistor R41. Terminal 2 of operational amplifier U19A is connected to terminal 1 of operational amplifier U19A and one end of resistor R77. The other end of resistor R77 is connected to one end of resistor R56, one end of capacitor C30, and terminal 2 of chip U20. Terminal 1 of chip U20 is connected to the operating voltage H_VCC. Terminal 3 of chip U20 is connected to terminal 4 of chip U20, the other end of resistor R56, the other end of capacitor C30, and the output terminal H_Vout. Terminal 5 of chip U20 is connected to one end of resistor R75 and then grounded. Terminal 6 of chip U20 is connected to one end of resistor R55. Then, terminal 7 of chip U20 is connected to one end of resistor R53, the other end of resistor R53 is connected to terminal 3 of operational amplifier U21A, the other end of resistor R55 is connected to the other end of resistor R75, one end of resistor R76 and terminal 2 of operational amplifier U21A respectively, terminal 1 of operational amplifier U21A is connected to the other end of resistor R76 and one end of resistor R54 respectively, the other end of resistor R54 is connected to one end of capacitor C31 and the output terminal Vout_fb+ respectively, the other end of capacitor C31 is connected to ground, and terminal 8 of chip U20 is connected to the operating voltage VCC.

[0035] Furthermore, such as Figure 4 As shown, the output terminal Vout_fb is also connected to one end of resistor R48. The other end of resistor R48 is connected to terminal 3 of integrated operational amplifier U11. Terminal 4 of integrated operational amplifier U11 is connected to terminal 1 of integrated operational amplifier U11 and one end of resistor R47. The other end of resistor R47 is connected to one end of capacitor C25 and terminal 1 of chip U9. Terminal 3 of chip U9 is connected to one end of resistor R43 and terminal 6 of chip U10. Terminals 2 and 6 of chip U9 are connected to ground. Terminal 5 of chip U9 is connected to the other end of resistor R43, one end of resistor R44, terminal 8 of chip U10, and the operating voltage VCC. Terminal 4 of chip U9 is connected to the other end of resistor R44 and terminal 7 of chip U10. Terminal 5 of chip U10 is connected to ground. Terminal 1 of chip U10 is connected to one end of resistor R45, the operating voltage 3V3_ISO, and one end of resistor R46. The other end of resistor R45 is connected to terminal 2 of chip U10 and the main control MCU. Terminal 3 of chip U10 is connected to the other end of resistor R46 and the main control MCU. Terminal 4 of chip U10 is connected to isolation ground.

[0036] Furthermore, such as Figure 4As shown, the output terminal Vout_fb- is also connected to one end of resistor R62. The other end of resistor R62 is connected to terminal 3 of integrated operational amplifier U14. Terminal 4 of integrated operational amplifier U14 is connected to terminal 1 of integrated operational amplifier U14 and one end of resistor R61. The other end of resistor R61 is connected to one end of capacitor C26 and terminal 1 of chip U12. Terminal 3 of chip U12 is connected to one end of resistor R57 and terminal 6 of chip U13. Terminals 2 and 6 of chip U12 are connected to ground. Terminal 5 of chip U12 is connected to the other end of resistor R57, one end of resistor R58, terminal 8 of chip U13, and the operating voltage VCC. Terminal 4 of chip U12 is connected to the other end of resistor R58 and terminal 7 of chip U13. Terminal 5 of chip U13 is connected to ground. Terminal 1 of chip U13 is connected to one end of resistor R59, the operating voltage 3V3_ISO, and one end of resistor R60. The other end of resistor R59 is connected to terminal 2 of chip U13 and the main control MCU. Terminal 3 of chip U13 is connected to the other end of resistor R60 and the main control MCU. Terminal 4 of chip U13 is connected to isolation ground.

[0037] Furthermore, such as Figure 4 As shown, the output terminal Vout_fb+ is also connected to one end of resistor R68. The other end of resistor R68 is connected to terminal 3 of integrated operational amplifier U17. Terminal 4 of integrated operational amplifier U17 is connected to terminal 1 of integrated operational amplifier U17 and one end of resistor R67. The other end of resistor R67 is connected to one end of capacitor C27 and terminal 1 of chip U15. Terminal 3 of chip U15 is connected to one end of resistor R63 and terminal 6 of chip U16. Terminals 2 and 6 of chip U15 are connected to ground. Terminal 5 of chip U15 is connected to the other end of resistor R63, one end of resistor R64, terminal 8 of chip U16, and the operating voltage VCC. Terminal 4 of chip U15 is connected to the other end of resistor R64 and terminal 7 of chip U16. Terminal 5 of chip U16 is connected to ground. Terminal 1 of chip U16 is connected to one end of resistor R65, the operating voltage 3V3_ISO, and one end of resistor R66. The other end of resistor R65 is connected to terminal 2 of chip U16 and the main control MCU. Terminal 3 of chip U16 is connected to the other end of resistor R66 and the main control MCU. Terminal 4 of chip U16 is connected to isolation ground.

[0038] Implementation Method 2 This embodiment provides a method for operating an adjustable positive and negative high-voltage generator suspended above high voltage. The method uses the adjustable positive and negative high-voltage generator described in Embodiment 1. Specifically, an MCU connected to an isolation chip controls three DACs to output three voltages. These three voltages are amplified by operational amplifiers and used to control the output voltages of three inverter circuits. The three inverter circuits are connected to three voltage multiplier circuits for voltage multiplication. After voltage multiplication, the three voltage multiplier circuits output H_Vout (providing floating high voltage to H_Vout- and H_Vout+), H_Vout- (a negative voltage floating on H_Vout), and H_Vout+ (a positive voltage floating on H_Vout), respectively. The three high voltages are then sampled. The sampled voltage on H_Vout is processed by operational amplifiers and sent to the three inverter circuits for inverter operation. Simultaneously, the sampled voltage on H_Vout and the remaining sampled voltage are fed into the MCU via voltage monitoring for real-time monitoring of the output voltage.

[0039] The maximum output voltage relative to ground is +8KV (adjustable); H_Vout- is -2KV relative to the maximum output voltage relative to H_Vout (adjustable); H_Vout+ is +2KV relative to the maximum output voltage relative to H_Vout (adjustable), and the output voltage is monitored in real time. The above voltages can be determined based on the given... Figure 1 After slight deformation, it automatically increases the maximum output voltage.

[0040] like Figure 2As shown, to prevent damage to the MCU after a high voltage anomaly, the MCU in this diagram is isolated by isolation chips U3 and U5 and then controlled by DACs U1, U4, and U7 via SPI communication. (Resistors R9, R10, R11, R12, R18, R19, and R20 are pull-down resistors connected to pins 3, 4, 5, and 6 of U3 and pins 2, 3, and 7 of U5, respectively. They provide a stable low-level reference to prevent signal floating and logic corruption, and also serve multiple functions such as anti-interference and circuit protection. Resistor R5 acts as a high-level logic input. When VE2 is high or off, VOA, VOB, and VOC outputs are enabled. When VE2 is low, VOA, VOB, and VOC outputs are disabled. In noisy environments, connecting VE2 to a high level via R5 ensures that the U3 output is enabled.) U1, U4, and U7 output V_DAC1, V_DCA2, and V_DCA3 respectively under MCU control. V_DAC1 is input to pin 5 of op-amp U2B after passing through R4. One end of resistor R1 is connected to pin 6 of op-amp U2B, and the other end is connected to ground. Resistor R2 is connected across pins 6 and 7 of op-amp U2B. Pin 7 of op-amp U2B, after low-pass filtering by resistor R3 and capacitor C1, outputs Vout-, which is used to control the voltage regulation of the negative high voltage (H_Vout-) floating on the H_Vout high voltage. The output principles of V_DCA2 and V_DCA3 are the same and will not be repeated here. Vout_F is used to control the voltage output of H_Vout, and Vout_+ is used to control the voltage regulation of the positive high voltage (H_Vout+) floating on H_Vout.

[0041] like Figure 3 As shown, Vout_-: as above Figure 3 The upper coil of the primary winding of transformer T1 is connected to one end of capacitor C6. The other end of the upper coil of the primary winding of transformer T1 and the other end of capacitor C6 are connected to the collector of transistor Q1. The LC circuit oscillates in the switching state of transistor Q1, with an oscillation frequency of:

[0042] The emitter of transistor Q1 is connected to ground. After power-on, the reference level Refer_volt is connected to pin 2 of op-amp U8A through resistor R36. The sampled voltage Vout_fb is connected to pin 2 of op-amp U8A through resistor R28. Pin 3 of U8A is connected to ground. Resistor R29 is connected between pins 1 and 2 of op-amp U8A.

[0043] The output voltage at pin 1 of op-amp U8A = -(((Refer_volt / R36) + (Vout_fb / R28)) * R29) Then, it is connected to pin 6 of op-amp U8B via resistor R34. Pin 5 of op-amp U8B is connected to ground. Resistor R27 is connected between pins 6 and 7 of op-amp U8B. The output voltage at pin 7 of op-amp U8B = R27 / R34 * (((Refer_volt / R36) + (Vout_fb / R28)) * R29) After passing through resistor R35 and capacitor C18 for low-pass filtering, the filtered voltage is input to the emitter of transistor Q2. The base of transistor Q2 is grounded through resistor R21, keeping the transistor in the ON state. The collector output of transistor Q2 is filtered by capacitor C9 and input to one end of resistor R25. The other end of resistor R25 is connected to one end of the lower coil of the primary winding of transformer T1, and the other end of the lower coil is connected to the base of transistor Q1. Bias resistor R25 provides the starting current. Transistor Q1 switches at high speed (saturation and cutoff) in the positive feedback loop formed by the upper and lower coils of the primary winding of transformer T1. When the transistor suddenly cuts off from saturation, the current in the transformer's upper coil is instantaneously interrupted. Due to the strong inertia of the inductor, it generates an extremely high reverse induced electromotive force (EMF). This induced EMF is coupled to the secondary coil of transformer T1 through the transformer core. According to the turns ratio formula, the voltage of the secondary coil ≈ induced EMF * secondary turns / primary upper coil turns. After the above process, transformer T1 operates in inverter mode. The secondary output voltage is multiplied by capacitors C4, C7, C5, C8, and diodes D1, D2, D3, and D4 to obtain voltage H_Vout-. The reference ground of the secondary winding of transformer T1 is connected to H_Vout. Additionally, one end of resistors R22, R23, and R24 is connected to H_Vout, and the other end is connected to H_Vout-. The voltage sampled from circuit R22 is connected to one end of resistor R73. The other end of resistor R73 is connected to pin 6 of op-amp U19B and one end of resistor R78. Pin 5 of op-amp U19B is connected to H_Vout. The other end of resistor R78 and pin 7 of op-amp U19B are connected to one end of resistor R49. The other end of resistor R49 is connected to pin 2 of isolation op-amp U18 and one end of resistor R71 and capacitor C28. The other ends of resistor R71 and capacitor C28 are connected to H_Vout. Pins 3 and 4 of isolation op-amp U18 are connected to H_Vout, and pin 1 is connected to H_VCC (H_VCC is a floating power supply; since floating power supplies are currently existing technology, they will not be explained in detail here).

[0044] Pin 7 of isolation op-amp U18 is connected to one end of resistor R50, and the other end of resistor R50 is connected to pin 5 of op-amp U21B. Pin 6 of isolation op-amp U18 is connected to one end of resistor R70, and the other end of resistor R70 is connected to pin 6 of op-amp U21B and one end of resistor R72. The other end of resistor R72 is connected to ground. Resistor R74 is connected across pins 6 and 7 of op-amp U21B. The output of pin 7 of op-amp U21B is low-pass filtered by resistor R69 and capacitor C29 to obtain Vout_fb- (the negative high voltage monitoring voltage floating on H_Vout).

[0045] Vout_F: As above Figure 3 The upper coil of the primary winding of transformer T2 is connected to one end of capacitor C13. The other end of the upper coil of the primary winding of transformer T2 and the other end of capacitor C13 are connected to the collector of transistor Q3. The LC circuit oscillates in the switching state of transistor Q3, with an oscillation frequency of:

[0046] The emitter of transistor Q3 is connected to ground. After power-on, the reference level Refer_volt is connected to pin 2 of op-amp U8A through resistor R36. The sampling voltage Vout_fb is also connected to pin 2 of op-amp U8A through resistor R28. Pin 3 of U8A is connected to ground. Resistor R29 is connected between pins 1 and 2 of op-amp U8A.

[0047] The output voltage at pin 1 of op-amp U8A = -(((Refer_volt / R36) + (Vout_fb / R28)) * R29) Then, it is connected to pin 6 of op-amp U8B via resistor R34. Pin 5 of op-amp U8B is connected to ground. Resistor R27 is connected between pins 6 and 7 of op-amp U8B. The output voltage at pin 7 of op-amp U8B = R27 / R34 * (((Refer_volt / R36) + (Vout_fb / R28)) * R29) After low-pass filtering by resistor R35 and capacitor C18, the filtered voltage is input to the emitter of transistor Q4. The base of transistor Q4 is grounded through resistor R26, keeping the transistor on. The collector output of transistor Q4 is filtered by capacitor C17 and input to one end of resistor R37. The other end of resistor R37 is connected to one end of the lower coil of the primary winding of transformer T2. The other end of the lower coil is connected to the base of transistor Q3. Bias resistor R37 provides the starting current. Transistor Q3 switches at high speed (saturation and cutoff) in the positive feedback loop formed by the upper and lower coils of the primary winding of transformer T2. When the transistor suddenly cuts off from saturation, the current in the upper coil of the transformer is instantaneously cut off. Due to the strong inertia of the inductor, it generates an extremely high reverse induced electromotive force (EMF). This induced EMF is coupled to the secondary coil of transformer T2 through the transformer core. According to the turns ratio formula, the voltage of the secondary coil ≈ induced EMF * number of secondary turns / number of turns of the primary upper coil. After the above process, transformer T2 operates in inverter mode. The secondary output voltage is multiplied by capacitors C10, C11, C12, C14, C15, C16 and diodes D5, D6, D7, D8, D9 to obtain voltage H_Vout. The reference ground of the secondary winding of transformer T2 is connected to PE. Resistors R30, R31, R32, R33, R51, and R52 are as described above. Figure 3 One end is connected to PE, and the other end is connected to H_Vout. A sampling voltage Vout_fb (the monitoring voltage of H_Vout) is obtained at resistor R30.

[0048] Vout_+: As above Figure 3 The upper coil of the primary winding of transformer T3 is connected to one end of capacitor C21. The other end of the upper coil of the primary winding of transformer T3 and the other end of capacitor C21 are connected to the collector of transistor Q5. The LC circuit oscillates in the switching state of transistor Q5, with an oscillation frequency of:

[0049] The emitter of transistor Q5 is connected to ground. After power-on, the reference level Refer_volt is connected to pin 2 of op-amp U8A through resistor R36. The sampling voltage Vout_fb is also connected to pin 2 of op-amp U8A through resistor R28. Pin 3 of U8A is connected to ground. Resistor R29 is connected between pins 1 and 2 of op-amp U8A.

[0050] The output voltage at pin 1 of op-amp U8A = -(((Refer_volt / R36) + (Vout_fb / R28)) * R29) Then, it is connected to pin 6 of op-amp U8B via resistor R34. Pin 5 of op-amp U8B is connected to ground. Resistor R27 is connected between pins 6 and 7 of op-amp U8B. The output voltage at pin 7 of op-amp U8B = R27 / R34 * (((Refer_volt / R36)(Vout_fb / R28)) * R29) After low-pass filtering by resistor R35 and capacitor C18, the filtered voltage is input to the emitter of transistor Q6. The base of transistor Q6 is grounded through resistor R38, keeping the transistor on. The collector output of transistor Q6 is filtered by capacitor C24 and input to one end of resistor R42. The other end of resistor R42 is connected to one end of the lower coil of the primary winding of transformer T3. The other end of the lower coil is connected to the base of transistor Q5. Bias resistor R42 provides the starting current. Transistor Q5 switches at high speed (saturation and cutoff) in the positive feedback loop formed by the upper and lower coils of the primary winding of transformer T3. When the transistor suddenly cuts off from saturation, the current in the upper coil of the transformer is instantly cut off. Due to the strong inertia of the inductor, it generates an extremely high reverse induced electromotive force (EMF). This induced EMF is coupled to the secondary coil of transformer T3 through the transformer core. According to the turns ratio formula, the voltage of the secondary coil ≈ induced EMF * number of secondary turns / number of turns of the primary upper coil. After the above process, transformer T3 operates in inverter mode. The secondary output voltage is multiplied by capacitors C19, C22, C20, C23 and diodes D10, D11, D12, D13 to obtain voltage H_Vout+. The reference ground of the secondary winding of transformer T3 is connected to H_Vout. Additionally, resistors R39, R40, and R41 are connected in series as shown above. Figure 3 One end is connected to H_Vout, and the other end is connected to H_Vout+. The other end of resistor R39 is connected to pin 3 of op-amp U19A. Pins 1 and 2 of op-amp U19A are cascaded. Pin 1 of op-amp U19A is connected to one end of resistor R77. The other end of resistor R77 is connected to pin 2 of isolation op-amp U20 and one end of resistor R56 and capacitor C30. The other end of resistor R56 and capacitor C30 is connected to H_Vout. Pins 3 and 4 of isolation op-amp U20 are connected to H_Vout. Pin 7 of isolation op-amp U20 is connected to one end of resistor R53. The other end of resistor R53... One end is connected to pin 3 of op-amp U21, pin 6 of isolation op-amp U20 is connected to one end of resistor R55, the other end of resistor R55 is connected to pin 2 of op-amp U21A and one end of resistor R75, the other end of resistor R75 is connected to ground, and resistor R76 is connected across pins 1 and 2 of op-amp U21A. The output of pin 1 of op-amp U21A is low-pass filtered by resistor R54 and capacitor C31 to obtain the sampling voltage Vout_fb+ (the positive high voltage monitoring voltage floating on H_Vout).

[0051] like Figure 4As shown, the sampled voltage Vout_fb is connected to pin 3 of op-amp U11 via resistor R48. Pins 4 and 1 of op-amp U11 are cascaded to form a voltage follower output. The output voltage from pin 1 of op-amp U11 is low-pass filtered by resistor R47 and capacitor C25 and then connected to pin 1 of chip U9. Pins 2 and 6 of chip U9 are connected to PE, and pin 5 is connected to VCC. Pins 3 and 4 of chip U9 are connected to pull-up resistors R43 and R44, respectively. Pins 3 and 4 of chip U9 are then connected to pins 6 and 7 of chip U10, respectively. Pins 2 and 3 of chip U10 are connected to the MCU via pull-up resistors R45 and R46 for voltage monitoring through IIC communication.

[0052] The sampled voltage Vout_fb- is connected to pin 3 of op-amp U14 via resistor R62. Pins 4 and 1 of op-amp U14 are cascaded to form a voltage follower output. The output voltage from pin 1 of op-amp U14 is low-pass filtered by resistor R61 and capacitor C26 and then connected to pin 1 of chip U12. Pins 2 and 6 of chip U12 are connected to PE, and pin 5 is connected to VCC. Pins 3 and 4 of chip U12 are connected to pull-up resistors R57 and R58, respectively. Pins 3 and 4 of chip U12 are then connected to pins 6 and 7 of chip U13, respectively. Pins 2 and 3 of chip U13 are connected to the MCU via pull-up resistors R59 and R60 for voltage monitoring through IIC communication.

[0053] The sampled voltage Vout_fb+ is connected to pin 3 of op-amp U17 via resistor R68. Pins 4 and 1 of op-amp U17 are cascaded to form a voltage follower output. The output voltage from pin 1 of op-amp U17 is low-pass filtered by resistor R67 and capacitor C27 and then connected to pin 1 of chip U15. Pins 2 and 6 of chip U15 are connected to PE, and pin 5 is connected to VCC. Pins 3 and 4 of chip U15 are connected to pull-up resistors R63 and R64, respectively. Pins 3 and 4 of chip U15 are then connected to pins 6 and 7 of chip U16, respectively. Pins 2 and 3 of chip U16 are connected to the MCU via pull-up resistors R65 and R66 for voltage monitoring through IIC communication.

[0054] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An adjustable positive and negative high-voltage generator suspended above high voltage, characterized in that, The generator includes a main control MCU, isolated driver DACⅠ, isolated driver DACⅡ, isolated driver DACⅢ, operational amplifier Ⅰ, operational amplifier Ⅱ, operational amplifier Ⅲ, inverter circuit Ⅰ, inverter circuit Ⅱ, inverter circuit Ⅲ, voltage doubler circuit with output H_Vout-, voltage doubler circuit with output H_Vout, voltage doubler circuit with output H_Vout+, sampling voltage module, operational amplifier processing module, and voltage monitoring module; The main control MCU is connected to the isolation driver DACⅠ, isolation driver DACⅡ, isolation driver DACⅢ, and voltage monitoring module. The isolation driver DACⅠ is connected to operational amplifier Ⅰ, the isolation driver DACⅡ is connected to operational amplifier Ⅱ, and the isolation driver DACⅢ is connected to operational amplifier Ⅲ. Operational amplifier Ⅰ is connected to inverter circuit Ⅰ, operational amplifier Ⅱ is connected to inverter circuit Ⅱ, and operational amplifier Ⅲ is connected to inverter circuit Ⅲ. Inverter circuit Ⅰ is also connected to inverter circuit Ⅱ, inverter circuit Ⅲ, and operational amplifier processing module. Inverter circuit Ⅰ is connected to a voltage multiplier circuit with output H_Vout-. Inverter circuit Ⅱ is connected to a voltage multiplier circuit with output H_Vout. Inverter circuit Ⅲ is connected to a voltage multiplier circuit with output H_Vout+. The voltage multiplier circuit with output H_Vout- is connected to the voltage multiplier circuit with output H_Vout, the voltage multiplier circuit with output H_Vout+, and sampling voltage module. The sampling voltage module is also connected to operational amplifier processing module and voltage monitoring module.

2. The adjustable positive and negative high-voltage generator according to claim 1, characterized in that, The main control MCU sends signals to isolated driver DACⅠ, isolated driver DACⅡ, and isolated driver DACⅢ. Isolated driver DACⅠ sends a signal to operational amplifier Ⅰ, isolated driver DACⅡ sends a signal to operational amplifier Ⅱ, and isolated driver DACⅢ sends a signal to operational amplifier Ⅲ. Operational amplifier Ⅰ sends a signal to inverter circuit Ⅰ, operational amplifier Ⅱ sends a signal to inverter circuit Ⅱ, and operational amplifier Ⅲ sends a signal to inverter circuit Ⅲ. Inverter circuit Ⅰ sends a signal to a voltage doubler circuit with output H_Vout-, and inverter circuit Ⅱ sends a signal to a voltage doubler circuit with output H_Vout-. The voltage doubler circuit with output H_Vout sends a signal, and the inverter circuit III sends a signal to the voltage doubler circuit with output H_Vout+. Both the voltage doubler circuit with output H_Vout- and the voltage doubler circuit with output H_Vout+ send signals to the voltage doubler circuit with output H_Vout and the sampling voltage module. The voltage doubler circuit with output H_Vout also sends a signal to the sampling voltage module. The sampling voltage module sends a signal to the operational amplifier processing module and the voltage monitoring module. The voltage monitoring module sends the monitored information to the main control MCU.

3. The adjustable positive and negative high-voltage generator according to claim 1, characterized in that, The isolated driver DAC specifically includes chip U3. Terminal 1 of chip U3 is connected to terminal 1 of chip U5 and the operating voltage 3V3_ISO. Terminal 2 of chip U3 is connected to terminal 8 of chip U3 and one end of resistors R12, R11, R10, and R9, then connected to isolation ground. The other end of resistor R12 is connected to terminal 3 of chip U3 and the main control MCU. The other end of resistor R11 is connected to terminal 4 of chip U3 and the main control MCU. The other end of resistor R10 is connected to terminal 5 of chip U3 and the main control MCU. The other end of resistor R9 is connected to... Terminal 6 of chip U3 is connected to the main control MCU. Terminal 10 of chip U3 is connected to one end of resistor R5. Terminal 11 of chip U3 is connected to terminal 4 of chip U4. Terminal 12 of chip U3 is connected to terminal 4 of chip U1. Terminal 13 of chip U3 is connected to terminal 5 of chip U1, terminal 5 of chip U4, and terminal 5 of chip U7. Terminal 14 of chip U3 is connected to terminal 6 of chip U1, terminal 6 of chip U4, and terminal 6 of chip U7. Terminal 16 of chip U3 is connected to the other end of resistor R5, the operating voltage VCC, terminal 8 of chip U1, terminal 8 of chip U4, and terminal 8 of chip U7. The 9th terminal of the chip U3 is connected to the 15th terminal of the chip U3 and then connected to ground. Terminal 2 of chip U5 is connected to one end of resistor R19. Terminal 3 of chip U5 is connected to one end of resistor R20 and the main control MCU. Terminal 4 of chip U5 is connected to the other ends of resistor R19 and resistor R20, and then connected to isolation ground. Terminal 8 of chip U5 is connected to the operating voltage VCC. Terminal 6 of chip U5 is connected to terminal 4 of chip U7. Terminal 7 of chip U5 is connected to one end of resistor R18. Terminal 5 of chip U5 is connected to the other end of resistor R18 and then connected to ground. Terminal 7 of chip U1 is connected to terminal 7 of chip U4 and terminal 7 of chip U7 respectively. Terminal 2 of chip U1 is connected to terminal 2 of chip U4 and terminal 2 of chip U7 respectively and then connected to ground. Terminal 3 of chip U1 is connected to the working voltage VDD, terminal 3 of chip U4 and terminal 3 of chip U7 respectively. Terminal 1 of chip U1 is connected to one end of resistor R4, and the other end of resistor R4 is connected to terminal 5 of operational amplifier U2B. Terminal 6 of operational amplifier U2B is connected to one end of resistor R1 and one end of resistor R2. The other end of resistor R1 is connected to ground. The other end of resistor R2 is connected to one end of resistor R3 and terminal 7 of operational amplifier U2B. The other end of resistor R3 is connected to one end of capacitor C1 and the Vout_- terminal. The other end of capacitor C1 is connected to ground. Terminal 1 of chip U4 is connected to one end of resistor R13, and the other end of resistor R13 is connected to terminal 3 of operational amplifier U2A. Terminal 2 of operational amplifier U2A is connected to one end of resistor R6 and one end of resistor R7, and the other end of resistor R6 is connected to ground. The other end of resistor R7 is connected to one end of resistor R8 and one end of operational amplifier U2A, and the other end of resistor R8 is connected to one end of capacitor C2 and the Vout_F terminal, and the other end of capacitor C2 is connected to ground. Terminal 1 of chip U7 is connected to one end of resistor R16. The other end of resistor R16 is connected to terminal 3 of operational amplifier U6. Terminal 4 of operational amplifier U6 is connected to one end of resistor R14 and one end of resistor R15. The other end of resistor R14 is connected to ground. The other end of resistor R15 is connected to one end of resistor R17 and terminal 1 of operational amplifier U6. The other end of resistor R17 is connected to one end of capacitor C3 and the Vout_+ terminal. The other end of capacitor C3 is connected to ground.

4. The adjustable positive and negative high-voltage generator according to claim 3, characterized in that, The Vout_- terminal is connected to one end of capacitor C6 and one side of the same-name terminal of the first group of transformer T1. The other end of capacitor C6 is connected to the collector of transistor Q1 and one side of the opposite-name terminal of the first group of transformer T1. The emitter of transistor Q1 is connected to ground. The base of transistor Q1 is connected to the same-name terminal of the second group of transformer T1. The opposite-name terminal of the second group of transformer T1 is connected to one end of resistor R25. The other end of resistor R25 is connected to the collector of transistor Q2 and one end of capacitor C9. The other end of capacitor C9 is connected to ground. The base of transistor Q2 is connected to ground after being connected in series with resistor R21. The other side of the same-name terminal of the first group of transformer T1 is connected to one end of capacitor C4. The other end of capacitor C4 is connected to the anode of diode D1, the cathode of diode D2, and one end of capacitor C5. The other side of the opposite-name terminal of the first group of transformer T1 is connected to one end of resistor R22, terminal 5 of operational amplifier U19B, the cathode of diode D1, one end of capacitor C7, and the output terminal H_Vout. The other end of capacitor C5 is connected to the anode of diode D3 and the cathode of diode D4. The other end of capacitor C7 is connected to... The anode of diode D2 and the cathode of diode D3 are connected to one end of capacitor C8. The other end of capacitor C8 is connected to the anode of diode D4, one end of resistor R24, and the output terminal H_Vout-. The other end of resistor R22 is connected to one end of resistor R23 and one end of resistor R73. The other end of resistor R23 is connected to the other end of resistor R24. The other end of resistor R73 is connected to terminal 6 of operational amplifier U19B and one end of resistor R78. The other end of resistor R78 is connected to terminal 7 of operational amplifier U19B. One end of resistor R49 is connected to the other end of resistor R49, which is connected to one end of resistor R71, one end of capacitor C28, and terminal 2 of chip U18. Terminal 1 of chip U18 is connected to the operating voltage H_VCC for floating power supply. Terminal 3 of chip U18 is connected to terminal 4 of chip U18, the other end of resistor R71, the other end of capacitor C28, and the output terminal H_Vout. Terminal 5 of chip U18 is connected to one end of resistor R72 and then to ground. Terminal 6 of chip U18 is connected to resistor R71... One end of the chip U18 is connected to the terminal of the IC U18. The 7th terminal of the IC U18 is connected to one end of the resistor R50. The other end of the resistor R70, one end of the resistor R72, and one end of the resistor R74 are connected to the 6th terminal of the op-amp U21B. The 7th terminal of the op-amp U21B is connected to the other end of the resistor R74 and one end of the resistor R69. The other end of the resistor R69 is connected to one end of the capacitor C29 and the output terminal Vout_fb-. The other end of the capacitor C29 is connected to ground. The 8th terminal of the chip U18 is connected to the operating voltage VCC.

5. The adjustable positive and negative high-voltage generator according to claim 4, characterized in that, The Vout_F terminal is connected to one end of capacitor C13 and one side of the same-name terminal of the first group of transformer T2. The other end of capacitor C13 is connected to the collector of transistor Q3 and one side of the opposite-name terminal of the first group of transformer T2. The emitter of transistor Q3 is connected to ground. The base of transistor Q3 is connected to the same-name terminal of the second group of transformer T2. The opposite-name terminal of the second group of transformer T2 is connected to one end of resistor R37. The other end of resistor R37 is connected to the collector of transistor Q4 and one end of capacitor C17. The other end of capacitor C17 is connected to ground. The base of transistor Q4 is connected to ground after series with resistor R26. The emitter of transistor Q4 is connected to the emitter of transistor Q2, the emitter of transistor Q6, one end of resistor R35, and one end of capacitor C18. The other end of capacitor C18 is connected to ground. The other end of resistor R35 is connected to one end of resistor R27 and terminal 7 of operational amplifier U8B. The other end of resistor R27 is connected to terminal 6 of operational amplifier U8B and one end of resistor R34. Terminal 5 of operational amplifier U8B is connected to ground. The other end of resistor R34 is connected to one end of resistor R29 and terminal 1 of operational amplifier U8A. The other end of resistor R29 is connected to terminal 2 of operational amplifier U8A, one end of resistor R28, and one end of resistor R36. Terminal 3 of operational amplifier U8A is connected to ground. The other end of resistor R28 is connected to the output terminal Vout_fb. The other end of resistor R36 is connected to the output terminal Refer_volt. The other side of the same-name terminal of the first group of transformer T2 is connected to one end of capacitor C10. The other end of capacitor C10 is connected to the negative terminal of diode D5, the positive terminal of diode D6, and one end of capacitor C11. The other side of the opposite-name terminal of the first group of transformer T2 is connected to one end of resistor R30, the positive terminal of diode D5, and one end of capacitor C14, and then connected to ground. The other end of resistor R30 is connected to one end of resistor R31 and the output terminal Vout_fb. The other end of resistor R31 is connected to one end of resistor R32. The other end of resistor R32 is connected to... One end of R33 is connected, the other end of resistor R33 is connected to one end of resistor R51, the other end of resistor R51 is connected to one end of resistor R52, the other end of resistor R52 is connected to the cathode of diode D9, one end of capacitor C16, and the output terminal H_Vout, the other end of capacitor C16 is connected to the anode of diode D8, the cathode of diode D7, and one end of capacitor C15, the anode of diode D7 is connected to one end of capacitor C12, and the other end of capacitor C12 is connected to the cathode of diode D8 and the anode of diode D9.

6. The adjustable positive and negative high-voltage generator according to claim 5, characterized in that, The Vout_+ terminal is connected to one end of capacitor C21 and one side of the same-name terminal of the first group of transformer T3. The other end of capacitor C21 is connected to the collector of transistor Q5 and one side of the opposite-name terminal of the first group of transformer T3. The emitter of transistor Q5 is connected to ground. The base of transistor Q5 is connected to the same-name terminal of the second group of transformer T3. The opposite-name terminal of the second group of transformer T3 is connected to one end of resistor R42. The other end of resistor R42 is connected to the collector of transistor Q6 and one end of capacitor C24. The other end of capacitor C24 is connected to ground. The base of transistor Q6 is connected to ground after being connected in series with resistor R38. The other side of the same-name terminal of the first group of transformer T3 is connected to one end of capacitor C19. The other end of capacitor C19 is connected to the negative terminal of diode D10, the positive terminal of diode D11, and one end of capacitor C20. The other side of the opposite-name terminal of the first group of transformer T3 is connected to one end of resistor R39, the positive terminal of diode D10, one end of capacitor C22, and the output terminal H_Vout. The other end of capacitor C20 is connected to the negative terminal of diode D12 and the positive terminal of diode D13. The other end of capacitor C22 is connected to the negative terminal of diode D11, the positive terminal of diode D12, and one end of capacitor C23. The other end of capacitor C23 is connected to the negative terminal of diode D13, one end of resistor R41, and the output terminal H_Vout+. The other end of resistor R39 is connected to one end of resistor R40 and terminal 3 of operational amplifier U19A. The other end of resistor R40 is connected to the other end of resistor R41. Terminal 2 of operational amplifier U19A is connected to terminal 1 of operational amplifier U19A and one end of resistor R77. The other end of resistor R77 is connected to one end of resistor R56, one end of capacitor C30, and terminal 2 of chip U20. Terminal 1 of chip U20 is connected to the floating power supply of operating voltage H_VCC. Terminal 3 of chip U20 is connected to terminal 4 of chip U20, the other end of resistor R56, the other end of capacitor C30, and the output terminal H_Vout. Terminal 5 of chip U20 is connected to one end of resistor R75 and then grounded. Terminal 6 of chip U20 is connected to one end of resistor R55. The following connections are made: terminal 7 of chip U20 is connected to one end of resistor R53; the other end of resistor R53 is connected to terminal 3 of operational amplifier U21A; the other end of resistor R55 is connected to the other end of resistor R75, one end of resistor R76, and terminal 2 of operational amplifier U21A; terminal 1 of operational amplifier U21A is connected to the other end of resistor R76 and one end of resistor R54; the other end of resistor R54 is connected to one end of capacitor C31 and the output terminal Vout_fb+; the other end of capacitor C31 is grounded; and terminal 8 of chip U20 is connected to the operating voltage VCC.

7. The adjustable positive and negative high-voltage generator according to claim 6, characterized in that, The output terminal Vout_fb is also connected to one end of resistor R48. The other end of resistor R48 is connected to terminal 3 of integrated operational amplifier U11. Terminal 4 of integrated operational amplifier U11 is connected to terminal 1 of integrated operational amplifier U11 and one end of resistor R47. The other end of resistor R47 is connected to one end of capacitor C25 and terminal 1 of chip U9. Terminal 3 of chip U9 is connected to one end of resistor R43 and terminal 6 of chip U10. Terminals 2 and 6 of chip U9 are connected to ground. Terminal 5 of chip U9 is connected to the other end of resistor R43, one end of resistor R44, terminal 8 of chip U10, and the operating voltage VCC. Terminal 4 of chip U9 is connected to the other end of resistor R44 and terminal 7 of chip U10. Terminal 5 of chip U10 is connected to ground. Terminal 1 of chip U10 is connected to one end of resistor R45, the operating voltage 3V3_ISO, and one end of resistor R46. The other end of resistor R45 is connected to terminal 2 of chip U10 and the main control MCU. Terminal 3 of chip U10 is connected to the other end of resistor R46 and the main control MCU. Terminal 4 of chip U10 is connected to isolation ground.

8. The adjustable positive and negative high-voltage generator according to claim 5, characterized in that, The output terminal Vout_fb- is also connected to one end of resistor R62. The other end of resistor R62 is connected to terminal 3 of integrated operational amplifier U14. Terminal 4 of integrated operational amplifier U14 is connected to terminal 1 of integrated operational amplifier U14 and one end of resistor R61. The other end of resistor R61 is connected to one end of capacitor C26 and terminal 1 of chip U12. Terminal 3 of chip U12 is connected to one end of resistor R57 and terminal 6 of chip U13. Terminals 2 and 6 of chip U12 are connected to ground. Terminal 5 of chip U12 is connected to the other end of resistor R57, one end of resistor R58, terminal 8 of chip U13, and the operating voltage VCC. Terminal 4 of chip U12 is connected to the other end of resistor R58 and terminal 7 of chip U13. Terminal 5 of chip U13 is connected to ground. Terminal 1 of chip U13 is connected to one end of resistor R59, the operating voltage 3V3_ISO, and one end of resistor R60. The other end of resistor R59 is connected to terminal 2 of chip U13 and the main control MCU. Terminal 3 of chip U13 is connected to the other end of resistor R60 and the main control MCU. Terminal 4 of chip U13 is connected to isolation ground.

9. The adjustable positive and negative high voltage generator according to claim 4, characterized in that, The output terminal Vout_fb+ is also connected to one end of resistor R68. The other end of resistor R68 is connected to terminal 3 of integrated operational amplifier U17. Terminal 4 of integrated operational amplifier U17 is connected to terminal 1 of integrated operational amplifier U17 and one end of resistor R67. The other end of resistor R67 is connected to one end of capacitor C27 and terminal 1 of chip U15. Terminal 3 of chip U15 is connected to one end of resistor R63 and terminal 6 of chip U16. Terminals 2 and 6 of chip U15 are connected to ground. Terminal 5 of chip U15 is connected to the other end of resistor R63, one end of resistor R64, terminal 8 of chip U16, and the operating voltage VCC. Terminal 4 of chip U15 is connected to the other end of resistor R64 and terminal 7 of chip U16. Terminal 5 of chip U16 is connected to ground. Terminal 1 of chip U16 is connected to one end of resistor R65, the operating voltage 3V3_ISO, and one end of resistor R66. The other end of resistor R65 is connected to terminal 2 of chip U16 and the main control MCU. Terminal 3 of chip U16 is connected to the other end of resistor R66 and the main control MCU. Terminal 4 of chip U16 is connected to isolation ground.

10. A method for operating an adjustable positive and negative high-voltage generator suspended above high voltage, characterized in that, The working method uses an adjustable positive and negative high voltage generator suspended on high voltage as described in any one of claims 1-9. Specifically, the working method involves using an MCU connected to an isolation chip to control three DACs, namely, isolation driver DACⅠ, isolation driver DACⅡ, and isolation driver DACⅢ, to output three voltages respectively. The three voltages are amplified by operational amplifier Ⅰ, operational amplifier Ⅱ, and operational amplifier Ⅲ respectively and then used to control the output voltage of the three inverter circuits. The three inverter circuits are connected to voltage multiplier circuits with outputs H_Vout-, H_Vout, and H_Vout+ respectively for voltage multiplication. After voltage multiplication, the three voltage multiplier circuits output H_Vout-, H_Vout, and H_Vout+ respectively. The three high-voltage circuits then pass through a sampling voltage module. The sampled voltage Vout_fb at the output H_Vout voltage is processed by an operational amplifier and then sent to inverter circuit I, inverter circuit II, and inverter circuit III respectively to operate the inverter circuits. At the same time, the sampled voltage Vout_fb at the output H_Vout- and the sampled voltage Vout_fb+ at the output H_Vout+ are sent to the MCU for voltage monitoring to monitor the output voltage in real time.

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