Task profile-based power electronic converter reliability evaluation method and device, electronic equipment and storage medium

Abstract

The invention discloses a reliability evaluation method and device for a power electronic converter based on a mission profile, electronic equipment and a storage medium, and belongs to the field of electronic circuit testing, and the method comprises the steps: obtaining mission profile data and device parameters of the power electronic converter in a work period; the task profile data comprises the environment temperature and the load working condition. And calculating a junction temperature curve of the power semiconductor based on the loss model and the thermal network model, and calculating a core temperature curve of the DC capacitor based on the equivalent model and the thermal impedance model. And extracting thermal characteristics of the devices according to the junction temperature curve and the core temperature curve and calculating the accumulated damage degree of the single devices, thereby completing reliability evaluation of the converter based on the accumulated damage degrees of all the devices. By implementing the method and the device, the problem that the reliability evaluation of the whole converter is inaccurate due to the fact that two differential failure mechanisms of thermal cycle fatigue of a power semiconductor device and thermal stress aging of a direct current capacitor cannot be distinguished in the prior art can be solved.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit testing, and more specifically to a reliability assessment method, apparatus, electronic device, and storage medium for power electronic converters based on task profiles. Background Technology

[0002] As a key core device connecting energy and load, the operational reliability of power electronic converters directly determines the safety and stability of the power system. Traditional reliability assessments are usually based on static analysis under rated or extreme operating conditions, which is difficult to reflect the complex environmental impacts in actual operation. Therefore, the introduction of mission profile technology, which uses time-series data including long-term ambient temperature and load conditions for dynamic assessment, has become the mainstream trend for accurately quantifying the cumulative damage of converters under real operating conditions and achieving accurate life prediction.

[0003] However, existing task profile-based assessment methods still have significant shortcomings in terms of comprehensiveness and mechanism correspondence. Current research mostly focuses on junction temperature fluctuations and fatigue failure of power semiconductor devices, often neglecting the lifespan bottlenecks of key passive components such as DC capacitors, or failing to fully consider the essential differences in the physical mechanisms of failure between the two. The lack of a unified assessment framework that can simultaneously cover these two different damage mechanisms leads to blind spots in the identification of overall converter weaknesses, making it impossible to arrive at objective and accurate overall system reliability assessment conclusions. Summary of the Invention

[0004] This invention provides a reliability assessment method, apparatus, electronic device, and storage medium for power electronic converters based on task profiles. It can solve the problem in the prior art where the reliability assessment of the entire converter is inaccurate because it fails to distinguish between the two different failure mechanisms of thermal cycling fatigue of power semiconductor devices and thermal stress aging of DC capacitors.

[0005] One embodiment of the present invention provides a reliability assessment method for power electronic converters based on task profiles, comprising: The task profile data of the power electronic converter, the characteristic parameters of each power semiconductor device, and the characteristic parameters of each DC capacitor are obtained within a preset working cycle; wherein, the power electronic converter includes several power semiconductor devices and several DC capacitors; the task profile data includes an ambient temperature sequence and a load condition sequence. Based on the mission profile data, and using the preset semiconductor loss model and preset thermal network model, the junction temperature variation curves of each power semiconductor device under the ambient temperature series are determined; based on the mission profile data, and using the preset capacitor equivalent model and preset thermal impedance model, the core temperature variation curves of each DC capacitor under the ambient temperature series are determined. Based on the junction temperature variation curves of each power semiconductor device, the thermal cycling characteristic parameters of each power semiconductor device are determined; based on the core temperature variation curves of each DC capacitor, the thermal stress characteristic parameters of each DC capacitor are determined. Based on the thermal cycling characteristic parameters of each power semiconductor device, the cumulative damage of each individual power semiconductor device is determined; based on the thermal stress characteristic parameters of each DC capacitor, the cumulative damage of each individual DC capacitor is determined; based on the cumulative damage of each individual power semiconductor device and the cumulative damage of each individual DC capacitor, the reliability of the power electronic converter is evaluated.

[0006] Furthermore, based on the mission profile data and a pre-defined semiconductor loss model and thermal network model, the junction temperature variation curves of each power semiconductor device under the ambient temperature sequence are determined, including: Based on the load condition sequence of the mission profile data, determine the load current sequence, voltage sequence, duty cycle sequence of the power electronic converter, and switching frequency sequence of each power semiconductor device. For each power semiconductor device, based on the on-state loss model in the preset semiconductor loss model, the on-state loss power of the current power semiconductor device is calculated and generated according to the load current sequence, the duty cycle sequence, and the characteristic parameters of the current power semiconductor device. Based on the switching loss model in the preset semiconductor loss model, the switching loss power of the current power semiconductor device is calculated and generated according to the load current sequence, the voltage sequence, the switching frequency sequence of the current power semiconductor device, and the characteristic parameters of the current power semiconductor device. Based on the current power loss power and the current power switching loss power of the power semiconductor device, calculate and generate the total power consumption sequence of the current power semiconductor device; The total power consumption sequence of the current power semiconductor device is input into the preset thermal network model, and iterative calculation is performed to generate the junction temperature rise sequence of the current power semiconductor device. Based on the ambient temperature sequence and the junction temperature rise sequence of the current power semiconductor device, determine the junction temperature change curve of the current power semiconductor device under the ambient temperature sequence.

[0007] Furthermore, based on the mission profile data and the preset capacitor equivalent model and thermal impedance model, the core temperature variation curves of each DC capacitor under the ambient temperature series are determined, including: Based on the load condition sequence of the mission profile data, determine the ripple current sequence flowing through each DC capacitor; For each DC capacitor, based on the preset capacitor equivalent model, the power loss sequence of the current DC capacitor is calculated and generated according to the ripple current sequence and characteristic parameters of the current DC capacitor. The power loss sequence of the current DC capacitor is input into the preset thermal impedance model for iterative calculation to generate the core temperature rise sequence of the current DC capacitor. Based on the ambient temperature sequence and the core temperature rise sequence of the current DC capacitor, determine the core temperature change curve of the current DC capacitor under the ambient temperature sequence.

[0008] Furthermore, determining the thermal cycling characteristic parameters of each power semiconductor device based on the junction temperature variation curves of each power semiconductor device includes: For each power semiconductor device, extract the peak and trough points from the junction temperature change curve of the current power semiconductor device to form an extreme point sequence. The extreme point sequence is subjected to cyclic counting to identify several independent thermal cycles contained in the junction temperature change curve of the current power semiconductor device. Extract the thermal cycle characteristic parameters of each of the plurality of thermal cycles; wherein, the thermal cycle characteristic parameters include junction temperature fluctuation amplitude and junction temperature average. The thermal cycling characteristic parameters of the aforementioned thermal cycles are summarized, and the summarized results are used as the thermal cycling characteristic parameters of the current power semiconductor device.

[0009] Furthermore, determining the thermal stress characteristic parameters of each DC capacitor based on the core temperature change curves of each DC capacitor includes: For the core temperature change curve of each DC capacitor, the core temperature change curve of the current DC capacitor is discretized according to the preset sampling frequency to form a core temperature sequence. Extract the core temperature value corresponding to each sampling time in the core temperature sequence; The core temperature value is used as the thermal stress characteristic parameter of the current DC capacitor.

[0010] Furthermore, determining the cumulative damage per unit of each power semiconductor device based on its thermal cycling characteristic parameters, and determining the cumulative damage per unit of each DC capacitor based on its thermal stress characteristic parameters, includes: For each power semiconductor device, extract multiple thermal cycles contained in the thermal cycling characteristic parameters of the current power semiconductor device; Substitute the characteristic parameters of each thermal cycle into the preset power semiconductor device lifetime model to obtain the number of cycles allowed before failure corresponding to each thermal cycle; Using the Miner linear cumulative damage criterion, the cumulative damage of a single power semiconductor device is obtained based on the number of cycles allowed before failure. For each DC capacitor, the sampling time interval corresponding to each sampling moment of the current DC capacitor is determined according to the sampling frequency; the thermal stress characteristic parameters of each sampling moment of the current DC capacitor are substituted into the preset capacitor life model to obtain the instantaneous expected life corresponding to each sampling moment of the current DC capacitor. Based on the sampling time interval and the instantaneous expected lifetime, calculate the single-point damage degree of the current DC capacitor at each sampling moment; The single-point damage degree of the current DC capacitor is accumulated by summing the single-point damage degree at all sampling times.

[0011] Furthermore, the reliability assessment of the power electronic converter based on the cumulative damage of each power semiconductor device and the cumulative damage of each DC capacitor includes: Based on the task profile data, determine the duration of the task profile; The ratio of the duration to the cumulative damage of each individual power semiconductor device is calculated as the expected lifetime of each power semiconductor device. The ratio of the duration to the cumulative damage of each DC capacitor is calculated as the expected lifespan of each DC capacitor. Compare the expected lifetimes of all power semiconductor devices and all DC capacitors, and select the minimum value as the reliability lifetime of the power electronic converter.

[0012] Based on the above method embodiments, the present invention provides corresponding apparatus embodiments.

[0013] An embodiment of the present invention provides a reliability evaluation device for a power electronic converter based on a task profile, comprising: a data acquisition module, a temperature calculation module, a feature extraction module, and a reliability evaluation module; The data acquisition module is used to acquire task profile data of the power electronic converter within a preset working cycle, characteristic parameters of each power semiconductor device, and characteristic parameters of each DC capacitor; wherein, the power electronic converter includes several power semiconductor devices and several DC capacitors; the task profile data includes an ambient temperature sequence and a load condition sequence. The temperature calculation module is used to determine the junction temperature change curve of each power semiconductor device under the ambient temperature sequence based on the mission profile data, a preset semiconductor loss model, and a preset thermal network model; and to determine the core temperature change curve of each DC capacitor under the ambient temperature sequence based on the mission profile data, a preset capacitor equivalent model, and a preset thermal impedance model. The feature extraction module is used to determine the thermal cycling characteristic parameters of each power semiconductor device based on the junction temperature change curve of each power semiconductor device; and to determine the thermal stress characteristic parameters of each DC capacitor based on the core temperature change curve of each DC capacitor. The reliability assessment module is used to determine the cumulative damage of each power semiconductor device based on the thermal cycling characteristic parameters of each power semiconductor device; to determine the cumulative damage of each DC capacitor based on the thermal stress characteristic parameters of each DC capacitor; and to perform a reliability assessment of the power electronic converter based on the cumulative damage of each power semiconductor device and the cumulative damage of each DC capacitor.

[0014] Based on the above method embodiments, the present invention provides corresponding electronic device embodiments.

[0015] One embodiment of the present invention provides an electronic device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the reliability assessment method for a power electronic converter based on a task profile as described in any of the above-described method embodiments.

[0016] Based on the above method embodiments, the present invention provides corresponding storage medium embodiments.

[0017] One embodiment of the present invention provides a storage medium storing a computer program thereon, wherein, when the computer program is running, it controls the device where the storage medium is located to execute any of the above-described method embodiments of the reliability assessment method for power electronic converters based on task profiles.

[0018] Compared with the prior art, the present invention has the following beneficial effects: This invention provides a method, apparatus, electronic device, and storage medium for reliability assessment of power electronic converters based on task profiles. The method acquires task profile data of the power electronic converter within a preset operating cycle, as well as characteristic parameters of each power semiconductor device and DC capacitor. The task profile data includes an ambient temperature sequence and a load condition sequence. Based on the task profile data, using a preset semiconductor loss model and thermal network model, the junction temperature variation curves of each power semiconductor device are calculated; using a capacitor equivalent model and thermal impedance model, the core temperature variation curves of each DC capacitor are calculated. Thermal cycling characteristic parameters of the power semiconductor devices are extracted from the junction temperature variation curves, and their cumulative damage per unit is calculated. Thermal stress characteristic parameters of the DC capacitors are extracted from the core temperature variation curves, and their cumulative damage per unit is calculated. Finally, based on the cumulative damage per unit of all power semiconductor devices and DC capacitors, the reliability of the power electronic converter is assessed.

[0019] This invention employs differentiated damage calculation logic for power semiconductor devices and DC capacitors. Based on their respective thermal models, it determines the junction temperature and core temperature variation curves, and accordingly extracts the thermal cycling characteristic parameters of power semiconductor devices and the thermal stress characteristic parameters of DC capacitors. In this way, the invention effectively solves the problem that existing technologies often overlook the differences in the physical failure mechanisms of different devices (i.e., semiconductors are mainly affected by thermal cycling fatigue, while capacitors are mainly affected by thermal stress aging). It avoids biases caused by a single evaluation object or confused failure mechanisms, and achieves a comprehensive and accurate reliability assessment of the entire power electronic converter that conforms to its actual physical characteristics. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating a reliability assessment method for power electronic converters based on task profiles, provided in an embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram of the structure of a reliability evaluation device for a power electronic converter based on a task profile, provided in an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] like Figure 1 As shown, to address the problem in the prior art where the failure to distinguish between the thermal cycling fatigue of power semiconductor devices and the thermal stress aging of DC capacitors leads to inaccurate overall reliability assessment of converters, an embodiment of the present invention provides a reliability assessment method for power electronic converters based on task profiles, comprising at least the following steps: Step S1: Obtain the task profile data of the power electronic converter within a preset working cycle, the characteristic parameters of each power semiconductor device, and the characteristic parameters of each DC capacitor; wherein, the power electronic converter includes several power semiconductor devices and several DC capacitors; the task profile data includes an ambient temperature sequence and a load condition sequence. Specifically, the power electronic converter, as the evaluation object, internally includes several power semiconductor devices and several DC capacitors. The power semiconductor devices can be metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors, and the DC capacitors can be aluminum electrolytic capacitors or film capacitors. The preset duty cycle is the time span for reliability assessment, which can be the entire life cycle of the power electronic converter or a specific operating year. The task profile data is time-series data describing the operating conditions of the power electronic converter within the preset duty cycle. The task profile data specifically includes an ambient temperature sequence and a load condition sequence. The ambient temperature sequence is a set of temperature values ​​of the environment in which the power electronic converter is located, recorded at preset sampling intervals, reflecting the fluctuation of environmental thermal stress over time. The load condition sequence is a set of load power or output current values ​​of the power electronic converter, recorded at preset sampling intervals, reflecting the changes in electrical load of the power electronic converter under operating modes.

[0024] Simultaneously, to support subsequent loss calculations and lifetime predictions, specific parameters for each device need to be obtained. For each power semiconductor device, the characteristic parameters include electrical characteristic parameters used to construct the loss model and reliability parameters used to construct the lifetime model; the electrical characteristic parameters include the on-state voltage drop threshold, on-state equivalent resistance, and switching loss fitting coefficient obtained based on the device datasheet; the reliability parameters include the proportionality coefficient (denoted as ) in the power cycle lifetime model determined through accelerated life testing. ) and temperature change index coefficient (denoted as For each DC capacitor, the characteristic parameters include electrical-thermal parameters used to construct the thermal stress model and baseline parameters used to construct the lifetime model; the electrical-thermal parameters include the equivalent series resistance (denoted as...). ) and thermal resistance (denoted as The thermal resistance is used to describe the heat transfer characteristics from the internal heat source of the capacitor to the environment; the reference parameter includes the reference lifetime under reference conditions (denoted as...). ) and reference temperature (denoted as By acquiring the aforementioned mission profile data containing long-term dynamic changes and detailed parameters describing the physical characteristics of the device, environmental fluctuations and load fluctuations in actual application scenarios can be introduced into the evaluation process. This provides real and complete data input for subsequent dynamic stress analysis and time-varying damage calculation based on physical models, thereby avoiding the problem of severe disconnect between evaluation results and actual operating conditions caused by traditional evaluation methods that only use static rated parameters.

[0025] Step S2: Based on the task profile data, and using the preset semiconductor loss model and preset thermal network model, determine the junction temperature change curve of each power semiconductor device under the ambient temperature sequence; based on the task profile data, and using the preset capacitor equivalent model and preset thermal impedance model, determine the core temperature change curve of each DC capacitor under the ambient temperature sequence. In a preferred embodiment, based on mission profile data and a preset semiconductor loss model and a preset thermal network model, the junction temperature variation curves of each power semiconductor device under an ambient temperature sequence are determined, including: Based on the load condition sequence of the mission profile data, determine the load current sequence, voltage sequence, duty cycle sequence of the power electronic converter, and switching frequency sequence of each power semiconductor device. For each power semiconductor device, based on the on-state loss model in the preset semiconductor loss model, the on-state loss power of the current power semiconductor device is calculated and generated according to the load current sequence, the duty cycle sequence, and the characteristic parameters of the current power semiconductor device. Based on the switching loss model in the preset semiconductor loss model, the switching loss power of the current power semiconductor device is calculated and generated according to the load current sequence, the voltage sequence, the switching frequency sequence of the current power semiconductor device, and the characteristic parameters of the current power semiconductor device. Based on the current power loss power and the current power switching loss power of the power semiconductor device, calculate and generate the total power consumption sequence of the current power semiconductor device; The total power consumption sequence of the current power semiconductor device is input into the preset thermal network model, and iterative calculation is performed to generate the junction temperature rise sequence of the current power semiconductor device. Based on the ambient temperature sequence and the junction temperature rise sequence of the current power semiconductor device, determine the junction temperature change curve of the current power semiconductor device under the ambient temperature sequence.

[0026] In a preferred embodiment, based on mission profile data and a preset capacitor equivalent model and a preset thermal impedance model, the core temperature variation curve of each DC capacitor under an ambient temperature sequence is determined, including: Based on the load condition sequence of the mission profile data, determine the ripple current sequence flowing through each DC capacitor; For each DC capacitor, based on the preset capacitor equivalent model, the power loss sequence of the current DC capacitor is calculated and generated according to the ripple current sequence and characteristic parameters of the current DC capacitor. The power loss sequence of the current DC capacitor is input into the preset thermal impedance model for iterative calculation to generate the core temperature rise sequence of the current DC capacitor. Based on the ambient temperature sequence and the core temperature rise sequence of the current DC capacitor, determine the core temperature change curve of the current DC capacitor under the ambient temperature sequence.

[0027] Specifically, in determining the junction temperature variation curves of each power semiconductor device, the macroscopic task profile data first needs to be converted into device-level electrical stress data. Based on the load condition sequence of the task profile data, the load current sequence, voltage sequence, duty cycle sequence of the power electronic converter, and switching frequency sequence of each power semiconductor device are determined. The load current sequence and voltage sequence reflect the output state of the converter within a preset operating cycle. Through the converter's topology, the load current sequence can be mapped to the operating current sequence flowing through each power semiconductor device. The duty cycle sequence and switching frequency sequence are determined by the converter's control strategy and directly affect the device's on-time and switching frequency.

[0028] For each power semiconductor device, based on the on-state loss model in the preset semiconductor loss model, and according to the load current sequence, the duty cycle sequence, and the characteristic parameters of the current power semiconductor device, the on-state loss power of the current power semiconductor device is calculated. The on-state loss model in the semiconductor loss model is constructed by linearly fitting the volt-ampere characteristic curve in the device datasheet. Specifically, the following formula is used to calculate the on-state loss power at any given time. On-state loss power : in, This represents the on-state voltage drop threshold for power semiconductor devices. These two parameters are the on-state equivalent resistance of the power semiconductor device, and they are the parts of the characteristic parameters related to on-state loss. For a moment The load current value; For a moment The duty cycle value.

[0029] Simultaneously, based on the switching loss model within the preset semiconductor loss model, and according to the load current sequence, the voltage sequence, the switching frequency sequence of the current power semiconductor device, and the characteristic parameters of the current power semiconductor device, the switching loss power of the current power semiconductor device is calculated. The switching loss model is typically constructed based on the fitting relationship between the device's switching energy and current. Specifically, the following formula is used to calculate the power loss at any given time. Switching loss power : in, For a moment The switching frequency; In the current The single-switch loss energy is obtained by polynomial fitting of the switching energy curve in the datasheet. For a moment The DC-side voltage value; The reference voltage is used for testing; the polynomial fitting coefficients and the reference voltage constitute the part of the characteristic parameters related to switching losses.

[0030] Based on the on-state power loss and switching power loss of the current power semiconductor device, a total power consumption sequence of the current power semiconductor device is calculated by numerical addition. Subsequently, this total power consumption sequence is input into a preset thermal network model for iterative calculation to generate a junction temperature rise sequence of the current power semiconductor device. The preset thermal network model preferably adopts the Foster thermal resistance-capacitance network model or the Cauer thermal resistance-capacitance network model. Utilizing electrothermal simulation theory, power loss is equated to a current source, and temperature rise is equated to voltage. The temperature rise is solved using an analytical transient thermal impedance formula. The transient thermal impedance... The formula for expressing this is as follows: in, Let be the order of the heat network model; For the first The equivalent thermal resistance of the first step; For the first The thermal time constant of order, and , For the first The equivalent heat capacity of each step is calculated. In practical discrete calculations, an iterative algorithm is used to calculate the junction temperature rise at each moment. That is, the current junction temperature rise is equal to the residual value of the junction temperature rise at the previous moment after natural cooling and the new temperature rise caused by the power consumption at the current moment. Finally, based on the ambient temperature sequence and the junction temperature rise sequence of the current power semiconductor device, the two are superimposed on the time axis to determine the junction temperature change curve of the current power semiconductor device under the ambient temperature sequence.

[0031] In determining the core temperature change curves of each DC capacitor, the ripple current sequence flowing through each DC capacitor is determined based on the load condition sequence of the mission profile data. This ripple current sequence is the main cause of capacitor heating, and its magnitude depends on the load current and the converter's modulation method. For each DC capacitor, based on a preset capacitor equivalent model, the power loss sequence of the current DC capacitor is calculated according to its ripple current sequence and characteristic parameters. The capacitor equivalent model mainly considers equivalent series resistance losses, and the specific calculation formula is as follows: in, For a moment The power loss of a DC capacitor; For a moment The effective value of the ripple current flowing through the DC capacitor; This is the equivalent series resistance of the DC capacitor.

[0032] Next, the power loss sequence of the current DC capacitor is input into a preset thermal impedance model for iterative calculation to generate the core temperature rise sequence of the current DC capacitor. The thermal impedance model describes the heat transfer path from the capacitor core to the casing, and then from the casing to the environment, using thermal path equations to calculate the temperature rise of the core relative to the environment. Finally, based on the ambient temperature sequence and the core temperature rise sequence of the current DC capacitor, the ambient temperature is superimposed on the core temperature rise as a reference value to determine the core temperature change curve of the current DC capacitor under the ambient temperature sequence. Through these steps, macroscopic task profile data can be accurately converted into microscopic temperature stress data within the device, providing accurate physical quantity input for subsequent lifetime prediction based on different device mechanisms.

[0033] Step S3: Based on the junction temperature change curves of each power semiconductor device, determine the thermal cycling characteristic parameters of each power semiconductor device; based on the core temperature change curves of each DC capacitor, determine the thermal stress characteristic parameters of each DC capacitor. In a preferred embodiment, determining the thermal cycling characteristic parameters of each power semiconductor device based on the junction temperature change curves of each power semiconductor device includes: For each power semiconductor device, extract the peak and trough points from the junction temperature change curve of the current power semiconductor device to form an extreme point sequence. The extreme point sequence is subjected to cyclic counting to identify several independent thermal cycles contained in the junction temperature change curve of the current power semiconductor device. Extract the thermal cycle characteristic parameters of each of the plurality of thermal cycles; wherein, the thermal cycle characteristic parameters include junction temperature fluctuation amplitude and junction temperature average. The thermal cycling characteristic parameters of the aforementioned thermal cycles are summarized, and the summarized results are used as the thermal cycling characteristic parameters of the current power semiconductor device.

[0034] In a preferred embodiment, determining the thermal stress characteristic parameters of each DC capacitor based on the core temperature change curve of each DC capacitor includes: For the core temperature change curve of each DC capacitor, the core temperature change curve of the current DC capacitor is discretized according to the preset sampling frequency to form a core temperature sequence. Extract the core temperature value corresponding to each sampling time in the core temperature sequence; The core temperature value is used as the thermal stress characteristic parameter of the current DC capacitor.

[0035] Specifically, for the power semiconductor device, since its failure is mainly caused by thermal fatigue due to temperature fluctuations, it is necessary to convert the continuous time-domain waveform into discrete stress cycle data. Specifically, for the junction temperature change curve of each power semiconductor device, peaks and troughs are extracted by identifying local extrema, and intermediate transitional data that do not constitute a cycle are removed, thus forming an extremum point sequence. Subsequently, cycle counting processing is performed on the extremum point sequence, and the closed stress-strain hysteresis loop in the extremum point sequence is identified using the logic of the rainflow counting algorithm, thereby identifying several independent thermal cycles contained in the junction temperature change curve of the power semiconductor device. For each identified independent thermal cycle, characteristic parameters of the thermal cycle are extracted; these characteristic parameters include at least the junction temperature fluctuation amplitude and the average junction temperature, where the junction temperature fluctuation amplitude characterizes the thermal stress intensity of the cycle, and the average junction temperature characterizes the average thermal level of the cycle. Finally, all the parameters of the identified thermal cycles are summarized, and the set of thermal cycle characteristic parameters of the several thermal cycles is used as the thermal cycle characteristic parameters of the current power semiconductor device, providing input for subsequent damage calculation based on the fatigue failure physical model.

[0036] In one embodiment, for the DC capacitor, since the failure of the DC capacitor is mainly caused by aging due to long-term thermal stress, and its lifespan is closely related to absolute temperature and duration, a discretized integration approach is used for parameter extraction. Specifically, for the core temperature change curve of each DC capacitor, the core temperature change curve is discretized according to a preset sampling frequency, cutting the continuous time waveform into a series of discrete points with equal time intervals to form a core temperature sequence; the sampling frequency should be set sufficiently to capture significant temperature changes in the task profile. Next, the core temperature value corresponding to each sampling moment in the core temperature sequence is extracted; unlike power semiconductor devices which focus on the amplitude of temperature fluctuations, DC capacitors focus on the absolute temperature level at each moment. The extracted core temperature value is used as the thermal stress characteristic parameter of the current DC capacitor, which directly reflects the thermal aging stress borne by the capacitor in each small time segment. Through the above steps, the cyclic parameters characterizing thermal fatigue characteristics and the temperature parameters characterizing thermal aging characteristics can be extracted for the distinctly different failure physical mechanisms of power semiconductor devices and DC capacitors, thereby achieving accurate quantification of the stress characteristics of different types of devices and solving the evaluation bias problem caused by the failure to distinguish the stress characteristics of devices in the prior art.

[0037] Step S4: Determine the cumulative damage of each power semiconductor device based on its thermal cycling characteristic parameters; determine the cumulative damage of each DC capacitor based on its thermal stress characteristic parameters; and conduct a reliability assessment of the power electronic converter based on the cumulative damage of each power semiconductor device and the cumulative damage of each DC capacitor.

[0038] In a preferred embodiment, determining the cumulative damage per unit of each power semiconductor device based on its thermal cycling characteristic parameters, and determining the cumulative damage per unit of each DC capacitor based on its thermal stress characteristic parameters, includes: For each power semiconductor device, extract multiple thermal cycles contained in the thermal cycling characteristic parameters of the current power semiconductor device; Substitute the characteristic parameters of each thermal cycle into the preset power semiconductor device lifetime model to obtain the number of cycles allowed before failure corresponding to each thermal cycle; Using the Miner linear cumulative damage criterion, the cumulative damage of a single power semiconductor device is obtained based on the number of cycles allowed before failure. For each DC capacitor, the sampling time interval corresponding to each sampling moment of the current DC capacitor is determined according to the sampling frequency; the thermal stress characteristic parameters of each sampling moment of the current DC capacitor are substituted into the preset capacitor life model to obtain the instantaneous expected life corresponding to each sampling moment of the current DC capacitor. Based on the sampling time interval and the instantaneous expected lifetime, calculate the single-point damage degree of the current DC capacitor at each sampling moment; The single-point damage degree of the current DC capacitor is accumulated by summing the single-point damage degree at all sampling times.

[0039] In a preferred embodiment, the reliability assessment of the power electronic converter based on the cumulative damage of each power semiconductor device and the cumulative damage of each DC capacitor includes: Based on the task profile data, determine the duration of the task profile; The ratio of the duration to the cumulative damage of each individual power semiconductor device is calculated as the expected lifetime of each power semiconductor device. The ratio of the duration to the cumulative damage of each DC capacitor is calculated as the expected lifespan of each DC capacitor. Compare the expected lifetimes of all power semiconductor devices and all DC capacitors, and select the minimum value as the reliability lifetime of the power electronic converter.

[0040] Specifically, damage calculations for power semiconductor devices primarily rely on thermal fatigue failure mechanisms. For each power semiconductor device, multiple thermal cycles are extracted from its thermal cycling characteristic parameters. These thermal cycles are independent stress cycles identified using the aforementioned rainflow counting method, each corresponding to a specific set of junction temperature fluctuation amplitudes and average junction temperatures. The characteristic parameters of each thermal cycle are substituted into a preset power semiconductor device lifetime model to obtain the allowable number of cycles before failure for each thermal cycle. The preset power semiconductor device lifetime model preferably employs the Coffin-Manson-Arrhenius model, which comprehensively considers the influence of temperature fluctuation amplitudes and average temperatures on the fatigue of the device's bond wires and solder layers. For the first... One thermal cycle, calculate the number of cycles allowed before failure. The formula is as follows: in, For current power semiconductor devices in the first The number of cycles allowed before failure under a thermal cycle; For the first The junction temperature fluctuation amplitude of each thermal cycle; For the first Average junction temperature (degrees Celsius) of each thermal cycle; These are device process constants; The fatigue index; Activation energy; This represents the Boltzmann constant. It should be noted that the process parameters in the above formulas... , , It needs to be obtained by fitting the aging test data of the device or the data sheet provided by the manufacturer.

[0041] After obtaining the permissible lifetime for each thermal cycle, the cumulative damage of the current power semiconductor device is calculated using the Miner linear cumulative damage criterion, based on the permissible number of cycles before failure. The Miner criterion assumes that the damage caused by each stress cycle is linearly additive; therefore, the total damage of the current power semiconductor device is calculated as follows: The calculation formula is as follows: in, This represents the cumulative damage level of a single power semiconductor device. The total number of thermal cycles identified within the mission profile; For the first The number of cycles allowed before failure corresponds to each thermal cycle.

[0042] In a preferred embodiment, damage calculation for DC capacitors is primarily based on the thermal aging mechanism of the insulating medium. For each DC capacitor, the sampling time interval corresponding to each sampling moment is determined according to the sampling frequency set in the preceding steps. The thermal stress characteristic parameters of each sampling moment of the current DC capacitor are substituted into a preset capacitor lifetime model to obtain the instantaneous expected lifetime corresponding to each sampling moment of the current DC capacitor. The capacitor lifetime model describes the theoretical duration for which a capacitor can maintain normal operation under specific temperature and voltage stresses, and typically follows Arrhenius's law. For the first... Calculate the instantaneous expected lifetime at each sampling time point. The formula is as follows: in, In the first The instantaneous expected lifetime of the current DC capacitor under the operating conditions at each sampling time; This is the reference life under rated operating conditions; For the first The operating voltage that the DC capacitor withstands at each sampling moment; This is the rated voltage of the DC capacitor; It is the voltage acceleration factor; This refers to the rated hot spot temperature of the DC capacitor. For the first The core temperature value of the DC capacitor at each sampling time (i.e., the aforementioned thermal stress characteristic parameter).

[0043] Based on the sampling time interval and the instantaneous expected lifetime, the single-point damage degree of the current DC capacitor at each sampling moment is calculated. Since temperature and voltage can be considered constant within the extremely short sampling time interval, the damage during this period is the ratio of duration to expected lifetime. The single-point damage degrees of the current DC capacitor at all sampling moments are summed to obtain the cumulative damage degree of the current DC capacitor. The calculation formula is as follows: in, This represents the current cumulative damage level of a single DC capacitor. This represents the total number of sampling points corresponding to the task profile. The sampling time interval; For the first The instantaneous expected lifetime at each sampling moment.

[0044] In a preferred embodiment, the reliability of the power electronic converter is assessed based on the cumulative damage of each power semiconductor device and the cumulative damage of each DC capacitor. First, the duration of the mission profile is determined based on the mission profile data. Since power electronic converters consist of multiple devices, and the failure of any critical device will lead to converter failure, it is necessary to identify the system's "weak link." The ratio of the duration of failure to the cumulative damage of each individual power semiconductor device is calculated as the expected lifetime of each power semiconductor device. Similarly, the ratio of the duration to the cumulative damage of each individual DC capacitor is calculated as the expected lifespan of each DC capacitor. The calculation formulas are as follows: in, This indicates the predicted lifespan of power semiconductor devices if they operate long-term according to the current mission profile. This indicates the predicted lifespan of the DC capacitor if it operates long-term according to the current task profile.

[0045] Finally, by comparing the expected lifetimes of all power semiconductor devices and all DC capacitors, and based on the "barrel effect" principle, the minimum value is selected as the reliability lifetime of the power electronic converter. This approach comprehensively considers the damage accumulation of different types of devices (switching devices and passive components) under different physical failure models. Based on actual task profiles, it enables accurate quantitative assessment of the overall lifetime of the power electronic converter, avoiding the problem of overly optimistic or pessimistic reliability assessments caused by considering only a single type of device. This provides a scientific basis for formulating converter maintenance strategies.

[0046] Based on the above method embodiments, the present invention provides corresponding apparatus embodiments.

[0047] like Figure 2 As shown, an embodiment of the present invention provides a reliability evaluation device for a power electronic converter based on a task profile, comprising: a data acquisition module, a temperature calculation module, a feature extraction module, and a reliability evaluation module; The data acquisition module is used to acquire task profile data of the power electronic converter within a preset working cycle, characteristic parameters of each power semiconductor device, and characteristic parameters of each DC capacitor; wherein, the power electronic converter includes several power semiconductor devices and several DC capacitors; the task profile data includes an ambient temperature sequence and a load condition sequence. The temperature calculation module is used to determine the junction temperature change curve of each power semiconductor device under the ambient temperature sequence based on the mission profile data, a preset semiconductor loss model, and a preset thermal network model; and to determine the core temperature change curve of each DC capacitor under the ambient temperature sequence based on the mission profile data, a preset capacitor equivalent model, and a preset thermal impedance model. The feature extraction module is used to determine the thermal cycling characteristic parameters of each power semiconductor device based on the junction temperature change curve of each power semiconductor device; and to determine the thermal stress characteristic parameters of each DC capacitor based on the core temperature change curve of each DC capacitor. The reliability assessment module is used to determine the cumulative damage of each power semiconductor device based on the thermal cycling characteristic parameters of each power semiconductor device; to determine the cumulative damage of each DC capacitor based on the thermal stress characteristic parameters of each DC capacitor; and to perform a reliability assessment of the power electronic converter based on the cumulative damage of each power semiconductor device and the cumulative damage of each DC capacitor.

[0048] It should be noted that the embodiments of the apparatus described above correspond to the embodiments of the present invention described above, and can realize the reliability evaluation method for power electronic converters based on task profiles as described in any one of the above embodiments of the present invention. Furthermore, the embodiments of the apparatus described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the accompanying drawings of the apparatus embodiments provided by the present invention, the connection relationship between modules indicates that they have a communication connection, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without creative effort.

[0049] Based on the above-described method embodiments of the present invention, a corresponding embodiment of an electronic device is provided.

[0050] An embodiment of the present invention provides an electronic device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the reliability assessment method for a power electronic converter based on task profile as described in any one of the present invention, or the processor executes the computer program to implement the functions of each module in the above-described device embodiments.

[0051] For example, the computer program may be divided into one or more modules, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules may be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of the computer program in the terminal device.

[0052] The terminal device may be a desktop computer, laptop, handheld computer, or cloud server, etc. The terminal device may include, but is not limited to, a processor and a memory.

[0053] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the terminal device, connecting all parts of the terminal device via various interfaces and lines.

[0054] The memory can be used to store the computer programs and / or modules. The processor implements various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory and by calling data stored in the memory. The memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, applications required for at least one function, etc.; the data storage area may store data created based on the use of the mobile phone, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital card (SD card), flash card, at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0055] Based on the above method embodiments, the present invention provides corresponding storage medium embodiments; Another embodiment of the present invention provides a storage medium including a stored computer program, wherein, when the computer program is executed, the device where the storage medium is located executes any of the above-described reliability assessment methods for power electronic converters based on task profiles.

[0056] The aforementioned storage medium is a computer-readable storage medium, and the computer program includes computer program code, which may be in the form of source code, object code, executable file, or certain intermediate forms. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0057] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0058] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A reliability assessment method for power electronic converters based on task profiles, characterized in that, include: The task profile data of the power electronic converter, the characteristic parameters of each power semiconductor device, and the characteristic parameters of each DC capacitor are obtained within a preset working cycle; wherein, the power electronic converter includes several power semiconductor devices and several DC capacitors; the task profile data includes an ambient temperature sequence and a load condition sequence. Based on the mission profile data, and using the preset semiconductor loss model and preset thermal network model, the junction temperature variation curves of each power semiconductor device under the ambient temperature series are determined; based on the mission profile data, and using the preset capacitor equivalent model and preset thermal impedance model, the core temperature variation curves of each DC capacitor under the ambient temperature series are determined. Based on the junction temperature variation curves of each power semiconductor device, the thermal cycling characteristic parameters of each power semiconductor device are determined; based on the core temperature variation curves of each DC capacitor, the thermal stress characteristic parameters of each DC capacitor are determined. Based on the thermal cycling characteristic parameters of each power semiconductor device, the cumulative damage of each individual power semiconductor device is determined; based on the thermal stress characteristic parameters of each DC capacitor, the cumulative damage of each individual DC capacitor is determined; based on the cumulative damage of each individual power semiconductor device and the cumulative damage of each individual DC capacitor, the reliability of the power electronic converter is evaluated.

2. The reliability assessment method for power electronic converters based on task profiles as described in claim 1, characterized in that, Based on the mission profile data, and using a pre-defined semiconductor loss model and a pre-defined thermal network model, the junction temperature variation curves of each power semiconductor device under the ambient temperature sequence are determined, including: Based on the load condition sequence of the mission profile data, determine the load current sequence, voltage sequence, duty cycle sequence of the power electronic converter, and switching frequency sequence of each power semiconductor device. For each power semiconductor device, based on the on-state loss model in the preset semiconductor loss model, the on-state loss power of the current power semiconductor device is calculated and generated according to the load current sequence, the duty cycle sequence, and the characteristic parameters of the current power semiconductor device. Based on the switching loss model in the preset semiconductor loss model, the switching loss power of the current power semiconductor device is calculated and generated according to the load current sequence, the voltage sequence, the switching frequency sequence of the current power semiconductor device, and the characteristic parameters of the current power semiconductor device. Based on the current power loss power and the current power switching loss power of the power semiconductor device, calculate and generate the total power consumption sequence of the current power semiconductor device; The total power consumption sequence of the current power semiconductor device is input into the preset thermal network model, and iterative calculation is performed to generate the junction temperature rise sequence of the current power semiconductor device. Based on the ambient temperature sequence and the junction temperature rise sequence of the current power semiconductor device, determine the junction temperature change curve of the current power semiconductor device under the ambient temperature sequence.

3. The reliability assessment method for power electronic converters based on task profiles as described in claim 2, characterized in that, Based on the mission profile data, and using the pre-defined capacitor equivalent model and pre-defined thermal impedance model, the core temperature variation curves of each DC capacitor under the ambient temperature series are determined, including: Based on the load condition sequence of the mission profile data, determine the ripple current sequence flowing through each DC capacitor; For each DC capacitor, based on the preset capacitor equivalent model, the power loss sequence of the current DC capacitor is calculated and generated according to the ripple current sequence and characteristic parameters of the current DC capacitor. The power loss sequence of the current DC capacitor is input into the preset thermal impedance model for iterative calculation to generate the core temperature rise sequence of the current DC capacitor. Based on the ambient temperature sequence and the core temperature rise sequence of the current DC capacitor, determine the core temperature change curve of the current DC capacitor under the ambient temperature sequence.

4. The reliability assessment method for power electronic converters based on task profiles as described in claim 3, characterized in that, The determination of thermal cycling characteristic parameters of each power semiconductor device based on the junction temperature variation curves of each device includes: For each power semiconductor device, extract the peak and trough points from the junction temperature change curve of the current power semiconductor device to form an extreme point sequence. The extreme point sequence is subjected to cyclic counting to identify several independent thermal cycles contained in the junction temperature change curve of the current power semiconductor device. Extract the thermal cycle characteristic parameters of each of the plurality of thermal cycles; wherein, the thermal cycle characteristic parameters include junction temperature fluctuation amplitude and junction temperature average. The thermal cycling characteristic parameters of the aforementioned thermal cycles are summarized, and the summarized results are used as the thermal cycling characteristic parameters of the current power semiconductor device.

5. The reliability assessment method for power electronic converters based on task profiles as described in claim 4, characterized in that, The determination of thermal stress characteristic parameters for each DC capacitor based on the core temperature change curves of each DC capacitor includes: For the core temperature change curve of each DC capacitor, the core temperature change curve of the current DC capacitor is discretized according to the preset sampling frequency to form a core temperature sequence. Extract the core temperature value corresponding to each sampling time in the core temperature sequence; The core temperature value is used as the thermal stress characteristic parameter of the current DC capacitor.

6. The reliability assessment method for power electronic converters based on task profiles as described in claim 5, characterized in that, The cumulative damage of each power semiconductor device is determined based on the thermal cycling characteristic parameters of each device. Based on the thermal stress characteristic parameters of each DC capacitor, the cumulative damage degree of each individual DC capacitor is determined, including: For each power semiconductor device, extract multiple thermal cycles contained in the thermal cycling characteristic parameters of the current power semiconductor device; Substitute the characteristic parameters of each thermal cycle into the preset power semiconductor device lifetime model to obtain the number of cycles allowed before failure corresponding to each thermal cycle; Using the Miner linear cumulative damage criterion, the cumulative damage of a single power semiconductor device is obtained based on the number of cycles allowed before failure. For each DC capacitor, the sampling time interval corresponding to each sampling moment of the current DC capacitor is determined according to the sampling frequency; the thermal stress characteristic parameters of each sampling moment of the current DC capacitor are substituted into the preset capacitor life model to obtain the instantaneous expected life corresponding to each sampling moment of the current DC capacitor. Based on the sampling time interval and the instantaneous expected lifetime, calculate the single-point damage degree of the current DC capacitor at each sampling moment; The single-point damage degree of the current DC capacitor is accumulated by summing the single-point damage degree at all sampling times.

7. The reliability assessment method for power electronic converters based on task profiles as described in claim 6, characterized in that, The reliability assessment of the power electronic converter based on the cumulative damage of each power semiconductor device and the cumulative damage of each DC capacitor includes: Based on the task profile data, determine the duration of the task profile; The ratio of the duration to the cumulative damage of each individual power semiconductor device is calculated as the expected lifetime of each power semiconductor device. The ratio of the duration to the cumulative damage of each DC capacitor is calculated as the expected lifespan of each DC capacitor. Compare the expected lifetimes of all power semiconductor devices and all DC capacitors, and select the minimum value as the reliability lifetime of the power electronic converter.

8. A reliability assessment device for power electronic converters based on task profiles, characterized in that, include: The module includes a data acquisition module, a temperature calculation module, a feature extraction module, and a reliability assessment module. The data acquisition module is used to acquire task profile data of the power electronic converter within a preset working cycle, characteristic parameters of each power semiconductor device, and characteristic parameters of each DC capacitor; wherein, the power electronic converter includes several power semiconductor devices and several DC capacitors; the task profile data includes an ambient temperature sequence and a load condition sequence. The temperature calculation module is used to determine the junction temperature change curve of each power semiconductor device under the ambient temperature sequence based on the mission profile data, a preset semiconductor loss model, and a preset thermal network model; and to determine the core temperature change curve of each DC capacitor under the ambient temperature sequence based on the mission profile data, a preset capacitor equivalent model, and a preset thermal impedance model. The feature extraction module is used to determine the thermal cycling characteristic parameters of each power semiconductor device based on the junction temperature change curve of each power semiconductor device; and to determine the thermal stress characteristic parameters of each DC capacitor based on the core temperature change curve of each DC capacitor. The reliability assessment module is used to determine the cumulative damage of each power semiconductor device based on the thermal cycling characteristic parameters of each power semiconductor device; to determine the cumulative damage of each DC capacitor based on the thermal stress characteristic parameters of each DC capacitor; and to perform a reliability assessment of the power electronic converter based on the cumulative damage of each power semiconductor device and the cumulative damage of each DC capacitor.

9. An electronic device, characterized in that, The device includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor, when executing the computer program, implements the reliability assessment method for a power electronic converter based on a task profile as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium includes a stored computer program, wherein, when the computer program is executed, it controls the device where the storage medium is located to perform the reliability assessment method for a power electronic converter based on a task profile as described in any one of claims 1 to 7.

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