A verification device for a chip set module without a register

Abstract

The application relates to the technical field of chip verification, in particular to a verification device for a chip component module without a register, which comprises a sequence configuration module, a register model, an adapter, a signal control sequence container and a signal control verification component; the sequence configuration module is used for generating a configuration sequence based on a read-write operation interface of the register model and a configuration requirement of a chip component module to be tested; the register model is used for initiating a register access request to the adapter based on the configuration sequence; the adapter is used for converting the register access request into a signal control sequence container control request and sending the signal control sequence container control request to a signal control sequence container; the signal control sequence container is used for converting the control sequence container control request into an excitation sequence and sending the excitation sequence to the corresponding signal control verification component; and the signal control verification component is used for converting the received excitation sequence into a driving signal and sending the driving signal to the chip component module to be tested through a corresponding control signal line. The application improves the chip verification efficiency and accuracy.

Description

Verification device for a chip component module without registers Technical Field

[0001] This invention relates to the field of chip verification technology, and in particular to a verification device for chip component modules without registers. Background Technology

[0002] In chip verification, especially at the subsystem level, it is often necessary to further subdivide the subsystem into multiple chip modules for verification based on their functionality and complexity. Some chip modules, due to their functional architecture, do not have their own internal registers and instead directly utilize register control signals from other chip modules. These modules lack register access interfaces and only possess various control signals; therefore, register models cannot be directly used. Instead, configuration and verification at the chip module level are performed by directly forcing control signals within the environment. However, this method cannot be reused as a configuration sequence by upper-level chip modules. Therefore, during subsystem verification, a subsystem-level register configuration sequence must be written again based on a programming guide or by referring to the forced control in the chip module verification environment. Thus, existing verification methods for chip modules without registers cannot achieve vertical reuse, resulting in low chip verification efficiency. Furthermore, existing technologies are prone to errors and omissions during the verification of chip modules without registers, leading to poor chip verification accuracy. Summary of the Invention

[0003] The purpose of this invention is to provide a verification device for chip component modules without registers, thereby improving the efficiency and accuracy of chip verification.

[0004] This invention provides a verification device for a chip component module without configured registers, comprising: a sequence configuration module, a register model, an adapter, a signal control sequence container, M signal control verification components, and a chip component module under test, where M ≥ 1.

[0005] The sequence configuration module is used to generate a configuration sequence based on the read and write operation interface of the register model and the configuration requirements of the chip under test (TB) component modules, and send it to the register model. The TB component modules are chip component modules that do not have registers set in the TB chip design. The register model is generated based on the register description file corresponding to the TB chip design.

[0006] The register model is used to initiate a register access request to the adapter based on the configuration sequence;

[0007] The adapter is used to convert the register access request into a signal control sequence container control request and send it to the signal control sequence container;

[0008] The signal control sequence container is used to convert the control sequence container control request into an excitation sequence and send it to the corresponding signal control verification component;

[0009] The signal control verification component is used to convert the received excitation sequence into a driving signal and send it to the chip under test module through the corresponding control signal line.

[0010] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the verification device for a chip component module without registers provided by this invention achieves considerable technological advancement and practicality, and has broad industrial application value. It has at least the following beneficial effects:

[0011] The verification device for chip components without registers provided by this invention can perform verification based on the register model in the chip design under test. It generates a configuration sequence based on the read and write operation interface of the register model and the configuration requirements of the chip components under test, without the need to set a forced drive control signal in the verification environment. This allows the verification information of chip components without registers to be vertically reused and is less prone to errors and omissions, thus improving the efficiency and accuracy of chip verification. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 is a schematic diagram of a verification device for a chip component module without registers provided in an embodiment of the present invention;

[0014] Figure 2 is a schematic diagram of the chip design architecture provided in an embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] This invention provides a verification device for a chip component module without registers, as shown in Figure 1. It includes: a sequence configuration module, a register model, an adapter, a signal control sequence container, M signal control verification components (UVC), and a chip component module under test, where M ≥ 1. It should be noted that in the example shown in Figure 1, M is 2. In actual applications, the value of M can be adjusted according to specific application requirements.

[0017] The sequence configuration module generates a configuration sequence based on the read / write operation interface of the register model and the configuration requirements of the chip under test (DUT) component modules, and sends it to the register model. The DUT component modules are those without registers in the DUT design. It is understood that the DUT design also includes chip component modules with registers; specifically, the DUT design can be a chip subsystem. As shown in Figure 2, the DUT design (shown as the system top level) includes three chip component modules: those without registers and those with registers. These modules are Module 1, Module 2, and Module 3. Modules 1 and 2 do not have register control bus interfaces; their control signals originate from Module 3, which contains the register control bus interface. Module 3 includes four registers: Register 1, Register 2, Register 3, and Register 4. Registers 1 and 2 control Module 1, and their control signals are derived from Module 3 and connected to Module 1. Register 3 controls Module 2, and its control signals are derived from Module 3 and connected to Module 2. Module 3 also has a register 4 for internal use, which does not have any control signals that need to be routed to the outside of module 3.

[0018] It should be noted that chip modules with configured registers can continue to be verified using existing implementation methods based on the register model. Chip modules without configured registers, i.e., the chip-to-test (DUT) modules described in this embodiment, can be verified using the verification device for chip modules without configured registers, or they can be verified based on the register model, without needing to individually set forced drive control signals for each DUT module in the verification environment. For higher-level DUT designs, all modules can be verified based on the register model; therefore, verification information from all modules of the DUT design can be directly reused during the DUT design verification process.

[0019] The register model is generated based on the register description file corresponding to the chip under test (DUT) design. Specifically, the register description file may include the mapping relationship between register identifiers and register addresses, register attribute information, register fields contained in each register, and attribute information of each register field. It should be noted that all existing methods for generating register models based on register description files fall within the scope of this invention and will not be elaborated upon here. The configuration sequence is insensitive to the composition of the underlying verification platform, and its called operation interfaces conform to the definition of general verification methodologies; therefore, the configuration sequence can be reused across different verification platforms.

[0020] The register model is used to initiate register access requests to the adapter based on the configuration sequence. It also provides general operations such as read / write operation interfaces. The register model implements a general processing method defined by the verification methodology, suitable for reuse across different verification platforms. The adapter converts the register access request into a signal control sequence container control request and sends it to the signal control sequence container. The signal control sequence container converts the control sequence container control request into an excitation sequence and sends it to the corresponding signal control verification component. The signal control sequence container can replace the direct control of the control signal drive in the prior art, realizing the interaction interface between the signal control sequence and the register model, allowing users to operate the signal control verification component by operating the register model. The signal control verification component converts the received excitation sequence into a drive signal and sends it to the chip under test module through the corresponding control signal line.

[0021] As one embodiment, the signal control sequence container includes an adapter interaction interface, an address signal mapping table, a container component, and M excitation sequence generation units. Each excitation sequence generation unit corresponds to a signal control verification component, and each signal control verification component is connected to the chip under test module through a corresponding control signal line.

[0022] The adapter interaction interface is used to obtain control sequence container control requests from the adapter and send them to the container component. The control sequence container control request includes a register address and a corresponding target value. The register address can be the address corresponding to the register or the address corresponding to the register field in the register, depending on the specific application requirements.

[0023] The address signal mapping table is generated based on the register description file corresponding to the chip under test design, and the address signal mapping table stores the mapping relationship between control signal line identifiers and register addresses.

[0024] The container component is used to look up the address signal mapping table based on the register address in the control sequence container control request, obtain the corresponding target control signal line identifier, determine the target excitation sequence generation unit and the target signal control verification component based on the target control signal line identifier, and send the target value to the target excitation sequence generation unit.

[0025] The excitation sequence generation unit is used to generate an excitation sequence based on the received target value.

[0026] It should be noted that, typically, the register identifier corresponding to the control signal line corresponds to the control signal line identifier, specifically, they may contain the same fields. Therefore, an address signal mapping table can be directly established based on the register description file corresponding to the chip under test (DUT) design. However, in some application scenarios, the content of the corresponding fields in the register description file may be changed, resulting in a discrepancy between the control signal line identifier in the register description file and the actual control signal line identifier. In this case, it is necessary to make changes during the generation of the address signal mapping table to ensure that the correct mapping relationship is established. As an example, during the generation of the address signal mapping table based on the register description file corresponding to the DUT design, if the control signal line identifier in the register description file corresponding to the DUT design is inconsistent with the actual control signal line identifier, then during the generation of the address signal mapping table, the actual control signal line identifier is used to establish the mapping relationship between the control signal line identifier and the register address.

[0027] As one embodiment, the adapter interaction interface is used to indirectly call the reg2bus and bus2reg protocol conversion functions in the register model during read and write operations through the register model, and provides a transaction level modeling (TLM) interface for the adapter to call to obtain the control sequence container control request generated based on the register access request conversion. The control sequence container control request can specifically be a standard data structure uvm_reg_bus_op that encapsulates register bus operation information.

[0028] In one embodiment, the stimulus sequence generated by the stimulus sequence generation unit is set as a passive sequence. The stimulus sequence generation unit is further configured to determine whether a call from the register model exists based on each clock cycle of the clock domain to which the control signal of the corresponding control signal line belongs. If a call exists, the drive signal controls the corresponding signal control verification component to output or obtain the corresponding drive value. It is understood that if the control sequence container control request is a write request, the drive signal controls the corresponding signal control verification component to output the corresponding drive value; if the control sequence container control request is a read request, the drive signal controls the corresponding signal control verification component to obtain the corresponding drive value.

[0029] As one embodiment, the configuration sequence includes configuration sequences generated based on the verification of any chip component module in the chip under test (DUT) design and the verification of the DUT itself. The configuration sequence is arranged in chronological order of configuration information. Each configuration information includes the configuration information of all registers in the DUT design, and each DUT component module corresponds to at least one register. It should be noted that the configuration sequence can correspond to any component module in the DUT design and the DUT design itself; that is, it can be reused by any component module in the DUT design and the DUT design itself. During the verification of a DUT component module, only the configuration information of the registers corresponding to the DUT component module itself in the configuration sequence can be obtained; the configuration information of other chip component modules is not visible. During the verification of the DUT itself, all configuration information in the configuration sequence is visible. Taking the DUT design structure shown in Figure 2 as an example, each configuration information includes configuration information corresponding to register 1, register 2, register 3, and register 4. However, during the verification of module 1, only the configuration information corresponding to register 1 and register 2 in the configuration sequence is effective for the verification of module 1; the configuration information corresponding to register 3 and register 4 is not visible to module 1. When verifying the design of the chip under test, all configuration information in the configuration sequence is visible to the chip design under test.

[0030] As one embodiment, the sequence configuration module is specifically used to set execution statements for the register model based on the read / write operation interface of the register model and the configuration requirements of the chip components, and to generate a configuration sequence. The specific implementation can be achieved using the following code statements:

[0031] class init_sequence

[0032] ral_model.reg_1.write(status, data);

[0033] ral_model.reg_2.write(status, data);

[0034] endclass

[0035] The above configuration method can be easily reused in higher-level verification environments, and the specific control of the signal lines is completed by the signal control sequence container. Other operations, such as clock (clk) adjustment, reset and other special scenario operation control, can be implemented through the functions of the signal control verification component itself.

[0036] Taking Figure 2 as an example, when a separate verification environment needs to be established for module 1, modeling is required based on the system structure shown in Figure 1. As one implementation: First, obtain the register description file of the chip under test (DUT) design. This file includes all characteristic information reflecting all registers in the system (i.e., register 1, register 2, register 3, and register 4). A relevant script or program reads the register description file of the DUT design and generates matching functional components based on user input. These functional components include, but are not limited to, control signal connection binding files, signal control verification components, register models (RAL), signal control sequence containers, and adapters. When the DUT is module 1, it will generate corresponding binding files for control signal 1 (register 1) and control signal 2 (register 2), signal control verification component 1 (register 1), signal control verification component 2 (register 2), a signal control sequence container, a register model, and an adapter for connecting the signal control sequence container. In contrast, when the chip under test (DUT) is module 2, it generates a bind file for the control signal 3 corresponding to register 3, a signal control verification component 3, a signal control sequence container, a register model, and an adapter for connecting the signal control sequence container. As another embodiment, when the DUT is module 3, since register 4 exists internally, it generates a bind file for register 4 access, a register interface control verification component, a register model, and an adapter for connecting the register interface. The register models generated for all modules in the DUT design are identical, thus the relevant configurations can be easily integrated into the DUT design environment.

[0037] After acquiring the corresponding components, they are integrated into the verification system of the relevant modules. The control signal connection includes the hierarchical information and name of the signal to be controlled, indicating which signal the relevant signal control verification component needs to connect to. The connection method may be one of various methods provided by SystemVerilog, such as bind, assign, force, etc. The signal control verification component will be adjusted according to the description file of the corresponding register. For example, if the relevant control signal is controlled by 2 bits of a register, the interface width of the corresponding signal control verification component will also be adjusted to 2 bits. The signal control sequence container will generate different control sequences depending on the component module of the chip under test. For example, when the component module of the chip under test is module 1, since only control signal 1 exists, the control sequence generated in the signal control sequence container will only contain the control sequence corresponding to signal control verification component 1. The address signal mapping table within the signal control sequence container will also be adjusted according to the component module of the chip under test. For example, when module 1 is selected, the mapping table will only generate a mapping between registers and control signal 1.

[0038] After all environment components are integrated, the components of the chip under test (DUT) can be configured using a register model. Since the configuration sequences are unaware of the underlying implementation details and the DUT design uses a completely unified register model, the configuration sequence for the entire DUT design can be managed in a unified manner and used by the verification environments of each component module. The configuration of each component module in the DUT design is updated to a unified subsystem configuration sequence, which generates configuration sequences for each component module and also generates the configuration sequence for the entire DUT design. Compared to traditional verification methods, which may require at least two updates to the configuration sequences of the component modules and the DUT design, and where the number of component modules increases, leading to increased maintenance costs, the unified register model in this embodiment only requires updating and maintaining a single configuration sequence. Furthermore, regardless of whether a component module itself has registers, the register model can be used for configuration.

[0039] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A verification device for a chip component module without registers, characterized in that, include: The system comprises a sequence configuration module, a register model, an adapter, a signal control sequence container, M signal control verification components, and a chip-under-test (DUT) module, where M ≥ 1. The sequence configuration module generates a configuration sequence based on the read / write operation interface of the register model and the configuration requirements of the DUT module, and sends it to the register model. The DUT module is a chip component without registers in the DUT design. The register model is generated based on the register description file corresponding to the DUT design. The register model initiates a register access request to the adapter based on the configuration sequence. The adapter converts the register access request into a signal control sequence container control request and sends it to the signal control sequence container. The signal control sequence container converts the control sequence container control request into an excitation sequence and sends it to the corresponding signal control verification component. The signal control verification component converts the received excitation sequence into a drive signal and sends it to the DUT module through the corresponding control signal line.

2. The apparatus according to claim 1, characterized in that, The signal control sequence container includes an adapter interaction interface, an address signal mapping table, a container component, and M excitation sequence generation units. Each excitation sequence generation unit corresponds to a signal control verification component, and each signal control verification component is connected to the chip under test (DUT) module via a corresponding control signal line. The adapter interaction interface is used to obtain a control sequence container control request from the adapter and send it to the container component. The control sequence container control request includes a register address and a corresponding target value. The address signal mapping table is generated based on the register description file corresponding to the DUT design, and stores the mapping relationship between control signal line identifiers and register addresses. The container component is used to look up the address signal mapping table based on the register address in the control sequence container control request, obtain the corresponding target control signal line identifier, determine the target excitation sequence generation unit and the target signal control verification component based on the target control signal line identifier, and send the target value to the target excitation sequence generation unit. The excitation sequence generation unit is used to generate an excitation sequence based on the received target value.

3. The apparatus according to claim 2, characterized in that, During the process of generating the address signal mapping table based on the register description file corresponding to the chip under test design, if the control signal line identifier in the register description file corresponding to the chip under test design is inconsistent with the actual control signal line identifier, then during the generation of the address signal mapping table, the actual control signal line identifier is used to establish the mapping relationship between the control signal line identifier and the register address.

4. The apparatus according to claim 2, characterized in that, The adapter interaction interface is used to indirectly call the reg2bus and bus2reg protocol conversion functions in the register model during read and write operations through the register model, and provides a transaction-level modeling interface for the adapter to call to obtain the control sequence container control request generated based on the register access request conversion.

5. The apparatus according to claim 2, characterized in that, The excitation sequence generated by the excitation sequence generation unit is set as a passive sequence. The excitation sequence generation unit is also used to determine whether there is a call from the register model according to each clock cycle of the clock domain to which the control signal of the corresponding control signal line belongs. If there is, the drive signal controls the corresponding signal control verification component to output or obtain the corresponding drive value.

6. The apparatus according to claim 1, characterized in that, The configuration sequence includes configuration sequences generated based on verification of any chip component module in the chip under test (DUT) design and verification of the DUT. The chip component modules include those without registers and those with registers. The configuration sequence is arranged in chronological order of configuration information. Each configuration information includes the configuration information of all registers in the DUT design, and each DUT component module corresponds to at least one register. During the verification of a DUT component module, only the configuration information of the register corresponding to the DUT component module itself can be obtained; the configuration information of other chip component modules is not visible. During the verification of the DUT chip, all configuration information in the configuration sequence is visible.

7. The apparatus according to claim 1, characterized in that, The sequence configuration module is specifically used to set the execution statements for the register model based on the read and write operation interface of the register model and the configuration requirements of the chip components, and to generate the configuration sequence.

8. The apparatus according to claim 1, characterized in that, The register description file corresponding to the chip under test design includes the mapping relationship between register identifiers and register addresses, register attribute information, register fields contained in each register, and attribute information of each register field.

9. The apparatus according to claim 1, characterized in that, The chip under test is designed as a chip subsystem.

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