Flash memory device and erasing method thereof
By adjusting the erase voltage in two discharge stages, the problem of increased critical voltage in flash memory devices was solved, thus extending the device's lifespan.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-05
- Publication Date
- 2026-03-27
AI Technical Summary
During cyclic operation, the critical voltage of flash memory devices increases due to the accumulation of electrons on the oxide sidewalls, especially on dummy word lines, which increases the difficulty of erasure verification and shortens the lifespan.
The method of reducing the erase voltage in two discharge stages is adopted, which includes raising the erase voltage from the reference voltage value to the erase voltage value during the erase operation, and then reducing it to the pass voltage value and the reference voltage value in two stages after the erase time.
It effectively reduces electric field strength, slows down the rise of critical voltage and degradation of dummy word lines, and extends the lifespan of flash memory devices.
Smart Images
Figure CN121747656A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present invention relates to a memory device, and more particularly, to a flash memory device capable of prolonging the service life and an erase method thereof BACKGROUND
[0002] The cycling operation is composed of an erase operation and a program operation. After a plurality of cycling operations, electrons accumulate in the oxide sidewall of the flash memory, causing the threshold voltage to increase, and the current flowing through the source and drain to decrease. As a result, more incremental step pulse erase (ISPE) is required, and the erase verification becomes more and more difficult to pass.
[0003] Due to the configuration position, the problem of threshold voltage increase is more obvious on the dummy word line than on the general word line. The more the number of cycling operations, the greater the degree of deterioration, and finally the electrons cannot be removed, resulting in failure to pass the erase verification. SUMMARY
[0004] The flash memory device of the present invention includes a memory array and a memory control circuit. The memory array includes a plurality of memory blocks. The memory control circuit is coupled to the memory array and configured to ramp up an erase voltage applied to a target memory block among the plurality of memory blocks from a reference voltage value to an erase voltage value during an erase operation, and to ramp down the erase voltage from the erase voltage value in two discharge phases after an erase time.
[0005] The erase method of the flash memory device of the present invention includes the steps of: ramping up an erase voltage applied to a target memory block among a plurality of memory blocks from a reference voltage value to an erase voltage value during an erase operation, and ramping down the erase voltage from the erase voltage value in two discharge phases after an erase time.
[0006] Based on the above, the flash memory device and the erase method thereof of the present invention can ramp down the erase voltage in two discharge phases. As a result, the increase of the threshold voltage and the deterioration of the dummy word line can be slowed down, thereby prolonging the service life of the flash memory device. BRIEF DESCRIPTION OF DRAWINGS
[0007] Figure 1 A schematic diagram showing a flash memory device according to an embodiment of the present invention;
[0008] Figure 2 A partial schematic diagram showing a target memory block according to an embodiment of the present invention;
[0009] Figure 3An erase method step flow chart of a flash memory device according to an embodiment of the present application;
[0010] Figure 4 An erase operation waveform diagram of a flash memory device according to an embodiment of the present application. DETAILED DESCRIPTION
[0011] Reference will now be made to the exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
[0012] Referring to Figure 1 , a flash memory device 100 according to an embodiment of the present application is, for example, a NAND type or a NOR type, and includes a memory array 110 and a memory control circuit 120. The memory array 110 includes a plurality of memory blocks 112. Each of the memory blocks 112 includes a plurality of memory cells. The number of the memory blocks 112 and the memory cells is not limited in the embodiment of the present application.
[0013] The memory control circuit 120 is coupled to the memory array 110. The memory control circuit 120 is configured to select a target memory block 114 from the plurality of memory blocks 112 in the memory array 110 according to a selection command to perform a designated operation. Figure 1 The memory control circuit 120 is shown as being located in the flash memory device 100, but the memory control circuit 120 can also be a device independent of the flash memory device 100.
[0014] Referring to Figure 2 , the target memory block 114 includes a substrate 200, a first well region 210, a second well region 220, first conductors 230_0 to 230_31, second conductors 240_0, 240_1, third conductors 250_0, 250_1, and fourth conductors 260_0, 260_1. In Figure 2 , the substrate 200 has a first conductivity type, the first well region 210 has a second conductivity type and is disposed on the substrate 200, and the second well region 220 has the first conductivity type and is disposed on the first well region 210. The first conductivity type can be P-type and the second conductivity type can be N-type, but the present application is not limited thereto as long as the first conductivity type and the second conductivity type are complementary to each other.
[0015] The first conductors 230_0-230_31 are disposed on the second well region 220. The first conductors 230_0-230_31 are configured to couple to the word lines WL0-WL31, respectively. The second conductors 240_0, 240_1 are also disposed on the second well region 220. The second conductors 240_0, 240_1 are configured to couple to the dummy word lines DWLS, DWLD, respectively. The third conductors 250_0, 250_1 are disposed on the second well region 220 immediately adjacent to the substrate 200. The third conductors 250_0, 250_1 are configured to couple to the first select gate line SGS and the second select gate line SGD, respectively. The fourth conductors 260_0, 260_1 are disposed on the doped regions 270 in the surface region of the substrate 200. The doped regions 270 have the second conductivity type and are configured to couple to the bit line BL and the source line SL, respectively.
[0016] In the planar direction D, the second conductor 240_0 coupling to the dummy word line DWLS is disposed between the first conductor 230_0 coupling to the word line WL0 and the third conductor 250_0, and the second conductor 240_1 coupling to the dummy word line DWLD is disposed between the first conductor 230_1 coupling to the word line WL1 and the third conductor 250_1. In other words, the dummy word lines DWLS, DWLD are disposed outside of the word lines WL0-WL31. As a result, due to the disposition, the etching load of the DWLS, DWLD is more severe than the other word lines, causing the problem of the threshold voltage increase to be more apparent on the dummy word lines DWLS, DWLD than on the word lines WL0-WL31.
[0017] Please refer to Figure 1 , Figure 2 and Figure 3 The erase method of the flash memory device of the present embodiment is applicable to the flash memory device 100 of Figure 1 The erase method of the present embodiment will be described below in conjunction with the components in the flash memory device 100.
[0018] In step S300, the memory control circuit 120 ramps up the erase voltage Vers applied to the target memory block 114 from a reference voltage value VR to an erase voltage value VWW during an erase operation. During the erase operation, the memory control circuit 120 can apply the erase voltage Vers to the second well region 220 of the target memory block 114.
[0019] Figure 4 The voltage waveforms of the erase voltage Vers applied to the second well region 220, the source line SL, the first select gate line SGS, and the second select gate line SGD are shown in FIG. 3. The vertical axis is the voltage value, and the horizontal axis is the time. As shown in FIG. 3, the erase voltage Vers is ramped up from the reference voltage value VR to the erase voltage value VWW during the erase operation. Figure 4As shown, during the erase operation, the memory control circuit 120 can ramp up the erase voltage Vers applied to the target memory block 114 from the reference voltage value VR to the erase voltage value VWW. When the erase voltage Vers is ramped up to exceed the pass voltage value VPASS, the data stored within the target memory block 114 starts to be erased, and thus this point of time can be taken as the starting point of the erase time tERS.
[0020] In step S302, after the erase time tERS, the memory control circuit 120 can ramp down the erase voltage Vers from the erase voltage value VWW in two discharge stages. The memory control circuit 120 can ramp down the erase voltage Vers from the erase voltage value VWW to the pass voltage value VPASS in a first discharge stage Stgl. As shown, after the erase voltage value VWW is ramped down to the pass voltage value VPASS, the erase voltage Vers can be maintained at the pass voltage value VPASS for a maintenance time tm. In practical applications, the erase time tERS is, for example, 350 microseconds, and the maintenance time tm is, for example, 20 microseconds, but the present application is not limited thereto. The memory control circuit 120 can ramp down the erase voltage Vers from the pass voltage value VPASS to the reference voltage value VR in a second discharge stage Stg2. Figure 4
[0021] The first discharge time tDISl taken by the first discharge stage Stgl is in the range between 0.01 times of a block erase time and 1 times of the block erase time. The second discharge time tDIS2 taken by the second discharge stage Stg2 is less than 1 times of the block erase time. In practical applications, the first discharge time tDISl is, for example, 40 microseconds, and the second discharge time tDIS2 is, for example, 50 microseconds. Furthermore, during the erase operation, the first discharge stage Stgl and the second discharge stage Stg2 are performed in the discharge stage for the second well region 220.
[0022] Ramping down the erase voltage Vers in two discharge stages can improve the pressure difference per unit time, effectively reduce the generated electric field strength, and thus slow down the increase of the critical voltage. Furthermore, in the present embodiment, the two-stage discharge of the erase voltage Vers is performed with the existing pass voltage value VPASS, which has the advantages of reducing the chip area and manufacturing cost.
[0023] The erase voltage value VWW is greater than the pass voltage value VPASS, and the pass voltage value VPASS is greater than the reference voltage value VR. In practical applications, the erase voltage value VWW is, for example, 19 volts, the pass voltage value VPASS is, for example, 9 volts, and the reference voltage value VR is, for example, 0 volt, but the present application is not limited thereto.
[0024] In addition, during the erase operation, the bit line BL and the source line SL are floating. The first select gate line SGS and the second select gate line SGD are floating after being pulled up to the select voltage VSG. In Figure 4 In the figure, the floating state of the source line SL, the first select gate line SGS and the second select gate line SGD are represented by chain lines.
[0025] During the erase operation, the potentials of the source line SL, the first select gate line SGS and the second select gate line SGD change with the potential of the second well region 220 due to the coupling effect. As shown in Figure 4 the figure, the potentials of the source line SL, the first select gate line SGS and the second select gate line SGD in the floating state change with the erase voltage Vers applied to the target memory block 114.
[0026] In summary, the flash memory device and the erase method thereof can adjust the erase voltage in two discharge stages. In this way, the generated electric field strength can be effectively reduced, the trapped electrons in the cycling operation can be reduced, the increase of the critical voltage and the degradation of the dummy word line can be slowed down, and the service life of the flash memory device can be prolonged.
[0027] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand: the technical solutions recorded in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A flash memory device, comprising: Comprising: a memory array including a plurality of memory blocks; and a memory control circuit coupled to the memory array, configured to ramp up an erase voltage applied to a target memory block among the plurality of memory blocks from a reference voltage value to an erase voltage value during an erase operation, and to ramp down the erase voltage from the erase voltage value in two discharge phases after an erase time.
2. The flash memory device of claim 1, wherein, The memory control circuit ramps down the erase voltage from the erase voltage value to a pass voltage value in a first discharge phase, and to the reference voltage value in a second discharge phase, the erase voltage value being greater than the pass voltage value, and the pass voltage value being greater than the reference voltage value.
3. The flash memory device of claim 2, wherein, A first discharge time taken by the first discharge phase ranges between 0.01 times of a block erase time and 1 times of the block erase time, and a second discharge time taken by the second discharge phase is less than 1 times of the block erase time.
4. The flash memory device of claim 1, wherein, The target memory block includes: a substrate having a first conductivity type; a first well region having a second conductivity type, and disposed on the substrate; a second well region having the first conductivity type, and disposed on the first well region; a plurality of first conductors disposed on the second well region, configured to respectively couple a plurality of word lines; a plurality of second conductors disposed on the second well region, configured to respectively couple a plurality of dummy word lines; two third conductors disposed on the second well region and the substrate in close proximity, configured to respectively couple a first select gate line and a second select gate line; and two fourth conductors disposed on a doped region in a surface region of the substrate, configured to respectively couple a bit line and a source line.
5. The flash memory device of claim 4, wherein, In a planar direction, the second conductors coupling the dummy word lines are disposed between the first conductors coupling the word lines and the third conductors.
6. The flash memory device of claim 4, wherein, During the erase operation, the bit line and the source line are in a floating state, and the first select gate line and the second select gate line are in the floating state after being ramped up to a select voltage value.
7. The flash memory device of claim 4, wherein, During the erase operation, the memory control circuit applies the erase voltage to the second well region.
8. The flash memory device of claim 4, wherein, During the erase operation, potentials of the source line, the first select gate line and the second select gate line vary with a potential of the second well region due to a coupling effect.
9. An erasing method of a flash memory device, the method comprising: The flash memory device includes a plurality of memory blocks, and the erase method includes the following steps: during an erase operation, ramping up an erase voltage applied to a target memory block among the plurality of memory blocks from a reference voltage value to an erase voltage value; and after an erase time, ramping down the erase voltage from the erase voltage value in two discharge phases. The step of ramping down the erase voltage from the erase voltage value in two discharge phases after the erase time includes:
10. The erasing method according to claim 9, wherein, ramping down the erase voltage from the erase voltage value to a pass voltage value in a first discharge phase; and ramping down the erase voltage from the pass voltage value to a reference voltage value in a second discharge phase, wherein the erase voltage value is greater than the pass voltage value, and the pass voltage value is greater than the reference voltage value.