Impedance matching circuit, control method thereof and thin film deposition equipment

Abstract

The invention provides an impedance matching circuit, thin film deposition equipment, a control method of the impedance matching circuit and a computer readable storage medium. The impedance matching circuit comprises a first impedance matching unit which is connected with a first radio frequency coil and a first radio frequency power supply, and the first radio frequency coil is arranged at the top of a process chamber of the thin film deposition equipment; the second impedance matching unit is connected with a second radio frequency coil and a second radio frequency power supply, and the second radio frequency coil is arranged on the side wall of the process chamber; and the controller is configured to adjust the capacitance value of the first impedance matching unit and / or the second impedance matching unit so as to adjust the working frequency difference of the first radio frequency coil and the second radio frequency coil to be above a preset difference threshold value.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more specifically to an impedance matching circuit, a thin film deposition apparatus, a control method for the impedance matching circuit, and a computer-readable storage medium. Background Technology

[0002] Thin film deposition is a crucial step in semiconductor chip manufacturing, and its process quality directly determines the core performance, structural reliability, and long-term stability of the chip. CVD (Chemical Vapor Deposition) is one of the traditional thin film deposition processes. As chip manufacturing processes advance to more advanced nodes of 3nm and below, HDP-CVD (High-Density Plasma Chemical Vapor Deposition) has gradually emerged as a deposition method that can meet key process requirements such as superior thin film thickness uniformity, interface cleanliness, compositional accuracy, and film layer adhesion. However, the traditional HDP-CVD method uses a single radio frequency power supply, resulting in a plasma distribution pattern of high density at the center and low density at the edges. This leads to a "thick center, thin edge" process defect in the thin film. At the same time, due to the weak directionality of the plasma generated by a single radio frequency power supply, it is easy to accumulate at the top of high aspect ratio gaps, resulting in voids inside the gaps and seriously affecting the electrical performance of the chip. To address the aforementioned issues, the dual-source synergistic HDP-CVD method has emerged. By placing radio frequency power supplies at the top and sidewalls of the process chamber, it overcomes the physical limitations of a single radio frequency power supply, helping to generate plasmas with high uniformity, high density, and excellent high aspect ratio filling capabilities, thereby improving chip manufacturing efficiency and product yield.

[0003] In existing technologies, to reduce signal reflection and improve energy transmission efficiency, radio frequency matching technology is used to adjust the circuit parameters of the power supply, so that the impedance between the power supply and the plasma reaches an optimal matching state. However, in actual process, after the top and sidewall RF power supplies have completed RF matching and reached a stable state, if their stable frequencies are very close and the frequency difference is much smaller than their own frequencies, signal superposition will occur, resulting in frequency beats. This causes jitter in the forward power and periodic fluctuations in the reflected power due to crosstalk during the process, thereby interfering with the stability of the plasma, damaging the uniformity of the deposited film and the adhesion of the film interface, and ultimately reducing chip production efficiency and product yield.

[0004] In order to overcome the above-mentioned defects in the existing technology, there is an urgent need in the field for an impedance matching circuit, a thin film deposition equipment, a control method for the impedance matching circuit, and a computer-readable storage medium that can improve the beat frequency phenomenon in the dual-source synergistic HDP-CVD process, thereby maintaining the stability of high-density plasma, ensuring the uniformity of the deposited thin film and the adhesion of the film interface, so as to improve chip production efficiency and product yield. Summary of the Invention

[0005] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed descriptions that follow.

[0006] To overcome the aforementioned deficiencies in the prior art, this invention provides an impedance matching circuit, a thin film deposition apparatus, a control method for the impedance matching circuit, and a computer-readable storage medium. By configuring an impedance matching unit with an adjustable capacitor for each of the top and sidewall RF power supplies, the operating frequency difference between the top and sidewall RF power supplies is adjusted to above a preset difference threshold. This improves the beat frequency phenomenon in the dual-source collaborative HDP-CVD process, thereby maintaining the stability of high-density plasma, ensuring the uniformity of the deposited thin film and the adhesion of the film interface, and improving chip production efficiency and product yield.

[0007] Specifically, the impedance matching circuit provided according to the first aspect of the present invention includes: a first impedance matching unit connected to a first radio frequency coil and a first radio frequency power supply, wherein the first radio frequency coil is disposed at the top of the process chamber of a thin film deposition apparatus; a second impedance matching unit connected to a second radio frequency coil and a second radio frequency power supply, wherein the second radio frequency coil is disposed on the side wall of the process chamber; and a controller configured to: adjust the capacitance value of the first impedance matching unit and / or the second impedance matching unit to adjust the operating frequency difference between the first radio frequency coil and the second radio frequency coil to a preset difference threshold or higher.

[0008] Furthermore, in some embodiments of the present invention, the difference threshold is not less than 30 kHz.

[0009] Furthermore, in some embodiments of the present invention, the controller is further configured to: in response to the activation of the first RF coil and the second RF coil, firstly adjust the capacitance value of the first impedance matching unit and / or the second impedance matching unit to perform impedance matching between the process chamber and the first RF power supply, and between the process chamber and the second RF power supply; and in response to the optimal impedance matching state being achieved between the process chamber and the first RF power supply, and between the process chamber and the second RF power supply, perform a secondary adjustment of the capacitance value of the first impedance matching unit and / or the second impedance matching unit to adjust the operating frequency difference between the first RF coil and the second RF coil to above the difference threshold.

[0010] Furthermore, in some embodiments of the present invention, the first impedance matching unit includes a first capacitor adjustment mechanism connected in series between the first RF coil and the first RF power supply, and / or a second capacitor adjustment mechanism connected in parallel with the first RF coil; the second impedance matching unit includes a third capacitor adjustment mechanism connected in series between the second RF coil and the second RF power supply, and / or a fourth capacitor adjustment mechanism connected in parallel with the second RF coil.

[0011] Furthermore, in some embodiments of the present invention, the first capacitor adjustment mechanism includes a first adjustable capacitor, the second capacitor adjustment mechanism includes a second adjustable capacitor and / or a first parallel capacitor array, wherein the first parallel capacitor array includes a plurality of first capacitors connected in parallel and a first switch connecting each of the first capacitors, the third capacitor adjustment mechanism includes a third adjustable capacitor, and the fourth capacitor adjustment mechanism includes a fourth adjustable capacitor and / or a second parallel capacitor array, wherein the second parallel capacitor array includes a plurality of second capacitors connected in parallel and a second switch connecting each of the second capacitors.

[0012] Furthermore, in some embodiments of the present invention, the step of first adjusting the capacitance value of the first impedance matching unit and / or the second impedance matching unit to perform impedance matching between the process chamber and the first RF power supply and / or the second RF power supply includes: changing the capacitance value of the first adjustable capacitor, the second adjustable capacitor, the third adjustable capacitor and / or the fourth adjustable capacitor to perform the initial adjustment.

[0013] Furthermore, in some embodiments of the present invention, the step of performing secondary adjustment on the capacitance value of the first impedance matching unit and / or the second impedance matching unit to adjust the operating frequency difference between the first RF coil and the second RF coil to above the difference threshold includes: adjusting the number of first capacitors connected to the first parallel capacitor array via the first switch, and / or adjusting the number of first capacitors connected to the second parallel capacitor array via the second switch to perform the secondary adjustment.

[0014] Furthermore, in some embodiments of the present invention, the first switch is a normally closed switch to connect each of the first capacitors to the first parallel capacitor array, and the second switch is a normally closed switch to connect each of the second capacitors to the second parallel capacitor array. The step of adjusting the number of first capacitors connected to the first parallel capacitor array via the first switch and / or adjusting the number of first capacitors connected to the second parallel capacitor array via the second switch to perform the secondary adjustment includes: determining a first radio frequency of the first radio frequency coil and a second radio frequency of the second radio frequency coil; determining the number of capacitors to be disconnected based on the difference between the first radio frequency and the second radio frequency; and disconnecting the corresponding number of capacitors from the parallel capacitor array corresponding to the lower of the first radio frequency and the second radio frequency to perform the secondary adjustment.

[0015] Furthermore, in some embodiments of the present invention, the step of performing secondary adjustment on the capacitance value of the first impedance matching unit and / or the second impedance matching unit to adjust the operating frequency difference between the first RF coil and the second RF coil to above the difference threshold includes: continuously acquiring the forward RF power provided by the first RF coil and / or the second RF coil to the process chamber; and in response to the periodic fluctuation of the forward RF power, determining that the operating frequency difference between the first RF coil and the second RF coil is less than the difference threshold, and performing the secondary adjustment on the capacitance value of the first impedance matching unit and / or the second impedance matching unit until the periodic fluctuation is eliminated.

[0016] Furthermore, the thin film deposition apparatus provided according to the second aspect of the present invention includes: a process chamber having a first radio frequency coil disposed at its top and a second radio frequency coil disposed on its sidewall; any of the impedance matching circuits provided by the first aspect of the present invention; a first radio frequency power supply connected to the first radio frequency coil via a first impedance matching unit of the impedance matching circuit; and a second radio frequency power supply connected to the second radio frequency coil via a second impedance matching unit of the impedance matching circuit.

[0017] Furthermore, the control method for the impedance matching circuit provided by the third aspect of the present invention includes the following steps: during the process of providing a radio frequency signal to the process chamber via a first radio frequency coil disposed at the top of the process chamber and a second radio frequency coil disposed on the side wall of the process chamber, adjusting the capacitance value of the first impedance matching unit and / or the second impedance matching unit to adjust the operating frequency difference between the first radio frequency coil and the second radio frequency coil to a preset difference threshold above, wherein the first impedance matching unit is connected to the first radio frequency coil and the corresponding first radio frequency power supply, and the second impedance matching unit is connected to the second radio frequency coil and the corresponding second radio frequency power supply.

[0018] Furthermore, the computer-readable storage medium provided according to the fourth aspect of the present invention stores computer instructions thereon, characterized in that, when the computer instructions are executed by a processor, the control method for the impedance matching circuit provided by the third aspect of the present invention is implemented. Attached Figure Description

[0019] The above-described features and advantages of the present invention will be better understood after reading the following detailed description of embodiments of the present disclosure in conjunction with the accompanying drawings. In the drawings, components are not necessarily drawn to scale, and components having similar related characteristics or features may have the same or similar reference numerals.

[0020] Figure 1 A schematic diagram of an impedance matching circuit structure provided according to some embodiments of the present invention is shown.

[0021] Figure 2 A schematic diagram of the circuit structure of an impedance matching unit provided according to some embodiments of the present invention is shown.

[0022] Figure 3 A schematic flowchart of a secondary impedance adjustment method according to some embodiments of the present invention is shown.

[0023] Figure label:

[0024] First impedance matching unit 01

[0025] Second impedance matching unit 02

[0026] First radio frequency coil 03

[0027] First RF Power Supply 04

[0028] Second RF coil 05

[0029] Second RF power supply 06

[0030] Impedance matching circuit 07

[0031] Process Chamber 08

[0032] First capacitor adjustment mechanism 10

[0033] Second capacitor adjustment mechanism 20

[0034] First adjustable capacitor 11

[0035] Second adjustable capacitor 21

[0036] First capacitor 22

[0037] First switch 23 Detailed Implementation

[0038] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Although the description of the present invention is presented in conjunction with preferred embodiments, this does not mean that the features of the invention are limited to these embodiments. On the contrary, the purpose of describing the invention in conjunction with embodiments is to cover other options or modifications that may be derived based on the claims of the present invention. To provide a thorough understanding of the invention, many specific details will be included in the following description. The invention may also be implemented without using these details. Furthermore, to avoid confusion or obscuring the focus of the invention, some specific details will be omitted in the description.

[0039] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0040] Furthermore, the terms "upper," "lower," "left," "right," "top," "bottom," "horizontal," and "vertical" used in the following description should be understood as the orientations shown in the relevant paragraphs and accompanying drawings. These relative terms are for illustrative purposes only and do not imply that the described apparatus must be manufactured or operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0041] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various components, regions, layers, and / or parts, these components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, regions, layers, and / or parts. Therefore, the first components, regions, layers, and / or parts discussed below may be referred to as second components, regions, layers, and / or parts without departing from some embodiments of the present invention.

[0042] In existing technologies, to reduce signal reflection and improve energy transmission efficiency, radio frequency matching technology is used to adjust the circuit parameters of the power supply, so that the impedance between the power supply and the plasma reaches an optimal matching state. However, in actual process, after the top and sidewall RF power supplies have completed RF matching and reached a stable state, if their stable frequencies are very close and the frequency difference is much smaller than their own frequencies, signal superposition will occur, resulting in frequency beats. This causes jitter in the forward power and periodic fluctuations in the reflected power due to crosstalk during the process, thereby interfering with the stability of the plasma, damaging the uniformity of the deposited film and the adhesion of the film interface, and ultimately reducing chip production efficiency and product yield.

[0043] To overcome the aforementioned deficiencies in the prior art, this invention provides an impedance matching circuit, a thin film deposition apparatus, a control method for the impedance matching circuit, and a computer-readable storage medium. By configuring an impedance matching unit with an adjustable capacitor for each of the top and sidewall RF power supplies, the operating frequency difference between the top and sidewall RF power supplies is adjusted to above a preset difference threshold. This improves the beat frequency phenomenon in the dual-source collaborative HDP-CVD process, thereby maintaining the stability of high-density plasma, ensuring the uniformity of the deposited thin film and the adhesion of the film interface, and improving chip production efficiency and product yield.

[0044] In some non-limiting embodiments, the impedance matching circuit provided in the first aspect of the present invention can be installed in the thin film deposition apparatus provided in the second aspect of the present invention.

[0045] In some non-limiting embodiments, the control method for the impedance matching circuit provided in the third aspect of the present invention can be implemented based on the computer-readable storage medium provided in the fourth aspect of the present invention.

[0046] Please refer to the reference. Figures 1-3 .

[0047] Figure 1 A schematic diagram of an impedance matching circuit structure provided according to some embodiments of the present invention is shown.

[0048] Figure 2 A schematic diagram of the circuit structure of an impedance matching unit provided according to some embodiments of the present invention is shown.

[0049] Figure 3 A schematic flowchart of a secondary impedance adjustment method according to some embodiments of the present invention is shown.

[0050] like Figure 1 As shown, the impedance matching circuit 07 provided in the first aspect of the present invention includes a first impedance matching unit 01, a second impedance matching unit 02, and a controller.

[0051] In some embodiments, the first impedance matching unit 01 connects the first radio frequency coil 03 and the first radio frequency power supply 04, wherein the first radio frequency coil 03 is disposed on the top of the process chamber 08 of the thin film deposition apparatus.

[0052] In some embodiments, the second impedance matching unit 02 connects the second RF coil 05 and the second RF power supply 06, wherein the second RF coil 05 is disposed on the side wall of the process chamber 08 of the thin film deposition equipment.

[0053] In some embodiments, the controller is configured to adjust the capacitance values ​​of the first impedance matching unit 01 and the second impedance matching unit 02 to adjust the difference in operating frequencies between the first RF coil 03 and the second RF coil 05 to a preset difference threshold.

[0054] Optionally, in some embodiments, the controller may also be configured to adjust the capacitance value of the first impedance matching unit 01 to adjust the difference in operating frequencies between the first RF coil 03 and the second RF coil 05 to a preset difference threshold.

[0055] Optionally, in some embodiments, the controller may also be configured to adjust the capacitance value of the second impedance matching unit 02 to adjust the difference in operating frequencies between the first RF coil 03 and the second RF coil 05 to a preset difference threshold.

[0056] Thus, by configuring an impedance matching unit with an adjustable capacitor for each of the top and sidewall RF power supplies, the present invention adjusts the difference in operating frequencies between the top and sidewall RF power supplies to a preset difference threshold, thereby improving the beat frequency phenomenon in the dual-source collaborative HDP-CVD process, maintaining the stability of high-density plasma, ensuring the uniformity of the deposited film and the adhesion of the film interface, and improving chip production efficiency and product yield.

[0057] Furthermore, in some embodiments, the difference threshold is not less than 30 kHz.

[0058] Thus, by limiting the difference threshold to 30kHz and above, this invention avoids frequency beat phenomena during the collaborative operation of the top and side wall RF power supplies, further ensuring the stability of high-density plasma and improving chip production efficiency and product yield.

[0059] Furthermore, in some embodiments, the controller is further configured to: in response to the activation of the first RF coil 03 and the second RF coil 05, first adjust the capacitance value of the first impedance matching unit 01 and / or the second impedance matching unit 02 to perform impedance matching between the process chamber 08 and the first RF power supply 04, and between the process chamber 08 and the second RF power supply 06.

[0060] Furthermore, in some embodiments, the controller is further configured to: in response to the optimal impedance matching state being achieved between the process chamber 08 and the first RF power supply 04, and between the process chamber 08 and the second RF power supply 06, perform secondary adjustment on the capacitance values ​​of the first impedance matching unit 01 and / or the second impedance matching unit 02, so as to adjust the difference in operating frequencies between the first RF coil 03 and the second RF coil 05 to above the difference threshold.

[0061] Specifically, in some embodiments, the controller is further configured to: determine that the process chamber 08 and the first RF power supply 04, as well as the process chamber 08 and the second RF power supply 06, have achieved optimal impedance matching in response to the lowest reflected energy generated by the process chamber 08 at the load end and the highest energy transmission efficiency of the RF power supply.

[0062] Thus, by first performing RF matching on the top and sidewall RF power supplies and then adjusting the stable operating frequency difference between the top and sidewall RF power supplies, this invention improves the beat frequency phenomenon in the dual-source collaborative HDP-CVD process while ensuring the lowest reflected energy at the load end and the most efficient RF power transmission. This reduces forward power jitter and periodic fluctuations in reflected power during the process, thereby balancing production efficiency and product yield in the semiconductor chip manufacturing process.

[0063] Furthermore, such as Figure 2 As shown, in some embodiments, the first impedance matching unit 01 includes a first capacitor adjustment mechanism 10 connected in series between the first RF coil 03 and the first RF power supply 04 and a second capacitor adjustment mechanism 20 connected in parallel with the first RF coil 03.

[0064] Optionally, in some embodiments, the first impedance matching unit 01 includes only a first capacitor adjustment mechanism 10 connected in series between the first RF coil 03 and the first RF power supply 04.

[0065] Optionally, in some embodiments, the first impedance matching unit 01 includes only the second capacitance adjustment mechanism 20 connected in parallel with the first radio frequency coil 03.

[0066] Furthermore, in some embodiments, the second impedance matching unit 02 includes a third capacitor adjustment mechanism connected in series between the second RF coil 05 and the second RF power supply 06 and a fourth capacitor adjustment mechanism connected in parallel with the second RF coil 05.

[0067] Optionally, in some embodiments, the second impedance matching unit 02 includes only a third capacitor adjustment mechanism connected in series between the second RF coil 05 and the second RF power supply 06.

[0068] Optionally, in some embodiments, the second impedance matching unit 02 includes only a fourth capacitor adjustment mechanism connected in parallel with the second RF coil 05.

[0069] Furthermore, in some embodiments, the first capacitor adjustment mechanism 10 includes a first adjustable capacitor 11, and the second capacitor adjustment mechanism 20 includes a second adjustable capacitor 21 and / or a first parallel capacitor array, wherein the first parallel capacitor array includes a plurality of first capacitors 22 connected in parallel, and a first switch 23 connecting each first capacitor.

[0070] Furthermore, in some embodiments, the third capacitor adjustment mechanism includes a third adjustable capacitor, and the fourth capacitor adjustment mechanism includes a fourth adjustable capacitor and / or a second parallel capacitor array, wherein the second parallel capacitor array includes a plurality of second capacitors connected in parallel, and a second switch connecting each second capacitor.

[0071] Furthermore, in some embodiments, the step of first adjusting the capacitance values ​​of the first impedance matching unit 01 and / or the second impedance matching unit 02 to perform impedance matching between the process chamber 08 and the first RF power supply 04 and / or the second RF power supply 06 includes: changing the capacitance values ​​of the first adjustable capacitor 11, the second adjustable capacitor 21, the third adjustable capacitor and / or the fourth adjustable capacitor to perform the initial adjustment.

[0072] Furthermore, in some embodiments, secondary adjustment is performed by changing the capacitance values ​​of the first adjustable capacitor 11, the second adjustable capacitor 21, the third adjustable capacitor, and / or the fourth adjustable capacitor to adjust the difference in operating frequencies between the first RF coil 03 and the second RF coil 05 to above the difference threshold.

[0073] Thus, the present invention can improve the beat frequency phenomenon in the dual-source synergistic HDP-CVD process, and reduce forward power jitter and periodic fluctuations in reflected power during the process.

[0074] Optionally, in some embodiments, the difference in operating frequencies between the first RF coil 03 and the second RF coil 05 can be adjusted to a difference threshold by secondary adjustment of the capacitance values ​​of the first impedance matching unit 01 and / or the second impedance matching unit 02. The above steps include: adjusting the number of first capacitors 22 connected to the first parallel capacitor array via the first switch 23, and / or adjusting the number of first capacitors connected to the second parallel capacitor array via the second switch to perform secondary adjustment.

[0075] Thus, by controlling the opening and closing states of the capacitor branch switches in the parallel capacitor array within the impedance matching unit, this invention adjusts the operating frequency difference between the first RF coil 03 and the second RF coil 05 to a preset difference threshold. This not only improves the beat frequency phenomenon in the dual-source collaborative HDP-CVD process and reduces forward power jitter and periodic fluctuations in reflected power during the process, but also, compared to the adjustment scheme of "secondary adjustment by changing the capacitance values ​​of the first adjustable capacitor 11, the second adjustable capacitor 21, the third adjustable capacitor, and / or the fourth adjustable capacitor," this invention, by adjusting the number of capacitors connected in the parallel capacitor array, can perform impedance adjustment over a wider range, thereby expanding the operating frequency adjustment range of the RF power supply. In practical process scenarios, this effectively avoids beat frequency interference caused by dual-source collaboration, ensures process stability, and improves chip production efficiency and product yield.

[0076] Furthermore, in some embodiments, the first switch 23 is a normally closed switch to connect each of the first capacitors 22 to the first parallel capacitor array, and the second switch is a normally closed switch to connect each of the second capacitors to the second parallel capacitor array.

[0077] Specifically, in some embodiments, the first switch 23 is a relay.

[0078] Furthermore, such as Figure 3 As shown, the steps of adjusting the number of first capacitors 22 connected to the first parallel capacitor array via the first switch 23 and / or adjusting the number of first capacitors connected to the second parallel capacitor array via the second switch for secondary adjustment include:

[0079] Step S01: Determine the first radio frequency of the first radio frequency coil 03 and the second radio frequency of the second radio frequency coil 05.

[0080] Step S02: Determine the number of capacitors that need to be disconnected based on the difference between the first radio frequency and the second radio frequency.

[0081] Furthermore, in some embodiments, the number of capacitors that need to be disconnected is determined according to the following formula:

[0082]

[0083] In the formula, n is the number of capacitors that need to be disconnected, x is the frequency difference between the current first RF frequency and the second RF frequency, and F 安全 To avoid the ideal difference between the first and second radio frequency frequencies that can cause beat frequency phenomena, F 对应频率 The lower of the first radio frequency and the second radio frequency.

[0084] Specifically, in some embodiments, F 安全The frequency is set to 100kHz. When x is between 0 and 39kHz, four switches are turned off to connect the remaining eight capacitors to the parallel capacitor array; when x is between 40 and 59kHz, three switches are turned off to connect the remaining nine capacitors to the parallel capacitor array; when x is between 60 and 79kHz, two switches are turned off to connect the remaining ten capacitors to the parallel capacitor array; when x is between 80 and 99kHz, one switch is turned off to connect the remaining eleven capacitors to the parallel capacitor array; when x is greater than or equal to 100kHz, no switches need to be turned off, so that all twelve capacitors are connected to the parallel capacitor array.

[0085] Step S03: Disconnect the corresponding number of capacitors from the parallel capacitor array corresponding to the lower of the first RF frequency and the second RF frequency to perform secondary adjustment.

[0086] Specifically, in some embodiments, when the first radio frequency is lower than the second radio frequency, if the frequency difference between the two is between 0 and 39 kHz, four first switches 23 are disconnected so that the remaining eight first capacitors 22 are connected to the first parallel capacitor array; when the frequency difference between the two is between 40 and 59 kHz, three first switches 23 are disconnected so that the remaining nine first capacitors 22 are connected to the first parallel capacitor array; when x is between 60 and 79 kHz, two first switches 23 are disconnected so that the remaining ten first capacitors 22 are connected to the first parallel capacitor array; when x is between 80 and 99 kHz, one first switch 23 is disconnected so that the remaining eleven first capacitors 22 are connected to the first parallel capacitor array; when x is greater than or equal to 100 kHz, it is not necessary to disconnect the first switches 23 so that all twelve first capacitors 22 are connected to the first parallel capacitor array.

[0087] Optionally, in some embodiments, when the first radio frequency is higher than the second radio frequency, if the frequency difference between the two is between 0 and 39 kHz, four second switches are disconnected so that the remaining eight second capacitors are connected to the second parallel capacitor array; when the frequency difference between the two is between 40 and 59 kHz, three second switches are disconnected so that the remaining nine second capacitors are connected to the second parallel capacitor array; when x is between 60 and 79 kHz, two second switches are disconnected so that the remaining ten second capacitors are connected to the second parallel capacitor array; when x is between 80 and 99 kHz, one second switch is disconnected so that the remaining eleven second capacitors are connected to the second parallel capacitor array; when x is greater than or equal to 100 kHz, it is not necessary to disconnect the second switches so that all twelve second capacitors are connected to the second parallel capacitor array.

[0088] Furthermore, in some embodiments, the step of adjusting the capacitance values ​​of the first impedance matching unit 01 and / or the second impedance matching unit 02 to adjust the operating frequency difference between the first RF coil 03 and the second RF coil 05 to above a difference threshold includes:

[0089] Step S11: Continuously collect the forward RF power supplied to the process chamber 08 by the first RF coil 03 and / or the second RF coil 05.

[0090] Step S12: In response to the periodic fluctuation of the forward RF power, it is determined that the difference between the operating frequencies of the first RF coil 03 and the second RF coil 05 is less than the difference threshold, and the capacitance values ​​of the first impedance matching unit 01 and / or the second impedance matching unit 02 are adjusted a second time until the periodic fluctuation is eliminated.

[0091] Furthermore, the thin film deposition apparatus provided by the second aspect of the present invention includes a process chamber 08, any impedance matching circuit 07 provided by the first aspect of the present invention, a first radio frequency power supply 04, and a second radio frequency power supply 06.

[0092] In some embodiments, the top of the process chamber 08 is provided with a first radio frequency coil 03, and its sidewalls are provided with a second radio frequency coil 05.

[0093] In some embodiments, the first RF power supply 04 is connected to the first RF coil 03 via the first impedance matching unit 01 of the impedance matching circuit 07.

[0094] In some embodiments, the second RF power supply 06 is connected to the second RF coil 05 via the second impedance matching unit 02 of the impedance matching circuit 07.

[0095] Furthermore, the control method for the impedance matching circuit 07 provided in the third aspect of the present invention includes the following steps: during the process of providing an RF signal to the process chamber 08 via a first RF coil 03 disposed at the top of the process chamber 08 and a second RF coil 05 disposed on the side wall of the process chamber 08, adjusting the capacitance values ​​of the first impedance matching unit 01 and / or the second impedance matching unit 02 to adjust the operating frequency difference between the first RF coil 03 and the second RF coil 05 to above a preset difference threshold, wherein the first impedance matching unit 01 is connected to the first RF coil 03 and the corresponding first RF power supply 04, and the second impedance matching unit 02 is connected to the second RF coil 05 and the corresponding second RF power supply 06.

[0096] Furthermore, the fourth aspect of the present invention provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the control method of the impedance matching circuit 07 provided by the third aspect of the present invention.

[0097] Although the methods described above are illustrated and depicted as a series of actions for the sake of simplicity, it should be understood and appreciated that these methods are not limited by the order of the actions, as some actions may occur in a different order and / or concurrently with other actions from the illustrations and descriptions herein or not illustrated and described herein but which may be understood by those skilled in the art, according to one or more embodiments.

[0098] Those skilled in the art will understand that information, signals, and data can be represented using any of a variety of different techniques and skills. For example, the data, instructions, commands, information, signals, bits, symbols, and chips described throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0099] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithm steps described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps are described above in a generalized manner in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the invention.

[0100] Although the controller described in the above embodiments can be implemented through a combination of software and hardware, it is understood that the controller can also be implemented in software or hardware. For hardware implementation, the controller can be implemented using one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, other electronic devices for performing the above functions, or a selection of combinations of the above devices. For software implementation, the controller can be implemented using independent software modules such as procedures and functions running on a general-purpose chip, each module performing one or more functions and operations described herein.

[0101] The various illustrative logic modules and circuits described in conjunction with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternatives, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration.

[0102] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of both. The software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read and write information to / from the storage medium. In an alternative, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In an alternative, the processor and storage medium may reside as discrete components in the user terminal.

[0103] In one or more exemplary embodiments, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software as a computer program product, the functionality may be stored or transmitted as one or more instructions or code on or through a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, encompassing any medium that facilitates the transfer of a computer program from one location to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such a computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and is accessible to a computer. Any connection is also legitimately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of a medium. As used in this article, disk and disc include compact discs (CDs), laser discs, optical discs, digital multi-purpose discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0104] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An impedance matching circuit, characterized in that, include: The first impedance matching unit connects the first RF coil and the first RF power supply, wherein the first RF coil is located at the top of the process chamber of the thin film deposition equipment; A second impedance matching unit connects the second RF coil to the second RF power supply, wherein the second RF coil is disposed on the side wall of the process chamber; and The controller is configured to adjust the capacitance value of the first impedance matching unit and / or the second impedance matching unit to adjust the operating frequency difference between the first RF coil and the second RF coil to a preset difference threshold.

2. The impedance matching circuit as described in claim 1, characterized in that, The difference threshold is not less than 30KHz.

3. The impedance matching circuit as described in claim 1, characterized in that, The controller is further configured to: In response to the activation of the first RF coil and the second RF coil, the capacitance values ​​of the first impedance matching unit and / or the second impedance matching unit are initially adjusted to perform impedance matching between the process chamber and the first RF power supply, and between the process chamber and the second RF power supply. as well as In response to the optimal impedance matching state being achieved between the process chamber and the first RF power supply, and between the process chamber and the second RF power supply, the capacitance values ​​of the first impedance matching unit and / or the second impedance matching unit are adjusted a second time to adjust the operating frequency difference between the first RF coil and the second RF coil to above the difference threshold.

4. The impedance matching circuit as described in claim 3, characterized in that, The first impedance matching unit includes a first capacitor adjustment mechanism connected in series between the first RF coil and the first RF power supply, and / or a second capacitor adjustment mechanism connected in parallel with the first RF coil. The second impedance matching unit includes a third capacitor adjustment mechanism connected in series between the second RF coil and the second RF power supply, and / or a fourth capacitor adjustment mechanism connected in parallel with the second RF coil.

5. The impedance matching circuit as described in claim 4, characterized in that, The first capacitor adjustment mechanism includes a first adjustable capacitor, and the second capacitor adjustment mechanism includes a second adjustable capacitor and / or a first parallel capacitor array, wherein the first parallel capacitor array includes a plurality of first capacitors connected in parallel, and a first switch connecting each of the first capacitors. The third capacitor adjustment mechanism includes a third adjustable capacitor, and the fourth capacitor adjustment mechanism includes a fourth adjustable capacitor and / or a second parallel capacitor array, wherein the second parallel capacitor array includes a plurality of second capacitors connected in parallel, and a second switch connecting each of the second capacitors.

6. The impedance matching circuit as described in claim 5, characterized in that, The step of first adjusting the capacitance value of the first impedance matching unit and / or the second impedance matching unit to perform impedance matching between the process chamber and the first RF power supply and / or the second RF power supply includes: The initial adjustment is performed by changing the capacitance values ​​of the first adjustable capacitor, the second adjustable capacitor, the third adjustable capacitor, and / or the fourth adjustable capacitor.

7. The impedance matching circuit as described in claim 5, characterized in that, The step of performing secondary adjustment on the capacitance values ​​of the first impedance matching unit and / or the second impedance matching unit to adjust the operating frequency difference between the first RF coil and the second RF coil to above the difference threshold includes: The secondary adjustment is performed by adjusting the number of first capacitors connected to the first parallel capacitor array via the first switch, and / or adjusting the number of first capacitors connected to the second parallel capacitor array via the second switch.

8. The impedance matching circuit as described in claim 7, characterized in that, The first switch is a normally closed switch to connect all the first capacitors to the first parallel capacitor array, and the second switch is a normally closed switch to connect all the second capacitors to the second parallel capacitor array. The step of adjusting the number of first capacitors connected to the first parallel capacitor array via the first switch and / or adjusting the number of first capacitors connected to the second parallel capacitor array via the second switch to perform the secondary adjustment includes: Determine the first radio frequency of the first radio frequency coil and the second radio frequency of the second radio frequency coil; Based on the difference between the first radio frequency and the second radio frequency, determine the number of capacitors that need to be disconnected; and Disconnect a corresponding number of capacitors from the parallel capacitor array corresponding to the lower of the first radio frequency and the second radio frequency to perform the secondary adjustment.

9. The impedance matching circuit as described in claim 5, characterized in that, The step of performing secondary adjustment on the capacitance values ​​of the first impedance matching unit and / or the second impedance matching unit to adjust the operating frequency difference between the first RF coil and the second RF coil to above the difference threshold includes: Continuously acquire the forward RF power supplied to the process chamber by the first RF coil and / or the second RF coil; and In response to the periodic fluctuations in the forward RF power, it is determined that the difference in operating frequencies between the first RF coil and the second RF coil is less than the difference threshold, and the capacitance values ​​of the first impedance matching unit and / or the second impedance matching unit are adjusted in the secondary manner until the periodic fluctuations are eliminated.

10. A thin film deposition apparatus, characterized in that, include: The process chamber has a first radio frequency coil on its top and a second radio frequency coil on its side wall; Impedance matching circuit as described in any one of claims 1 to 9; The first radio frequency power supply is connected to the first radio frequency coil via the first impedance matching unit of the impedance matching circuit; as well as The second RF power supply is connected to the second RF coil via the second impedance matching unit of the impedance matching circuit.

11. A control method for an impedance matching circuit, characterized in that, Includes the following steps: During the process of providing radio frequency signals to the process chamber via a first radio frequency coil located at the top of the process chamber and a second radio frequency coil located on the side wall of the process chamber, the capacitance values ​​of the first impedance matching unit and / or the second impedance matching unit are adjusted to adjust the operating frequency difference between the first radio frequency coil and the second radio frequency coil to a preset difference threshold above. The first impedance matching unit is connected to the first radio frequency coil and the corresponding first radio frequency power supply, and the second impedance matching unit is connected to the second radio frequency coil and the corresponding second radio frequency power supply.

12. A computer-readable storage medium storing computer instructions thereon, characterized in that, When the computer instructions are executed by the processor, the control method for the impedance matching circuit as described in claim 11 is implemented.

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