Comparator circuit

Abstract

A comparator circuit includes a matching capacitor in series with a first switching device and a second switching device. The first switching device and the second switching device are connected in parallel between the matching capacitor and a reference voltage. The comparator circuit further comprises a sampling capacitor which is connected with the third switching device and the fourth switching device in series. A third switching device is connected in series between the sampling capacitor and the DAC, and a fourth switching device is connected in series between the sampling capacitor and the input voltage. The comparator circuit also includes a comparator having an inverting input terminal and a non-inverting input terminal. The inverting input terminal is capacitively coupled to the matching capacitor, and the non-inverting input terminal is capacitively coupled to the sampling capacitor. The comparator circuit further comprises a fifth switching device and a sixth switching device, and the fifth switching device and the sixth switching device are connected between the matching capacitor and the sampling capacitor in series.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to comparators in electronic circuits. More specifically, embodiments of the present disclosure relate to high-speed auto-zero comparators with modulatable reference and reference observability support. BACKGROUND

[0002] Comparators are devices that are widely used in electronic circuits. They typically compare two voltages or currents and output a digital signal indicating which is larger. Comparators typically include a dedicated high-gain differential amplifier and are often used in devices that measure and digitize analog signals, such as analog-to-digital converters (ADCs) and relaxation oscillators.

[0003] In certain applications (e.g., automotive, industrial, microcontrollers, programmable systems on chip (PSoC), etc.), high-bandwidth voltage-to-pulse width modulation (PWM) transfer functions are needed to support certain switching loop implementations. These applications also require precise event detection mechanisms (e.g., overvoltage or overcurrent) to enable fast fault and accurate detection.

[0004] To address these requirements, precision comparators with modulatable reference (e.g., controlled by a digital-to-analog converter (DAC)) can be used, such as Figure 1 a high-speed auto-zero comparator circuit 100 with dedicated auto-zero phase as shown.

[0005] As shown in Figure 1 Comparator circuit 100 includes a comparator 102 connected to input terminals 121-122 (e.g., inverting and non-inverting terminals) that are capacitively coupled to a matching capacitor 101 and a sampling capacitor 111 of comparator circuit 100. Comparator 102 provides a complementary output signal at an output terminal 123 by comparing input signals applied to input terminals 121-122. Matching capacitor 101 (also referred to as dummy capacitor) and sampling capacitor 111 can have the same capacitance value. As further shown in Figure 1 Comparator circuit 100 also includes switches 103-104 connected in series between matching capacitor 101 and sampling capacitor 111, with matching capacitor 101 connected between ground (GND) and switch 103. Input terminal 121 is also connected to a node between matching capacitor 101 and switch 103, and input terminal 122 is also connected to a node between switch 104 and sampling capacitor 111. A common mode voltage (VCM) is connected to a node between switch 103 and switch 104.

[0006] Further, the comparator circuit 100 also includes a switch 105 connected between the input voltage VIN and the sampling capacitor 111, and switches 106-107 connected in series between a node between the switch 105 and the sampling capacitor 111 and GND. The comparator circuit 100 also includes a capacitive digital-to-analog converter (CAP DAC) 120 connected to a node between the sampling capacitor 111 and the input terminal 122. As shown, the CAP DAC 120 includes a capacitor (or capacitor array) 112 and a switch array 108-110. The switch 108 is connected in series between the capacitor array 112 and GND or a reference voltage high (VREFH), and the node between the sampling capacitor 111 and the input terminal 122. The switches 109-110 are connected in parallel between the node between the capacitor 112 and the switch 108 and VREFH to form a capacitive DAC.

[0007] During the auto-zero phase, the switches 103, 104, 106, 107, 110 are closed, and the rest of the switches are open. During the sampling phase, the switches 103, 105, 110 are closed. During the resolution phase, the switches 106, 107 are closed, and the DAC switch array (108, 109) is configured to inject a reference voltage in the form of charge, which results in the voltage at the switch 104 being resolved by the comparator 102 at its output terminal 123.

[0008] Unfortunately, in the architecture of the comparator circuit 100, VREFH is not observable, there is a gain error due to mismatch between the sampling capacitor 111 and the CAP DAC 120, the sampling capacitor used becomes larger to contain the gain error (which results in slower DAC conversion), and the larger sampling capacitor will correspond to lower input impedance. Further, with the architecture of the comparator circuit 100, a periodic dedicated auto-zero phase is required, resulting in periodic blind zones containing the offset voltage of the comparator 102. SUMMARY

[0009] Some embodiments provide a comparator circuit comprising: a matching capacitor in series with a first switching device and a second switching device, wherein the first switching device and the second switching device are in parallel between the matching capacitor and a reference voltage. The matching capacitor further comprises: a sampling capacitor in series with a third switching device and a fourth switching device, wherein the third switching device is in series between the sampling capacitor and a DAC, and the fourth switching device is in series between the sampling capacitor and an input voltage; and a comparator having an inverting input terminal and a non-inverting input terminal, wherein the inverting input terminal is capacitively coupled to the matching capacitor, and the non-inverting input terminal is capacitively coupled to the sampling capacitor; and a fifth switching device and a sixth switching device in series between the matching capacitor and the sampling capacitor.

[0010] Some embodiments provide a comparator circuit comprising: a plurality of cascaded comparator amplifiers; a matching capacitor in series with a first switching device and a second switching device, wherein the first switching device and the second switching device are in parallel between the matching capacitor and a common mode voltage; and a sampling capacitor in series with a third switching device and a fourth switching device, wherein the third switching device is in series between the sampling capacitor and an input voltage, and the fourth switching device is in series between the sampling capacitor and a reference voltage; wherein a first comparator of the plurality of cascaded comparator amplifiers comprises an inverting input terminal and a non-inverting input terminal, wherein the inverting input terminal is capacitively coupled to the matching capacitor, and the non-inverting input terminal is capacitively coupled to the sampling capacitor.

[0011] Some embodiments provide a comparator circuit comprising: a plurality of cascaded comparator amplifiers; a matching capacitor in series with a first switching device and a second switching device, wherein the first switching device and the second switching device are in parallel between the matching capacitor and a common mode voltage; and a sampling capacitor in series with a third switching device and a fourth switching device, wherein the third switching device is in series between the sampling capacitor and an input voltage, and the fourth switching device is in series between the sampling capacitor and a DAC; wherein a first comparator of the plurality of cascaded comparator amplifiers comprises an inverting input terminal and a non-inverting input terminal, wherein the inverting input terminal is capacitively coupled to the matching capacitor, and the non-inverting input terminal is capacitively coupled to the sampling capacitor. BRIEF DESCRIPTION OF DRAWINGS

[0012] Embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like references indicate similar elements. FIG. 1 illustrates a comparator circuit according to some embodiments.

[0013] Figure 1is a schematic diagram of a conventional auto-zero comparator circuit with a modulatable reference using a capacitive DAC.

[0014] Figure 2 is a schematic diagram of an incremental auto-zero comparator circuit according to an embodiment.

[0015] Figure 3A is a schematic diagram showing an incremental auto-zero high-speed comparator circuit operating in a sampling phase according to an embodiment.

[0016] Figure 3B is a schematic diagram showing an incremental auto-zero high-speed comparator circuit operating in a resolution phase according to an embodiment. Figure 3A

[0017] Figure 3C is a timing diagram showing clock signals and comparator output signals associated with the comparator circuit of Figures 3A-3B

[0018] Figure 4 is a schematic diagram of an incremental auto-zero high-speed comparator circuit with a DAC as a reference according to an embodiment.

[0019] Figure 5A is a schematic diagram of an incremental auto-zero high-speed comparator circuit with reference voltage observability according to an embodiment.

[0020] Figure 5B is a timing diagram showing signals associated with the comparator circuit of Figure 5A DETAILED DESCRIPTION

[0021] Various embodiments and aspects of the application will be described in relation to the details discussed below, and the accompanying drawings will illustrate the various embodiments. The following description and drawings are illustrative of the application and are not to be construed as limiting the application. Numerous specific details are described to provide a thorough understanding of various embodiments of the present application. However, in certain instances, well-known or conventional details are not described in order to provide a concise discussion of embodiments of the present application.

[0022] Reference throughout the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0023] ​​​According to one aspect, a comparator circuit can include a matching capacitor in series with a first switching device and a second switching device. The first switching device and the second switching device can be connected in parallel between the matching capacitor and a reference voltage. The comparator circuit can also include a sampling capacitor in series with a third switching device and a fourth switching device. The third switching device can be connected in series between the sampling capacitor and a DAC, and the fourth switching device can be connected in series between the sampling capacitor and an input voltage. The comparator circuit can also include a comparator having an inverting input terminal and a non-inverting input terminal. The inverting input terminal can be capacitively coupled to the matching capacitor, and the non-inverting input terminal can be capacitively coupled to the sampling capacitor. The comparator circuit can also include a fifth switching device and a sixth switching device connected in series between the matching capacitor and the sampling capacitor.

[0024] According to another aspect, a comparator circuit can include a plurality of cascaded comparator amplifiers. The comparator circuit can also include a matching capacitor in series with a first switching device and a second switching device. The first switching device and the second switching device can be connected in parallel between the matching capacitor and a common mode voltage. The comparator circuit can also include a sampling capacitor in series with a third switching device and a fourth switching device. The third switching device can be connected in series between the sampling capacitor and an input voltage, and the fourth switching device can be connected in series between the sampling capacitor and a reference voltage. In an implementation, a first comparator of the cascaded comparator amplifiers can include an inverting input terminal and a non-inverting input terminal. The inverting input terminal can be capacitively coupled to the matching capacitor, and the non-inverting input terminal can be capacitively coupled to the sampling capacitor.

[0025] According to yet another aspect, a comparator circuit can include a plurality of cascaded comparator amplifiers. The comparator circuit can also include a matching capacitor in series with a first switching device and a second switching device. The first switching device and the second switching device can be connected in parallel between the matching capacitor and a common mode voltage. The comparator circuit can also include a sampling capacitor in series with a third switching device and a fourth switching device. The third switching device can be connected in series between the sampling capacitor and an input voltage, and the fourth switching device can be connected in series between the sampling capacitor and a DAC. In an implementation, a first comparator of the cascaded comparator amplifiers can include an inverting input terminal and a non-inverting input terminal. The inverting input terminal can be capacitively coupled to the matching capacitor, and the non-inverting input terminal can be capacitively coupled to the sampling capacitor.

[0026] Figure 2 is a schematic diagram of an incremental auto-zero comparator circuit according to an implementation. Referring to Figure 2The comparator circuit 200 can include, but is not limited to, switches (or switching devices) 201-202, 204-205, 207-208 (e.g., metal oxide semiconductor (MOS) switches), a matching capacitor 203, a sampling capacitor 206, a voltage digital-to-analog converter (DAC) 209, and a comparator 210 (e.g., a differential amplifier such as an operational amplifier (op-amp), a latch comparator, etc.).

[0027] As shown, the comparator 210 can be connected to input terminals 221-222 (e.g., inverting and non-inverting terminals), which can be capacitively coupled to the matching capacitor 203 and the sampling capacitor 206, respectively. The comparator 210 can provide a complementary output signal at an output terminal 211 by comparing input signals applied to the input terminals 221-222. In some implementations, the matching capacitor 203 and the sampling capacitor 206 can have the same capacitance value. As further shown in Figure 2 As further shown, the switches 204-205 can be connected in series between the matching capacitor 203 and the sampling capacitor 206. The switches 201-202 can be connected in parallel between a reference voltage (VREF) and the matching capacitor 203. The switch 207 can be connected in series with the DAC 209 and the sampling capacitor 206, with the switch 207 between the DAC 209 and the sampling capacitor 206. The switch 208 can be connected in series with an input voltage (VIN) and the sampling capacitor 206, with the switch 208 between the VIN and the sampling capacitor 206. In implementations, the VIN and the DAC 209, along with their input bits, can be swapped with each other to obtain a complementary comparison. In implementations, the circuitry connected to the negative input 221 of the comparator and the circuitry connected to the positive input 222 of the comparator can be swapped to generate a complementary function.

[0028] In implementations, the input terminal 221 can also be connected to a node between the matching capacitor 203 and the switch 204, and the input terminal 222 can also be connected to a node between the switch 205 and the sampling capacitor 206. The VREF can also be connected to a node between the switch 204 and the switch 205.

[0029] In operation, during a first phase of the clock cycle (e.g., the sample and auto-zero phase φ1), switches 202, 204-205, and 208 can be on (closed), and switches 201 and 207 can be off (open). During a second phase of the clock cycle (e.g., the resolve phase φ2), switches 202, 204-205, and 208 can be off (open), and switches 201 and 207 can be on (closed) to connect the DAC 209 to the sample capacitor 206 and VREF to the match capacitor 201. In this scenario, the sample capacitor 206 can be used to compare VIN to the DAC voltage generated by the DAC input bit configuration value.

[0030] In an implementation, the comparator circuit 200 can also include a windowed sampling mechanism of the DAC voltage including a resistor 223, a switch (or switching device) 224, and a DAC sample capacitor 225 connected in series between the DAC 209 (and VIN) and GND 226. In the sample phase, the switch 224 can be on (closed) to sample the DAC 209 using the DAC sample capacitor 225 to obtain DAC observability. This implementation allows for a separate windowed phase (φDAC) to control the switch 224, which can have a delayed rising edge (phase delay) compared to the sample phase when the DAC 209 is sampled. Further, the dedicated φDAC phase enables incremental charging of the DAC sample capacitor 225 when the DAC 209 is in a stable phase, thereby avoiding overshoot / undershoot error integration.

[0031] Using the architecture of the comparator 200, there is no dead zone because incremental auto-zeroing of the offset voltage of the comparator 210 is performed while sampling the signal (e.g., VIN). Further, the signal sampling (first phase) is followed by voltage superposition of the DAC 209 (second phase) for comparison. In this way, there is no voltage division in the sampled voltage (thus, a smaller sample capacitor can be used), the DAC 209 needs to charge the small parasitic capacitance of the sample capacitor 206 (which results in a relatively low power faster transient), and there is no gain error due to non-capacitor mismatch. Further, with the architecture of the comparator 200, windowed DAC sampling for DAC observability can be performed during operation. Thus, the DAC reference is observable without transient parameter performance loss, which is often a requirement for safety critical applications.

[0032] Figure 3A is a schematic diagram illustrating an incremental auto-zeroing high-speed comparator circuit operating in a sample phase, in accordance with an implementation. Referring to Figure 3AThe auto-zeroing high-speed comparator circuit 300 includes, but is not limited to, comparators 309, 314, 319, switches (or switching devices) 301-302, 304-305, 307-308, 312-313, 317-318 (e.g., MOS switches), a matching capacitor 303, a sampling capacitor 306, and capacitors 310-311, 315-316.

[0033] As shown, comparators (or comparator amplifiers) 309, 314, and 319 can be connected in cascade to provide greater gain with minimal delay time. Output terminals 333-334 of comparator 309 can be capacitively coupled to input terminals 335-336 of comparator 314 via capacitors 310-311, respectively. Output terminals 337-338 of comparator 314 can be capacitively coupled to input terminals 339-340 of comparator 319 via capacitors 315-316, respectively. In some embodiments, comparators 309 and 314 can be preamplifiers (e.g., differential amplifiers such as op-amps) that amplify input signals applied to input terminals 331-332, and comparator 319 can be a latching comparator (e.g., a strong-arm latch) that outputs a complementary output signal at output terminal 320 by comparing the amplified input signals. In embodiments, each of terminals 333-340 can be an inverting terminal or a non-inverting terminal.

[0034] With continued reference to Figure 3A Comparator 309 can be connected to input terminals 331-332 (e.g., inverting and non-inverting terminals), which can be capacitively coupled to matching capacitor 303 and sampling capacitor 306, respectively. In some embodiments, matching capacitor 303 and sampling capacitor 306 can have the same capacitance value. Switches 304-305 can be connected in series between matching capacitor 303 and sampling capacitor 306. A common mode voltage (VCM) can be connected to a node between switch 304 and switch 305. In embodiments, switches 301-302 can be connected in parallel between VCM and matching capacitor 303. Switch 307 can be connected in series with an input voltage (VINP) 321 and sampling capacitor 306, with switch 307 disposed between VINP 321 and sampling capacitor 306. Switch 308 can be connected in series with a reference voltage 322 and sampling capacitor 306, with switch 308 disposed between VREF 322 and sampling capacitor 306.

[0035] In an implementation, switches 312-313 can be connected in series between capacitor 310 and capacitor 311, with VCM connected to the node between switch 312 and switch 313. Similarly, switches 317-318 can be connected in series between capacitor 315 and capacitor 316, with VCM connected to the node between switch 317 and switch 318.

[0036] Still referring to Figure 3A During the sampling phase, switches 301, 304-305, 307, 312-313, and 317-318 can be on (closed), and switches 302 and 308 can be off (open) to sample VINP 321 via sampling capacitor 306. In the sampling phase, the voltage across sampling capacitor 306 can equal (VCM - VINP). Further, the same sampling phase can be used for auto-zeroing of comparators 309, 314, and 319 when VINP is sampled. At each sampling cycle, the charge lost on the auto-zero capacitors (e.g., capacitors 310, 311, 315, 318) can also be replenished, or the offset of the comparators can also be stored in the auto-zero capacitors in an incremental manner. This incremental auto-zeroing of the offset voltage will eliminate the need for a separate AZ phase, avoiding blind zones of the comparators.

[0037] Now referring to Figure 3B During the resolution phase, switches 301, 304-305, 307, 312-313, and 317-318 can be off (open), and switches 302 and 308 can be on (closed). In this phase, the voltages at input terminals 331-332 can be used for comparison. In some implementations, the voltage at input terminal 331 (V N ) and the voltage at input terminal 332 (V P ) can be calculated as follows:

[0038] V P = (VCM - VINP + VREF)

[0039] V N = VCM

[0040] Figure 3C is a timing diagram showing the clock signal and comparator output signal associated with the comparator circuit of Figures 3A-3B . In Figure 3CIn this embodiment, clock signal 380 can be used, for example, to control switches 301 to 302, 304 to 305, 307 to 308, 312 to 313, and 317 to 318. As shown, clock signal 380 may include multiple sampling and auto-zeroing phases 350A to 350C (e.g., during a low state) and multiple resolution phases 351A to 351C (e.g., during a high state). The phase duration 370 of the sampling and auto-zeroing phases and the phase duration 371 of the resolution phases may both be in the range of nanoseconds (ns), but embodiments of this disclosure are not limited to this example. Figure 3C In this configuration, a complementary comparator output signal 390 can be generated at output terminal 320. The output signal 390 may include multiple valid data areas 360A to 360C.

[0041] Figure 4 This is a schematic diagram illustrating an incremental automatic return-to-zero high-speed comparator circuit with a DAC as a reference, according to an embodiment. Figure 4 In the middle, the comparator circuit 400 is similar to Figure 3B The comparator circuit 300. Therefore, for the sake of brevity, the common components between comparator circuit 400 and comparator circuit 300 will not be described here (e.g., comparators 309, 314, 319, switches 301 to 302, 304 to 305, 307 to 308, 312 to 313, 317 to 318, matching capacitor 303, sampling capacitor 306, and capacitors 310 to 311, 315 to 316).

[0042] like Figure 4 As shown, the output of DAC 410 can be used as a reference instead of VREF 322 (e.g., as...). Figure 3B (As shown). In this embodiment, the DAC output is superimposed on the same (small) sampling capacitor 306 in the resolving phase. Furthermore, the architecture of the comparator circuit 400 does not have a voltage divider relative to the sampling capacitor 306; therefore, there is no additional gain error, and a significant reduction in the sampling capacitor can be achieved. This architecture also allows the DAC 410 to be lightly loaded by the parasitic capacitance of the base plate of the sampling capacitor 306, resulting in a faster DAC transient response.

[0043] Figure 5A This is a schematic diagram illustrating an incremental auto-zero high-speed comparator circuit with observable reference voltage according to an embodiment. Figure 5A In the middle, the comparator circuit 500 is similar to Figure 4comparator circuit 400. Thus, for brevity, common components between comparator circuit 500 and comparator circuit 400 (e.g., comparators 309, 314, 319, switches 301-302, 304-305, 307-308, 312-313, 317-318, matching capacitor 303, sampling capacitor 306, capacitors 310-311, 315-316, and DAC 410) will not be described herein.

[0044] As shown in FIG. 5, comparator circuit 500 can include a comparator circuit 500 that is similar to comparator circuit 400. Thus, for brevity, common components between comparator circuit 500 and comparator circuit 400 (e.g., comparators 309, 314, 319, switches 301-302, 304-305, 307-308, 312-313, 317-318, matching capacitor 303, sampling capacitor 306, capacitors 310-311, 315-316, and DAC 410) will not be described herein. Figure 5A As shown, in addition to the components shown in comparator circuit 400, comparator circuit 500 can include a windowed sampling mechanism 530 of the DAC voltage that includes a resistor 512, a switch (or switching device) 514, and a DAC sampling capacitor 516 connected in series between DAC 410 and GND 518. In the sampling phase, switch 514 can also be turned on (closed) to sample DAC 410 using DAC sampling capacitor 516 to obtain DAC observability. This embodiment allows for a separate windowed phase (φDAC) to be used to control switch 514, which can have a delayed rising edge (phase delay) compared to the sampling phase when DAC 410 is being sampled. Furthermore, the dedicated φDAC phase enables incremental charging of DAC sampling capacitor 516 when DAC 410 is in the settling phase, thereby avoiding overshoot / undershoot error integration.

[0045] Figure 5B is a timing diagram showing signals associated with comparator circuit 500. In Figure 5B the incremental auto-zero concept is shown, in which the DAC offset is stored in the auto-zero capacitor in increments in successive auto-zero phases, such that after a number of clock cycles, a significant portion of the offset of the comparator is eliminated. As shown, clock signal 501 can be used to control switches 301-302, 304-305, 307-308, 312-313, 317-318, 514. Clock signal 501 can include a plurality of sampling and auto-zero phases 550A-550C (e.g., during a low state) and a plurality of resolution phases 551A-551C (e.g., during a high state). The phase duration 540 of the sampling and auto-zero phases and the phase duration 541 of the resolution phases can each be in the range of nanoseconds, although embodiments of the present disclosure are not limited to this example. In Figure 5B at output terminal 320. Output signal 502 can include a plurality of valid data regions 560A-560C.

[0046] As shown in FIG. 5, comparator circuit 500 can include a comparator circuit 500 that is similar to comparator circuit 400. Thus, for brevity, common components between comparator circuit 500 and comparator circuit 400 (e.g., comparators 309, 314, 319, switches 301-302, 304-305, 307-308, 312-313, 317-318, matching capacitor 303, sampling capacitor 306, capacitors 310-311, 315-316, and DAC 410) will not be described herein. Figure 5BAs further shown, the sampling phase 503 and the windowing phase (φDAC) 504 can have a delayed rising edge time 570 to enable a DAC (e.g., DAC 410) to stabilize prior to sampling. The sampled DAC voltage is shown in a DAC voltage signal 505, and a voltage signal 590 shows the integrated (or superimposed) DAC voltage at a sampling capacitor (e.g., sampling capacitor 516) of the DAC.

[0047] Various units, circuits, or other components can be described or claimed as “configured to” or “configurable to” perform one or more tasks. In this context, the phrase “configured to” or “configurable to” generally means that the unit / circuit / component is equipped with a particular structure that performs the task(s). As such, the unit / circuit / component is configured to perform the task(s) even when the unit / circuit / component is not currently operational (e.g., not powered on). The described unit / circuit / component includes hardware — e.g., circuitry, memory to store program instructions executable to implement the operation, etc. — that is specifically placed into a

[0048] In the foregoing specification, embodiments of the application have been described with reference to specific exemplary embodiments thereof. It is evident, however, that various modifications can be made thereto without departing from the broader spirit and scope of the application as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A comparator circuit, comprising: A matching capacitor is connected in series with a first switching device and a second switching device, wherein the first switching device and the second switching device are connected in parallel between the matching capacitor and a reference voltage; A sampling capacitor is connected in series with a third switching device and a fourth switching device, wherein the third switching device is connected in series between the sampling capacitor and the digital-to-analog converter, and the fourth switching device is connected in series between the sampling capacitor and the input voltage; A comparator having an inverting input terminal and a non-inverting input terminal, wherein the inverting input terminal is capacitively coupled to the matching capacitor, and the non-inverting input terminal is capacitively coupled to the sampling capacitor; and A fifth switching device and a sixth switching device are connected in series between the matching capacitor and the sampling capacitor.

2. The comparator circuit according to claim 1, wherein, The reference voltage is connected to the node between the fifth switching device and the sixth switching device.

3. The comparator circuit according to claim 1, wherein, During the sampling phase, the second, fourth, fifth, and sixth switching devices are closed, and the first and third switching devices are open, so as to automatically return the offset voltage of the comparator to zero and sample the input voltage.

4. The comparator circuit according to claim 1, wherein, During the phase resolution, the second, fourth, fifth, and sixth switching devices are disconnected, and the first and third switching devices are closed to charge the sampling capacitor via the digital-to-analog converter.

5. The comparator circuit according to claim 1, further comprising the first switching device, the second switching device, the third switching device, the fourth switching device, and the digital-to-analog converter, wherein, The first switching device, the second switching device, the third switching device, the fourth switching device, the fifth switching device, and the sixth switching device selectively open and close in response to the phase of a clock signal.

6. A comparator circuit, comprising: Multiple cascaded comparator amplifiers; A matching capacitor, wherein the matching capacitor is connected in series with a first switching device and a second switching device, wherein the first switching device and the second switching device are connected in parallel between the matching capacitor and the common-mode voltage; and A sampling capacitor is connected in series with a third switching device and a fourth switching device, wherein the third switching device is connected in series between the sampling capacitor and the input voltage, and the fourth switching device is connected in series between the sampling capacitor and the reference voltage; The first comparator in the plurality of cascaded comparator amplifiers includes an inverting input terminal and a non-inverting input terminal, wherein the inverting input terminal is capacitively coupled to the matching capacitor and the non-inverting input terminal is capacitively coupled to the sampling capacitor.

7. The comparator circuit according to claim 6, further comprising: The first switching device, the second switching device, the third switching device, and the fourth switching device; A fifth switching device and a sixth switching device are connected in series between the matching capacitor and the sampling capacitor.

8. The comparator circuit according to claim 7, wherein: The comparator circuit also includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; The output terminal of the first capacitor is capacitively coupled to the input terminal of the second capacitor in the plurality of cascaded comparator amplifiers via the first capacitor and the second capacitor, respectively. The output terminal of the second capacitor is capacitively coupled to the input terminal of the third capacitor in the plurality of cascaded comparator amplifiers via the third capacitor and the fourth capacitor, respectively.

9. The comparator circuit according to claim 8, further comprising: A seventh switching device and an eighth switching device, wherein the seventh switching device and the eighth switching device are connected in series between the first capacitor and the second capacitor; as well as A ninth switching device and a tenth switching device are connected in series between the third capacitor and the fourth capacitor.

10. The comparator circuit according to claim 9, wherein, The common-mode voltage is connected to the node between the fifth and sixth switching devices, the node between the seventh and eighth switching devices, and the node between the ninth and tenth switching devices.

11. The comparator circuit according to claim 10, wherein, During the first phase of the clock cycle, the first, third, fifth, sixth, seventh, eighth, ninth, and tenth switching devices are closed, and the second and fourth switching devices are open, so that the offset voltages of the first, second, and third comparators are automatically returned to zero, and the input voltage is sampled.

12. The comparator circuit according to claim 11, wherein, During the second phase of the clock cycle, the first, third, fifth, sixth, seventh, eighth, ninth, and tenth switching devices are disconnected, while the second and fourth switching devices are closed, charging the sampling capacitor via the reference voltage.

13. A comparator circuit, comprising: Multiple cascaded comparator amplifiers; A matching capacitor, wherein the matching capacitor is connected in series with a first switching device and a second switching device, wherein the first switching device and the second switching device are connected in parallel between the matching capacitor and the common-mode voltage; and A sampling capacitor is connected in series with a third switching device and a fourth switching device, wherein the third switching device is connected in series between the sampling capacitor and the input voltage, and the fourth switching device is connected in series between the sampling capacitor and the digital-to-analog converter; The first comparator in the plurality of cascaded comparator amplifiers includes an inverting input terminal and a non-inverting input terminal, wherein the inverting input terminal is capacitively coupled to the matching capacitor and the non-inverting input terminal is capacitively coupled to the sampling capacitor.

14. The comparator circuit according to claim 13, further comprising: The first switching device, the second switching device, the third switching device, and the fourth switching device; A fifth switching device and a sixth switching device are connected in series between the matching capacitor and the sampling capacitor.

15. The comparator circuit according to claim 14, wherein: The comparator circuit also includes a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; The output terminal of the first capacitor is capacitively coupled to the input terminal of the second capacitor in the plurality of cascaded comparator amplifiers via the first capacitor and the second capacitor, respectively. The output terminal of the second capacitor is capacitively coupled to the input terminal of the third capacitor in the plurality of cascaded comparator amplifiers via the third capacitor and the fourth capacitor, respectively.

16. The comparator circuit according to claim 15, further comprising: A seventh switching device and an eighth switching device, wherein the seventh switching device and the eighth switching device are connected in series between the first capacitor and the second capacitor; as well as A ninth switching device and a tenth switching device are connected in series between the third capacitor and the fourth capacitor.

17. The comparator circuit according to claim 16, wherein, The common-mode voltage is connected to the node between the fifth and sixth switching devices, the node between the seventh and eighth switching devices, and the node between the ninth and tenth switching devices.

18. The comparator circuit according to claim 17, further comprising: A resistor, a switching device, and a sampling capacitor of the digital-to-analog converter are connected in series between the digital-to-analog converter and ground.

19. The comparator circuit according to claim 18, wherein, During the sampling phase of the clock cycle, the first, third, fifth, sixth, seventh, eighth, ninth, and tenth switching devices are closed, and the second and fourth switching devices are open, so that the offset voltages of the first, second, and third comparators are automatically returned to zero, and the input voltage is sampled.

20. The comparator circuit according to claim 19, wherein, During a dedicated windowing phase of the clock cycle, the switching device closes to sample the digital-to-analog converter (DAC) via the DAC sampling capacitor, wherein the dedicated windowing phase has a phase delay relative to the sampling phase.

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