A level shifting circuit with adjustable output swing

Abstract

The application discloses a level conversion circuit with adjustable output swing, and relates to the technical field of integrated circuits, comprising an input inverting buffer module, a level conversion control module and an output driving module. The input inverting buffer module is connected with a signal input end and is used for outputting two internal driving signals with opposite logic; the level conversion control module is used for resetting the level of a gate control voltage by capacitive coupling and a switch tube; and the output driving module comprises a first transmission gate connected between a first level VDDH and a signal output end, and a second transmission gate connected between a second level VDDL and the signal output end. By controlling the opening and closing of the first and second transmission gates, the application realizes flexible and adjustable output swing according to VDDH and VDDL. Without increasing the chip area, the application shortens the switching time of the subsequent circuit, improves the switching rate of the circuit, reduces the power consumption, and is suitable for high-speed and low-power consumption circuits.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a level conversion circuit with adjustable output swing. Background Technology

[0002] A level-shifting circuit is a circuit used to connect digital or analog circuits operating in different voltage domains. Its switching mechanism converts signals from a low voltage domain to a high voltage domain, or vice versa. Existing technologies include... Figure 1 As shown, VDD0 is the high-voltage power supply voltage, and VDD1 is the low-voltage power supply voltage. This circuit can convert a digital signal in the VDD0 voltage domain to a digital signal in the VDD1 voltage domain. Its output swing is fixed at VDD1, making it unsuitable for multi-voltage domain circuits. Furthermore, in high-speed circuit applications, the excessively large output swing leads to slow switching rates and high power consumption in subsequent circuits. Increasing the switching rate of subsequent circuits can not only reduce jitter in the output signal but also improve the output signal quality. In conventional designs, the driving capability of the control signal can be increased through a level-shifting circuit, but this method significantly increases the chip layout area. Without sacrificing chip area and power consumption, reducing the output swing of the level-shifting circuit can shorten the switching time of the subsequent circuit's operating state, thereby accelerating the circuit state switching rate.

[0003] Therefore, how to flexibly adjust the output swing to shorten switching time and increase circuit speed without sacrificing chip area and power consumption, while being compatible with multi-voltage domain applications, is a problem that urgently needs to be solved in the current technology field. Summary of the Invention

[0004] This invention provides a level conversion circuit with adjustable output swing to solve the problems of fixed output swing in existing level conversion circuits, which result in slow switching rate and high power consumption in high-speed applications, and the problem that increasing the speed by simply increasing the device size will lead to an increase in chip area.

[0005] To solve the above problems, the technical solution adopted by the present invention is as follows:

[0006] A level shifting circuit with adjustable output swing, comprising:

[0007] The input inverting buffer module is connected to the signal input terminal IN and is used to receive input signals and output two internal drive signals with opposite logic levels.

[0008] The level conversion control module is connected to the input inverting buffer module, the first level VDDH and the second level VDDL. The level conversion control module includes multiple capacitors and multiple switching transistors, which are used to convert the internal drive signal into multiple gate control voltages by using capacitive coupling, and to perform level reset of the gate control voltages by the switching transistors.

[0009] An output driving module is connected to the level conversion control module, the first level VDDH, the second level VDDL, and the signal output terminal OUT. The output driving module includes a first transmission gate connected between the first level VDDH and the signal output terminal OUT, and a second transmission gate connected between the second level VDDL and the signal output terminal OUT. The control terminals of the first transmission gate and the second transmission gate respectively receive the corresponding gate control voltage.

[0010] When the input signal is high, the level conversion control module controls the first transmission gate to open and the second transmission gate to close, and the signal output terminal OUT outputs the first level VDDH;

[0011] When the input signal is low, the level conversion control module controls the first transmission gate to turn off and the second transmission gate to turn on, and the signal output terminal OUT outputs the second level VDDL.

[0012] Furthermore, the input inverting buffer module includes a first inverter IN1, a second inverter IN2, a third inverter IN3, and a fourth inverter IN4;

[0013] The input terminal of the first inverter IN1 is connected to the signal input terminal IN, and the output terminal of the first inverter IN1 is connected to the input terminal of the second inverter IN2 and the input terminal of the third inverter IN3 respectively; the output terminal of the third inverter IN3 is connected to the input terminal of the fourth inverter IN4.

[0014] The output of the second inverter IN2 outputs one of the internal drive signals, and the output of the fourth inverter IN4 outputs the other of the internal drive signals.

[0015] Furthermore, the plurality of capacitors in the level conversion control module include a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; the positive terminals of the first capacitor C1 and the second capacitor C2 are both connected to the output terminal of the second inverter IN2; the positive terminals of the third capacitor C3 and the fourth capacitor C4 are both connected to the output terminal of the fourth inverter IN4.

[0016] Further, the plurality of switching transistors in the level conversion control module include a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a first NMOS transistor NM1, and a second NMOS transistor NM2; the source of the third PMOS transistor PM3 is connected to the first level VDDH, the drain is connected to the negative terminal of the first capacitor C1, and the gate is connected to the output terminal of the fourth inverter IN4; the source of the fourth PMOS transistor PM4 is connected to the first level VDDH, the drain is connected to the negative terminal of the third capacitor C3, and the gate is connected to the output terminal of the second inverter IN2; the first PMOS transistor PM3 has a source connected to the first level VDDH, a drain connected to the negative terminal of the third capacitor C3, and a gate connected to the output terminal of the second inverter IN2; the first PMOS transistor PM3 has a source connected to the first level VDDH, the drain connected to the negative terminal of the third capacitor C3, and the ... The source of an NMOS transistor NM1 is connected to the second voltage level VDDL, the drain is connected to the negative terminal of the second capacitor C2, and the gate is connected to the output terminal of the fourth inverter IN4; the source of a second NMOS transistor NM2 is connected to the second voltage level VDDL, the drain is connected to the negative terminal of the fourth capacitor C4, and the gate is connected to the output terminal of the second inverter IN2; the source of a first PMOS transistor PM1 is connected to the negative terminal of the first capacitor C1, and both the gate and drain are connected to the negative terminal of the second capacitor C2; the source of a second PMOS transistor PM2 is connected to the negative terminal of the third capacitor C3, and both the gate and drain are connected to the negative terminal of the fourth capacitor C4.

[0017] Further, the first transmission gate is composed of a fifth PMOS transistor PM5 and a third NMOS transistor NM3, and the second transmission gate is composed of a sixth PMOS transistor PM6 and a fourth NMOS transistor NM4; the source of the fifth PMOS transistor PM5 and the source of the third NMOS transistor NM3 are both connected to the first voltage level VDDH, and the drain of the fifth PMOS transistor PM5 and the drain of the third NMOS transistor NM3 are both connected to the signal output terminal OUT; the source of the sixth PMOS transistor PM6 and the source of the fourth NMOS transistor NM4 are both connected to the second voltage level VDDL, and the drain of the sixth PMOS transistor PM6 and the drain of the fourth NMOS transistor NM4 are both connected to the signal output terminal OUT.

[0018] Furthermore, the connection relationship between the gate control voltage and the first and second transmission gates is as follows: the gate of the fifth PMOS transistor PM5 is connected to the negative terminal of the third capacitor C3, the gate of the third NMOS transistor NM3 is connected to the negative terminal of the second capacitor C2; the gate of the sixth PMOS transistor PM6 is connected to the negative terminal of the first capacitor C1, and the gate of the fourth NMOS transistor NM4 is connected to the negative terminal of the fourth capacitor C4.

[0019] Furthermore, the body terminals of the first PMOS transistor PM1 to the sixth PMOS transistor PM6 are all connected to the first voltage level VDDH; the body terminals of the first NMOS transistor NM1 to the fourth NMOS transistor NM4 are all connected to the second voltage level VDDL.

[0020] Compared with the prior art, the beneficial effects of the present invention are:

[0021] (1) By setting a first level VDDH and a second level VDDL independent of the internal logic voltage, the present invention allows the output signal swing (VDDH-VDDL) to be flexibly adjusted according to the actual needs of the subsequent circuit. By reducing the output swing, the charging and discharging time of the subsequent circuit nodes can be significantly shortened, thereby accelerating the switching rate of the circuit state, reducing signal jitter, and effectively reducing dynamic power consumption, which is particularly suitable for high-speed integrated circuit interfaces.

[0022] (2) The present invention utilizes the capacitive coupling principle and transmission gate structure to drive the output, without blindly increasing the width-to-length ratio of the transistor in order to improve the driving speed, thereby avoiding a significant increase in the chip layout area while ensuring performance.

[0023] (3) Through the coupling effect of capacitors (C1-C4) and the specific reset mechanism of switching transistors (PM1-PM4, NM1-NM2), the circuit can generate instantaneous overdrive voltage or appropriate bias voltage to control the output stage. Even when the first level VDDH voltage value is low, the circuit can still reliably complete the level conversion, which makes the circuit compatible with multiple voltage domain combinations and highly versatile.

[0024] (4) The output drive module adopts a transmission gate structure composed of PMOS and NMOS, which is connected to VDDH and VDDL respectively. Compared with single-transistor drive, the transmission gate structure utilizes the characteristics of complementary transistors to ensure more stable conduction characteristics and lower on-resistance when the output is high or low, further ensuring the quality of the output signal.

[0025] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, embodiments of the present invention are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1This is a schematic diagram of a level conversion circuit in the prior art.

[0028] Figure 2 This is a level conversion circuit diagram with adjustable output swing provided by an embodiment of the present invention.

[0029] Figure 3 This is a waveform diagram of the input signal IN and the output signal OUT under the first VDDL and VDDH numerical conditions of an embodiment of the present invention.

[0030] Figure 4 This is a waveform diagram showing the changes in the input signal IN and the output signal OUT under the second VDDL and VDDH numerical conditions according to an embodiment of the present invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0032] like Figure 2 As shown, this invention provides a level conversion circuit with adjustable output swing, including a first inverter IN1, a second inverter IN2, a third inverter IN3, a fourth inverter IN4, four polarized capacitors (first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4), six switching transistors (first PMOS transistor PM1, second PMOS transistor PM2, third PMOS transistor PM3, fourth PMOS transistor PM4, first NMOS transistor NM1, second NMOS transistor NM2), a first transmission gate (composed of fifth PMOS transistor PM5 and third NMOS transistor NM3), a second transmission gate (composed of sixth PMOS transistor PM6 and fourth NMOS transistor NM4), a first level VDDH, a second level VDDL, a signal input terminal IN, and a signal output terminal OUT. The first to sixth PMOS transistors are of the same type, and the first to fourth NMOS transistors are of the same type.

[0033] The input inverter buffer module consists of four inverters: IN1, IN2, IN3, and IN4. This module receives the input signal and generates two internal drive signals with opposite logic levels (i.e., signals from node A and node AN) through the inverter chain. A level conversion control module consists of four polarized capacitors and six switching transistors. This module uses capacitive coupling to convert the internal drive signals into multiple gate control voltages and uses the switching transistors for level reset. The voltage at the negative terminal of each capacitor is the gate control voltage. An output drive module consists of a first transmission gate and a second transmission gate. This module drives the output to either the first level VDDH or the second level VDDL based on the gate control voltage.

[0034] In this embodiment, the first voltage level VDDH is greater than the second voltage level VDDL, meaning the first voltage level VDDH is a high-level voltage signal and the second voltage level VDDL is a low-level voltage signal. The body terminals of all PMOS transistors are connected to the first voltage level VDDH, and the body terminals of all NMOS transistors are connected to the second voltage level VDDL. The power supply voltage for the first inverter IN1, the second inverter IN2, the third inverter IN3, and the fourth inverter IN4 is VDD.

[0035] The connection relationships of the components are as follows:

[0036] The signal input terminal IN is connected to the input terminal of the first inverter IN1. The output terminal of the first inverter IN1 is connected to the input terminal of the second inverter IN2 and the input terminal of the third inverter IN3. The input terminal of the fourth inverter IN4 is connected to the output terminal of the third inverter IN3. The output terminal of the second inverter IN2 is node A, and the output terminal of the fourth inverter IN4 is node AN. The inverters are powered by VDD power supply.

[0037] The source of the first PMOS transistor PM1 is connected to the negative terminal of the first capacitor C1, at node B1. The gate and drain are connected to the negative terminal of the second capacitor C2, at node B2. The positive terminals of the first capacitor C1 and the second capacitor C2 are connected to the output node A of the second inverter IN2.

[0038] The source of the second PMOS transistor PM2 is connected to the negative terminal of the third capacitor C3, and its gate and drain are connected to the negative terminal of the fourth capacitor C4. The positive terminals of the third capacitor C3 and the fourth capacitor C4 are connected to the output node AN of the fourth inverter IN4.

[0039] The source of the third PMOS transistor PM3 is connected to the first voltage level VDDH, the drain is connected to the negative terminal of the first capacitor C1, and the gate is connected to the output node AN of the fourth inverter IN4.

[0040] The source of the fourth PMOS transistor PM4 is connected to the first level VDDH, the drain is connected to the negative terminal of the third capacitor C3, and the gate is connected to the output node A of the second inverter IN2.

[0041] The source of the first NMOS transistor NM1 is connected to the second level VDDL, the drain is connected to the negative terminal of the second capacitor C2, and the gate is connected to the output node AN of the fourth inverter IN4.

[0042] The source of the second NMOS transistor NM2 is connected to the second level VDDL, the drain is connected to the negative terminal of the fourth capacitor C4, and the gate is connected to the output node A of the second inverter IN2.

[0043] The fifth PMOS transistor PM5 and the third NMOS transistor NM3 form a transmission gate. The gate of the fifth PMOS transistor PM5 is connected to the negative terminal of the third capacitor C3, and the gate of the third NMOS transistor NM3 is connected to the negative terminal of the second capacitor C2. The sources of both the fifth PMOS transistor PM5 and the third NMOS transistor NM3 are connected to the first voltage level VDDH, and the drains of both the fifth PMOS transistor PM5 and the third NMOS transistor NM3 are connected to the signal output terminal OUT.

[0044] The sixth PMOS transistor PM6 and the fourth NMOS transistor NM4 form a transmission gate. The gate of the sixth PMOS transistor PM6 is connected to the negative terminal of the first capacitor C1, and the gate of the fourth NMOS transistor NM4 is connected to the negative terminal of the fourth capacitor C4. The sources of both the sixth PMOS transistor PM6 and the fourth NMOS transistor NM4 are connected to the second voltage level VDDL, and the drains of both the sixth PMOS transistor PM6 and the fourth NMOS transistor NM4 are connected to the signal output terminal OUT.

[0045] The working principle of this circuit is as follows:

[0046] When the input signal is high, the voltage of the output node A of the second inverter IN2 is VDD, and the voltage of the output node AN of the fourth inverter IN4 is 0 V. When VDD - VDDH < VTHP3 (VTHP3 is the threshold voltage of the third PMOS transistor PM3) and VDD - VDDL > VTHN2 (VTHN2 is the threshold voltage of the second NMOS transistor NM2) are satisfied, the third PMOS transistor PM3 and the second NMOS transistor NM2 are turned on. The node B1 (the common connection point of the negative electrode of C1, the source electrode of PM1, and the drain electrode of PM3) is connected to the first level VDDH, and the node B2N (the common connection point of the negative electrode of C4, the gate and drain electrodes of PM2, and the drain electrode of NM2) is connected to the second level VDDL; the voltage of the node B2 (the common connection point of the negative electrode of C2, the gate and drain electrodes of PM1, and the drain electrode of NM1) is pulled up, and the voltage of the node B1N (the common connection point of the negative electrode of C3, the source electrode of PM2, and the drain electrode of PM4) is pulled down. The voltage difference between the node B2 and VDDH is greater than VTHN3 (i.e., the threshold voltage of the third NMOS transistor NM3), and the voltage difference between the node B1N and VDDH is less than the VTHP3 of PM3. That is, the third NMOS transistor NM3 is turned on, the fifth PMOS transistor PM5 is turned on, the fourth NMOS transistor NM4 is turned off, and the sixth PMOS transistor PM6 is turned off. The signal output terminal OUT outputs VDDH.

[0047] When the input signal is low, the voltage of the output node A of the second inverter is 0 V, and the voltage of the output node AN of the fourth inverter is VDD. When VDD - VDDH < VTHP4 (VTHP4 is the threshold voltage of the fourth PMOS transistor PM4) and VDD - VDDL > VTHN1 (VTHN1 is the threshold voltage of the first NMOS transistor NM1) are satisfied, the fourth PMOS transistor PM4 and the first NMOS transistor NM1 are turned on. The node B1N is connected to VDDH, the node B2 is connected to VDDL, the voltage of the node B1 is pulled down, and the voltage of the node B2N is pulled up. The voltage difference between the node B1 and VDDL is less than the threshold voltage VTHP6 of the sixth PMOS transistor PM6, and the voltage difference between the node B2N and VDDL is greater than the threshold voltage VTHN4 of the fourth NMOS transistor NM4. That is, the third NMOS transistor NM3 is turned off, the fifth PMOS transistor PM5 is turned off, the fourth NMOS transistor NM4 is turned on, and the sixth PMOS transistor PM6 is turned on. The signal output terminal OUT outputs VDDL.

[0048] Figure 3 It is the simulation result under a certain condition in the specific embodiment. The high level of the input signal is 1.8 V, the power supply voltage VDD of the inverter is set to 1.8 V, VDDH is set to 0.5 V, VDDL is set to 0 V, and the input signal frequency is 100 MHZ. Figure 4The simulation results are based on another condition in Specific Embodiment 1, where the high level of the input signal is 1.8V, the inverter power supply voltage VDD is set to 1.8V, VDDH is set to 1.2V, VDDL is set to 0.6V, and the input signal frequency is 100MHz. The simulation waveforms show that the present invention can convert high-speed input signals into corresponding high and low level digital signals and output them under different combinations of VDDL and VDDH. Therefore, the level conversion circuit provided in this embodiment can realize the level conversion function of high-speed digital signals within a wide adjustable range of VDDL and VDDH, as well as the function of adjustable output signal swing, making it suitable for various voltage domain scenarios, especially for high-speed, low-power integrated circuits.

[0049] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A level conversion circuit with adjustable output swing, characterized in that, include: The input inverting buffer module is connected to the signal input terminal IN and is used to receive input signals and output two internal drive signals with opposite logic levels. The level conversion control module is connected to the input inverting buffer module, the first level VDDH and the second level VDDL. The level conversion control module includes multiple capacitors and multiple switching transistors, which are used to convert the internal drive signal into multiple gate control voltages by using capacitive coupling, and to perform level reset of the gate control voltages by the switching transistors. An output driving module is connected to the level conversion control module, the first level VDDH, the second level VDDL, and the signal output terminal OUT. The output driving module includes a first transmission gate connected between the first level VDDH and the signal output terminal OUT, and a second transmission gate connected between the second level VDDL and the signal output terminal OUT. The control terminals of the first transmission gate and the second transmission gate respectively receive the corresponding gate control voltage. When the input signal is high, the level conversion control module controls the first transmission gate to open and the second transmission gate to close, and the signal output terminal OUT outputs the first level VDDH; When the input signal is low, the level conversion control module controls the first transmission gate to turn off and the second transmission gate to turn on, and the signal output terminal OUT outputs the second level VDDL.

2. The level conversion circuit with adjustable output swing according to claim 1, characterized in that, The input inverter buffer module includes a first inverter IN1, a second inverter IN2, a third inverter IN3, and a fourth inverter IN4; The input terminal of the first inverter IN1 is connected to the signal input terminal IN, and the output terminal of the first inverter IN1 is connected to the input terminal of the second inverter IN2 and the input terminal of the third inverter IN3 respectively; the output terminal of the third inverter IN3 is connected to the input terminal of the fourth inverter IN4. The output of the second inverter IN2 outputs one of the internal drive signals, and the output of the fourth inverter IN4 outputs the other of the internal drive signals.

3. The level conversion circuit with adjustable output swing according to claim 2, characterized in that, The plurality of capacitors in the level conversion control module include a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; the positive terminals of the first capacitor C1 and the second capacitor C2 are both connected to the output terminal of the second inverter IN2; the positive terminals of the third capacitor C3 and the fourth capacitor C4 are both connected to the output terminal of the fourth inverter IN4.

4. The level conversion circuit with adjustable output swing according to claim 3, characterized in that, The plurality of switching transistors in the level conversion control module include a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a first NMOS transistor NM1, and a second NMOS transistor NM2; the source of the third PMOS transistor PM3 is connected to the first level VDDH, the drain is connected to the negative terminal of the first capacitor C1, and the gate is connected to the output terminal of the fourth inverter IN4; the source of the fourth PMOS transistor PM4 is connected to the first level VDDH, the drain is connected to the negative terminal of the third capacitor C3, and the gate is connected to the output terminal of the second inverter IN2; the first N... The source of MOSFET NM1 is connected to the second voltage level VDDL, the drain is connected to the negative terminal of the second capacitor C2, and the gate is connected to the output terminal of the fourth inverter IN4; the source of the second NMOS transistor NM2 is connected to the second voltage level VDDL, the drain is connected to the negative terminal of the fourth capacitor C4, and the gate is connected to the output terminal of the second inverter IN2; the source of the first PMOS transistor PM1 is connected to the negative terminal of the first capacitor C1, and both the gate and drain are connected to the negative terminal of the second capacitor C2; the source of the second PMOS transistor PM2 is connected to the negative terminal of the third capacitor C3, and both the gate and drain are connected to the negative terminal of the fourth capacitor C4.

5. The level conversion circuit with adjustable output swing according to claim 4, characterized in that, The first transmission gate is composed of a fifth PMOS transistor PM5 and a third NMOS transistor NM3, and the second transmission gate is composed of a sixth PMOS transistor PM6 and a fourth NMOS transistor NM4. The source of the fifth PMOS transistor PM5 and the source of the third NMOS transistor NM3 are both connected to the first voltage level VDDH, and the drain of the fifth PMOS transistor PM5 and the drain of the third NMOS transistor NM3 are both connected to the signal output terminal OUT. The source of the sixth PMOS transistor PM6 and the source of the fourth NMOS transistor NM4 are both connected to the second voltage level VDDL, and the drain of the sixth PMOS transistor PM6 and the drain of the fourth NMOS transistor NM4 are both connected to the signal output terminal OUT.

6. The level conversion circuit with adjustable output swing according to claim 5, characterized in that, The connection relationship between the gate control voltage and the first and second transmission gates is as follows: the gate of the fifth PMOS transistor PM5 is connected to the negative terminal of the third capacitor C3, and the gate of the third NMOS transistor NM3 is connected to the negative terminal of the second capacitor C2; the gate of the sixth PMOS transistor PM6 is connected to the negative terminal of the first capacitor C1, and the gate of the fourth NMOS transistor NM4 is connected to the negative terminal of the fourth capacitor C4.

7. The level conversion circuit with adjustable output swing according to claim 5, characterized in that, The body terminals of the first PMOS transistor PM1 to the sixth PMOS transistor PM6 are all connected to the first voltage level VDDH; the body terminals of the first NMOS transistor NM1 to the fourth NMOS transistor NM4 are all connected to the second voltage level VDDL.

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