8: 1 high-speed parallel-to-serial circuit
By generating pulse signals for an eight-phase clock and simplifying the design of transistor combinations, the problems of speed limitation, low integration and high power consumption of existing parallel-to-serial conversion circuits are solved, realizing a high-speed, low-power 8:1 parallel-to-serial circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-21
- Publication Date
- 2026-03-27
AI Technical Summary
Existing parallel-to-serial conversion circuits suffer from limited conversion rates due to clock speeds, low integration density, large layout area, high power consumption, and unbalanced internal loads, resulting in limited performance.
An eight-phase clock is generated using a pulse generation circuit unit. Combined with buffer, data sampling, and summing circuit units, and a pre-charge-sampling-reset stage design, an 8x serial data output rate is achieved. Power consumption and load imbalance issues are reduced by simplifying transistor combinations.
It achieves a serial data rate up to 8 times the clock frequency, reduces static power consumption, reduces chip area, and improves circuit stability and data transmission accuracy.
Smart Images
Figure CN121749997A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, specifically relating to an 8:1 high-speed parallel-to-serial converter circuit. Background Technology
[0002] The core idea of SerDes (serializer or deserializer) is to utilize the "time-division multiplexing" principle to merge low-speed parallel data streams into high-speed serial data streams for transmission at the transmitting end, and perform the reverse conversion process at the receiving end. Existing parallel-to-serial conversion circuits typically employ a multi-stage cascaded architecture. Their core characteristic is that the data conversion process is completed collaboratively by multiple stages of parallel-to-serial circuits. The preceding stages process relatively low-speed parallel data, which is then integrated stage by stage, and finally, a single stage completes the final conversion from parallel data to serial data at its highest speed. Therefore, the maximum operating speed of this final stage circuit is directly determined by the input clock frequency. Common parallel-to-serial circuit structures are tree structures and shift register structures. Tree structures consist of several 2-to-1 multiplexers and D flip-flops, and the maximum data speed of a tree structure is equal to the input clock frequency of the last stage D flip-flop. Similarly, shift register structures consist of several D flip-flops, and their maximum data speed is also equal to the input clock frequency of the D flip-flops. However, these shift register structures still have the following technical limitations: 1. The conversion rate of existing technologies is limited by the clock rate. The nature of the existing architecture determines that its output data rate has an upper limit, usually not exceeding twice the input clock frequency. This frequency bottleneck severely restricts the performance of parallel-to-serial conversion circuits in high-speed SerDes. 2. Low integration and large layout area: Due to the extensive use of D flip-flops in the circuit structure and the inherent complexity of the logic control circuit, the physical area required for the entire functional module to be implemented on the chip is large, which is detrimental to improving integration and reducing costs. 3. Insufficient power consumption optimization: Especially in circuits that use current logic to achieve high-speed operation, there is usually a direct current path from power supply to ground. This working mechanism leads to significant static power consumption, resulting in high overall power consumption. 4. Uneven internal load and limited performance: Uneven load conditions at different nodes within the circuit lead to inconsistent signal path delays. Summary of the Invention
[0003] The objective of this invention can be achieved through the following technical solutions: An 8:1 high-speed parallel-to-serial converter includes a pulse generation circuit unit, a buffer circuit unit, a data sampling circuit unit, and a summing circuit unit. The pulse generation circuit unit is used to receive an eight-phase clock and generate eight pulse signals with a duty cycle of one-eighth. The buffer circuit unit buffers the input data and pulse signals. The data sampling circuit unit uses the pulse signals to sample the buffered parallel data. The summing circuit unit is used to perform staged summation on the output of the data sampling circuit unit and finally output serial data.
[0004] Preferably, the outputs of the Nth m-type sampling circuit and the (N+4th)th m-type sampling circuit of the data sampling circuit unit are connected to achieve a two-to-one selection, and the outputs of the Nth p-type sampling circuit and the (N+4th)th p-type sampling circuit are connected to achieve a two-to-one selection. The connected outputs are sent to the summing circuit unit, and the outputs of the four summing circuit units are then connected to achieve a four-to-one selection. Finally, the circuit as a whole completes an eight-to-one selection.
[0005] Preferably, the data sampling circuit unit includes 8 p-type sampling circuits and 8 m-type sampling circuits, and each p-type sampling circuit and each m-type sampling circuit includes a pre-charge transistor, a sampling transistor and a reset transistor.
[0006] Preferably, the pre-charge tube includes Mmn4 and Mmp3, Mpn0 and Mpp4; the sampling tube includes Mmp2 and Mpn1; and the reset tube includes Mmn1 and Mmn0, Mpp2 and Mpp3.
[0007] Preferably, the operation of the data sampling circuit unit includes three stages: a pre-charging stage, a sampling stage, and a reset stage. During the pre-charging phase, the pre-charging transistors Mmn4 and Mmp3 or Mpn0 and Mpp4 form an inverter to pre-charge and discharge the capacitor at point Xm or Xp before sampling. The sampling transistor and the reset transistor Mmn1 or Mpp2 are in the off state, providing a high-impedance state for the output node. During the sampling phase, the sampling transistor is turned on to sample the voltage of Xm or Xp respectively. The sampling time is one-eighth of a clock cycle. During this period, the reset transistor Mmn1 or Mpp2 remains in the off state to avoid voltage competition. During the reset phase, the reset transistor is turned on, allowing the output node voltage to be reset to a high or low potential, while the sampling transistor is turned off, presenting a high impedance state.
[0008] Preferably, the rate of the serial data is 8 times the input eight-phase clock frequency.
[0009] Preferably, the input parallel data, after passing through the buffer circuit unit, is synchronously input to the data sampling circuit unit along with the pulse signal to ensure accurate sampling timing.
[0010] Preferably, the pulse signals are PLUSE0-PLUSE315, the phases of the eight pulse signals are sequentially 45° apart, and the high levels of adjacent pulse signals do not overlap, and the duration of the high level is 1 / 8 of the input eight-phase clock cycle.
[0011] Preferably, the eight-phase clock is CK0-CK315, and the eight pulse signals generated by the pulse generation circuit unit correspond one-to-one with the connection of the eight-phase clock.
[0012] The beneficial effects of this invention are as follows: This invention presents an 8:1 high-speed parallel-to-serial converter circuit. Through a pulse generation circuit unit, it converts an eight-phase clock into eight 1 / 8 duty cycle pulse signals. Combined with a pre-charge-sampling-reset phase operating mode, it achieves sequential sampling of eight parallel data streams within one clock cycle, increasing the serial output rate to eight times the input clock frequency. Simultaneously, the summing circuit unit employs a step-by-step merging logic, first selecting one from two and then four from one, avoiding the surge in output node load capacitance caused by direct eight-to-one selection. This significantly reduces circuit charging and discharging time, improves circuit stability and data transmission accuracy in high-speed scenarios, and solves the performance limitations of existing circuits due to load imbalance and the maximum data rate limitation of parallel-to-serial converters caused by the input clock. Furthermore, the data sampling circuit unit of the present invention, through the alternating switching design of the sampling transistor and the reset transistor, makes the output node in a high-impedance state during the non-sampling and reset phases, cutting off the DC path from the power supply to ground, significantly reducing static power consumption, and overcoming the defect of high power consumption in existing current-mode logic circuits; at the same time, the circuit as a whole adopts a simplified transistor combination architecture, eliminating the need for a large number of D flip-flops and complex control circuits, and greatly reducing the chip layout area. Attached Figure Description
[0013] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings.
[0014] Figure 1 This is a schematic diagram of the overall circuit framework of the present invention; Figure 2 This is a schematic diagram showing the connection between the data sampling circuit unit and the summing circuit unit of the present invention; Figure 3 The diagram shows the specific circuit diagrams of the p-type sampling circuit (right) and the m-type sampling circuit (left) of this invention. Figure 4 This is a timing diagram of the first p-type sampling circuit and the fifth p-type sampling circuit of the present invention; Figure 5 This is the complete timing diagram of the 8:1 high-speed parallel-to-serial converter circuit of the present invention. Detailed Implementation
[0015] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided.
[0016] Before the widespread adoption of SerDes technology, integrated circuits primarily relied on parallel interfaces for data communication. This approach increased the total transmission bandwidth by increasing the number of data lines. However, as data rates climbed to the Gb / s level, parallel buses required strict synchronization between numerous data signals and clock signals. Under high-speed conditions, minute length differences in printed circuit board traces or within the chip could generate significant clock and data skew, leading to sampling errors at the receiving end. Severe crosstalk existed between dense parallel signal lines, and the simultaneous switching of numerous signals generated significant synchronous switching noise, drastically degrading signal quality. Numerous signal lines required more chip input / output pins, more complex circuit board routing, and larger connectors, significantly increasing system packaging cost and size.
[0017] To overcome the aforementioned limitations of parallel interfaces, SerDes technology was developed. The core idea of this technology is to utilize the principle of "time division multiplexing" to combine low-speed parallel data streams into a high-speed serial data stream for transmission at the transmitting end, and perform the reverse conversion process at the receiving end. This significantly reduces the number of physical interconnects, fundamentally solving the problem of parallel layout. The parallel-to-serial conversion circuit is the core circuit of the SerDes transmitter, and its performance directly determines the transmission rate and reliability of the entire interface.
[0018] To address the shortcomings of existing parallel-to-serial conversion circuits, such as limited speed, unbalanced load, high power consumption, and large area, please refer to [link to relevant documentation]. Figures 1-5 This embodiment provides a high-speed parallel-to-serial converter circuit, specifically an 8:1 high-speed parallel-to-serial converter circuit. This circuit is mainly used in the last stage of the parallel-to-serial converter in a high-speed circuit transmitter, capable of increasing the data rate to eight times the clock frequency, while also possessing advantages such as low jitter, low power consumption, small area, and simple logic. The circuit includes a pulse generation circuit unit, a buffer circuit unit, a data sampling circuit unit, and a summing circuit unit. Each circuit unit is connected to the signal and power supply through metal interconnect wires, and the entire circuit is integrated within a CMOS process chip. The connection relationship of each circuit unit is as follows: Figure 1 As shown, the composition of each circuit unit and the logical relationship between each unit are as follows; The pulse generation circuit unit consists of simple logic gates composed of several PMOS and several NMOS transistors. PLUSE0 uses two PMOS transistors controlled by CK45 and CK180 respectively, connected in series to form a pull-up path, and an NMOS transistor controlled by CK45 to form a pull-down path. That is, from power supply to ground, the sequence is: PMOS controlled by CK45, PMOS controlled by CK180, and NMOS controlled by CK45. When CK180 falls, CK45 is low, at which point the pull-up path is on and the pull-down path is off; when CK45 rises, the pull-up path is off and the pull-down path is on. Similarly, the remaining PLUSE transistors can be generated using several PMOS and several NMOS transistors. The naming convention between PLUSE and CK does not need to be one-to-one; for subsequent circuits, only the PLUSE transistors need to be named sequentially, simplifying the subsequent circuit design logic.
[0019] The pulse generation circuit unit operates as follows: it receives an eight-phase clock (CK0-CK315) and generates eight pulse signals (PLUSE0-PLUSE315) with a duty cycle of 1 / 8. This provides a precise timing reference for data sampling and is a key prerequisite for achieving an 8x clock frequency. The eight pulse signals are sequentially phased by 45°, and the high levels of adjacent pulse signals do not overlap. The duration of the high level is 1 / 8 of the input eight-phase clock cycle. Each pulse samples one data channel within 1 / 8 of the clock cycle, and the eight pulses sequentially complete the sampling of eight data channels within one clock cycle, enabling the serial output rate to reach 8x the clock frequency. The eight-phase clock is CK0-CK315, and the eight pulse signals generated by the pulse generation circuit unit correspond one-to-one with the connections of the eight-phase clock.
[0020] The buffer circuit unit consists of two parts: clock and data buffer circuits. Both clock and data buffer circuits are formed by cascading basic inverters. The number of cascaded inverters and their driving capability can be flexibly adjusted according to the driving capability of the preceding circuit and the load of the following circuit. In high-speed applications, the buffer circuit can be omitted, and the data and pulse clock can be directly sent to the data sampling circuit, avoiding jitter during cascading.
[0021] The data sampling circuit unit uses pulse signals to sample the buffered parallel data, including 8 p-type sampling circuits and 8 m-type sampling circuits. Each p-type sampling circuit and each m-type sampling circuit includes an NMOS transistor and a PMOS transistor. Each of the 8 p-type sampling circuits and 8 m-type sampling circuits includes a pre-charge transistor, a sampling transistor, and a reset transistor. The aspect ratio of each transistor is set according to its function: the pre-charge transistors are Mmn4 and Mmp3, Mpn0 and Mpp4; the sampling transistors are Mmp2 and Mpn1; and the reset transistors are Mmn1 and Mmn0, Mpp2 and Mpp3. This scheme uses a simple transistor combination of pre-charge transistors, sampling transistors, and reset transistors, so that the summing circuit unit does not need complex logic gates, the overall circuit has no redundant components, the logic is simplified and the number of components is reduced, which greatly reduces the chip layout area. Furthermore, through the high-impedance design of the sampling transistor and the reset transistor alternately switching on and off, other sampling circuits can change the output node voltage, avoiding voltage competition and cutting off the DC path from the working mechanism, thereby reducing power consumption.
[0022] Please see Figure 2 , Figure 2 The connection diagram between the data sampling circuit unit and the summing circuit unit is given. In the sampling circuit unit, the outputs of the Nth m-type sampling circuit and the (N+4th)th m-type sampling circuit are connected to achieve a 2-to-1 (2-in-1) multiplexer. The outputs of the Nth p-type sampling circuit and the (N+4th)th p-type sampling circuit are connected to achieve a 2-to-1 multiplexer, avoiding the large load capacitance problem caused by a direct 8-to-1 multiplexer. N is an integer ranging from 1 to 4. The connected outputs are sent to the summing circuit unit, which further merges the four 2-to-1 outputs to achieve a 4-to-1 (4-in-1) multiplexer. Finally, the conversion from 8 parallel data channels to 1 serial data channel is completed. By performing staged operations, the load capacitance of the output nodes is alleviated. Compared with a direct 8-to-1 multiplexer, the load capacitance is significantly reduced, improving the circuit response speed and stability. Specifically, the four outputs data_sample_m<0:3> of the m-type sampling circuit are connected to the gates of the four NMOS transistors, and the four outputs data_sample_p<0:3> of the p-type sampling circuit are connected to the gates of the four PMOS transistors. Then, the drains of all the MOS transistors are directly connected together for output. The source of the NMOS transistor is connected to ground, and the source of the PMOS transistor is connected to the power supply.
[0023] When the DIN pin of the input sampling circuit is low, the m-type sampling circuit outputs a high level because the pull-up path is on and the pull-down path is off. At this time, the NMOS connected to this sampling circuit is turned on, pulling the OUT node low and outputting a low level. The p-type sampling circuit is in a high-impedance state because the pull-up and pull-down paths are off and outputs a high level. At this time, the PMOS connected to this sampling circuit is turned off, presenting a high-impedance state, which does not affect the NMOS pulling low. At this time, the other three pairs of PMOS and NMOS are also in their respective high-impedance states.
[0024] Similarly, when DIN is high, the PMOS connected to the sampling circuit turns on, pulling the OUT node high and outputting a high level, while the NMOS is in a high-impedance state. At this time, the other three pairs of PMOS and NMOS are also in their respective high-impedance states.
[0025] Please see Figure 3 , Figure 3 The specific structures of a p-type sampling circuit (right) and an m-type sampling circuit (left) are given. The operation of the sampling circuit can be divided into a pre-charging stage, a sampling stage, and a reset stage.
[0026] The pre-charge transistors include Mmn4 and Mmp3, Mpn0 and Mpp4; the sampling transistors include Mmp2 and Mpn1; and the reset transistors include Mmn1 and Mmn0, Mpp2 and Mpp3. During the pre-charge phase, the pre-charge transistors Mmn4 and Mmp3 or Mpn0 and Mpp4 form an inverter. Therefore, regardless of the stage, the pre-charge transistors will pre-charge Xm or Xp, thus completing the charging and discharging of the capacitor at point Xm or Xp before sampling, thereby improving the circuit's response speed. The sampling transistors Mmp2 or Mpn1 are in the off state, providing a high-impedance state to the output node Xm or Xp, allowing the pre-charge circuit to change the voltage at the output node Xm or Xp, avoiding voltage competition. During the sampling phase, the sampling transistor is turned on to sample the voltage of Xm or Xp. The sampling time is one-eighth of a clock cycle. During this period, the reset transistor Mmn1 or Mpp2 remains off to avoid voltage competition. During the reset phase, the reset transistor is turned on, resetting the output node voltage to a high or low potential. Simultaneously, the sampling transistor is turned off, exhibiting a high impedance state to avoid voltage contention and the power supply to ground path, thus reducing power consumption.
[0027] Existing current-mode logic has a DC path from power supply to ground, resulting in high static power consumption. In this solution, the sampling circuit alternately switches the sampling transistor and the reset transistor during the pre-charging, sampling, and reset phases. For example, the reset transistor is off during sampling and the sampling transistor is off during reset, so that the output node is always in a high-impedance state, avoiding voltage competition between different sampling circuits. At the same time, it cuts off the DC path from power supply to ground, significantly reducing static power consumption.
[0028] Please see Figure 4 , Figure 4 Timing diagrams for the first and fifth p-type sampling circuits are given. The result of the first sampling circuit is output during the high-impedance state of the fifth sampling circuit, and the result of the fifth sampling circuit is output during the high-impedance state of the first sampling circuit, thus achieving a two-to-one selection.
[0029] Please see Figure 5 , Figure 5The timing diagram of an 8:1 high-speed parallel-to-serial converter is given. The eight-phase clock generates corresponding pulse signals in sequence to sample the input data (DIN0-DIN7). The final output (OUT) is serial data at eight times the clock frequency, which shows the timing relationship between the eight-phase clock, pulse signals, input data and output data.
[0030] The overall workflow of the circuit is as follows: An eight-phase clock input pulse generation circuit unit generates eight pulse signals with a 1 / 8 duty cycle. The buffer circuit unit buffers the input data (DIN0-DIN7) and pulse signals; The data sampling circuit unit uses pulse signals to sample eight parallel data streams according to the pre-charge-sampling-reset timing sequence, and adjacent sampling circuits alternately output through high impedance to avoid conflicts. The sampling unit circuit and the summing circuit unit first perform a two-to-one selection, and then the summing circuit unit performs a four-to-one selection, finally outputting serial data (OUT) at a rate of 8 times the clock frequency.
[0031] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. An 8:1 high-speed parallel-to-serial converter circuit, characterized in that: It includes a pulse generation circuit unit, a buffer circuit unit, a data sampling circuit unit, and a summing circuit unit; The pulse generation circuit unit is used to receive an eight-phase clock and generate eight pulse signals with a duty cycle of one-eighth. The buffer circuit unit buffers the input data and pulse signals. The data sampling circuit unit uses the pulse signals to sample the buffered parallel data. The summing circuit unit is used to perform staged summation on the output of the data sampling circuit unit and finally output serial data.
2. The 8:1 high-speed parallel-to-serial converter circuit according to claim 1, characterized in that: The outputs of the Nth m-type sampling circuit and the (N+4th)th m-type sampling circuit of the data sampling circuit unit are connected to achieve a two-to-one selection. The outputs of the Nth p-type sampling circuit and the (N+4th)th p-type sampling circuit are connected to achieve a two-to-one selection. The connected outputs are sent to the summing circuit unit. The outputs of the four summing circuit units are then connected to achieve a four-to-one selection. Finally, the circuit as a whole completes an eight-to-one selection.
3. The 8:1 high-speed parallel-to-serial converter circuit according to claim 1, characterized in that: The data sampling circuit unit includes 8 p-type sampling circuits and 8 m-type sampling circuits. Each p-type sampling circuit and each m-type sampling circuit includes a pre-charge transistor, a sampling transistor, and a reset transistor.
4. The 8:1 high-speed parallel-to-serial converter circuit according to claim 2, characterized in that: The pre-charge tubes include Mmn4 and Mmp3, Mpn0 and Mpp4; the sampling tubes include Mmp2 and Mpn1; the reset tubes include Mmn1 and Mmn0, Mpp2 and Mpp3.
5. The 8:1 high-speed parallel-to-serial converter circuit according to claim 3, characterized in that: The operation of the data sampling circuit unit includes three stages: pre-charging stage, sampling stage, and reset stage. During the pre-charging phase, the pre-charging transistors Mmn4 and Mmp3 or Mpn0 and Mpp4 form an inverter to pre-charge and discharge the capacitor at point Xm or Xp before sampling. The sampling transistor and the reset transistor Mmn1 or Mpp2 are in the off state, providing a high-impedance state for the output node. During the sampling phase, the sampling transistor is turned on to sample the voltage of Xm or Xp respectively. The sampling time is one-eighth of a clock cycle. During this period, the reset transistor Mmn1 or Mpp2 remains in the off state to avoid voltage competition. During the reset phase, the reset transistor is turned on, allowing the output node voltage to be reset to a high or low potential, while the sampling transistor is turned off, presenting a high impedance state.
6. The 8:1 high-speed parallel-to-serial converter circuit according to claim 1, characterized in that: The rate of the serial data is 8 times the input eight-phase clock frequency.
7. The 8:1 high-speed parallel-to-serial converter circuit according to claim 1, characterized in that: The input parallel data, after passing through the buffer circuit unit, is synchronously input to the data sampling circuit unit along with the pulse signal to ensure accurate sampling timing.
8. The 8:1 high-speed parallel-to-serial converter circuit according to claim 1, characterized in that: The pulse signals are PLUSE0-PLUSE315, and the phases of the eight pulse signals are 45° apart. The high levels of adjacent pulse signals do not overlap, and the duration of the high level is 1 / 8 of the input eight-phase clock cycle.
9. An 8:1 high-speed parallel-to-serial converter circuit according to claim 9, characterized in that: The eight-phase clocks are CK0-CK315, and the eight pulse signals generated by the pulse generation circuit unit correspond one-to-one with the connections of the eight-phase clocks.