Circuit board assembly and manufacturing method thereof

Abstract

The invention provides a circuit board assembly and a manufacturing method thereof. The circuit board assembly includes a first circuit layer, a second circuit layer, a heat sink, a wafer, a photosensitive insulating layer and a conductive structure. The heat dissipation base is located between the first circuit layer and the second circuit layer. The wafer is arranged on the heat dissipation seat. The photosensitive insulating layer is located between the first circuit layer and the second circuit layer and covers and surrounds the wafer. The conductive structure is disposed between the wafer and the second circuit layer, and electrically connects the wafer and the second circuit layer. The circuit board assembly covers the embedded wafer through the photosensitive insulating layer so as to replace laser drilling to form a conductive blind hole or a conductive buried hole.

Description

Technical Field

[0001] This application relates to a circuit board assembly and a method for manufacturing the same. Background Technology

[0002] In recent years, electronic products have trended towards multifunctionality, high circuit density, and miniaturization. Circuit board technology has evolved to include the ability to embed chips within the circuit board. The pads of chips embedded in the circuit board are typically electrically connected to external circuitry using conductive blind vias or conductive buried vias. The formation of conductive blind vias generally includes laser drilling. However, laser drilling can potentially damage the chip's pads, causing short circuits or chip failure.

[0003] In addition, to prevent the chip pads from being punctured, the current practice is to modify the material of the chip pads before drilling so that the pads are not easily damaged by the laser beam, thereby preventing the pads from being punctured by the laser. Summary of the Invention

[0004] At least one embodiment of this application provides a circuit board assembly and a method for manufacturing the same, wherein the circuit board assembly covers an embedded wafer with a photosensitive insulating layer to replace laser drilling to form conductive blind vias or conductive buried vias.

[0005] At least one embodiment of this application provides a circuit board assembly comprising a first circuit layer, a second circuit layer, a heat sink, a chip, a photosensitive insulating layer, and a conductive structure. The heat sink is located between the first and second circuit layers. The chip is disposed on the heat sink. The photosensitive insulating layer is located between the first and second circuit layers, and covers and surrounds the chip. The conductive structure is disposed between the chip and the second circuit layer, and electrically connects the chip and the second circuit layer.

[0006] In at least one embodiment of this application, the circuit board assembly further includes a dielectric layer and an adhesive material. The dielectric layer is located between the first circuit layer and the photosensitive insulating layer. The dielectric layer surrounds the heat sink. The adhesive material is distributed on the heat sink to fix the heat sink and the dielectric layer.

[0007] In at least one embodiment of this application, the thickness of the photosensitive insulating layer covering the wafer is in the range of 30 micrometers to 50 micrometers.

[0008] In at least one embodiment of this application, the wafer has wafer pads. The wafer pads are electrically connected to conductive structures. The wafer pads are made of aluminum or copper. The wafer pads contact the conductive structures.

[0009] In at least one embodiment of this application, the circuit board assembly further includes a conductive adhesive layer. The conductive adhesive layer is bonded between the chip and the heat sink. The heat sink is conductive and electrically connected to the first circuit layer. The chip is electrically connected to the first circuit layer via the conductive adhesive layer and the heat sink.

[0010] In at least one embodiment of this application, the heat sink is made of copper. The conductive structure is made of copper. The photosensitive insulating layer is made of photosensitive polyimide.

[0011] The method for manufacturing a circuit board assembly provided in at least one embodiment of this application includes: providing a substrate; disposing a heat sink within the substrate; disposing a wafer on the heat sink; forming a photosensitive insulating material on the wafer, wherein the photosensitive insulating material covers the wafer and the heat sink; forming a through-hole in the photosensitive insulating material, wherein the bottom of the through-hole exposes the wafer; after forming the through-hole, forming a photosensitive insulating layer in the photosensitive insulating material; after disposing the heat sink, forming a first metal layer on the substrate, wherein the first metal layer covers the heat sink, and the heat sink is located between the first metal layer and the photosensitive insulating layer; forming a second metal layer on the photosensitive insulating layer, wherein the photosensitive insulating layer is located between the second metal layer and the first metal layer; and forming a conductive structure within the through-hole, wherein the conductive structure electrically connects the second metal layer and the wafer.

[0012] In at least one embodiment of this application, the via is formed by a photolithography process.

[0013] In at least one embodiment of this application, the manufacturing method further includes: before setting the heat sink, setting a release layer on the substrate so that the heat sink subsequently set adheres to the release layer; after setting the heat sink, setting an adhesive on the heat sink to fix the heat sink and the substrate; and after setting the adhesive, removing the release layer.

[0014] Setting the chip on a heat sink includes: setting solder on the heat sink; placing the chip on the solder; and pressurizing and heating the chip and solder to form a conductive adhesive layer on the solder.

[0015] Based on the above, in the circuit board assembly disclosed in the above embodiments, the photosensitive insulating layer covers the wafer, so that the vias can be formed by photolithography to replace laser drilling, thereby avoiding damage or destruction of the wafer's pads by laser. Attached Figure Description

[0016] To gain a more complete understanding of the embodiments and their advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein:

[0017] Figure 1 This is a cross-sectional schematic diagram of a circuit board assembly according to at least one embodiment of this application;

[0018] Figure 2 yes Figure 1 A partial cross-sectional view of the step of forming an accommodating space in the manufacturing method of a circuit board assembly;

[0019] Figure 3 Yes, yes Figure 1 A partial cross-sectional view of the steps for setting the heat sink and adhesive material in the manufacturing method of the circuit board assembly;

[0020] Figure 4 yes Figure 1 A partial cross-sectional view of the solder setting step in the manufacturing method of a circuit board assembly;

[0021] Figure 5 yes Figure 1 A partial cross-sectional view of the step of setting up the wafer in the manufacturing method of the circuit board assembly;

[0022] Figure 6 yes Figure 1 A partial cross-sectional schematic diagram of the step of forming a photosensitive insulating material in the manufacturing method of a circuit board assembly;

[0023] Figure 7 yes Figure 1 A partial cross-sectional schematic diagram of the step of forming a photosensitive insulating layer in the manufacturing method of a circuit board assembly;

[0024] Figure 8 yes Figure 1 A partial cross-sectional view of the step of forming a metal layer in the manufacturing method of a circuit board assembly;

[0025] Figure 9 yes Figure 1 A partial cross-sectional schematic diagram of the step of forming a conductive structure in the manufacturing method of a circuit board assembly.

[0026] Figure 10 yes Figure 1 A partial cross-sectional view of the steps in the manufacturing method of a circuit board assembly, namely forming an adhesive layer and another metal layer; and

[0027] Figure 11 yes Figure 1 A partial cross-sectional view of the steps in the manufacturing method of a circuit board assembly for forming conductive blind vias and conductive through-holes. Detailed Implementation

[0028] In the following text, to clearly present the technical features of this application, the dimensions (e.g., length, width, thickness, and depth) of the elements (e.g., layers, films, substrates, and regions) in the accompanying drawings will be enlarged proportionally, and the number of some elements may be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings or the dimensions and shapes presented by the elements, but should cover dimensions, shapes, and deviations from both due to actual manufacturing processes and / or tolerances. For example, a flat surface shown in the drawings may have rough and / or non-linear characteristics, and an acute angle shown in the drawings may be rounded. Therefore, the elements presented in the accompanying drawings are primarily for illustrative purposes and are not intended to precisely depict the actual shape of the elements, nor are they intended to limit the claims of this application.

[0029] Secondly, the terms "approximately," "approximately," or "substantially" used in this document not only cover explicitly stated numerical values ​​and ranges, but also the permissible deviation range understood by those skilled in the art, whereby such deviation range can be determined by errors generated during measurement, which may arise from limitations of the measurement system or process conditions, for example. Furthermore, "approximately" can indicate a deviation within one or more standard deviations of the aforementioned numerical values, such as ±30%, ±20%, ±10%, or ±5%. The terms "approximately," "approximately," or "substantially" used in this document can be chosen based on optical, etching, mechanical, or other properties to select an acceptable deviation range or standard deviation, and are not applied to all optical, etching, mechanical, and other properties using a single standard deviation. Additionally, for clarity in the following embodiments, components with the same or similar functions are indicated by the same designation.

[0030] Figure 1 This is a schematic cross-sectional view of a circuit board assembly 100 according to at least one embodiment of this application. (See attached image) Figure 1 The circuit board assembly 100 includes multiple circuit layers 111-114, an adhesive layer 121, a dielectric layer 122, at least one heat sink 130, adhesive material 140, at least one chip 150, at least one conductive adhesive layer 160, a photosensitive insulating layer 170, at least one conductive structure 180, and solder resist layers 191 and 192. Figure 1 In the example, circuit board assembly 100 includes two heat sinks 130, two chips 150, two conductive adhesive layers 160, and multiple conductive structures 180, but is not limited thereto. Furthermore, circuit board assembly 100 also has multiple conductive blind vias 210 and multiple conductive through-holes 220. Circuit board assembly 100 can be applied to DC-DC converters, DC-AC converters, power supply circuit boards, or electronic products with power modules, but is not limited thereto.

[0031] exist Figure 1 In this example, the circuit board assembly 100 includes four wiring layers 111-114. An adhesive layer 121 and a dielectric layer 122 are stacked with the wiring layers 111-114. The wiring layers 111-114 can be made of copper, or copper and other metals (e.g., titanium). The adhesive layer 121 bonds adjacent wiring layers 111 and 112. The adhesive layer 121 may include a material with a high glass transition temperature (Tg), such as epoxy resin or polyimide (PI). Additionally, the adhesive layer 121 may also include glass fiber.

[0032] A dielectric layer 122 is sandwiched between adjacent circuit layers 113 and 114. The dielectric layer 122 may also comprise glass fiber and epoxy resin. Each conductive blind via 210 extends from circuit layer 111 to circuit layer 112 and electrically connects circuit layers 111 and 112. Each conductive through-via 220 penetrates circuit layers 111 to 114 and electrically connects circuit layers 111 to 114. The conductive blind via 210 and conductive through-via 220 may be made of copper.

[0033] These heat sinks 130 are located between circuit layers 112 and 114. Further, the heat sink 130 is embedded within the dielectric layer 122, the circuit layer 113, and a portion of the circuit layer 114; that is, the dielectric layer 122, the circuit layer 113, and a portion of the circuit layer 114 surround the heat sink 130. The heat sink 130 is conductive, and the material of the heat sink 130 may include copper. The heat sink 130 has two opposing surfaces 131 and 132. Surface 131 is adjacent to the circuit layer 112 and flush with the upper surface of the circuit layer 113, while surface 132 is covered by and electrically connected to the circuit layer 114.

[0034] The adhesive 140 is adhesive and can be distributed on multiple heat sinks 130. The adhesive 140 is used to secure the heat sinks 130, dielectric layer 122, and circuit layers 113 and 114. For example, the adhesive 140 is distributed between the sides of the multiple heat sinks 130 and the dielectric layer 122, between the sides of the multiple heat sinks 130 and the circuit layer 113, and between the sides of the multiple heat sinks 130 and a portion of the circuit layer 114. The adhesive 140 can be made of resin.

[0035] These chips 150 are located between circuit layers 112 and 114 and are mounted on these heat sinks 130. Figure 1 In this example, chip 150 may be a metal oxide semiconductor field-effect transistor (MOSFET), but is not limited thereto. Chip 150 has a plurality of chip pads 151 to 153. The chip pads 151 (e.g., drain pads) of the plurality of chips 150 are respectively attached to the surfaces 131 of a plurality of heat sinks 130 via multilayer conductive adhesive layers 160. In each chip 150, chip pads 152 (gate pads) and chip pads 153 (source pads) are spaced apart and adjacent to the circuit layer 112, and are electrically connected to the circuit layer 112 via a plurality of conductive structures 180. Furthermore, the material of chip pad 151 may be titanium, nickel, or silver, while the material of chip pads 152 to 153 includes aluminum copper (AlCu).

[0036] The conductive adhesive layer 160 can be sintered silver paste with a thermal conductivity in the range of 180 to 200 W / mK. Therefore, the conductive adhesive layer 160 can rapidly conduct heat generated by the wafer 150 to the heat sink 130. Furthermore, the conductive adhesive layer 160 is conductive, allowing the wafer pad 151 to be electrically connected to the wiring layer 114 via the conductive adhesive layer 160 and the heat sink 130.

[0037] A photosensitive insulating layer 170 is located between circuit layers 112 and 114. The photosensitive insulating layer 170 covers and surrounds the wafer 150, and also covers the surface 131 of the heat sink 130, the surface of circuit layer 113, and the surface of dielectric layer 122. Therefore, the photosensitive insulating layer 170 is also located between dielectric layer 122 and circuit layer 112. The material of the photosensitive insulating layer 170 comprises photosensitive polyimide. The thickness t of the photosensitive insulating layer 170 covering the wafer 150 is in the range of 30 micrometers to 50 micrometers. The photosensitive insulating layer 170 has good insulation properties and is suitable for isolating circuit layers 112 and 113.

[0038] Multiple conductive structures 180 are disposed between the wafer 150 and the circuit layer 112, and electrically connect the wafer 150 and the circuit layer 112. Further, some conductive structures 180 may contact the circuit layer 112, the adhesive layer 121, the photosensitive insulating layer 170, and the wafer pad 152, and electrically connect the circuit layer 112 and the wafer pad 152. Other conductive structures 180 may contact the circuit layer 112, the adhesive layer 121, the photosensitive insulating layer 170, and the wafer pad 153, and electrically connect the circuit layer 112 and the wafer pad 153. The adhesive layer 121 and the photosensitive insulating layer 170 can isolate two adjacent conductive structures 180. The material of the conductive structures 180 includes copper. Figure 1 In the example, the material of the conductive structure 180 includes copper and other metals (such as titanium). In particular, the width of the conductive structure 180 can be close to the width of the chip pads 152 and 153 to achieve a heat dissipation effect.

[0039] Two solder resist layers 191 and 192 are located on circuit layers 111 and 114, respectively, with circuit layers 111-114 situated between the two solder resist layers 191 and 192. Solder resist layer 191 can contact the surface of circuit layer 111 and the surface of the adhesive layer 121 exposed by circuit layer 111, while solder resist layer 192 can contact the surface of circuit layer 114 and the surface of the dielectric layer 122 exposed by circuit layer 114. Solder resist layer 191 exposes the component pads of circuit layer 111, while solder resist layer 192 exposes the component pads of circuit layer 114.

[0040] the following Figures 2 to 11 Exposure Figure 1 A method for manufacturing a circuit board assembly 100, wherein Figure 2 yes Figure 1 A partial cross-sectional view of the step of forming the accommodating space 330 in the manufacturing method of the circuit board assembly 100. (See attached diagram.) Figure 2 First, a substrate 300 is provided, wherein the substrate 300 includes multiple metal layers 310, 320 and dielectric layer 122. The metal layers 310, 320 and dielectric layer 122 are stacked, and the dielectric layer 122 is sandwiched between the metal layers 310, 320.

[0041] Next, a plurality of accommodating spaces 330 are formed within the substrate 300. These accommodating spaces 330 are spaced apart and extend through the metal layers 310, 320 and the dielectric layer 122. The accommodating spaces 330 can be formed by machining, for example, by a machine tool using computer numerical control (CNC).

[0042] Figure 3 yes Figure 1 A partial cross-sectional view of the step of setting the heat sink 130 and the adhesive material 140 in the manufacturing method of the circuit board assembly 100. (See attached diagram.) Figure 2 and Figure 3 A release layer 340 is disposed on the substrate 300, for example, on the metal layer 310 or 320. The release layer 340 may be an adhesive tape, and its material may be polyethylene terephthalate (PET). Next, a heat sink 130 is disposed within the accommodating space 330, and the release layer 340 is adhered to the heat sink 130. The heat sink 130 may be a copper block, and the thickness of the copper block may be the same as the thickness of the substrate 300.

[0043] Next, adhesive material 140 is placed in the receiving space 330. Adhesive material 140 can be distributed on the sides of the heat sink 130 and fill the gap between the heat sink 130 and the substrate 300. The material of adhesive material 140 can be resin. For example, release layer 340 can be attached to metal layer 310. After heat sink 130 is placed, adhesive material 140 is formed by a printing process (e.g., screen printing), and adhesive material 140 can bond the substrate 300 and heat sink 130 after heating, thereby fixing heat sink 130 in the receiving space 330.

[0044] Figure 4 yes Figure 1 A partial cross-sectional view of the step of setting solder 160a in the manufacturing method of the circuit board assembly 100. (See attached diagram.) Figure 3 and Figure 4After the adhesive 140 bonds the substrate 300 and the heat sink 130, the release layer 340 is removed. Next, a patterned metal layer 310 is formed to create the circuit layer 113. For example, the patterned metal layer 310 can be formed by photolithography and etching processes.

[0045] Next, solder 160a is applied to the surface 131 of the heat sink 130. Solder 160a can be silver paste and can be formed on the surface 131 via a stencil printing process. It is worth noting that before applying solder 160a, a surface finish can be performed on the area of ​​surface 131 where solder 160a is pre-applied, such as electroless nickel immersion gold (ENIG), tin plating, or electroplating, to prevent the copper on surface 131 from oxidizing with air, thus ensuring effective soldering with solder 160a later.

[0046] Figure 5 yes Figure 1 A partial cross-sectional view of the step of setting the wafer 150 in the manufacturing method of the circuit board assembly 100. (See attached diagram.) Figure 4 and Figure 5 The chip 150 is placed on solder 160a, with the chip pad 151 contacting the solder 160a. Then, the chip 150 and solder 160a are pressurized and heated, for example, to 10 MPa and to at least 250 degrees Celsius, for example, 300 degrees Celsius, causing the solder 160a to form a conductive adhesive layer 160. The chip 150 is attached to and electrically connected to the heat sink 130 via the conductive adhesive layer 160. For example, the conductive adhesive layer 160 is a sintered silver paste formed by pressurizing and heating silver paste, and the chip pads 151-153 do not need to be modified beforehand.

[0047] Figure 6 yes Figure 1 A partial cross-sectional view of the step of forming the photosensitive insulating material 170a in the manufacturing method of the circuit board assembly 100. (See attached diagram.) Figure 5 and Figure 6 A photosensitive insulating material 170a is formed on the surface 131 of the wafer 150 and the heat sink 130, the adhesive material 140, the circuit layer 113, and the dielectric layer 122, and the thickness t of the photosensitive insulating material 170a covering the wafer 150 is in the range of 30 micrometers to 50 micrometers. The photosensitive insulating material 170a can be formed by coating, and it can be a photosensitive polyimide. It is worth mentioning that after the photosensitive insulating material 170a is formed, it can be preheated (e.g., baked).

[0048] Figure 7 yes Figure 1A partial cross-sectional view of the step of forming the photosensitive insulating layer 170 in the manufacturing method of the circuit board assembly 100. (See attached diagram.) Figure 6 and Figure 7 Multiple through-holes 171 and 172 are formed in the photosensitive insulating material 170a. The bottom of the through-hole 171 exposes the wafer pad 152, while the bottom of the through-hole 172 exposes the wafer pad 153. Subsequently, the photosensitive insulating material 170a is heated (e.g., baked) to solidify it and form the photosensitive insulating layer 170.

[0049] It is worth mentioning that these vias 171 and 172 can be formed using photolithography, replacing laser drilling. Therefore, the wafer pads 152-153 do not need to be pre-modified and will not be damaged by the laser beam. Furthermore, the dimensions of these vias 171 and 172 can be easily controlled using photolithography. For example, these vias 171 and 172 can easily be formed with larger apertures, such as approaching the width of the wafer pads 152 and 153.

[0050] Figure 8 yes Figure 1 A partial cross-sectional view of the step of forming metal layers 360 and 370 in the manufacturing method of the circuit board assembly 100. (See attached diagram.) Figure 7 and Figure 8 A metal layer 360 is formed on the photosensitive insulating layer 170, and a metal layer 370 is formed on the surface 132 of the metal layer 320 and the heat sink 130. The metal layer 360 covers the wafer pads 152 and 153 exposed by the photosensitive insulating layer 170 and vias 171 and 172, electrically connecting the metal layer 360 to the wafer pads 152 and 153. The metal layer 370 covers the surface 132 of the metal layer 320 and the heat sink 130, electrically connecting the metal layer 320 and the heat sink 130. In other words, the photosensitive insulating layer 170, the wafer 150, the heat sink 130, and the metal layer 320 are located between the metal layers 360 and 370.

[0051] For example, the materials for metal layers 360 and 370 can be copper and other metals (such as titanium). The metal layers 360 and 370 can be formed by sputtering and flash plating. Figure 8 In the example, each metal layer 360, 370 is first formed by sputtering a titanium layer and a copper layer sequentially, with the titanium layer having a thickness of 0.1 micrometers and the copper layer having a thickness in the range of 0.3 to 0.5 micrometers. Then, each metal layer 360, 370 is flash-plated to form a copper layer, wherein the thickness of the copper layer is less than or equal to 7.5 micrometers.

[0052] Figure 9 yes Figure 1A partial cross-sectional view of the step of forming the conductive structure 180 in the manufacturing method of the circuit board assembly 100. (See attached diagram.) Figure 8 and Figure 9 Multiple conductive structures 180 are formed within vias 171 and 172 to fill them. For example, these conductive structures 180 can be formed on the metal layer 360 using selective electroplating. During the selective electroplating process, a mask layer can be formed on the metal layer 360 first, and then photolithography can be used to align the vias 171 and 172 with the areas of the metal layer 360 exposed by the mask layer. This mask layer can be a dry film.

[0053] Next, electroplating is performed to form the conductive structures 180 within the vias 171 and 172, respectively, and the masking layer is removed after electroplating. It should be noted that each conductive structure 180 includes a metal layer 360 within the via 171 or 172 and a structure filled by electroplating. Therefore, these conductive structures 180 electrically connect the wafer 150 and the metal layer 360. Next, the surfaces of the metal layer 360 and these conductive structures 180 are ground to ensure that the surfaces of the metal layer 360 and these conductive structures 180 remain on the same plane.

[0054] Figure 10 yes Figure 1 A partial cross-sectional view of the steps in the manufacturing method of the circuit board assembly 100, namely forming the adhesive layer 121 and the metal layer 380. (See attached diagram.) Figure 9 and Figure 10 First, a patterned metal layer 360 is formed to create a circuit layer 112. For example, the patterned metal layer 360 can be created using photolithography and etching processes. Next, an adhesive layer 121 and a metal layer 380 can be sequentially stacked and laminated on the circuit layer 112 using a build-up method.

[0055] Figure 11 yes Figure 1 A partial cross-sectional view of the step of forming conductive blind vias 210 and conductive through vias 220 in the manufacturing method of the circuit board assembly 100. (See attached diagram.) Figure 10 and Figure 11 The conductive blind via 210 is formed as described below. For example, multiple vias are formed in the metal layer 380 and the adhesive layer 121. These vias extend from the metal layer 380 to the adhesive layer 121 and expose the circuit layer 112 or the conductive structure 180. For example, the vias can be formed using photolithography and laser drilling. After laser drilling, a desmear process can be performed to remove any residual material at the bottom of the via.

[0056] Next, a metal layer is formed on the inner wall surface of the through hole using plating through hole (PTH) electroplating, and then the through hole is filled with electroplating to form a conductive blind via 210. Thus, the conductive blind via 210 can conduct through the metal layer 380 and the circuit layer 112 or the conductive structure 180. The conductive via 220 is formed as follows. For example, multiple through holes are formed by machining the metal layers 320, 370, and 380, the circuit layers 112 and 113, the adhesive layer 121, the photosensitive insulating layer 170, and the dielectric layer 122. Next, a metal layer is formed on the inner wall surface of the through hole using through-hole electroplating to form a conductive via 220. Thus, the conductive via 220 can conduct through the metal layers 320, 370, and 380 and the circuit layers 112 and 113.

[0057] See Figure 1 and Figure 11 Next, a patterned metal layer 380 is formed to create a circuit layer 111. Patterned metal layers 320 and 370 are then formed to create a circuit layer 114. The patterned metal layers 320, 370, and 380 can all be fabricated using photolithography and etching processes. Then, solder resist layers 191 and 192 are formed on the circuit layers 111 and 114, respectively, with the circuit layers 111 and 114 positioned between the solder resist layers 191 and 192. This essentially completes the fabrication of the circuit board assembly 100.

[0058] In summary, in the circuit board assembly 100 disclosed in the above embodiments, the photosensitive insulating layer 170 covers the wafer 150, allowing the vias 171 and 172 to be formed via photolithography, replacing laser drilling. This prevents the wafer 150 from being damaged by the laser beam, thereby improving the yield of the circuit board assembly 100 and reducing the cost of laser processing. Furthermore, since laser drilling is not used, the materials of the wafer pads 152 and 153 do not need to be modified before the wafer 150 is placed within the circuit board assembly 100, thus saving manufacturing steps and costs.

[0059] Secondly, the photosensitive insulating layer 170 can easily form large-diameter through-holes 171 and 172 through photolithography, enabling the subsequently formed conductive structure 180 to achieve good heat dissipation. It is worth mentioning that the heat sink 130 combines thermal and electrical conductivity, making it suitable for placement on the chip 150. Furthermore, the photosensitive insulating layer 170 has good electrical insulation and thermal conductivity, making it suitable for application within the circuit board assembly 100.

[0060] Although this application has been disclosed above with reference to embodiments, it is not intended to limit this application. Those skilled in the art to which this application pertains may make some modifications and refinements without departing from the spirit and scope of this application. Therefore, the scope of protection of this application shall be determined by the appended claims.

[0061] [Symbol Explanation]

[0062] 100: Circuit board assembly

[0063] 111~114: Line Layer

[0064] 121: Adhesive layer

[0065] 122: Dielectric layer

[0066] 130: Heatsink

[0067] 131, 132: Surface

[0068] 140: Adhesive Material

[0069] 150: Chip

[0070] 151-153: Chip pads

[0071] 160: Conductive adhesive layer

[0072] 160a: Solder

[0073] 170: Photosensitive insulating layer

[0074] 170a: Photosensitive insulating material

[0075] 171, 172: Through holes

[0076] 180: Conductive structure

[0077] 191, 192: Solder resist layer

[0078] 210: Conductive blind hole

[0079] 220: Conductive via

[0080] 300:Substrate

[0081] 310, 320, 360, 370, 380: Metal layer

[0082] 330: Storage space

[0083] 340: Peeling layer

[0084] t: thickness.

Claims

1. A circuit board assembly, characterized in that, Include: First line layer; Second line layer; A heat sink is located between the first circuit layer and the second circuit layer; The chip is mounted on the heat sink; A photosensitive insulating layer is located between the first and second circuit layers, and covers and surrounds the wafer; as well as A conductive structure is disposed between the wafer and the second circuit layer, and electrically connects the wafer and the second circuit layer.

2. The circuit board assembly as claimed in claim 1, characterized in that, Also includes: A dielectric layer is located between the first circuit layer and the photosensitive insulating layer, wherein the dielectric layer surrounds the heat sink; and Adhesive material is distributed on the heat sink to fix the heat sink and the dielectric layer.

3. The circuit board assembly as claimed in claim 1, characterized in that, The photosensitive insulating layer covers the wafer with a thickness ranging from 30 micrometers to 50 micrometers.

4. The circuit board assembly as claimed in claim 1, characterized in that, The wafer has wafer pads that are electrically connected to the conductive structure, and the wafer pads are made of aluminum or copper and contact the conductive structure.

5. The circuit board assembly as claimed in claim 1, characterized in that, Also includes: A conductive adhesive layer is bonded between the wafer and the heat sink. The heat sink is conductive and electrically connected to the first circuit layer. The wafer is electrically connected to the first circuit layer via the conductive adhesive layer and the heat sink.

6. The circuit board assembly as claimed in claim 1, characterized in that, The heat sink is made of copper, the conductive structure is made of copper, and the photosensitive insulating layer is made of photosensitive polyimide.

7. A method for manufacturing a circuit board assembly, characterized in that, Include: Provide substrate; A heat sink is disposed within the substrate; The chip is mounted on the heat sink; A photosensitive insulating material is formed on the wafer, wherein the photosensitive insulating material covers the wafer and the heat sink; A through-hole is formed in the photosensitive insulating material, wherein the bottom of the through-hole exposes the wafer; After the through-hole is formed, the photosensitive insulating material forms a photosensitive insulating layer; After the heat sink is installed, a first metal layer is formed on the substrate, wherein the first metal layer covers the heat sink and the heat sink is located between the first metal layer and the photosensitive insulating layer. A second metal layer is formed on the photosensitive insulating layer, wherein the photosensitive insulating layer is located between the second metal layer and the first metal layer; and A conductive structure is formed within the via, wherein the conductive structure electrically connects the second metal layer and the wafer.

8. The manufacturing method as described in claim 7, characterized in that, The through-hole was formed by photolithography.

9. The manufacturing method as described in claim 7, characterized in that, Also includes: Before setting the heat sink, a release layer is set on the substrate so that the heat sink is then attached to the release layer. After the heat sink is installed, adhesive is applied to the heat sink to fix the heat sink and the substrate. as well as After applying the adhesive material, remove the release layer.

10. The manufacturing method as described in claim 7, characterized in that, The chip is configured to include, on the heat sink: Solder is applied to the heat sink; Place the wafer on the solder; and The wafer and the solder are pressurized and heated so that the solder forms a conductive adhesive layer.

Images