SiC power semiconductor device, preparation method, metal-semiconductor contact interface structure and application

Abstract

The invention discloses a SiC power semiconductor device, a preparation method, a metal semiconductor contact interface structure and application, and belongs to the field of semiconductors. The SiC power semiconductor device comprises a source electrode and a drain electrode, and the material of the source electrode and / or the drain electrode is an MAX phase. The structure is reasonable, the specific MAX phase is selected as a material for constructing the source electrode and / or the drain electrode, then reliable and stable metal-semiconductor ohmic contact is formed, compared with pure metal, the multi-element MAX phase can adjust the interface performance by adjusting and controlling the local structure of an interface, the interface transport performance is further improved, and the contact resistance is reduced.

Description

Technical Field

[0001] This invention relates to a SiC power semiconductor device, its fabrication method, gold-semiconductor contact interface structure, and its application, belonging to the field of semiconductor device technology. Background Technology

[0002] In the manufacturing process of electronic devices, constructing stable and reliable metal-semiconductor contacts has always been a critical technical requirement, especially for applications under certain harsh conditions. Although SiC materials possess excellent high-temperature stability and oxidation resistance, their metal electrode contact interfaces still face many challenges in practical devices. Under harsh conditions such as high temperatures, metal contact interfaces are prone to surface oxidation and destructive interdiffusion of elements, leading to a significant degradation in the electrical performance of the device. Therefore, to realize the performance advantages of SiC-based devices in harsh environments, developing metal contact solutions with low contact resistance and high stability, especially ohmic contacts for p-type 4H-SiC, has become a critical problem that urgently needs to be solved in current industrial applications.

[0003] The main challenge in fabricating ohmic contacts stems from the high Schottky barrier at the metal-SiC interface. Extensive research has revealed two main methods for fabricating wide-bandgap semiconductor ohmic contacts: first, high-dose ion implantation to heavily dope the semiconductor surface, significantly enhancing tunneling current and reducing barrier effects; second, deposition and annealing processes to fabricate metal alloy electrodes, such as TiAl-based, Ni-based, and noble metal alloys. Studies show that annealing optimizes the interface structure, promoting the formation of transition layers between the metal and SiC, including metal silicides (e.g., Ni₂Si), metal carbides (e.g., Al₄C₃), and multi-metal compounds (e.g., NiAl₃, TiAl₃, and Ti₃SiC₂), effectively reducing the Schottky barrier height. However, the interface reaction is difficult to control and repeat. Notably, the local bonding state at the SiC / Ti₃SiC₂ interface significantly influences the performance of p-type 4H-SiC ohmic contacts, but the specific theoretical mechanisms remain to be elucidated. Currently, titanium-based metals remain the primary method for achieving stable, low-resistance ohmic contacts (contact resistance approximately 10 ohms). -5 -10 -6 Ω·cm 2 The main material system (within the scope) has been developed, but its performance reproducibility is still not ideal. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide a SiC power semiconductor device with reliable and stable metal-semiconductor ohmic contacts and a method for fabricating the same; a second objective of the present invention is to provide the application of the MAX phase as the source and / or drain of a SiC power semiconductor device; and a third objective of the present invention is to provide a gold-semiconductor contact interface structure with reliable and stable metal-semiconductor ohmic contacts.

[0005] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows: A SiC power semiconductor device includes a source and a drain, with a SiC semiconductor layer disposed between the source and the drain, wherein the source and / or drain are made of MAX phase.

[0006] Furthermore, the MAX phase is Ti3AC2, where A is Ir.

[0007] Furthermore, the SiC power semiconductor device is a SiC MOSFET device.

[0008] Furthermore, the SiC power semiconductor device includes a drain, an n-type SiC, a p-based region, and a source, which are stacked sequentially from bottom to top. An n+ region is provided between the p-based region and the source. The top of the p-based region is at least partially in direct contact with the source, and the top of the n+ region is in direct contact with the source. The n-type SiC, the p-based region, and the n+ region constitute a SiC semiconductor layer.

[0009] Preferably, the interface between the SiC semiconductor layer and the MAX phase is Si / Ti (i.e., SiC surface terminated by Si to Ti3IrC2 terminated by Ti) or Si / C (i.e., SiC surface terminated by Si to Ti3IrC2 terminated by C).

[0010] Furthermore, it also includes a dielectric layer that covers a portion of the side surface of the n-type SiC, a portion of the side surface of the p-base region, a portion of the side surface of the n+ region, and a portion of the side surface of the source electrode, and a gate electrode is provided on the dielectric layer.

[0011] Furthermore, the gate is made of heavily doped polycrystalline silicon material.

[0012] Based on the same inventive concept, the present invention also provides: a method for fabricating the SiC power semiconductor device as described above, comprising the following steps: S1. Provide n-type SiC, and grow a p-based region on the n-type SiC using an epitaxial process; S2. Selectively form an n+ region on top of the p-base region to obtain a stacked structure composed of the n+ region and the p-base region; S3. Grooves are etched into the side of the stacked structure; The trench extends from top to bottom through the n+ region and the p-based region and into the n-type SiC. S4. A dielectric layer is grown in the trench; S5. A gate is fabricated on the dielectric layer; S6. Fabricate the source electrode on the top surface of the stacked structure; fabricate the drain electrode on the bottom surface of n-type SiC.

[0013] Based on the same inventive concept, the present invention also provides: the application of the MAX phase as the source and / or drain of SiC power semiconductor devices.

[0014] Furthermore, the MAX phase is Ti3AC2, where A is Ir.

[0015] Based on the same inventive concept, the present invention also provides: a gold-semiconductor contact interface structure, comprising a stacked electrode layer and a semiconductor layer, wherein the electrode layer is composed of a MAX phase. Optionally, the MAX phase is Ti3AC2, wherein A is Ir.

[0016] This invention employs the MAX phase as the material for constructing the source and / or drain. The selected MAX phase exhibits good thermal stability at high temperatures and excellent mechanical strength along the carrier transport direction. This MAX phase / 4H-SiC interface structure can significantly reduce the Schottky barrier. Further transport simulations confirm that, within the actual doping concentration range of SiC power semiconductor devices, ideal ohmic contact characteristics can be formed between the MAX phase and 4H-SiC.

[0017] Compared to single-metal materials, multi-component MAX phases possess the ability to optimize performance by modulating the local structure of the interface, thereby enhancing carrier transport characteristics and reducing contact resistance. Furthermore, thanks to the chemical inertness of the MAX phase, it can effectively suppress the outward diffusion of silicon during the long-term service of SiC power semiconductor devices, and a pure metal layer (such as a Ti or Ir layer) is maintained on the MAX phase surface, thus creating favorable conditions for subsequent packaging and wire bonding processes.

[0018] The metal-semiconductor ohmic contact between the source and / or drain of the SiC power semiconductor device of the present invention and SiC is reliable and stable, and can also exert its working advantages under harsh conditions such as high temperature.

[0019] The SiC power semiconductor device of this invention has a rational structure. By selecting a specific MAX phase as the material for constructing the source and / or drain, a reliable and stable metal-semiconductor ohmic contact is formed. Compared with pure metals, the multi-element MAX phase can adjust and control the local structure of the interface to regulate interface performance, further improving interface transport performance and reducing contact resistance. Moreover, the MAX phase is chemically inert, which can effectively prevent silicon from diffusing outward during long-term aging and retain a pure metal layer on the surface, which is beneficial for further encapsulation line bonding processes, thereby improving the reliability of the power device under harsh conditions. Attached Figure Description

[0020] Figure 1 This is a schematic diagram (side view) of a SiC power semiconductor device structure and a schematic diagram (side view, corresponding to the upper right and upper left corners) of a gold semiconductor contact interface structure according to the present invention.

[0021] Figure 2 This is the band structure and density of states diagram of the Ti3IrC2MAX phase.

[0022] Figure 3 This is the dispersion spectrum of Ti3IrC2MAX.

[0023] Figure 4 It is the anisotropy of the elastic modulus of the Ti3IrC2MAX phase.

[0024] Figure 5 The structural changes of Ti3IrC2 at different temperatures (300 K-1800 K) were simulated by de novo molecular dynamics.

[0025] Figure 6 The potential energy changes of Ti3IrC2 at different temperatures (300 K-1800 K) were simulated by de novo molecular dynamics.

[0026] Figure 7 The atomic force changes of Ti3IrC2 at different temperatures (300 K-1800 K) were simulated from scratch using molecular dynamics.

[0027] Figure 8 It is a Ti3IrC2 / 4H-SiC gold semi-contact interface structure model.

[0028] Figure 9 This is a model of a Ti3IrC2 / 4H-SiC gold semi-contact interface dual-ended transmission device. The meaning of each atom model is as follows: Figure 8 The meanings of the various atomic models are consistent.

[0029] Figure 10 This is a diagram showing the Schottky barrier height of a high-temperature resistant pure metal and Ti3IrC2 in contact with 4H-SiC.

[0030] Figure 11 This is an IV curve of the Ti3IrC2 / 4H-SiC gold semi-contact interface structure.

[0031] Figure 12 yes Figure 8 The diagram shows the structural changes of the Ti3IrC2 / 4H-SiC gold semi-contact interface at 1800 K.

[0032] In the above figures: 1, source; 2, gate; 3, drain; 4, dielectric layer; 5, n+ region; 6, n++ region; 7, p-base region; 8, n-type SiC. Detailed Implementation

[0033] The present invention will be described in detail below with reference to embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other. For ease of description, the words "upper," "lower," "left," and "right" appearing below only indicate that they are consistent with the upper, lower, left, and right directions of the drawings themselves, and do not limit the structure.

[0034] Ti3IrC2 has a hexagonal symmetric structure (space group P63 / mmc), with two chemical unit cells per unit cell. This crystal structure consists of alternating stacks of edge-connected Ti3C2 octahedra and Ir atomic layers: Ti3C2 units are arranged in pairs, separated by Ir layers acting as mirrors; Ti and Ir layers are staggered, with carbon atoms filling the interstitial positions of the octahedra, while Ir atoms occupy the centers of slightly larger triangular prisms, allowing for larger atoms to be accommodated. The configuration of the Ti3C2 octahedra is the same as that observed in rock salt carbides. MAX phase materials can be classified into three structural types—211 (n=1), 312 (n=2), and 413 (n=3)—based on the number of M layers stacked between A layers. Ti3IrC2 belongs to the 312 type. The lattice parameters of the Ti3IrC2 phase were further obtained using the first-principles calculation software VASP6.2.1. The calculation process and parameters are as follows: A PBE functional with a generalized gradient approximation is used to describe electron exchange and correlation interactions. During the calculation, the interaction between ionic cores and valence electrons is described using the projected plane wave method. Traditional PBE methods underestimate the bandgap of semiconductor materials, which has a greater impact on the wide-bandgap semiconductor 4H-SiC. Therefore, this invention further employs an advanced HSE06 hybrid functional to correct the band structure calculations, thereby obtaining theoretical values ​​close to experimental results. For all structures involved in the calculation, the wavefunction cutoff energy is set to 520 eV, and the convergence threshold for the self-consistent cyclic iteration energy is 1 × 10⁻⁶ eV. -5The convergence value of the interatomic forces is 0.01 eV / Å. For the heterojunction interface model, to avoid the mutual influence between two adjacent thin layers in the aperiodic direction, a vacuum layer exceeding 20 Å is selected to eliminate the influence. The optimization results show that its lattice constant a is 3.02 Å. In addition, structural measurements show that the average bond length of the six-coordinate Ti-C bond is 2.13 Å, and the Ti-Au bond length is 2.73 Å. All the obtained lattice parameters are in high agreement with existing experimental data (Inorganic Chemistry, 2022, Vol. 61, No. 4, 2129-2140), verifying the reliability of the theoretical model and calculation method used in this invention.

[0035] To further investigate the electronic properties of Ti3IrC2, this invention calculated its band structure and projected density of states using the first-principles calculation software VASP6.2.1. Given the excellent conductivity of the MAX phase itself, the band gap size is not a primary concern during the analysis; the focus is on ensuring the accuracy of the electronic state calculations. The electronic structure of Ti3IrC2 is as follows: Figure 2 As shown in the diagram, the band structure clearly reveals that Ti3IrC2 exhibits typical metallic behavior. The electronic states near the Fermi level primarily originate from the d orbitals of Ti; the valence band is dominated by the p orbitals of C, while the conduction band is mainly composed of Ti d orbitals. Density of states analysis further reveals that in the Ti3C2 structural unit, there is significant hybridization between the d orbitals of Ti and the p orbitals of C, forming strong Ti-C covalent bonds. This characteristic is highly similar to the bonding mode of its corresponding binary carbide, MXene. Simultaneously, there is some overlap between the d orbitals of Ti and A, exhibiting characteristics of metallic bonding. In summary, the MAX phase Ti3IrC2 material possesses a composite characteristic of metallic, covalent, and ionic bonding in its chemical bonding mode.

[0036] Phonons play a crucial role in the study of material dynamics and thermal properties. To assess the dynamic stability of the Ti3IrC2 phase, this invention constructs a fully relaxed supercell model containing 108 atoms and uses the first-principles calculation software VASP6.2.1 to calculate the phonon dispersion relation of Ti3IrC2. Figure 3 The obtained phonon dispersive spectrum is presented. The results show that no imaginary frequencies appear throughout the high-symmetry path and its vicinity, thus confirming the structural dynamic stability of Ti3IrC2.

[0037] To systematically evaluate the mechanical properties of Ti3IrC2, this invention uses the first-principles calculation software VASP6.2.1 to calculate the elastic constants of Ti3IrC2, and then analyzes the ease with which it undergoes elastic deformation, i.e., the rigidity characteristics of the material. Figure 4The elastic modulus distribution of Ti3IrC2 in different directions is shown, clearly reflecting the spatial variation of the material's stiffness. The results indicate that Ti3IrC2 exhibits isotropic stiffness characteristics in the xy-plane, while displaying higher stiffness along the z-axis (0001) direction. Furthermore, compared to Ti3AuC2, Ti3FeC2, Ti3CoC2, Ti3NiC2, and Ti3ZnC2, Ti3IrC2 possesses superior mechanical properties. Therefore, when Ti3IrC2 is used as an electrode material in vertical power devices, its superior mechanical properties along the c-axis contribute to improving the structural stability and reliability of the device under extreme conditions such as thermal cycling.

[0038] To evaluate the thermal stability of Ti3IrC2, this invention conducted ab initio molecular dynamics simulations of Ti3IrC2 in the temperature range of 300 K to 1800 K using the first-principles calculation software VASP6.2.1. Figure 5 , Figure 6 and Figure 7 The evolution of the system's structure, energy, and forces at different temperatures is illustrated. Simulation results show that as the temperature increases, only minor displacements occur among the atoms in Ti3IrC2. Even at temperatures above 1100 K, the atoms remain largely in their initial positions, and the crystal framework remains intact, indicating that the material possesses excellent high-temperature tolerance. Furthermore, throughout the heating process, the fluctuations in the system's potential energy and interatomic forces remain at low levels, further demonstrating that the Ti3IrC2 phase remains thermodynamically stable even at temperatures as high as 1800 K. These results fully demonstrate that Ti3IrC2 material exhibits excellent thermal stability and structural integrity under high-temperature conditions, providing crucial assurance for its application in high-temperature power devices.

[0039] Due to limitations in research methods, the interface between the metallic MAX phase (Ti3IrC2) and 4H-SiC has not yet been studied in depth at the atomic scale. This invention, based on various established Ti3IrC2 / 4H-SiC interface models, directly studies the properties of the corresponding material interface through first-principles calculations.

[0040] The 4H-SiC unit cell contains four Si-C bilayers, forming a tetrahedral coordination configuration. It contains two different lattice sites (h-site and k-site), resulting in diverse stacking sequences. The 4H-SiC(0001) surface has eight stacking configurations, with the outermost atoms being Si(1h), C(1h), Si(1k), C(1k), C(2h), Si(2h), C(2k), and Si(2k). The basic structural unit of Ti3IrC2 consists of two symmetrical Ti3C2 layers connected by Ir atomic layers. Its (0001) surface exhibits four stacking arrangements, with the outermost layers being Ti(1), C(1), Ti(2), and C(2) atomic layers.

[0041] To gain a deeper understanding of the atomic configuration and stable chemical bonding mechanism of the Ti3IrC2 / SiC interface, this invention constructs a systematic theoretical model: based on the combination of eight different terminal surfaces of 4H-SiC and four terminal structures of Ti3IrC2, a total of 32 possible stacking sequences (interface models) are constructed. It should be noted that, due to the small lattice mismatch between 4H-SiC and Ti3IrC2, the supercell model can effectively neglect the influence of interfacial strain.

[0042] To select a stable configuration from the 32 interface models mentioned above, 4H-SiC and MAX phase layer models for all stacking types were first established along the 0001 direction. Each SiC layer contains 9 SiC atomic layers, while the Ti3IrC2 layer consists of no less than 11 atomic layers to ensure sufficient surface energy convergence and maintain bulk material properties. Subsequently, the corresponding interface models were constructed and subjected to thorough structural optimization.

[0043] Because different interface models have different numbers of atoms, directly comparing the total energy cannot effectively assess their relative stability. Therefore, this invention uses adhesion energy as the evaluation criterion. This physical quantity represents the energy required to separate the interface into two free surfaces, to more accurately reflect the interfacial bonding strength. Calculation results show that all 4H-SiC surfaces terminated with Si (including Si(1h), Si(1k), Si(2h), or Si(2k)) exhibit the strongest adhesion to Ti3IrC2 terminated with Ti (see [link to relevant documentation]). Figure 8 (The two figures on the right in the middle); and all 4H-SiC surfaces with Si terminals (including C(1k) or C(1h)) are most stable for binding with C-terminated Ti3IrC2 (see the two figures on the right in the middle). Figure 8 (The two pictures on the left in the middle).

[0044] Based on the adhesion energy calculations, the study focused on the gold-semiconductor contact interface structure with the strongest bonding (see [link to study]). Figure 8In this preferred gold-semiconductor contact interface structure, a good chemical bond is formed between the Si-C bonding network on the SiC substrate surface and Ti3IrC2, and no obvious reconstruction or lattice deformation occurs in the interface region, successfully achieving a high-quality interface with atomically flat surface.

[0045] To further investigate the carrier transport behavior at the Ti3IrC2 / 4H-SiC(0001) interface, this invention constructs a gold-semiconductor contact interface structure for simulating electron transport processes based on the electrical contact configuration of the electrode region in actual SiC power semiconductor devices (see [link]). Figure 9 The quantum transport properties of the interface were systematically calculated using first-principles quantum transport methods. To ensure that the simulation conditions are consistent with the actual device fabrication process, the vertical conduction structure commonly used in SiC power semiconductor devices for high-power applications needs to be considered: during the fabrication of ohmic contact electrodes, a highly active P+ / N+ heavily doped region is formed between the metal electrodes (source and drain) and the 4H-SiC epitaxial layer through high-energy ion implantation and subsequent annealing. This structure helps to reduce the width of the semiconductor depletion layer, promotes electron tunneling, and thus achieves ohmic contacts with low on-resistance.

[0046] To accurately evaluate the Schottky barrier change and carrier transport behavior of the Ti3IrC2 / SiC gold semi-contact interface structure in practical SiC power semiconductor devices, a two-terminal device model including fully relaxed left and right electrodes and a central scattering region was constructed (see [link to model]). Figure 9 The model of this two-terminal device (i.e., a gold-semiconductor contact interface structure) is approximately 6 Å long (x-direction), 11 Å wide (y-direction), and 140 Å high (z-direction). The Ti3IrC2 layer is approximately 60 Å thick, and the SiC layer is approximately 80 Å thick. The two-terminal device model includes an electrode layer (corresponding to...) Figure 9 The left side of the red dashed line) and the semiconductor layer (corresponding to Figure 9(The right side of the red dashed line in the image) The electrode layer is composed of Ti3IrC2, and the semiconductor layer is composed of 4H-SiC. At the interface between the electrode layer and the semiconductor layer, the 4H-SiC surface terminated by Si is paired with the Ti3IrC2 surface terminated by Ti (i.e., the interface between the electrode layer and the semiconductor layer is Si / Ti). The dual-ended device model is further divided into a left electrode, an extended layer, a central scattering region, and a right electrode (virtual electrode), distributed from left to right. The left electrode and the extended layer are both composed of Ti3IrC2, while the central scattering region and the right electrode are both composed of 4H-SiC. The central region concentrates the main scattering mechanism of the Ti3IrC2 / SiC metal-semiconductor interface, and the electrode portion is set as a semi-infinite extended structure. After completing the device structure modeling, the system is calculated using a first-principles quantum transport simulation method. This model fully considers the interface coupling between the electrode and the channel region and the Fermi level pinning effect. Furthermore, this method can effectively examine the influence of different doping concentrations on the semiconductor transport characteristics and is suitable for simulating the electrical behavior of heavily P+ / N+ doped layers in SiC power semiconductor devices. Based on the optimized electronic structure information, the voltage-current (IV) output characteristics of the device along the current transport direction were further systematically calculated, thus comprehensively revealing its electrical transport performance.

[0047] Adopted and Figure 9 Using the same two-terminal device model, the Schottky barrier height of high-temperature resistant pure metal and Ti3IrC2 contact 4H-SiC was simulated and calculated. See the results below. Figure 10 When in contact with pure metal electrodes such as W, Ti, and Mo, the metal-semiconductor interface exhibits n-type Schottky contact characteristics; while when in contact with Pt, Pd, and Ni electrodes, a p-type Schottky contact is formed. The relevant simulation results are in good agreement with existing experimental data (Phys. Status Solidi (B), 2024, Vol. 261, No. 5, 2400076). For the Ti3IrC2 material system, the local atomic configuration of its interface region can effectively control the Schottky barrier height. Specifically, compared with Ti3AuC2, when the Ti3IrC2 / SiC interface forms a Si-C-Ti bond structure, a lower barrier height p-type Schottky contact can be achieved, demonstrating significant potential for realizing p-type ohmic contacts.

[0048] To further verify whether an ohmic contact is formed between Ti3IrC2 and 4H-SiC, this invention calculates... Figure 9 The current response characteristics of the gold semi-contact interface structure under different bias voltages ( Figure 11 The doping concentration of 4H-SiC is 10%. 20 cm -3Under these conditions, the IV characteristic curve exhibits a good linear relationship, consistent with the basic characteristics of an ohmic contact. However, Figure 11 The upper left and lower right insets show that the IV curves still exhibit Schottky contact characteristics at lower doping levels, indicating that the Schottky barrier has not yet been effectively suppressed.

[0049] To evaluate the thermal stability of the Ti3IrC2 / 4H-SiC interface in the aforementioned gold semi-contact interface structure, this invention targets... Figure 9 The Ti3IrC2 / 4H-SiC gold semi-contact interface structure shown was subjected to first-principles molecular dynamics simulations at 1800 K. The thermal stability of the Ti3IrC2 / 4H-SiC interface was simulated. Figure 12 Demonstrated at 1800 K Figure 8 The structural evolution of the Ti3IrC2 / 4H-SiC interface is shown. Simulation results indicate that at temperatures up to 1800 K, only minor displacements occur among the atoms in the Ti3IrC2 / 4H-SiC interface. These results fully demonstrate that the Ti3IrC2 / 4H-SiC interface exhibits excellent thermal stability and structural integrity under high-temperature conditions, providing crucial assurance for its application in high-temperature power devices.

[0050] See Figure 1 A SiC power semiconductor device, specifically a SiC MOSFET, comprises a drain 3, an n-type SiC 7, a p-base region 6, and a source 1 stacked sequentially from bottom to top. An n+ region 5 is provided between the p-base region 6 and the source 1. The top of the p-base region 6 is at least partially in direct contact with the source 1, and the cross-section of the p-base region 6 is L-shaped. The top of the n+ region 5 is in direct contact with the source 1. The source 1 and drain 3 are made of the MAX phase. The SiC power semiconductor device also includes a dielectric layer 4, which covers a portion of the sidewalls of the n-type SiC 7, the p-base region 6, the n+ region 5, and the source 1. A gate 2 is provided on the dielectric layer 4 (insulating layer), and the gate 2 is made of heavily doped polycrystalline silicon. The dielectric layer 4 is made of silicon dioxide. The MAX phase is Ti3AC2, where A is Ir. The interface between source 1 and n+ region 5, and the interface between drain 3 and n-type SiC7, is n++ region 51. n-type SiC7, p-based region 6, and n+ region 5 constitute the SiC semiconductor layer.

[0051] Optionally, the above-mentioned SiC power semiconductor device can be constructed using the following method: S1. Provide an n-type SiC substrate (i.e., n-type SiC7, formed after 4H-SiC doping), and grow the p-based region 6 on the substrate by epitaxial process.

[0052] S2. An n+ region is selectively formed on top of the p-based region using photolithography and ion implantation processes.

[0053] S3. Using an anisotropic dry etching process, trenches are etched in the stacked structure composed of n+ region 5 and p base region 6, with a depth penetrating through the n+ region 5 and p base region 6 and extending into the n-type SiC7.

[0054] S4. A dielectric layer 4 is grown on the entire semiconductor surface including the trench sidewalls and bottom by one or a combination of thermal oxidation and chemical vapor deposition methods.

[0055] S5. On the dielectric layer 4, doped polysilicon is filled by chemical vapor deposition to form a gate conductor (i.e., gate 2).

[0056] S6. In an ultra-high vacuum environment (<1×10⁻⁶) -8 Ir and Ti metal layers are sequentially deposited on the top surface of the stacked structure and the bottom surface of n-type SiC7 by magnetron sputtering or electron beam evaporation, respectively. The molar ratio of Ti in the Ti metal layer to Ir in the Ir metal layer is controlled to be approximately 3:1 to facilitate the final formation of Ti3IrC2. Ir / Ti stacked structures are obtained on the top surface of the stacked structure and the bottom surface of the n-type SiC7, respectively, to obtain the device blank.

[0057] The rough blank of the device is placed in a rapid thermal annealing furnace and heated. During the heating process, Ti in the Ti metal layer begins to interdiffusion with Ir in the Ir metal layer. Simultaneously, the SiC semiconductor layer undergoes thermal decomposition at the interface with the Ir / Ti stack, releasing Si and C atoms. The Si atoms penetrate the initial Ir metal layer and react with the Ti in the Ti metal layer, forming a Si / Ti contact interface near the SiC / Ir interface. The C atoms are effectively confined to the interface region by the Ir metal layer and react with the diffused Ti and Ir. Under suitable stoichiometric ratios (Ti:Ir ≈ 3:1) and temperatures (e.g., 500℃-1000℃), the entire Ir metal layer and part of the Ti metal layer transform into Ti3IrC2 (MAX phase), located above the newly formed Si / Ti interface.

[0058] Furthermore, a Ti3IrC2 metal layer is finally formed by physical vapor deposition. This Ti3IrC2 metal layer forms an ohmic contact with both the n+ region and the p-base region, constituting source 1. A Ti3IrC2 metal layer is also formed on the back side of the n-type SiC substrate, constituting drain 3.

[0059] Therefore, the source and the n+ region actually form a structure similar to Figure 9 The gold-semiconductor contact interface structure shown has a drain electrode that actually forms a similar structure to the n-type SiC7. Figure 9The gold-semiconductor contact interface structure is shown. It can be inferred that the aforementioned SiC power semiconductor device also possesses the advantages mentioned above regarding the Ti3IrC2 and gold-semiconductor contact interface structure.

[0060] The above embodiments should be understood as being used only to illustrate the present invention more clearly, and not to limit the scope of the present invention. After reading the present invention, any modifications of the present invention in various equivalent forms by those skilled in the art fall within the scope defined by the appended claims.

Claims

1. A SiC power semiconductor device, comprising a source (1) and a drain (3), wherein a SiC semiconductor layer is disposed between the source (1) and the drain (3), characterized in that, The source (1) and / or drain (3) are made of MAX phase.

2. The SiC power semiconductor device according to claim 1, characterized in that, The MAX phase is Ti3AC2, where A is Ir; preferably, the interface between the SiC semiconductor layer and the MAX phase is Si / Ti or Si / C.

3. The SiC power semiconductor device according to claim 1, characterized in that, SiC power semiconductor devices are SiC MOSFET devices.

4. The SiC power semiconductor device according to claim 1, characterized in that, The SiC power semiconductor device includes a drain (3), an n-type SiC (7), a p-base region (6) and a source (1) stacked sequentially from bottom to top. An n+ region (5) is provided between the p-base region (6) and the source (1). The top of the p-base region (6) is at least partially in direct contact with the source (1), and the top of the n+ region (5) is in direct contact with the source (1).

5. The SiC power semiconductor device according to claim 4, characterized in that, It also includes a dielectric layer (4), which covers part of the side surface of the n-type SiC (7), part of the side surface of the p-base region (6), part of the side surface of the n+ region (5) and part of the side surface of the source (1), and a gate (2) is provided on the dielectric layer (4).

6. The method for fabricating a SiC power semiconductor device as described in claim 5, characterized in that, Includes the following steps: S1. Provide n-type SiC (7), and grow p-based regions (6) on the n-type SiC (7) by epitaxial process. S2. Selectively form an n+ region (5) on top of the p base region (6) to obtain a stacked structure consisting of the n+ region (5) and the p base region (6); S3. Grooves are etched into the side of the stacked structure; The trench extends from top to bottom through the n+ region (5) and the p-based region (6) and into the n-type SiC (7); S4. A dielectric layer is grown in the trench (4). S5. A gate (2) is prepared on the dielectric layer (4); S6. The source electrode (1) is prepared on the top surface of the stacked structure; the drain electrode (3) is prepared on the bottom surface of the n-type SiC (7).

7. Application of the MAX phase as the source (1) and / or drain (3) of SiC power semiconductor devices.

8. The application according to claim 7, characterized in that, The MAX phase is Ti3AC2, where A is Ir.

9. A gold-semiconductor contact interface structure, comprising stacked electrode layers and semiconductor layers, characterized in that, The electrode layer is composed of a MAX phase.

10. The gold-semiconductor contact interface structure according to claim 9, characterized in that, The MAX phase is Ti3AC2, where A is Ir.

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