Ferroelectric field effect transistor

Abstract

A ferroelectric field effect transistor includes an active region, a ferroelectric stack structure on the active region, and a gate electrode on the ferroelectric stack structure. The ferroelectric stack structure includes a plurality of ferroelectric layers having different coercive fields from each other. Wherein the ferroelectric field effect transistor is configured to implement multi-valued storage based on a polarization state of the plurality of ferroelectric layers.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of non-volatile memory, and in particular to a ferroelectric field effect transistor. BACKGROUND

[0002] A ferroelectric field effect transistor (FeFET) is a semiconductor device designed based on the spontaneous polarization characteristics of ferroelectric materials. When an external electric field is applied, the polarization direction of the ferroelectric material will flip, and this polarization state can be maintained after the external electric field is removed, thereby realizing non-volatile storage of data. However, the ferroelectric material only has two stable states corresponding to two opposite polarization directions, and the intermediate polarization state is unstable. When multi-value storage is performed, the threshold voltage is easily disturbed, reducing the reliability of the stored data. SUMMARY

[0003] In view of the above problems, the present disclosure provides a ferroelectric field effect transistor.

[0004] According to a first aspect of the present disclosure, a ferroelectric field effect transistor is provided, comprising an active region, a ferroelectric stack structure on the active region, and a gate electrode on the ferroelectric stack structure. The ferroelectric stack structure comprises a plurality of ferroelectric layers having different coercive fields from each other. Wherein the ferroelectric field effect transistor is configured to realize multi-value storage based on the polarization states of the plurality of ferroelectric layers.

[0005] According to an embodiment of the present disclosure, the ferroelectric stack structure comprises n ferroelectric layers, and the ferroelectric field effect transistor has 2 n storage states, wherein n is a positive integer greater than or equal to 2.

[0006] According to an embodiment of the present disclosure, the ferroelectric stack structure comprises a first ferroelectric layer and a second ferroelectric layer, and the storage states include: both the first ferroelectric layer and the second ferroelectric layer have a polarization state toward the active region; both the first ferroelectric layer and the second ferroelectric layer have a polarization state away from the active region, the first ferroelectric layer has a polarization state toward the active region and the second ferroelectric layer has a polarization state away from the active region; and the first ferroelectric layer has a polarization state away from the active region and the second ferroelectric layer has a polarization state toward the active region.

[0007] According to an embodiment of the present disclosure, the ferroelectric field effect transistor has a plurality of threshold voltages, and the plurality of threshold voltages depend on the respective coercive fields and thicknesses of the plurality of ferroelectric layers.

[0008] According to an embodiment of the present disclosure, the ferroelectric stack structure comprises n ferroelectric layers, n is a positive integer greater than or equal to 2, and the threshold voltage of the ferroelectric field effect transistor is V0±E1d1±E2d2±···±E n d nwherein V0 is a flat band voltage of the ferroelectric field effect transistor, E1, E2, ···, En are n coercive fields of the n ferroelectric layers, respectively, d1, d2, ···, dn are thicknesses of the n ferroelectric layers, respectively, and Vth is a threshold voltage of the ferroelectric field effect transistor. n wherein V0 is a flat band voltage of the ferroelectric field effect transistor, E1, E2, ···, En are n coercive fields of the n ferroelectric layers, respectively, d1, d2, ···, dn are thicknesses of the n ferroelectric layers, respectively, and Vth is a threshold voltage of the ferroelectric field effect transistor. n wherein V0 is a flat band voltage of the ferroelectric field effect transistor, E1, E2, ···, En are n coercive fields of the n ferroelectric layers, respectively, d1, d2, ···, dn are thicknesses of the n ferroelectric layers, respectively, and Vth is a threshold voltage of the ferroelectric field effect transistor.

[0009] According to an embodiment of the present disclosure, in response to a write voltage applied to the gate electrode, the polarization states of the plurality of ferroelectric layers are independently flipped or not flipped according to a size of the write voltage relative to a plurality of threshold voltages, so that data corresponding to the write voltage is stored in the ferroelectric field effect transistor.

[0010] According to an embodiment of the present disclosure, in response to a read voltage applied to the gate electrode, the stored data is read from the ferroelectric field effect transistor according to a threshold voltage exhibited by the ferroelectric field effect transistor.

[0011] According to an embodiment of the present disclosure, each ferroelectric layer comprises hafnium oxide or hafnium zirconium oxide.

[0012] According to an embodiment of the present disclosure, a first ferroelectric layer and a second ferroelectric layer in the plurality of ferroelectric layers have different concentrations of a doping element and / or different thicknesses to achieve different coercive fields.

[0013] According to an embodiment of the present disclosure, the doping element comprises at least one of Si, Al, Zr, Y, Gd, La or Sr.

[0014] According to an embodiment of the present disclosure, a ferroelectric field effect transistor is provided. The ferroelectric field effect transistor comprises a plurality of ferroelectric layers having different coercive fields from each other, and the coercive field difference between the ferroelectric layers is utilized so that the polarization states of the ferroelectric layers can have a plurality of combinations, so that the ferroelectric field effect transistor has a plurality of storage states, and thus multi-value storage of the transistor is realized. BRIEF DESCRIPTION OF DRAWINGS

[0015] The above content of the present disclosure and other purposes, features and advantages will be more apparent through the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0016] Figure 1 A structural schematic diagram of a ferroelectric field effect transistor is shown;

[0017] Figure 2 A structural schematic diagram of a ferroelectric field effect transistor according to an embodiment of the present disclosure is shown;

[0018] Figures 3-6 Schematic diagrams of storage states of a ferroelectric field effect transistor according to an embodiment of the present disclosure are shown, respectively;

[0019] Figure 7 A threshold voltage distribution diagram of a ferroelectric field effect transistor according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0020] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to specific examples and with reference to the drawings.

[0021] The endpoints of the ranges and any values disclosed herein are intended to be inclusive of that precise value and are also intended to be inclusive of values approximately or reasonably close to that precise value. For numeric values, the endpoints of each range, the endpoints of each range and individual point values, and individual point values can be combined with each other to generate one or more new numeric ranges, which should be considered as specifically disclosed herein.

[0022] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to be limiting of the present disclosure. As used herein, the term "including" "comprising" and the like are meant to be inclusive and mean that there are no exclusive, additional or further elements, steps, operations, and / or components. Additionally, terms such as "first", "second", and the like can be used herein to describe various elements, but do not connote an ordering, unless specifically stated.

[0023] All terms used herein including technical and scientific terms have the meanings commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein are not intended to limit the present disclosure, which are to be interpreted as having a meaning that is consistent with the context of the specification. The terminology used herein should be interpreted as having a meaning that is consistent with the context of the specification.

[0024] In the description of the present disclosure, it should be understood that the terms "longitudinal", "length", "circumferential", "front", "back", "left", "right", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the present disclosure and simplify the description, and therefore cannot be understood as indicating or implying that the subsystems or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present disclosure.

[0025] Similarly, in order to simplify the present disclosure and help understand one or more of the various disclosed aspects, in the above description of exemplary embodiments of the present disclosure, various features of the present disclosure are sometimes grouped together in a single embodiment, figure or description thereof. The description referring to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with that embodiment or example are included in at least one embodiment or example of the present disclosure. The illustrative expressions of the above terms in the specification do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0026] Ferroelectric material is a material with spontaneous polarization and high dielectric constant. The polarization state of the ferroelectric material can be reversed under the action of an external electric field, and can remain in this polarization state without continuous power supply. In addition, the ferroelectric material has fast read-write speed, excellent durability and low power consumption, so it is considered as one of the important components of non-volatile memory devices. Ferroelectric field effect transistor (FeFET) is a semiconductor device designed based on the spontaneous polarization characteristics of ferroelectric material, so as to realize the non-volatile storage performance of the device.

[0027] Figure 1 A structure diagram of a ferroelectric field effect transistor is shown.

[0028] As shown in Figure 1 , the ferroelectric field effect transistor can include an active region on a substrate, and a ferroelectric layer and a gate electrode on the active region. The active region can include source / drain and a channel between the source / drain. When an external electric field is applied on the gate electrode and the external electric field is greater than the coercive field of the ferroelectric layer, the polarization state of the ferroelectric material will be reversed. When the ferroelectric layer has a polarization state facing the channel (as shown in Figure 1 , the polarization direction is downward), it corresponds to the logic state "1"; when the ferroelectric layer has a polarization state facing away from the channel (as shown in Figure 1 , the polarization direction is upward), it corresponds to the logic state "0". The threshold voltage of the transistor in the two logic states is different, which can represent the two storage states. However, the ferroelectric material is only in a stable state when the polarization direction is upward or downward, and the intermediate polarization state is unstable. When multi-value storage is performed, the threshold voltage is easily disturbed, which reduces the reliability of multi-value storage data.

[0029] Therefore, embodiments of the present disclosure provide a ferroelectric field effect transistor. The ferroelectric field effect transistor includes a plurality of ferroelectric layers with different coercive fields from each other. The coercive field difference between the ferroelectric layers is used to make the ferroelectric field effect transistor have a plurality of storage states, thereby realizing multi-value storage of the transistor. The plurality of threshold voltages of the ferroelectric field effect transistor can be determined by adjusting the coercive fields and thicknesses of the plurality of ferroelectric layers.

[0030] Figure 2 A structure diagram of a ferroelectric field effect transistor according to an embodiment of the present disclosure is shown.

[0031] As shown in Figure 2 , the ferroelectric field effect transistor of the embodiments of the present disclosure can include an active region 1, a ferroelectric stack structure 2 on the active region 1, and a gate electrode 3 on the ferroelectric stack structure 2. The ferroelectric stack structure can include a plurality of ferroelectric layers with different coercive fields from each other (as shown in Figure 1 a1,..., an The ferroelectric field effect transistor can be configured to achieve multi-value storage based on the polarization states of the plurality of ferroelectric layers.

[0032] In some embodiments, the active region 1 can include a channel providing a carrier (e.g., electron) transport path, and source / drain electrodes on opposite sides of the channel, etc. The active region 1 can include a semiconductor material such as polysilicon, etc. Each ferroelectric layer can include a ferroelectric material such as hafnium oxide (HfO2) or hafnium zirconium oxide (Hf x Zr 1-x O2, referred to as HZO, etc. Hafnium zirconium oxide is a solid solution oxide composed of Hf and Zr, which can be Hf 0.5 Zr 0.5 O2, etc.

[0033] According to embodiments of the present disclosure, a ferroelectric field effect transistor is provided. The ferroelectric field effect transistor includes a plurality of ferroelectric layers having different coercive fields from each other. The coercive field difference between the ferroelectric layers allows the polarization states of the ferroelectric layers to have multiple combinations, so that the ferroelectric field effect transistor has multiple storage states, thereby realizing multi-value storage of the transistor.

[0034] Continuing to refer to Figure 2 , the ferroelectric stack structure 2 includes n ferroelectric layers, and the ferroelectric field effect transistor can have 2 n storage states, where n is a positive integer greater than or equal to 2. According to embodiments of the present disclosure, different ferroelectric materials generally have different coercive fields, and the polarization state of a ferroelectric material does not flip under an electric field intensity less than the coercive field, and the polarization state flips under an electric field intensity greater than or equal to the coercive field. The two polarization states of a ferroelectric material, upward or downward, are stable storage states of the ferroelectric material, and the n ferroelectric layers of the ferroelectric stack structure 2 can each have a stable polarization state upward or downward, so that the ferroelectric stack structure 2 can have 2 n storage states, thereby realizing multi-value storage of the device.

[0035] Figures 3-6 The schematic diagrams of the storage states of the ferroelectric field effect transistor according to embodiments of the present disclosure are shown respectively. It needs to be explained that, Figures 3-6 the schematic diagrams of the storage states of the ferroelectric stack structure including two ferroelectric layers, the ferroelectric stack structure of the present disclosure can include a plurality of ferroelectric layers having different coercive fields, which will not be described here.

[0036] As Figures 3-6As shown, the ferroelectric stacked structure 2 may include a first ferroelectric layer a1 and a second electric layer a2. Depending on the polarization states of the first ferroelectric layer a1 and the second electric layer a2, the storage states of the ferroelectric stacked structure may include: both the first ferroelectric layer a1 and the second ferroelectric layer a2 having a polarization state oriented towards the active region (e.g., ...). Figure 3 As shown); both the first ferroelectric layer a1 and the second ferroelectric layer a2 have polarization states facing away from the active region (as shown). Figure 4 As shown); the first ferroelectric layer a1 has a polarization state facing the active region while the second ferroelectric layer a2 has a polarization state away from the active region (as shown). Figure 5 As shown); and the first ferroelectric layer a1 has a polarization state facing away from the active region while the second ferroelectric layer a2 has a polarization state facing the active region (as shown). Figure 6 (As shown).

[0037] According to embodiments of this disclosure, the first ferroelectric layer a1 and the second ferroelectric layer a2 have different coercive fields. Under the action of an external electric field, they can have different polarization states. Ferroelectric layers in different polarization states can correspond to different storage states, thereby realizing multi-value storage of the device.

[0038] In some embodiments, the ferroelectric stack structure 2 may comprise n ferroelectric layers, where n is a positive integer greater than or equal to 2. The ferroelectric field-effect transistor can exist in multiple storage states and may have multiple threshold voltages V. The multiple threshold voltages V may depend on the coercive field E and thickness d of each of the multiple ferroelectric layers. The threshold voltage V of the ferroelectric field-effect transistor may be V0±E1d1±E2d2±…±E… n d n Where V0 is the flat-band voltage of the ferroelectric field-effect transistor, and E1, E2, ..., E n Let d1, d2, ..., d be the coercive fields of each of the n ferroelectric layers. n Let n be the thickness of each of the n ferroelectric layers. For example, when the polarization state of the first ferroelectric layer a1 is downward and the polarization state of the second ferroelectric layer a2 is upward, the threshold voltage V of the ferroelectric field-effect transistor can be V0 + E1d1 - E2d2; or when the polarization state of the first ferroelectric layer a1 is upward and the polarization state of the second ferroelectric layer a2 is upward, the threshold voltage V of the ferroelectric field-effect transistor can be V0 - E1d1 - E2d2.

[0039] Figure 7 A threshold voltage distribution diagram of a ferroelectric field-effect transistor according to an embodiment of the present disclosure is shown. Figure 7 The threshold voltage distribution diagram is shown for a ferroelectric field-effect transistor with two ferroelectric layers (first ferroelectric layer a1 and second ferroelectric layer a2). The threshold voltage distribution diagrams of other ferroelectric field-effect transistors with multiple ferroelectric layers will not be described here.

[0040] like Figure 7 As shown, the threshold voltage V of a ferroelectric field-effect transistor can be V0±E1d1±E2d2, that is, it can be expressed as V0-E1d1-E2d2, V0+E1d1-E2d2, V0-E1d1+E2d2, and V0+E1d1+E2d2. Where V0 is the flat-band voltage of the ferroelectric field-effect transistor, E1 is the coercive field of the first ferroelectric layer a1, E2 is the coercive field of the second ferroelectric layer a2, d1 is the thickness of the first ferroelectric layer a1, and d2 is the thickness of the second ferroelectric layer a2. Figure 7 The distribution diagram of the threshold voltage V in the ferroelectric field-effect transistor is shown. The ferroelectric field-effect transistor has four storage states ("00", "01", "10" and "11" respectively).

[0041] According to embodiments of this disclosure, the coercive field of a ferroelectric material is the energy barrier that must be overcome to reverse the domain reversal within the ferroelectric material, and can be expressed as a driving voltage per unit thickness. The product of the coercive field and the thickness of the ferroelectric material can characterize the voltage required to drive polarization reversal in the ferroelectric material; therefore, the threshold voltage of a ferroelectric field-effect transistor can depend on the coercive field and thickness of the ferroelectric layer. In the case of a ferroelectric field-effect transistor having multiple ferroelectric layers, it can have multiple threshold voltages, thereby characterizing multiple storage states.

[0042] In some embodiments, in response to a write voltage applied to the gate electrode 3, the polarization states of the multiple ferroelectric layers can be independently flipped or not flipped depending on the magnitude of the write voltage relative to a plurality of threshold voltages, thereby storing data corresponding to the write voltage in the ferroelectric field-effect transistor. For example, refer to Figures 3-7 A ferroelectric field-effect transistor comprising two ferroelectric layers can cause the first ferroelectric layer a1 and the second ferroelectric layer a2 to flip or not flip depending on the magnitude of the write voltage relative to multiple threshold voltages (V0-E1d1-E2d2, V0+E1d1-E2d2, V0-E1d1+E2d2, and V0+E1d1+E2d2), i.e., different ranges within which the write voltage falls under the threshold voltage distribution. The combinations of polarization states of the first ferroelectric layer a1 and the second ferroelectric layer a2 correspond to different storage states, thereby storing corresponding data in the ferroelectric field-effect transistor.

[0043] According to embodiments of this disclosure, a ferroelectric field-effect transistor includes multiple ferroelectric layers and has multiple storage states, with each ferroelectric layer requiring a different driving voltage to undergo polarization reversal. When a write voltage is applied to the gate electrode, whether the polarization state of each ferroelectric layer reverses or not is determined based on the relative magnitude of the write voltage and multiple threshold voltages, thereby enabling the storage of data corresponding to the write voltage and achieving multi-value storage.

[0044] According to an embodiment of the present disclosure, in response to a read voltage applied to the gate electrode, the stored data can be read from the ferroelectric field effect transistor according to a threshold voltage exhibited by the ferroelectric field effect transistor. The read voltage is applied to the gate electrode, and the read voltage is lower than a voltage required for the polarization of the ferroelectric layer to be reversed, and does not cause the polarization of the ferroelectric layer to be reversed. The current stored data can be read according to the exhibited threshold voltage.

[0045] According to an embodiment of the present disclosure, the read operation of the ferroelectric field effect transistor does not require the polarization of the ferroelectric layer to be reversed at a high voltage, reduces material fatigue caused by repeated polarization reversal of the ferroelectric material, and can prolong the service life of the device.

[0046] In some embodiments, the first ferroelectric layer a1 and the second ferroelectric layer a2 in the plurality of ferroelectric layers can have different concentrations of doping elements and / or different thicknesses to achieve different coercive fields. The doping elements can include at least one of Si, Al, Zr, Y, Gd, La, or Sr.

[0047] According to an embodiment of the present disclosure, the coercive field of the ferroelectric layer can be regulated by the concentration of the doping elements and / or the thickness of the ferroelectric layer, and a plurality of ferroelectric layers having different coercive fields from each other can be achieved, thereby being applied to the multi-value storage field of the non-volatile memory device.

[0048] Those skilled in the art can understand that the features described in various embodiments of the present disclosure can be combined and / or integrated in various combinations, even if such combinations or integrations are not explicitly described in the present disclosure. In particular, the features described in various embodiments of the present disclosure can be combined and / or integrated in various combinations without departing from the spirit and teachings of the present disclosure. All such combinations and / or integrations fall within the scope of the present disclosure.

[0049] The embodiments of the present disclosure are described above. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be advantageously combined for use. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims

1. A ferroelectric field-effect transistor, characterized in that, include: Active region; The ferroelectric stacked structure on the active region comprises multiple ferroelectric layers with different coercive fields. as well as The gate electrode on the ferroelectric stacked structure; The ferroelectric field-effect transistor is configured to achieve multi-value storage based on the polarization states of the plurality of ferroelectric layers.

2. The ferroelectric field-effect transistor according to claim 1, characterized in that, The ferroelectric stacked structure comprises n ferroelectric layers, and the ferroelectric field-effect transistor has 2 n There are several storage states, where n is a positive integer greater than or equal to 2.

3. The ferroelectric field-effect transistor according to claim 2, characterized in that, The ferroelectric stacked structure includes a first ferroelectric layer and a second electric layer; The storage state includes: Both the first ferroelectric layer and the second ferroelectric layer have a polarization state oriented toward the active region; Both the first ferroelectric layer and the second ferroelectric layer have a polarization state that is opposite to the active region; The first ferroelectric layer has a polarization state facing the active region, while the second ferroelectric layer has a polarization state away from the active region; and The first ferroelectric layer has a polarization state facing away from the active region, while the second ferroelectric layer has a polarization state facing the active region.

4. The ferroelectric field-effect transistor according to claim 1, characterized in that, The ferroelectric field-effect transistor has multiple threshold voltages, which depend on the coercivity and thickness of each of the multiple ferroelectric layers.

5. The ferroelectric field-effect transistor according to claim 4, characterized in that, The ferroelectric stacked structure comprises n ferroelectric layers, where n is a positive integer greater than or equal to 2, and the threshold voltage of the ferroelectric field-effect transistor is V0±E1d1±E2d2±···±E n d n Where V0 is the flat-band voltage of the ferroelectric field-effect transistor, and E1, E2, ..., E n Let d1, d2, ..., d be the coercive fields of the n ferroelectric layers respectively. n Let be the thickness of each of the n ferroelectric layers.

6. The ferroelectric field-effect transistor according to claim 4, characterized in that, In response to a write voltage applied to the gate electrode, the polarization states of the plurality of ferroelectric layers independently flip or do not flip depending on the magnitude of the write voltage relative to the plurality of threshold voltages, thereby storing data corresponding to the write voltage in the ferroelectric field-effect transistor.

7. The ferroelectric field-effect transistor according to claim 4, characterized in that, In response to the read voltage applied to the gate electrode, the stored data is read from the ferroelectric field-effect transistor according to the threshold voltage exhibited by the ferroelectric field-effect transistor.

8. The ferroelectric field-effect transistor according to any one of claims 1 to 5, characterized in that, Each of the ferroelectric layers comprises hafnium oxide or hafnium zirconium oxide.

9. The ferroelectric field-effect transistor according to any one of claims 1 to 5, characterized in that, The first ferroelectric layer and the second ferroelectric layer in the plurality of ferroelectric layers have different concentrations of doping elements and / or different thicknesses to achieve different coercive fields.

10. The ferroelectric field-effect transistor according to claim 9, characterized in that, The doping element includes at least one of Si, Al, Zr, Y, Gd, La or Sr.

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