Power semiconductor device and method of manufacturing power semiconductor device

Abstract

A method of manufacturing a power semiconductor device includes: providing a semiconductor body having a front side with a substantially horizontal region above both an active region and an edge termination region (1-3) of the semiconductor body; forming (20), at the front side (110), a first insulating layer (11) over both the active region (1-1) and the edge termination region (1-3); forming (20) a first mask layer (12) at the first insulating layer (11), wherein the first mask layer (12) at least partially covers the edge termination region (1-3) and exposes the active region (1-1); and removing (22) a portion of the first insulating layer (11) covering the active region (1-1); when the first mask layer (12) or the modified first mask layer (12) or another mask layer (13) covers the edge termination region (1-3), the edge termination region (1-3) is subjected (24) to a first implantation process step to form one or more doped semiconductor regions (1-31) in the edge termination region (1-3).

Description

TECHNICAL FIELD

[0001] The present specification relates to embodiments of power semiconductor devices and embodiments of methods of manufacturing power semiconductor devices. Some embodiments presented herein relate to integration of high voltage termination structures with silicon oxide and variable lateral doping, VLD, regions. BACKGROUND

[0002] Many functions of modern devices in automotive, consumer and industrial applications, such as converting electrical energy and driving electric motors or machines, rely on power semiconductor devices. For example, just to name a few, insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs) and diodes have been used in various applications, including but not limited to switching in power supplies and power converters.

[0003] Power semiconductor devices comprise a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device. The load current is conducted by means of an active region of the power semiconductor device. The active region is surrounded by an edge termination region, which is terminated by an edge of the chip.

[0004] Thus, high voltage devices can require a definition of the active region and the edge termination region, which can also need to be aligned with each other. In some implementations, the edge termination is chosen to exhibit a VLD (lateral doping variation) configuration for reliability reasons. In the area of the edge termination region, the surface of the semiconductor body can also have a termination structure, for example based on thermal oxidation, for example due to low density of interface charges and traps.

[0005] The present specification presents techniques related to low cost manufacturing methods of edge termination regions of power semiconductor devices. SUMMARY

[0006] The subject matter of the independent claims is presented. Features of exemplary embodiments are defined in the dependent claims.

[0007] According to one embodiment, a method of manufacturing a power semiconductor device comprises: providing a semiconductor body, wherein the semiconductor body has a front side with a substantially horizontal area over both an active region and an edge termination region of the semiconductor body; forming a first insulating layer over the front side, over both the active region and the edge termination region; forming a first masking layer at the first insulating layer, wherein the first masking layer at least partially covers the edge termination region and exposes the active region; and removing a portion of the first insulating layer covering the active region; subjecting the edge termination region to a first implantation process step to form one or more doped semiconductor regions in the edge termination region, when the first masking layer or a modified first masking layer or another masking layer covers the edge termination region.

[0008] According to another embodiment, a power semiconductor device is presented, wherein the power semiconductor device has been manufactured according to the method described in the preceding paragraph.

[0009] According to a further embodiment, a power semiconductor device comprises: a semiconductor body, wherein the semiconductor body has a front side with a substantially horizontal area above both an active region and an edge termination region of the semiconductor body; a first insulating layer above the edge termination region, wherein the first insulating layer is a thermal oxide in contact with the front side and has a thickness in the range of 50 nm to 500 nm; and a laterally doped varying, VLD, region below the front side in the edge termination region.

[0010] According to yet a further embodiment, a power semiconductor device comprises: a semiconductor body, wherein the semiconductor body has a front side with a substantially horizontal area above both an active region and an edge termination region of the semiconductor body; a first insulating layer above the edge termination region and in contact with the front side; and a doped semiconductor region below the front side in the edge termination region, wherein the doped semiconductor region exhibits a dopant concentration profile along a vertical direction according to which: the dopant concentration of the front side has an initial value N A_0 ; the dopant concentration reaches a maximum value N MAX larger than the initial value N A_0 at a first vertical distance Z A_MAX from the front side; the dopant concentration continuously decreases along the vertical direction after the first vertical distance Z MAX and re-achieves the initial value N MED at a second vertical distance Z A_0 from the front side; and (N A_MAX -N A_0 ) / N A_MAX is not larger than 1 / 3.

[0011] Those skilled in the art will realize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0012] Portions of the figures herein can be illustrated by way of example, not limitation, in which like references indicate similar elements. In fact, because the various embodiments of the application can be implemented in any of numerous ways, the application is not limited to the examples described herein. In addition, there are numerous variations and modifications of the application that are encompassed by the present disclosure, and the specific embodiments described herein are provided for the purposes of illustration only. Figures 1-3 A method of manufacturing a power semiconductor device according to some embodiments is schematically and exemplarily illustrated based on a segment of a vertical cross-section of the power semiconductor device being manufactured; Figure 4 A dopant concentration profile in a power semiconductor device according to one or more embodiments is schematically and exemplarily illustrated; and Figure 5A section of a vertical cross-section of a power semiconductor device according to one or more embodiments is schematically and exemplarily illustrated. DETAILED DESCRIPTION

[0013] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown, by way of illustration, specific embodiments in which the application can be practiced.

[0014] In this respect, directional terms such as "top," "bottom," "upper," "lower," "above," "below," and the like can be used with reference to the orientation of the figures being described. Because components of embodiments can be positioned in a number of orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present application. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present application is defined by the appended claims.

[0015] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation of the application and is not meant as a restriction of the application. For example, features illustrated or described as part of one embodiment can be used with another embodiment to yield still a further embodiment. It is intended that the present application include such modifications and variations. The particular language used in the specification is not intended to limit the scope of the application. The figures are not drawn to scale and are merely used to illustrate the concepts. For the purpose of clarity, not every component is called out in the figures, but the same numbers are used in different figures to refer to the same or similar components.

[0016] The term "horizontal" as used in this specification is intended to describe an orientation that is generally parallel to a horizontal surface of a semiconductor substrate or semiconductor structure. This can for example be a surface of a semiconductor wafer or die or chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below can be horizontal directions, wherein the first lateral direction X and the second lateral direction Y can be perpendicular to each other.

[0017] The term "vertical" as used in this specification is intended to describe an orientation that is generally arranged perpendicular to a horizontal surface, i.e. parallel to a normal direction of a surface of a semiconductor wafer / chip / die. For example, the extension direction Z mentioned below can be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y. The extension direction Z is also referred to herein as "vertical direction Z".

[0018] The first conductivity type is opposite to the second conductivity type. In the present specification, n-doping is referred to as the "first conductivity type", while p-doping is referred to as the "second conductivity type". Alternatively, the opposite doping relationship can be employed, such that the first conductivity type can be p-doped, and the second conductivity type can be n-doped. A dopant dose can be defined as the integral of the dopant concentration of atoms of the respective conductivity type within the respective doped region in the vertical direction Z. The dopant dose can be the amount of dopant implanted per unit area.

[0019] In the context of the present specification, the terms "in ohmic contact", "in electrical contact", "in ohmic connection" and "electrically connected" are intended to describe the presence of a low-ohmic electrical connection or low-ohmic current path between two regions, segments, areas, parts or components of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode of a semiconductor device and a part or component, wherein "low-ohmic" can mean that the properties of the respective contact are substantially not influenced by ohmic resistances. Further, in the context of the present specification, the term "in contact" is intended to describe the presence of a direct physical connection between two elements of a respective power semiconductor device; for example, the transition between two elements in contact with each other can not include further intermediate elements, and / or the like.

[0020] Further, in the context of the present specification, the term "electrically insulated" is used in its generally reasonable understanding and is thus intended to describe that two or more components are positioned separately from each other and that no ohmic connection connecting those components is present. However, components that are electrically insulated from each other can nevertheless be coupled to each other, for example mechanically and / or capacitively and / or inductively and / or electrostatically coupled (for example, in the case of a junction). To give an example, two electrodes of a capacitor can be electrically insulated from each other and at the same time mechanically and capacitively coupled to each other, for example by means of an insulating portion, for example a dielectric.

[0021] The specific embodiments described in the present specification relate to, but are not limited to, power semiconductor devices that can be used in a power converter or power supply. Thus, in one embodiment, such a power semiconductor device can be configured to carry a load current to be fed to a load and / or a load current provided by a power supply, respectively. For example, the power semiconductor device can comprise one or more active power semiconductor cells, for example monolithically integrated diode cells, derivatives of monolithically integrated diode cells, monolithically integrated transistor cells, for example monolithically integrated IGBT or MOSFET cells and / or derivatives thereof. Such diode / transistor cells can be integrated within a single chip. A plurality of such cells can constitute a cell field arranged within an active region of the power semiconductor device.

[0022] The term "blocking state" in the context of power semiconductor devices can refer to the state in which the power semiconductor is configured to block the flow of load current when an external voltage is applied. More specifically, a power semiconductor device can be configured to prevent forward load current from flowing through it when a forward bias voltage is applied. In contrast, a power semiconductor device can be configured to conduct forward load current in its "forward conduction state" when a forward bias voltage is applied. The transition between the forward blocking state and the forward conduction state can be controlled by a control electrode, or more specifically, by the potential of the control electrode. Of course, these electrical characteristics can only be applied within a predetermined operating range of the external voltage and the current density within the power semiconductor device. Therefore, the term "forward bias blocking state" can refer to the state in which the power semiconductor device is in a forward blocking state when a forward bias voltage is applied.

[0023] As used in this specification, the term "power semiconductor device" is intended to describe a power semiconductor device on a single chip that has high voltage blocking and / or high current carrying capacity. In other words, depending on the application, such a power semiconductor device is intended for high current, typically in the range of a few amperes, such as up to tens or hundreds of amperes, and / or high voltage, typically above 100V, more typically 300V and above, such as up to at least 600V or even higher, such as up to at least 1.2kV, or even up to 6kV or higher.

[0024] For example, the term "power semiconductor device" as used in this specification does not refer to a logic semiconductor device used for, for example, storing data, computing data, and / or other types of semiconductor-based data processing.

[0025] For example, the power semiconductor device described below can be a single semiconductor chip and can be configured to be used as a power component in low, medium and / or high voltage applications.

[0026] Figures 1 to 3 A method for manufacturing a power semiconductor device 1 according to some embodiments is illustrated schematically and exemplaryly based on a segment of a vertical cross-section of the power semiconductor device being manufactured.

[0027] The method includes stage 20 (see Figure 1 The semiconductor body 10 is provided in the ( ). For example, the semiconductor body 10 is based on silicon (Si).

[0028] like Figure 1 As shown, the semiconductor body 10 has a front side 110, which has a region that is substantially horizontal above both the active region 1-1 and the edge termination region 1-3 of the semiconductor body 10.

[0029] The method also includes phase 20 (see Figure 1In the process, at the front side 110, a first insulating layer 11 is formed above both the active region 1-1 and the edge termination region 1-3. For example, the first insulating layer 11 is based on an oxide. The first insulating layer 11 can be formed by performing an oxidation process and / or a deposition process.

[0030] The method also includes phase 20 (see Figure 1 In the first insulating layer 11, a first mask layer 12 is formed. The first mask layer 12 at least partially covers the edge termination regions 1-3 and, for example, at least partially or completely exposes the active region 1-1. For example, the first mask layer 12 defines a lateral transition between the edge termination regions 1-3 and the active region 1-2.

[0031] The method also includes phase 22 (see Figure 2A In this process, a portion of the first insulating layer 11 covering the active region (1-1) is removed. In one embodiment, during stage 22 (see...), Figure 2B The first mask layer 12 is also removed and / or modified and / or replaced with another mask layer 13.

[0032] The method also includes phase 24 (see Figure 3 In the process, after the first mask layer 12 or a modified first mask layer 12 or another mask layer 13 is opened above the edge termination region 1-3, the edge termination region 1-3 is subjected at least partially to the first injection processing step (marked by "I"). 2 (indicated by the thick arrow) to form one or more doped semiconductor regions 1-31 in the edge termination regions 1-3.

[0033] For example, the first injection process step can be performed using an injection energy of less than 500 keV, less than 200 keV, or even less than 100 keV. The actual injection energy can be selected based on the thickness t of the first insulating layer 11.

[0034] For example, a first implantation process is performed to form laterally doped VLD regions 1-31 below the front side 110 and in the edge termination regions 1-3. For example, the method includes modifying the first mask layer 12 by forming a plurality of openings 1213 in the first mask layer 12 to obtain a modified first mask layer 12, wherein the openings 1213 correspond to the desired laterally doped VLD regions 1-31. The laterally doped VLD regions 1-31 can then be formed during the first implantation process. Alternatively, instead of modifying the first mask layer 12, the mask layer 12 can be replaced by another layer 13 that presents the openings 1213 corresponding to the desired laterally doped VLD regions 1-31. After the first implantation process, a diffusion process can be performed to obtain continuous VLD regions 1-31.

[0035] Following the diffusion process, VLD regions 1-31 can exhibit a continuous function of the doping concentration in the semiconductor body 10, such as a linear gradient, starting at the interface with the active region 1-1 where the doping concentration has the highest value. The doping concentration decreases towards the outer edge of the edge-terminating region 1-2, and may eventually result in a doping concentration that is substantially no increase compared to the background doping of the semiconductor body 10. While the doping concentration of VLD regions 1-31 at the interface with the active region 1-1 is high enough not to be completely depleted by the space charge region in the electrostatic barrier operation, the space charge region in the electrostatic barrier operation will reach the interface between the semiconductor body 10 and the first insulating layer 11 at the outer portion of VLD regions 1-31. Along the path from the active region 1-1 to the outer edge termination, the doping in VLD regions 1-31 can have one or more regions of constant concentration (e.g., at the interface with the active region 1-1) and one or more steep steps of doping concentration, such as at the outer edge of VLD regions 1-31. Because the diffusion process may not be sufficient to fully distribute the implanted dopant atoms, a moving average of the dopant concentration can be formed, the lateral width of which is, for example, 3 or 5 times the depth of the VLD regions 1-31 in the semiconductor body 10, resulting in the average dopant concentration within the VLD regions 1-31 as described above.

[0036] In one embodiment, VLD regions 1-31 can present a junction-terminated-extended (JTE) configuration. While VLD regions 1-31 show a gradient in doping concentration, the doping concentration can gradually decrease at the JTE edge termination and remain substantially constant within a step. Furthermore, at the JTE edge termination, it can start from a doping concentration that is too high to be fully depleted by the space charge region and has one or more additional doping concentration steps with doping concentrations that can be fully depleted.

[0037] Still refer to Figure 3 As shown in stage 24, the method may further include forming another mask layer 14 to at least partially cover the active region 1-1 before performing the first injection processing step. This ensures that the active region 1-1 is not subjected to the first injection processing step. In another embodiment, the active region 1-1 may also be subjected to the first injection processing step, for example, while simultaneously being covered with a structured mask.

[0038] For example, refer to Figure 1In stage 20, as exemplarily illustrated, the first insulating layer 11 comprises or is composed of thermally grown oxide. For example, the formation of the first insulating layer 11 does not include a deposition process step. For example, the semiconductor body 10 is based on silicon (Si), and the first insulating layer 11 is thermally grown silicon oxide (SiO2). During the thermal growth of SiO2, some of the initially available semiconductor material of the semiconductor body 10 is consumed, resulting in a step at the front side 110 of the semiconductor body 10. Therefore, the insulating layer 11 can be partially buried beneath the original extension of the front side 110.

[0039] For example, refer to Figure 1 In stage 20, as exemplarily shown, prior to the formation of the first mask layer 12 at the first insulating layer 11, the thickness t of the first insulating layer 11 is in the range of 50 nm to 500 nm. Furthermore, in one embodiment, the thickness t of the first insulating layer 11 is substantially constant over its total horizontal extension (along the first and second lateral directions X and Y).

[0040] Furthermore, in one embodiment, the edge termination regions 1-3 are subjected to (see...) during the execution. Figure 3 In step 24) of the first implantation process, a first insulating layer 11 is present. The first insulating layer 11 may be configured to mask dopant ions implanted at an implantation energy of 10 keV or less.

[0041] In one embodiment, the first insulating layer 11 may be arranged to adjoin the front side 110 of the semiconductor body 10, or correspondingly not penetrate the semiconductor body 10. For example, the first insulating layer 11 may be arranged so as not to extend further along the vertical direction Z as the front side 110 formed by the portion of the semiconductor body 10 in the active region 1-1. Of course, this optional provision takes into account that the first insulating layer 11 may be based on a thermal growth process, according to which the front side 110 of the original semiconductor body 10 undergoes an oxidation process.

[0042] refer to Figure 2A and 2B In one embodiment, the method may further include subjecting the active region (1-1) to a second injection processing step (see stage 22) after removing (see stage 22) the portion of the first insulating layer 11 covering the active region (1-1). 2 (indicated by the thick arrow) to form one or more doped semiconductor regions 1-11 in the active region 1-1.

[0043] The second injection processing step can be executed after the first injection processing step. Alternatively, the second injection processing step can be executed before the first injection processing step.

[0044] Depending on how the first insulating layer removal step is performed and / or how the first mask layer 12 is modified, removed, or replaced, a small gap g may remain between one or more doped semiconductor regions 1-11 and the first insulating layer 11 (see [link to documentation]). Figure 2A Alternatively, a small lateral overlap may be formed between one or more doped semiconductor regions 1-11 and the first insulating layer 11 (see [reference]). Figure 2B In any case, it can be ensured that one or more doped semiconductor regions 1-11 are at least adjacent to or overlap with VLD regions 1-31 after the diffusion step, such as... Figure 3 and 5 As shown.

[0045] After diffusion, the blocking pn junction in active region 1-1 must be electrically connected to VLD region 1-31. This is possible with only minor over-etching and strong diffusion in the first insulating layer 11. Figure 2A and 2B The final result may be very small and indistinguishable. This is achieved by utilizing the large over-etching of insulating layer 11 and according to... Figure 2A The process, Figure 5 The lateral ends of the doped regions 1-11 may end before reaching the full thickness of the insulating layer 11.

[0046] Before further processing of the device, for example by equipping it with a package, the (modified) first mask layer 12 or another mask layer 13 correspondingly covering the edge termination regions 1-3 can be removed. In addition, the second mask layer 14 can be removed.

[0047] For example, see Figure 5 After mask removal, a passivation layer 15 can be formed over the first insulating layer 11 in the edge termination regions 1-3. For example, the passivation layer 15 includes at least one of inorganic insulating material, silicon nitride, silicon oxide, electroactive material, semi-insulating polycrystalline silicon, diamond-like carbon, DLC, silicon-rich Si3N4, organic insulating material, imide, or silicone resin.

[0048] Still referencing Figure 5 In one embodiment, the method may further include forming a metal layer 1-12 at the semiconductor body 10. For example, the metal layer 1-12 is in direct physical contact with the semiconductor body 10 (e.g., partially or everywhere), wherein a portion of the first insulating layer 11 covering the active regions (1-1) has previously been removed (see [link to documentation]). Figure 1 , 2A(The transition from stage 20 to stage 22 is shown in 2B). For example, metal layers 1-12 form part of the first load terminal of the power semiconductor device 1. For example, metal layers 1-12 are in direct physical contact with the remainder of the first insulating layer 11, such as the portion of the first insulating layer 11 that was not removed during removal stage 22. Overlapping portions of metal layers 1-12 may extend over the first insulating layer 11. Typically, the formation of metal layers 1-12 can be completed after removal stage 22 and after processing in stage 24.

[0049] This document also presents a power semiconductor device 1, which has been manufactured according to the method of one of the foregoing embodiments.

[0050] For example, a power semiconductor device includes a semiconductor body 10 having a front side having a substantially horizontal region above both the active region and the edge-termination region of the semiconductor body; a first insulating layer above the edge-termination region, wherein the first insulating layer is a thermally grown oxide in contact with the front side and has a thickness in the range of 50 nm to 500 nm; and a laterally doped VLD region below the front side in the edge-termination region. An embodiment of this power semiconductor device corresponds to an embodiment of the method described above. Therefore, regarding embodiments of the power semiconductor device, see above.

[0051] According to another embodiment, the power semiconductor device includes a semiconductor body having a front side having a substantially horizontal region above both an active region and an edge-termination region of the semiconductor body; a first insulating layer located above the edge-termination region and in contact with the front side; and a doped semiconductor region below the front side in the edge-termination region, wherein the doped semiconductor region exhibits a dopant concentration distribution along a vertical direction, according to which the dopant concentration of the front side has an initial value N. A_0 The dopant concentration is at the first vertical distance Z from the front side. MAX The value reaches a value greater than the initial value N. A_0 The maximum value N A_MAX The dopant concentration at the first vertical distance Z MAX Then it continues to decrease vertically, and at the second vertical distance Z from the front side MED The initial value N is reached again. A_0 ; and (N) A_MAX -N A_0 ) / N A_MAX No more than 1 / 3.

[0052] Regarding the above embodiments of power semiconductor device 1, refer to Figure 4 The diagram schematically and exemplaryly illustrates the dopant concentration distribution in a power semiconductor device 1 according to one or more embodiments. The horizontal axis represents the dopant concentration N in VLD regions 1-31.A Size (in any unit, e.g., 1 / cm) 3 The vertical axis shows the horizontal direction along the vertical direction Z (in arbitrary units, such as μm).

[0053] Therefore, in the embodiment, the dopant concentration at the front side 110 below the first insulating layer 11 has an initial value N. A_0 Along the vertical direction Z, the dopant concentration is at a first vertical distance Z from the front side of 110. MAX The maximum value N is reached at this point. A_MAX (It is greater than the initial value N) A_0 Then, the dopant concentration is determined at the first vertical distance Z. MAX Then it continues to decrease along the vertical direction Z, and at a second vertical distance Z 110 from the front side MED The initial value N is reached again. A_0 .

[0054] In one embodiment, the dopant concentration distribution exhibits another maximum value, which may be greater than or less than the maximum value N. A_MAX .

[0055] For example, the above embodiments of power semiconductor devices may present a MOSFET configuration, an IGBT configuration, or a configuration derived from a MOSFET configuration or an IGBT configuration.

[0056] The above text explains embodiments of power semiconductor devices and corresponding manufacturing methods.

[0057] For example, these power semiconductor devices are based on silicon (Si). Therefore, a single-crystal semiconductor region or layer, such as the semiconductor body and its regions / areas, such as multiple regions, can be a single-crystal Si region or Si layer. In other embodiments, polycrystalline silicon or amorphous silicon can be used.

[0058] However, it should be understood that the semiconductor body and its regions can be made of any semiconductor material suitable for manufacturing semiconductor devices. Examples of such materials include, but are not limited to, the following: elemental semiconductor materials, such as silicon (Si) or germanium (Ge); group IV compound semiconductor materials, such as silicon carbide (SiC) or silicon germanium (SiGe); binary, ternary, or quaternary III-V semiconductor materials, such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or gallium arsenide indium phosphide (InGaAsP); and binary or ternary II-VI semiconductor materials, to name just a few, such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe). The semiconductor materials mentioned above are also referred to as "homogeneous junction semiconductor materials." When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, the following: aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For power semiconductor switching applications, Si, SiC, GaAs, and GaN materials are currently the primary materials used.

[0059] For ease of description, spatial relative terms such as "below," "below," "lower part," "above," "upper part," etc., are used to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the corresponding devices other than those depicted in the figures. Furthermore, terms such as "first," "second," etc., are also used to describe various elements, sections, segments, etc., and are not intended to be limiting. Throughout this description, the same terms may refer to the same elements.

Claims

1. A method for manufacturing a power semiconductor device (1), comprising: - Provide (20) a semiconductor body (10), wherein the semiconductor body (10) has a front side (110) having a region at a substantially horizontal level above both the active region (1-1) and the edge termination region (1-3) of the semiconductor body (10); - At the front side (110), a first insulating layer (20) is formed above both the active region (1-1) and the edge termination region (1-3); - A first mask layer (12) is formed (20) at the first insulating layer (11), wherein the first mask layer (12) at least partially covers the edge termination region (1-3) and exposes the active region (1-1); and -Remove (22) a portion of the first insulating layer (11) covering the active region (1-1); - When the first mask layer (12) or the modified first mask layer (12) or another mask layer (13) covers the edge termination region (1-3), the edge termination region (1-3) is subjected to the first implantation process step (24) to form one or more doped semiconductor regions (1-31) in the edge termination region (1-3).

2. The method according to claim 1, wherein, The first insulating layer (11) comprises or is composed of thermally grown oxides.

3. The method according to claim 1 or 2, wherein, Before forming the first mask layer (12) at the first insulating layer (11), the thickness (t) of the first insulating layer (11) is in the range of 50 nm to 500 nm.

4. The method according to claim 3, wherein, The thickness (t) of the first insulating layer (11) is substantially constant within the total horizontal extension of the first insulating layer (11).

5. The method according to claim 3 or 4, wherein, When performing the step of subjecting the edge termination region (1-3) to the first injection process step (24), the thickness (t) of the first insulating layer (11) is present.

6. The method according to any one of the preceding claims, wherein, The first insulating layer (11) is configured to mask doped ions implanted at an implantation energy of less than 10 keV.

7. The method according to any one of the preceding claims, wherein, The first insulating layer (11) is adjacent to the front side (110) of the semiconductor body (10), or correspondingly does not penetrate the semiconductor body (10).

8. The method according to any one of the preceding claims, wherein the semiconductor body (10) is based on silicon (Si), and wherein the first insulating layer (11) is thermally grown silicon oxide (SiO2).

9. The method according to any one of the preceding claims further comprises subjecting the active region (1-1) to a second implantation process (22) after removing (22) a portion of the first insulating layer (11) covering the active region (1-1) to form one or more doped semiconductor regions (1-11) in the active region (1-1).

10. The method according to any one of the preceding claims, wherein, The first injection process is performed with an injection energy of less than 500 keV.

11. The method according to any one of the preceding claims, wherein, Perform a first implantation process to form a laterally doped VLD region (1-31) below the front side (110) in the edge termination region (1-3).

12. The method of claim 11, further comprising: - A modified first mask layer (12) is obtained by modifying the first mask layer (12) by forming a plurality of openings (1213) in the first mask layer (12), wherein the openings (1213) correspond to the expected lateral doping variation VLD regions (1-31); and - A transversely doped VLD region is formed during the first implantation process (1-31).

13. The method according to any one of the preceding claims, wherein, Before performing the first injection process step, another mask layer (14) is formed to at least partially cover the active region (1-1).

14. The method according to any one of the preceding claims further includes removing the first mask layer (12), modifying the first mask layer (12), or correspondingly the other mask layer (13).

15. The method according to any one of the preceding claims, wherein, The first mask layer (12) defines the lateral transition between the edge termination region (1-3) and the active region (1-2).

16. The method according to any one of the preceding claims further includes forming a passivation layer (15) over the first insulating layer (11) in the edge termination region (1-3).

17. The method according to claim 16, wherein the passivation layer (15) comprises at least one of inorganic insulating material, silicon nitride, silicon oxide, electroactive material, semi-insulating polycrystalline silicon, diamond-like carbon, DLC, silicon-rich Si3N4, organic insulating material, imide or silicone resin.

18. The method according to any one of the preceding claims further includes forming a metal layer (1-12) on the semiconductor body (10), wherein the metal layer (1-12) is in direct physical contact with the semiconductor body (10), wherein a portion of the first insulating layer (11) covering the active region (1-1) is pre-removed (22).

19. The method according to claim 18, wherein, The metal layer (1-12) is in direct physical contact with the remainder of the first insulating layer (11).

20. A power semiconductor device (1), wherein the power semiconductor device (1) is manufactured according to the method of any one of the preceding claims.

21. A power semiconductor device (1), comprising: - Semiconductor body (10), wherein the semiconductor body (10) has a front side (110) having a region that is substantially horizontal above both the active region (1-1) and the edge termination region (1-3) of the semiconductor body (10); - A first insulating layer (11) above the edge termination region (1-3), wherein the first insulating layer (11) is a thermally grown oxide that is in contact with the front side (110) and has a thickness (t) in the range of 50 nm to 500 nm. and - Below the front side (110) in the edge termination region (1-3), there is a lateral doping variation VLD region (1-31).

22. A power semiconductor device (1), comprising: - Semiconductor body (10), wherein the semiconductor body (10) has a front side (110) having a region that is substantially horizontal above both the active region (1-1) and the edge termination region (1-3) of the semiconductor body (10); - A first insulating layer (11) is located above the edge termination region (1-3) and in contact with the front side (110); and - Below the front side (110) of the edge termination region (1-3), there is a doped semiconductor region (1-31), wherein the doped semiconductor region exhibits a dopant concentration distribution along the vertical direction (Z), according to which: The dopant concentration at the front side (110) has an initial value (N). A_0 ); The dopant concentration is at the first vertical distance (Z) from the front side (110). MAX The value at point N is greater than the initial value. A_0 The maximum value of (N) A_MAX ); dopant concentration at the first vertical distance (Z) MAX Then it continues to decrease along the vertical direction (Z), and at the second vertical distance (Z) from the front side (110) MED The initial value (N) is reached again at point ) A_0 );and ο(N A_MAX -N A_0 ) / N A_MAX No more than 1 / 3.

23. The power semiconductor device (1) according to any one of claims 17 to 19, wherein, The power semiconductor device (1) is one of a diode, a MOSTFET or an IGBT, or a derivative of one of the aforementioned devices.

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