SiC power device with low on-resistance and low thermal resistance and preparation process

Abstract

The invention relates to the technical field of semiconductors, in particular to a SiC power device with low on resistance and low thermal resistance and a preparation process. Comprising an N + substrate and an N-epitaxial layer which are sequentially arranged from bottom to top; the N-epitaxial layer is provided with a plurality of JFET (Junction Field Effect Transistor) regions which respectively extend downwards from the top surface of the N-epitaxial layer, and the downward extending depth of the JFET regions is smaller than the thickness of the N-epitaxial layer; the plurality of P type base regions are respectively connected with the JFET region; the P + region is positioned at the side part of the P-type base region, and the depth of the P + region is equal to that of the P-type base region; the N + regions extend downwards from the top surface of the P-type base region, and the depth of the N + regions extending downwards is smaller than that of the P-type base region; the resistance and the thermal resistance of the whole substrate layer can be remarkably reduced, so that the on resistance of the silicon carbide power device is reduced, the heat dissipation performance is improved, and the energy efficiency and the reliability of the device are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a SiC power device with low on-resistance and low thermal resistance and a preparation process thereof. BACKGROUND

[0002] Compared with silicon material, silicon carbide (SiC) material exhibits many advantages, such as the energy band width of 4H-SiC is 3 times of silicon, which leads to a much lower intrinsic carrier concentration at any given temperature and a much smaller collision ionization coefficient at any given electric field, so that at the same doping concentration, the breakdown voltage of 4H-SiC is about 56.2 times of silicon; and the thermal conductivity of 4H-SiC is 2-3 times of silicon, so that it has excellent performance of extracting heat from the device. These characteristics of silicon carbide are particularly suitable for the manufacture of power semiconductor devices.

[0003] However, in the actual preparation process of SiC substrate material (PVT, HTCVD or LPE long crystal method), crystal defects (interstitial atoms, Si vacancies, C vacancies, doping atoms, dislocations, grain boundaries, stacking faults, inclusions, etc.) will inevitably exist, and at the same time, in order to maximize the reduction of its resistance, the substrate is generally heavily doped. Since the thermal conductivity of SiC material is mainly affected by phonon transfer, the thermal resistance is mainly caused by the scattering effect caused by various substances in the phonon transfer process. These defects and impurities cause the scattering of phonons, further reduce the mean free path, and reduce the thermal conductivity. The thermal conductivity of heavily doped 4H-SiC substrate decreases from a theoretical value of 490 W / m·K to a range of 100 to 150 W / m·K, and as the working temperature of the power device increases, the lattice vibration becomes more intense, the collision between phonons becomes more frequent, and the heat transfer efficiency becomes lower. Therefore, in the high temperature range (usually 400K-700K) of normal operation of SiC power devices, the thermal conductivity decreases with the increase of temperature, and further decreases to below 100 W / m·K, so its thermal conductivity and thermal stability are far inferior to those of copper, silver and other metal materials.

[0004] In the preparation process of SiC semiconductor power devices, impurity doping needs to be achieved through multiple ion implantation and thermal activation processes. In the thermal activation stage, the impurities directly below the diffusion window of the mask plate mainly migrate in the vertical direction, and finally form a parallel plane junction; while in the edge area of the diffusion window, the impurities will not only move vertically downward, but also horizontally diffuse under the mask layer, so that a cylindrical junction area (C area) is formed at the straight edge of the window, and a spherical junction area (S area) is formed at the four corners of the rectangular window (as shown in Figure 10As shown in the figure, the red rectangular line represents the injection region. Due to the existence of the junction bending effect of the cylindrical and spherical junction region, the electric field distribution of the region will appear significant concentration: taking 4H-SiC material as an example, the electric field strength of such bending junction region will generally be enhanced to 2.5-3.5 MV / m (much higher than the electric field level of the planar junction region). The excessive concentration of the electric field will cause the breakdown voltage of these regions to be much lower than that of the planar junction region, becoming the “weak point” of the device, ultimately greatly reducing the overall breakdown voltage of the SiC power device, and being one of the key factors restricting its high-voltage characteristics.

[0005] At present, with the increasing emphasis on energy saving and emission reduction in the world in recent years, new energy vehicles have gradually become one of the future directions of automobile development. As an important part of them, electric vehicles have attracted great attention and attention in today's society. However, there is still a problem hindering electric vehicles, which is the endurance mileage. The short endurance mileage not only limits the range and time of people using electric vehicles, but also limits the sales and promotion of electric vehicles. It puts forward higher requirements for the power consumption control and efficiency improvement of semiconductor power devices in electric vehicles, and reducing the on-resistance of semiconductor power devices is an important means to reduce the power consumption of electric vehicles. The on-resistance of power devices mainly comes from metal contact resistance, drift region resistance, substrate resistance, etc. In silicon carbide power devices below 1700V, the substrate resistance accounts for a large proportion. The traditional technical means to reduce the substrate resistance is the substrate thinning technology, but for the preparation of silicon carbide power devices, the substrate thinning process is much more difficult. On the one hand, compared with traditional silicon materials, silicon carbide materials have much higher hardness, close to diamond hardness, and at the same time, because they are brittle materials, the thinner the thickness, the greater the processing fragility, and the greater the wafer warping. On the other hand, the thinning process is completed before the ohmic contact, but for the preparation of silicon carbide devices, high-temperature annealing is required to form the ohmic contact, which means that many processes in the device manufacturing process are carried out in a thin sheet state, greatly increasing the possibility of fragmentation. Therefore, it is very difficult to complete the silicon carbide substrate thinning process with ordinary process lines.

[0006] Furthermore, all semiconductor devices have limited size, and devices are packaged by cutting wafers into chips. Using a diamond blade or laser ablation to cut the wafer, this process can cause serious damage to the lattice. For power devices, if the cutting passes through the PN junction that bears high voltage, lattice damage can cause a large leakage current, resulting in a decrease in breakdown voltage and long-term reliability.

[0007] Therefore, under the existing size specification requirements, how to design a power device that reduces the substrate resistance and thermal resistance while reducing the failure risk caused by junction edge breakdown and ultimately enhances the working reliability is a technical problem that the present invention needs to solve. SUMMARY

[0008] The present application aims at the above problems, and provides a SiC power device with low on-resistance and low thermal resistance and a preparation process, which can reduce the risk of failure caused by junction edge breakdown, reduce the substrate resistance and thermal resistance, and enhance the working reliability of the device.

[0009] The technical scheme of the present application is: A SiC power device with low on-resistance and low thermal resistance comprises an N+ substrate and an N- epitaxial layer arranged in sequence from bottom to top. The N- epitaxial layer is provided with: A plurality of JFET regions, each extending downward from the top surface of the N- epitaxial layer, and the depth of the JFET region extending downward is less than the thickness of the N- epitaxial layer; A plurality of P-type base regions, each connected with the JFET region; A P+ region located at the side of the P-type base region and having a depth equal to that of the P-type base region; A plurality of N+ regions, each extending downward from the top surface of the P-type base region, and the depth of the N+ region extending downward is less than that of the P-type base region; A plurality of floating field rings, each extending downward from the top surface of the N- epitaxial layer; and the lateral width of each floating field ring increases from the device end to the middle part; An N+ channel stop region located at the side of the floating field ring and extending downward from the top surface of the N- epitaxial layer; Field oxide arranged on the top surface of the P+ region, N- epitaxial layer, floating field ring and N+ channel stop region; Gate oxide arranged on the top surface of the JFET region, P-type base region, N+ region and P+ region; A plurality of polysilicon gates, each arranged on the top surface of the corresponding gate oxide; A plurality of dielectric layers, each arranged on the top of the gate oxide and covering the polysilicon gate; A plurality of front ohmic contact metal layers, each arranged on the top surface of the N+ region and P+ region and connected with the gate oxide and dielectric layer on the side; Gate traces arranged in the dielectric layer and connected with the field oxide; Gate pads arranged on the top surface of the gate traces and extending out of the dielectric layer; Source pads arranged on the top surface of the dielectric layer and front ohmic contact metal layer; A passivation layer arranged on the dielectric layer and connected with the gate pads and source pads; A polyimide insulating protective layer arranged on the top surface of the passivation layer and connected with the gate pads and source pads; The N+ substrate bottom is provided with a plurality of bottom hollow grooves; the grooves are located within the projected area of the front ohmic contact metal layer, that is, the transverse cross-sectional width of the grooves is not greater than the transverse cross-sectional width of the front ohmic contact metal layer; The N+ substrate bottom and the grooves are provided with a back metal layer.

[0010] Specifically, the grooves extend towards the top surface of the N+ substrate; the distance between the groove bottom and the top surface of the N+ substrate is 5-20 um.

[0011] Specifically, the depth to which the grooves extend is less than the thickness of the N+ substrate.

[0012] Specifically, the passivation layer is not less than two layers, including a BPSG layer and a silicon nitride layer arranged in sequence from bottom to top.

[0013] Specifically, the back metal layer includes a back ohmic contact layer and a back gold surface layer.

[0014] A preparation process of a SiC power device with low on-resistance and low thermal resistance, comprising the following steps: Step 1: substrate preparation and epitaxial layer growth; Step 2: JFET region, P-type base region, N+ region and P+ region preparation; Step 3: injection region thermal activation and damage layer removal; Step 4: terminal field oxide layer preparation; Step 5: gate structure preparation; Step 6: lead hole making and front pad electrode preparation; Step 7: passivation layer preparation; Step 8: polyimide insulating protective layer preparation; Step 9: substrate back groove preparation and drain pad preparation In order to further reduce the substrate resistance and thermal resistance, improve the device breakdown voltage and working reliability, a substrate back groove preparation process is added, and the specific steps are as follows: S9.1, back mask layer making After cleaning and pretreating the back surface of the thinned and polished substrate, removing the surface impurities and oxide layer, a uniform back mask layer is prepared; S9.2, dry etching to form grooves Through etching process, the preset opening area of the back mask layer is etched; The active region mask layer opening area is aligned with the front ohmic contact metal layer pattern, and the opening projected area is within the projection of the front ohmic contact metal layer pattern; After the mask layer opening etching is completed, the substrate back opening area is etched to form grooves; S9.3, metal layer deposition to prepare back ohmic contact layer and drain pad: Through metal layer deposition, annealing and subsequent processing, the preparation of back ohmic contact layer and drain pad is completed, and at the same time the removal of the bonding material is realized, the on-resistance and thermal resistance are reduced, and the device conduction performance, heat dissipation efficiency and working reliability are improved; the specific process is as follows: 9.31, back ohmic contact layer deposition; A layer of metal material is uniformly deposited on the opening area and the entire back surface of the substrate by sputtering or evaporation process; 9.32, laser annealing to form ohmic contact to form back ohmic contact layer; 9.33, back gold surface layer deposition The back gold surface layer is deposited on the surface of the back ohmic contact layer by sputtering, evaporation or electrochemical deposition process.

[0015] Specifically, the JFET region preparation step in step 2 includes: Using silicon carbide epitaxial layer as substrate, photoresist as mask layer, and through photoetching technology to complete JFET region patterning definition; the implantation dose is less than 10 15 cm -2 , under room temperature conditions, different energy and different dose of nitrogen element is implanted in steps to form JFET region with concentration gradient distribution; after implantation, the photoresist mask layer is removed by dry stripping and wet etching process.

[0016] Specifically, the P-type base region preparation step in step 2 includes: On the surface of the JFET implantation region, P-type base region implantation window pattern is made by photoetching technology, and aluminum element is implanted in steps with different energy under high temperature condition of 400℃-700℃ to form P-type base region with concentration gradient distribution; after implantation, the mask layer is removed.

[0017] Specifically, the N+ region preparation step in step 2 includes: Cover the oxide mask on the surface of the P-type base region, and complete the N+ region implantation pattern definition by photoetching technology; under high temperature condition of 400℃-700℃, nitrogen element is implanted in steps with different energy to form N+ region with concentration gradient distribution.

[0018] Specifically, the P + + region and terminal P + floating field ring synchronous preparation step includes: Cover the oxide and polysilicon mask on the surface of the device, and make P+ region implantation pattern by photoetching technology; under high temperature condition of 400℃-700℃, aluminum element is implanted in steps with different energy to form P + + region with concentration gradient distribution; The implantation pattern of the floating field ring has been integrated into the P + In the lithography pattern of the P + The implantation of the P + The doping concentration of the P 16 ~1×10 18 cm -3

[0019] The present application provides a silicon carbide MOS power device structure, comprising a bottom trench substrate, an epitaxial layer, a gate oxide layer, a polysilicon gate, an insulating layer, a Source Pad, a Gate Pad, a Drain Pad, a gradually changing width floating field ring formed at the edge of the device, and a back trench position of the substrate consistent with the position of the front ohmic contact metal layer; wherein the projected area of the back trench position of the substrate is not greater than the projected area of the front ohmic contact metal layer, which can avoid the application of strong electric field at the P-type base zone cylindrical or spherical junction position, ensure that there is no electric field line congestion phenomenon in the JFET and other weak voltage resistance areas, so as to not affect the breakdown voltage of the silicon carbide power device.

[0020] The present structure has a gradually changing floating field ring around the active area, which improves the voltage resistance of the silicon carbide device through the floating field ring. The farther away from the active area, the smaller the lateral cross section, and therefore the lower the electric field strength in this area, which is consistent with the expansion trend of the device edge depletion layer, thereby improving the voltage resistance and reliability of the device edge. The present structure has a plurality of trenches in the substrate layer, and the back ohmic contact metal layer formed on the surface of the trench can provide a more optimal current path, heat dissipation path and heat dissipation area for the device. The effective thickness of the silicon carbide substrate layer resistance is only the thickness between the trench bottom and the epitaxial layer, which significantly reduces the resistance and thermal resistance of the entire substrate layer, thereby reducing the on-resistance and improving the heat dissipation of the silicon carbide power device, and improving the energy efficiency and reliability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 is a JFET region preparation structure schematic diagram; Figure 2 is a P-type base region preparation structure schematic diagram; Figure 3 is a N+ region and terminal channel cutoff ring synchronous preparation structure schematic diagram; Figure 4 is a P+ region and terminal P+ floating field ring synchronous preparation structure schematic diagram; Figure 5 is a terminal field oxide layer preparation structure schematic diagram; Figure 6 is a gate structure preparation structure schematic diagram; Figure 7 is a lead hole manufacturing and front Pad electrode preparation structure schematic diagram; ​Figure 8 is a schematic diagram of a preparation structure of a passivation layer and a polyimide insulating protective layer; Figure 9 is a schematic diagram of a preparation structure of a substrate back trench and a drain pad; Figure 10 is a schematic diagram of a background technical solution. DETAILED DESCRIPTION

[0022] Embodiments of the present application will be described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numbers represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application, and cannot be understood as a limitation of the present application.

[0023] In the description of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0024] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0025] Reference will now be made to Figures 1-9 described according to an embodiment of the present application; A preparation process of a SiC power device with low on-resistance and low thermal resistance comprises the following steps: Embodiment 1: This embodiment takes N-channel enhancement type planar SiC MOS as an example: Step 1: Substrate preparation and epitaxial layer growth A silicon carbide substrate is provided, the substrate is an N-type silicon carbide single crystal substrate, and the substrate has a substrate front surface and a substrate back surface arranged opposite to each other. An N-epitaxial layer is grown on the N+ silicon carbide substrate front surface, and the doping concentration and thickness of the N-epitaxial layer are adjusted according to the breakdown voltage requirement of the device design.

[0026] Step 2: Multi-region ion implantation and mask layer preparation S2.1 First, an alignment marker layer is fabricated on the epitaxial layer using photolithography and etching processes.

[0027] S2.2, using a silicon carbide epitaxial layer as the implantation target, the JFET region, P-type base region, and N-type epitaxial region are sequentially fabricated. + District and P + District. Specifically: JFET region fabrication (e.g.) Figure 1 (as shown) Using a silicon carbide epitaxial layer as a substrate and photoresist as a mask layer, the JFET region is patterned and defined using photolithography; due to the implantation dose being less than 10... 15 cm -2 At room temperature, nitrogen elements are implanted stepwise with different energies and dosages to form a JFET region with a concentration gradient distribution. After implantation, the photoresist mask layer is removed by dry stripping and wet etching processes.

[0028] Preparation of base regions (e.g.) Figure 2 (as shown) An oxide and polysilicon mask is coated on the surface of the epitaxial layer. A P-type base region implantation window pattern is fabricated using photolithography. Aluminum is implanted in a stepwise manner with different energies at high temperatures of 400℃-700℃ to form a P-type base region with a concentration gradient distribution. After implantation, the mask layer is removed.

[0029] Simultaneous fabrication of the zone and terminal channel stop ring (e.g.) Figure 3 (as shown) An oxide mask is covered on the surface of the epitaxial layer, and the N+ region implantation pattern is defined by photolithography. Nitrogen elements are implanted in steps with different energies under high temperature conditions of 400℃-700℃ to form N+ regions with a concentration gradient distribution.

[0030] The terminal channel cutoff ring (or N+ channel cutoff region) is implanted simultaneously at this level. As a region with extremely high doping concentration, it is almost never depleted, thus physically "terminating" the formation of parasitic channels and blocking this leakage path. It can also serve as an effective "electric field termination point," confining the depletion region of the main junction to a safe area inside the chip and preventing the electric field from accumulating at the fragile chip edges. After implantation, the mask layer is removed.

[0031] + District and terminal P + Simultaneous preparation of floating field rings (e.g.) Figure 4 (as shown) An oxide and polysilicon mask are coated on the surface of the epitaxial layer, and a P+ region (including the P+ contact region within the P-type base region and the device edge termination region) implantation pattern is fabricated using photolithography. Aluminum is implanted in stages at different energies under high temperature conditions of 400℃-700℃ to form a P+ region with a concentration gradient. + district.

[0032] To avoid electric field congestion in the power device termination region, a gradient width design is preferred: from the active region towards the device termination, P + The width of the floating field ring gradually decreases, and its design principle is: P + The smaller the opening width of the floating field ring, the lower the effective doping concentration in that region (the region of implantation and thermal activation diffusion after implantation) after thermal activation. Therefore, after implantation and thermal activation of the P+ floating field ring region, a gradual concentration distribution is generated in the device terminal region (by controlling the size of the mask opening, the larger the opening, the higher the effective doping concentration; since the initial concentration and diffusion degree are different in different regions, the final junction depth is also gradual, usually becoming shallower from the active region to the edge). Because the floating field ring is closer to the main junction (the PN junction formed by the active region, P-type base region, and drift region), the electric field strength at the edge of its depletion layer (the depletion layer refers to the depletion layer formed when the PN junction is reverse-biased; the edge refers to the position of the cylindrical or spherical junction) is greater, and the donor charge concentration in the space charge region of the cylindrical or spherical junction is higher. This requires neutralization with a higher concentration of acceptor charge (aluminum ions) to prevent premature device breakdown at this location. After implantation, the mask layer is removed.

[0033] Floating field ring and P + Regional process collaboration: The injection pattern of the floating field ring has been integrated into the above P. + In the area lithography pattern, with P + The injection process is completed simultaneously in the P+ region, eliminating the need for additional mask layer preparation, photolithography, and injection steps. This simplifies the process while ensuring the precise alignment of the floating field ring and the P+ region. + The aluminum ion implantation energy and dose in the zone and the floating field ring are individually controlled to ensure that the floating field ring forms a preset doping concentration (typically 1×10⁻⁶). 16 ~1×10 18 cm -3 It combines depth with concentration gradient distribution through multi-energy injection to match the electric field gradient requirements.

[0034] Preferably, the device edge adopts a floating field ring design, and the number of floating field rings n≥3; the width of the floating field rings decreases outward from the edge of the active region (P-type base region); the spacing between each floating field ring can be consistent or a gradient design can be adopted to increase the number of floating field rings, but its minimum size is limited by the photolithography capability.

[0035] The number of floating field rings satisfies n≥3. The width of the floating field rings decreases sequentially from the edge of the active region outwards (e.g., the width of the inner protective ring is 3~5μm, the width of the adjacent outer protective ring decreases by 0.5~1μm, and the width of the outermost protective ring is not less than 1μm). The spacing between each protective ring is set according to the device withstand voltage requirements, generally 2~4μm. Preferably, to save device area and maximize breakdown voltage within a limited termination region, the key parameters of the floating field ring need to be designed according to the following optimization scheme: 1) Total width matching: The total lateral width of multiple floating field rings must be equal to the width of the depletion layer when the main junction parallel plane junction breaks down; 2) Depletion layer width calculation (4H-SiC system): The maximum depletion layer width corresponding to the breakdown voltage is calculated using the following formula: W pp =1.82*10 11 N D -7 / 8 Among them, W pp For the maximum depletion layer width, N D The doping concentration in the drift region; 3) Spacing design: The spacing between the floating field ring and the main junction, as well as the spacing between each guard ring, are all set to 2Dt, where D is the diffusion coefficient of the dopant element and t is the diffusion time during the thermal activation process; 4) Single ring width design: The width L of the nth floating field ring n Satisfy the following formula: L n =N d *(W) pp / n)²*π / 4 / D0 Where, N d This represents the doping concentration of the drift layer, expressed in ions / cm³. D0 is P + Zone doping concentration, in ions / cm³ 2 .

[0036] Step 3: Thermal activation of the injection area and removal of the damaged layer After completing all ion implantation of N - A carbon film is uniformly coated on the surface of the epitaxial layer, with the thickness of the carbon film ensuring complete coverage of the implanted region. This carbon film is used to prevent the volatilization of silicon atoms on the silicon carbide surface during thermal activation. The substrate covered with the carbon film is placed in a high-temperature annealing furnace for high-temperature thermal activation treatment. The thermal activation temperature is 1600~1900℃, and the holding time is 10~60min, which allows the implanted dopant elements to be fully activated and form the desired electrical region.

[0037] After thermal activation, the carbon film is oxidized and removed using a high-temperature oxidation process, and the damaged layer generated during ion implantation and high-temperature activation is sacrificially oxidized. Subsequently, the sacrificial oxide layer is removed by a wet etching process using hydrofluoric acid etching solution, restoring the crystal integrity of the silicon carbide surface.

[0038] Step 4: Preparation of the terminal field oxygen layer (e.g.) Figure 5 (as shown) After removing the damaged layer, the device surface is cleaned. A 0.5–3 μm thick oxide layer is grown on the device surface using one or a combination of ALD, LPCVD, or PECVD processes. The oxide layer is then densified by high-temperature reflow at 900–1200 °C. Active regions are then created using photolithography and etching processes, forming field oxide in the P+ region, the N- epitaxial layer, multiple floating field rings, and the top of the N+ channel cutoff region.

[0039] Its working mechanism is as follows: When a high voltage is applied to the PN junction, the depletion region expands, and the electric field lines terminate densely on the semiconductor surface. Since εair≈1 < εSiC≈9.7, according to the boundary conditions of electrodynamics, the electric field lines "do not like" entering the air, resulting in a large number of electric field lines crowding at the tips or regions with small radii of curvature on the semiconductor surface, causing electric field concentration; while εox≈3.9 > εair≈1, it effectively suppresses the electric field concentration on the termination surface through the physical mechanism of dielectric voltage division and smoothing the electric field, guiding the breakdown point to the semiconductor bulk (bulk breakdown), thereby maximizing the breakdown voltage potential of the material itself and significantly improving the blocking voltage and reliability of the device.

[0040] Step 5: Gate structure fabrication (e.g.) Figure 6 (as shown) The device surface after the terminal field oxygen is completed is cleaned, and a gate oxide layer is grown on the device surface using a high-temperature thermal oxidation process. The thickness of the oxide layer is adjusted according to the electrical requirements of the device, such as threshold voltage and withstand voltage.

[0041] The gate oxide layer is annealed at a temperature of 900~1350℃ for a holding time of 10~60min to improve the density and interface properties of the oxide layer.

[0042] A layer of doped polysilicon gate with a thickness of about 500 nm is grown in situ on the gate oxide layer using chemical vapor deposition to form a low-resistance gate electrode.

[0043] Gate patterns are fabricated using photolithography and etching processes. Optional options include: the active region gate pattern can be any of the following: striped, circular, hexagonal, or atomic array distribution. The pattern design must be compatible with the JFET region, P-type base region, and N-type... + Source region and P +The design patterns of the zones are matched to ensure optimal electrical performance of the devices, and the Gate runner (gate trace, which is subsequently connected to the Gate Pad metal) is formed simultaneously.

[0044] Step 6: Fabrication of lead holes and preparation of front-side Pad electrodes (e.g.) Figure 7 (as shown) On the upper surface of the polysilicon gate, a dielectric layer is deposited using a chemical vapor deposition process. The dielectric layer material is preferably one or a combination of silicon dioxide, silicon nitride, or silicon oxynitride. Subsequently, the dielectric layer undergoes a densification thermal treatment. In this case, there are at least two dielectric layers; taking two layers as an example, they include a BPSG layer and a silicon nitride layer sequentially arranged from bottom to top. Source leads are fabricated on the dielectric layer using photolithography and etching processes. The positions of the source leads correspond to the N+ and P+ regions. Preferably, the projected area of ​​the leads is smaller than the combined projected area of ​​the N+ and P+ regions. Then, a 100-500 nm Ni metal layer is deposited inside the leads and on the surface of the dielectric layer using a sputtering process, followed by a first rapid annealing at 400-700°C to form Ni. x Si y The alloy compound, with unreacted Ni on the dielectric layer surface removed using Piranha etching solution, is followed by a second rapid annealing at 800-1000°C to form a low-resistance front-side ohmic contact metal layer. The lateral cross-sectional width of the front-side ohmic contact metal layer is equal to the lateral cross-sectional width of the lead hole. Figure 7 As shown.

[0045] Next, through photolithography and etching processes, gate leads are fabricated by creating windows in the dielectric layer. The positions of the leads correspond to the polysilicon gate wiring areas. Using sputtering, evaporation, or chemical vapor deposition processes, a 3-5 μm metal layer is deposited inside the leads and on the surface of the dielectric layer. The preferred metal layer materials are Ti / TiN / AlCu, Ta / TaN / W, Ta / TaN / Cu stacks, or combinations thereof. Then, through photolithography and etching processes, the corresponding Gate Pads and Source Pads are fabricated.

[0046] High-temperature furnace tube annealing or rapid annealing processes are used to perform alloy annealing on the metal layer material to reduce contact resistance, enhance adhesion, and improve the quality of the metal film.

[0047] Step 7: Preparation of passivation layer and polyimide insulating protective layer (e.g.) Figure 8 (as shown) A passivation layer is grown on the device surface using one or a combination of ALD, LPCVD, or PECVD processes. The passivation layer material is one or a combination of silicon oxide, silicon nitride, aluminum oxide, and silicon oxynitride. Through photolithography and development processes, source pad and gate pad windows for packaging are formed on the passivation layer, while the remaining surfaces remain fully covered by the passivation layer.

[0048] Next, a 5-10 μm polyimide insulating protective layer is spin-coated onto the entire surface of the device to ensure coverage of all electrode and dielectric layer areas.

[0049] Through photolithography and development processes, source pad and gate pad windows for packaging are created on the polyimide insulating protective layer, while the remaining surface remains fully covered by polyimide. This design significantly improves the insulation performance of the high-voltage operating area after device packaging, avoids insulation breakdown under high voltage, and ensures device reliability.

[0050] Step 8: Substrate back trench fabrication and drain pad fabrication (e.g.) Figure 9 (as shown) Before fabricating the back trenches and drain pads on the substrate, pretreatment of the substrate is necessary to ensure the accuracy of subsequent processes and device performance. The pretreatment stage can employ bonding processes, using wax bonding of quartz glass or sapphire to protect the front side of the substrate. Alternatively, a thinning process can be used to control the substrate thickness to 100-150 μm, while chemical mechanical polishing can be combined to polish the back side of the substrate, improving its flatness. To further reduce substrate resistance and thermal resistance, and improve device breakdown voltage and operational reliability, a back trench fabrication process is added, with the specific steps as follows: S9.1 Back Mask Layer Fabrication The back side of the thinned and polished substrate is cleaned and pretreated to remove surface impurities and oxide layers, and a uniform back mask layer is then prepared. The mask layer material can be one of Ti / ITO, Ni, Al, or oxides, with Ti / ITO composite layers being preferred—because the ITO component does not react with fluorine ions and exhibits excellent chemical and structural stability under high plasma energy environments, effectively ensuring the accuracy of subsequent etching processes.

[0051] Dry etching to form trenches Leveraging the ability of infrared light to penetrate glass and SiC, an infrared alignment process is employed to achieve high-precision alignment of the alignment marks on the back and front sides of the substrate, ensuring that the trench positions match the front device structure. After photolithography, the pre-defined opening areas of the back mask layer are etched using either ICP (Inductively Coupled Plasma Etching) or RIE (Reactive Ion Etching) dry etching processes.

[0052] The opening area of ​​the back mask layer is consistent with the P-type base region pattern in the front active region, and its projected area falls entirely within the projection range of the P-type base region pattern, avoiding exceeding the area and affecting the performance of the device termination region. The preferred solution is to align the opening area of ​​the active region mask layer with the front lead hole (CT) pattern, and ensure that the projected area of ​​the opening is completely within the projection of the lead hole pattern. Since the CT is usually designed only inside the active region, this solution can achieve the sharing of a single photomask with the CT layer, significantly reducing manufacturing costs.

[0053] After the mask layer openings are etched, the Bosch process is used for dry etching to create trenches in the mask layer opening areas on the back side of the substrate. The etching gas is preferably one or a combination of SF6, CF4, NF3, BF3, and CHF3, while the passivation gas is one or more of C4F8, C4F6, CHF3, C2H2, and CH4. Ar and O2 are used as auxiliary and conditioning gases, respectively. By optimizing the gas ratio, the etching rate and trench profile can be precisely controlled.

[0054] The etching depth is controlled within the range of 0 ≤ aperture depth < substrate thickness, and must not exceed the interface between the substrate and the drift layer to avoid reducing the device's breakdown voltage capability. Preferably, the distance d from the bottom of the trench to the epitaxial layer is 5-20 μm. On the one hand, to reduce on-resistance and thermal resistance, d should be as small as possible; however, on the other hand, if d is too small, the metal end subsequently filled in the trench will be too close to the depletion layer height electric field region in the epitaxial layer. The introduced metal equipotential boundary conditions will distort the uniform distribution of the electric field, forcing the surrounding electric field lines to converge and bend on its surface, ultimately leading to a sharp increase in local electric field intensity. Electric field concentration will induce slow charge trapping or material degradation, reducing the device's avalanche breakdown voltage capability and long-term reliability. To balance the electric field and reliability, d must have a safety margin. Simulation demonstration for SiC power devices <1700V, with an epitaxial concentration of 1.0 × 10¹ 6 cm⁻³, epitaxial thickness 5-20um, controlling d within 5-20um yields the best overall performance.

[0055] After etching, the trench sidewalls form a wavy "scallop" profile. The amplitude of the scallop can be adjusted by modifying the etching / passivation cycle time, gas ratio, pressure, and power. Preferably, in the last cycle of Bosch etching, the etching step is adjusted to an isotropic mode (high etching gas flow rate, zero bias / low bias), using this "isotropic over-etching" step to round the corners. This not only reduces electric field concentration, improves breakdown voltage and device reliability, but also eliminates stress concentration, prevents crack initiation and propagation, enhances mechanical strength and reliability, improves device reliability under thermal stress, and improves the quality and uniformity of metallization coverage and filling processes.

[0056] For silicon carbide MOSFET structures, a high electric field is easily generated within the gate oxide layer (the JFET region beneath the gate oxide) under forward blocking conditions. According to Gauss's law, the electric field of the oxide layer and the electric field of the semiconductor satisfy the following relationship: E 氧化层 =(ε 半导体 / ε 氧化物 E 半导体 , Where E 氧化层 ε represents the electric field strength of the oxide layer. 半导体 ε is the dielectric constant of the semiconductor. 氧化物 E is the dielectric constant of the oxide. 半导体 The electric field strength is that of the semiconductor.

[0057] The electric field strength in the oxide layer is approximately three times that in the semiconductor. For 4H-SiC devices, the breakdown critical value of 3 × 10⁻⁶ is reached. 6 V·cm -1 At that time, the electric field of the oxide layer will exceed 9 × 10 6 V·cm -1 This not only exceeds device reliability limits but can also lead to oxide layer cracking, causing burn-in and breakdown. This invention avoids these problems by optimizing the back trench design: On the one hand, the location of the substrate aperture is consistent with the location of the CT aperture and the projected area falls within the range of the CT aperture. When the body diode is reverse biased, the back aperture area can face the P-type base region at 0V potential (the potential of the P-type base region is anchored through the P+ ohmic contact in the P-type base region), away from the JFET region below the gate oxide layer, the cylindrical or spherical junction at the edge of the P-type base region, the terminal region and other weak locations with low breakdown voltage. This avoids the back aperture area being in a high electric field region and reduces the boundary effect that may cause the weak location to experience electric field enhancement.

[0058] On the other hand, this allows the substrate opening to be located far from the edge of the final chip, preventing the high field strength and the lattice subsurface damage caused by the chip edge during the dicing process from being superimposed together, which would increase the chip leakage current and avoid reliability failure; thus, it can achieve a synergistic effect of reducing substrate resistance and ensuring breakdown voltage.

[0059] S9.3, Metal layer deposition to prepare ohmic contact layer and drain pad: This step involves metal layer deposition, annealing, and subsequent processing to fabricate the ohmic contact layer and drain pad, while simultaneously removing bonding material. The core objective is to reduce contact resistance and thermal resistance, thereby improving device conductivity, heat dissipation efficiency, and operational reliability. The specific process is as follows: 9.31, Ohmic contact layer deposition A back-side ohmic contact layer is uniformly deposited on the opening area and the entire back-side surface of the substrate using sputtering or evaporation processes. The preferred material for the back-side ohmic contact layer is one or more composite systems selected from Ni, Ti, Ni / Ti, Al / Ti, Ti / Al, Ni / Al, Ni / Ti / Al, and Ti / Ni / Al. The thickness is controlled between 10 and 300 nm, and the specific thickness can be adjusted according to the contact resistance requirements of the device and the characteristics of subsequent annealing processes.

[0060] 9.32, Laser annealing forms ohmic contacts The deposited back-side ohmic contact layer is subjected to laser annealing, with the annealing laser energy density strictly controlled between 2 and 10 J / cm². The high temperature causes the back-side ohmic contact layer to form a stable and low-resistance ohmic contact alloy layer with the silicon carbide substrate, significantly reducing interfacial contact resistance and ensuring device current transmission efficiency. Strict temperature uniformity control is necessary during the annealing process to avoid localized overheating that could damage the substrate or cause alloying failure of the metal layer.

[0061] 9.33, Deposition of back gold surface layer (drain pad) A gold backing surface layer is deposited on the surface of the ohmic contact layer using sputtering, evaporation, or electrochemical deposition processes, such as... Figure 9 As shown, this is the drain pad. The back gold surface layer material can be one or more composite combinations of Ti / Ni / Ag, Ti / Ni / Au, Ti / TiN / Cu, Ta / TaN / Cu, Ti / Pt / Au, Ti / TiN / Al, and Ti / TiN / AlCu, with Ag, Cu, and Au being preferred materials with high thermal conductivity. These materials effectively reduce the overall thermal resistance of the device: firstly, the openings on the back of the substrate significantly shorten the effective heat transfer path in the active region of the N-epitaxial layer; secondly, the back gold surface layer material topology shapes the back trench morphology, greatly increasing the contact area between the back gold surface layer material and the SiC substrate material, which helps increase the heat dissipation area and significantly improves heat dissipation efficiency; furthermore, during power device operation, heat from the active region can be efficiently conducted to the pads and heat sink through the high thermal conductivity metal material, thereby directly and effectively reducing the operating junction temperature. In addition, the device structure has low on-resistance, resulting in lower heat generation, significantly improving the device's high-temperature operating stability and long-term reliability.

[0062] It is worth further explaining that the high thermal conductivity metals Ag, Cu, Au, and Al are mainly affected by electronic thermal conductivity. In the range of 200K-800K, the electronic thermal conductivity of the metals tends to be constant. This is because as the temperature rises, the increase in electronic specific heat capacity and the decrease in relaxation time cancel each other out on the effect of electronic thermal conductivity. Moreover, the proportion of phonon thermal conductivity in these materials is relatively small, and the total thermal conductivity remains at a high level as the temperature rises. This is unlike SiC substrate materials, where phonon thermal conductivity is dominant and the total thermal conductivity decreases significantly with increasing temperature. Therefore, the temperature stability of the thermal conductivity of these metal materials is far superior to that of SiC substrate materials, which further improves the high-temperature operating stability and long-term reliability of the devices.

[0063] The way the metal layer fills the opening area on the back side needs to be designed in conjunction with the current capacity requirements of the device: if it is a high current device, the metal layer can be used to completely fill the opening area to improve the current carrying capacity; if it is a conventional current device, only a metal layer needs to be deposited on the surface of the opening area to balance performance and manufacturing cost.

[0064] 9.34, Bonding Material Removal After the gold backing surface layer is deposited, laser lift-off is used for debonding. Then, a specialized cleaning process thoroughly removes the wax bonding material and residual impurities from the front side, ensuring the cleanliness of the substrate front side and preventing residual contaminants from affecting subsequent processes and device performance. After cleaning, the substrate surface is inspected to ensure there is no bonding material residue or surface damage.

[0065] Step 10, Finished Product Processing After completing all the above processes, the device undergoes final cleaning and electrical testing.

[0066] Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A SiC power device that combines low on-resistance and low thermal resistance, characterized in that, It includes an N+ substrate and an N- epitaxial layer arranged sequentially from bottom to top; The N-epipolar layer is provided with: Multiple JFET regions are provided, each extending downward from the top surface of the N-epitaxial layer; The P-type base region is provided in multiple forms, each of which is connected to the JFET region. The P+ region is located on the side of the P-type base region; There are multiple N+ regions, which extend downward from the top of the P-type base region, and the depth of the downward extension of the N+ regions is less than the depth of the P-type base region. Multiple floating field rings are provided, each extending downward from the top surface of the N-epitaxy layer; the lateral width of the multiple floating field rings increases from the end of the device towards the middle. The N+ channel cutoff region is located on the side of the floating field ring and extends downward from the top surface of the N- epitaxial layer; Field oxygen is disposed on the top surface of the P+ region, N-epipolar layer, floating field ring and N+ channel cutoff region; Gate oxide is disposed on the top surface of the JFET region, the P-type base region, the N+ region, and the P+ region; A plurality of polysilicon gates are provided, each located on a corresponding gate oxide top surface; Multiple dielectric layers are provided, each located on top of the gate oxide and covering the polysilicon gate. The front ohmic contact metal layer has multiple layers, which are located on the top surface of the N+ region and the P+ region, and the sides are connected to the gate oxide and the dielectric layer, respectively. The gate trace is located within the dielectric layer and is connected to the field oxygen. A gate pad is disposed on the top surface of the gate trace and extends from the dielectric layer; Source pads are disposed on the top surface of the dielectric layer and the front ohmic contact metal layer; A passivation layer is disposed on the dielectric layer and connected to the gate pad and the source pad; A polyimide insulating protective layer is located on the top surface of the passivation layer and is connected to the gate pad and the source pad; The N+ substrate has multiple bottom-hollowed grooves; The trench is located within the projected area of ​​the front ohmic contact metal layer, that is, the lateral cross-sectional width of the trench is not greater than the lateral cross-sectional width of the front ohmic contact metal layer. The N+ substrate has a back metal layer at the bottom and in the trench.

2. The SiC power device with both low on-resistance and low thermal resistance according to claim 1, characterized in that, The trench extends toward the top surface of the N+ substrate; the distance between the bottom of the trench and the top surface of the N+ substrate is 5-20 μm.

3. The SiC power device with both low on-resistance and low thermal resistance according to claim 1, characterized in that, The trench extends to a depth less than the thickness of the N+ substrate.

4. A SiC power device with both low on-resistance and low thermal resistance according to claim 1, characterized in that, The passivation layer consists of at least two layers, including a BPSG layer and a silicon nitride layer arranged sequentially from bottom to top.

5. A SiC power device with both low on-resistance and low thermal resistance according to claim 1, characterized in that, The back metal layer includes a back ohmic contact layer and a back gold surface layer.

6. A fabrication process for a SiC power device exhibiting both low on-resistance and low thermal resistance, as described in claim 1, characterized in that... Includes the following steps: Step 1: Substrate preparation and epitaxial layer growth; Step 2: Fabrication of JFET region, P-type base region, N+ region and P+ region; Step 3: Thermal activation of the injection area and removal of the damaged layer; Step 4: Preparation of the terminal field oxygen layer; Step 5: Gate structure fabrication; Step 6: Lead hole fabrication and front pad electrode preparation; Step 7: Passivation layer preparation; Step 8: Preparation of polyimide insulating protective layer; Step 9: Substrate back trench fabrication and drain pad fabrication To further reduce substrate resistance and thermal resistance, and improve device breakdown voltage and operational reliability, a substrate back trench fabrication process has been added. The specific steps are as follows: S9.1, Backside Mask Layer Fabrication After thinning and polishing, the back side of the substrate is cleaned and pretreated to remove surface impurities and oxide layers, and a uniform back mask layer is prepared. The pre-defined opening area of ​​the back mask layer is etched using an etching process; Align the opening area of ​​the active region mask layer with the pattern of the front ohmic contact metal layer, and ensure that the projected area of ​​the opening is within the projection of the front ohmic contact metal layer pattern. After the mask layer opening is etched, trench etching is performed on the opening area on the back side of the substrate; S9.3, Metal layer deposition to prepare the back ohmic contact layer and drain pad: The back-side ohmic contact layer and drain pad are fabricated through metal layer deposition, annealing, and subsequent processing, while simultaneously removing bonding material. This reduces on-resistance and thermal resistance, improving device conductivity, heat dissipation efficiency, and operational reliability. The specific process is as follows: 9.31, Deposition of ohmic contact layer on the back side; A layer of metal material is uniformly deposited on the opening area and the entire back surface of the substrate using sputtering or evaporation processes. 9.32, Laser annealing forms ohmic contacts, creating a back ohmic contact layer; 9.33, Gold-plated surface layer deposition A back gold surface layer is deposited on the back ohmic contact layer surface using sputtering, evaporation, or electrochemical deposition processes.

7. The fabrication process of a SiC power device with both low on-resistance and low thermal resistance according to claim 1, characterized in that, Step 2, the JFET region fabrication steps include: Using silicon carbide epitaxial layer as substrate and photoresist as mask layer, the JFET region is patterned and defined by photolithography. Nitrogen elements are implanted stepwise with different energies and doses to form a JFET region with a concentration gradient distribution. After implantation, the photoresist mask layer is removed by dry stripping and wet etching processes.

8. The fabrication process of a SiC power device with both low on-resistance and low thermal resistance according to claim 1, characterized in that, Step 2, the preparation of the P-type base region, includes the following steps: On the surface of the JFET implantation region, a P-type base region implantation window pattern is fabricated using photolithography. Aluminum elements are implanted in a stepwise manner with different energies to form a P-type base region with a concentration gradient distribution. After implantation, the mask layer is removed.

9. The fabrication process of a SiC power device with both low on-resistance and low thermal resistance according to claim 1, characterized in that, Step 2, the preparation steps for the N+ region, include: An oxide mask is coated on the surface of the P-type base region, and the N+ region implantation pattern is defined by photolithography. Nitrogen elements are implanted in steps with different energies to form N+ regions with a concentration gradient distribution.

10. The fabrication process of a SiC power device with both low on-resistance and low thermal resistance according to claim 1, characterized in that, In step 2, P + District and terminal P + The steps for synchronously preparing the floating field ring include: An oxide and polysilicon mask is coated on the device surface, and a P+ region implantation pattern is fabricated using photolithography. Aluminum is then implanted in stages with different energies to form a P+ region with a concentration gradient. + district; The injection pattern of the floating field ring is integrated into the above P. + In the area lithography pattern, with P + The injection was completed simultaneously in the district.

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