MIXED (100) AND (110) SURFACE BAND FETs IN INTEGRATING A PROCESS

Abstract

The present disclosure relates to mixed (100) and (110) surface ribbon FETs in an integration process, and to integrated circuit (IC) devices having non-planar transistor structures of complementary conductivity types. The IC device may include a first transistor and a second transistor, with the nanobelt stack in a channel region of the first transistor and one or more fins in a channel region of the second transistor, and the one or more fins may be on a trench isolation over the substrate. The nanobelt may have an upper (100) surface and a lower (100) surface, and the sidewalls of the one or more fins may be (110) surfaces. The fins on the isolation structure may be between the nanobelt stacks, the nanobelts may be over the sub-fins of the substrate, and the isolation structure may be between the sub-fins. The fins may be epitaxially grown from sidewalls of the nanobelt stack in the first transistor as vertical nanobelts (and the vertical nanobelts have the same lattice as and aligned with the nanobelt stack).

Description

Background Technology

[0001] Gate-all-around (GAA) field-effect transistors (FETs) offer improvements over FinFETs, such as the ability to adjust the channel width using nanoribbon width, increased gate electrostatic control over the FET channel (and thus a higher on / off current ratio), and so on. However, switching from fins (as channels) to other forms in metal-oxide-semiconductor (MOS) FETs often degrades PMOS performance (compared to NMOS performance), for example, due to differences in electron and hole mobility on the primary transport surfaces of the channel structure. Assuming a conventional (100) silicon substrate, the large (110) sidewalls of the FinFET channel are well-suited for PMOS, but the top and bottom (100) surfaces of the nanoribbons (or nanosheets) in a GAA FET are better suited for NMOS conduction. While using other silicon substrates (e.g., (110) wafers) can address this PMOS issue, this reorientation may then cause similar NMOS degradation (and introduce other problems, such as wafer splitting).

[0002] New technologies and structures are needed to improve the performance of CMOS devices, for example, by employing configurations optimized for each of the NMOS FET and PMOS FET. Attached Figure Description

[0003] The contents described herein are illustrated in the accompanying drawings by way of example rather than limitation. For simplicity and clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, reference numerals are repeated in the drawings where deemed appropriate to indicate corresponding or similar elements, for example, having the same or similar functions. This disclosure will be described in more specific and detailed manner by means of the accompanying drawings:

[0004] Figure 1A , Figure 1B and Figure 1C Cross-sectional profiles and plan views of an integrated circuit (IC) device having a FinFET (field-effect transistor) structure adjacent to a gate-all-around (GAA) FET structure are shown according to some embodiments;

[0005] Figure 2 This is a flowchart of a method for forming both a FinFET channel and a nanoribbon GAAFET channel in the same IC device, according to some embodiments;

[0006] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G and Figure 3H Cross-sectional profiles and plan views of a workpiece or device having a FinFET structure adjacent to a GAA FET structure at various manufacturing stages are shown according to some embodiments.

[0007] Figure 4 A diagram of an example data server machine employing an IC device is shown, wherein the IC device has nanoribbons and fins to serve as channels in adjacent transistors; and

[0008] Figure 5 This is a block diagram of an example computing device according to some embodiments. Detailed Implementation

[0009] In the following detailed description, reference is made to the accompanying drawings, which illustrate by way of illustration specific embodiments in which the claimed subject matter can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the described subject matter. While the various embodiments differ, they are not necessarily mutually exclusive. For example, specific features, structures, or characteristics described herein in conjunction with one embodiment may be implemented in other embodiments without departing from the spirit and scope of the claimed subject matter.

[0010] The reference to "an embodiment" or "an embodiment" in this specification indicates that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one implementation covered within this specification. Therefore, the use of the phrase "an embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. Furthermore, the position or arrangement of various elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of the subject matter is defined only by the appended claims as properly interpreted and by the full scope of their equivalents.

[0011] As used herein, the terms “above,” “to,” “between,” and “on” can refer to the relative position of a layer with respect to other layers. A layer “above,” “on,” or “integrated into” another layer can be in direct contact with that layer or can have one or more intermediate layers. A layer “between” layers can be in direct contact with those layers or can have one or more intermediate layers.

[0012] The terms “coupling” and “connection” and their derivatives are used herein to describe structural relationships between components. These terms are not intended to be synonyms for each other. Rather, in certain embodiments, “connection” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupling” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intermediary elements between them), and / or that two or more elements cooperate or interact with each other (e.g., as in causal, electrical, functional, etc.).

[0013] The terms "circuit" or "module" can refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term "signal" can refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a," "an," and "the" include plural references. The meanings of "in" include "in" and "on."

[0014] The vertical orientation is in the z-direction, and terms such as "top," "bottom," "above," and "below" refer to relative positions with their usual meaning in the z-direction. However, embodiments are not necessarily limited to the orientations or configurations shown in the figures.

[0015] The terms “substantially,” “nearly,” “approximately,” “around,” and “about” generally mean within + / - 10% of the target value (unless specifically specified). Unless otherwise stated in the specific context of use, the term “primarily” means greater than 50% or more than half. For example, a composition that is primarily the first component means that more than half of the composition is the first component. The term “primarily” means the majority or largest portion. For example, a composition that is primarily the first component means that the composition contains more first component than any other component. A composition that is primarily the first and second component means that the composition contains more first and second components than any other component.

[0016] Unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” and “third” to describe common objects merely indicates different instances of similar objects being referenced and is not intended to imply that objects described in this way must be in a given sequence in time, space, rank, or any other way.

[0017] For the purposes of this disclosure, the phrases “A and / or B” and “A or B” mean (A), (B) or (A and B). For the purposes of this disclosure, the phrases “A, B and / or C” mean (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

[0018] Views labeled "Section," "Profile," and "Planar" correspond to orthogonal planes in the Cartesian coordinate system. Therefore, section and profile views are taken in the xz and yz planes, and planar views are taken in the xy plane. Typically, the profile view in the xz plane is the section view. Where appropriate, the figures are labeled with axes to indicate the orientation of the view.

[0019] The structure and techniques for improving integrated circuit (IC) devices having gate-all-around (GAA) metal-oxide-semiconductor (MOS) field-effect transistors (FETs) implemented using complementary MOS (CMOS) technology are disclosed.

[0020] The structures described herein employ both GAA FETs and fin FETs, thereby utilizing, for example, each channel structure in which the corresponding lattice structure and surface orientation are most favorable for a particular FET conductivity type. For example, in a (100) silicon substrate, a GAA FET with a nanoband channel structure (e.g., with larger top and bottom (100) surfaces and minimal (110) sidewall surfaces) can be deployed in an NMOS FET, and a PMOS FinFET can utilize a larger fin (110) sidewall surface.

[0021] FinFETs can be formed in unconventional ways, for example, adjacent to a nanoribbon stack and without the need for fin etching, where fin etching is used to cut fins from a semiconductor substrate. The material stack can be grown upwards from a crystalline substrate (e.g., a (100) silicon wafer), and, for example, in a GAA FET process for fabricating a nanoribbon stack, the material stack can include channel material layers interleaved with sacrificial material layers. A second material stack can then be grown from the sidewalls of the first GAA FET material stack, wherein the fins of the FinFET are grown as vertically oriented nanoribbons (part of a second laterally grown material stack).

[0022] By growing from a crystalline substrate, the first material stack and the (laterally oriented) nanoribbons can comprise the same lattice structure (e.g., the lattice structure is continuous and aligned in the same orientation), and this lattice structure can then be retained in the fins (or vertically oriented nanoribbons) grown from the first material stack and the nanoribbons. Vertically oriented nanoribbons (or fins) and laterally oriented nanoribbons can be advantageously used in transistors of complementary conductivity types by means of surfaces with different crystal planes (e.g., (100) and (110)). For example, a FinFET with (110) sidewalls can have a p-type work function metal (WFM) in the gate electrode above the channel fin and acceptor (p-type) impurities as dopants in the source and drain bodies at either end of the channel fin. A GAA FET having (100) upper and lower nanoribbon surfaces can have an n-type WFM in the gate electrode (above and between the nanoribbons in the stacked body) and donor (n-type) impurities as dopants in the source and drain bodies at the ends of the nanoribbons.

[0023] While the GAA FET nanoribbon can be on top of the sub-fin region of a crystalline substrate, one or more FinFET fins can be on top of a trench isolation dielectric, for example, between the sub-fins and the GAA FET, which can be an indication of the described fabrication process. One or more fins can be directly on the isolation dielectric, which can be formed as a base beneath one or more FinFET fins.

[0024] Figure 1A , Figure 1B and Figure 1C Cross-sectional outlines and plan views of an IC device 100 having a FinFET structure 102 adjacent to a GAA FET structure 101A / 101B according to some embodiments are shown. Views 103, 104, and 105 are outline views through different sections of the device 100, wherein parallel views 103 and 104 are located in the yz plane, respectively laterally passing through the first channel region 121 and the second channel region 132, and laterally passing through the source and drain bodies 111 and 112, and view 105 is located in the xz plane, longitudinally passing through the fin channel region 132. Plan view 106 shows the relative orientations of outline views 103, 104, and 105 and their corresponding viewing planes A-A', B-B', and C-C'. Figure 1A Adjacent gate electrodes 125, 135 are shown on the nanoribbon 120 in the GAA FET structure 101A / 101B and on the fin 130 in the FinFET structure 102. Figure 1B The diagram shows a gate electrode 135 on a fin 130 in a FinFET structure 102, and a separate gate electrode 125 on a nanoribbon 120 in a GAA FET structure 101A / 101B. Figure 1C A shared gate electrode 125 is shown on the fin 130 in the FinFET structure 102 and on the nanoribbon 120 in the GAA FET structures 101A / 101B.

[0025] Figure 1A An IC device 100 is shown, comprising a transistor structure 102 between transistor structures 101A and 101B. Contour view 103 is first shown in the mapping context of planar view 106, and then again in conjunction with accompanying contour views 104 and 105. As shown in view 103, each of the GAA FET structures 101A and 101B includes a stack 122 of nanoribbons 120 in a first channel region 121 above a substrate 199. Each stack 122 of the nanoribbons 120 extends in the x-direction, thereby coupling between a first source and drain body 111 in the transistor structures 101A / 101B. View 104 shows one of the source and drain bodies 111 of each of the transistor structures 101A and 101B. Nanoribbon 120 is a lateral nanoribbon 120, for example, having substantially horizontal upper (or top) and lower (or bottom) surfaces 127, 128 with smaller sidewalls than the nanoribbon 120. In many embodiments, the upper surface 127 and lower surface 128 of the nanoribbon 120 are (100) surfaces, which can provide improved performance for the NMOS transistor structures 101A / 101B (e.g., higher electron mobility relative to (110) surfaces).

[0026] As shown in View 103, the FinFET structure 102 includes a plurality of fins 130 in a second channel region 132 on a dielectric structure 140 above a substrate 199. The fins 130 extend in the x-direction, and two fins 130 are coupled between a pair of second source and drain bodies 112 in the transistor structure 102. View 104 shows one source and drain body 112 of the transistor structure 102. The fins 130 stand substantially vertically, extending upward from the isolation structure 140 and substantially orthogonal to the nanoribbon 120. The fins 130 are vertical nanoribbons, for example, where the substantially vertical sidewalls 131 are significantly larger than the small upper surface 137 of the fin. In many embodiments, the sidewalls 131 of the fin 130 are (110) surfaces, which can provide improved performance for the PMOS transistor structure 102 (e.g., higher hole mobility relative to (100) surfaces).

[0027] Substrate 199 includes a plurality of sub-fins 123. Each stack 122 of nanoribbons 120 is on top of a sub-fin 123. Isolation structures 140 are located on top of substrate 199, between stacks 122, and between sub-fins 123 below each stack 122. Dielectric structures 140 are located in trenches 194. Trenches 194 are located on substrate 199 and between sub-fins 123. For example, trenches 194 and sub-fins 123 may be formed together, wherein sub-fins 123 are formed from substrate 199 by forming trenches 194 in substrate 199. Each sub-fin 123 is located between a pair of structures 140 on substrate 199. Dielectric structures 140 may include any suitable dielectric material, such as oxides (e.g., oxides thermally grown on substrate 199). In many embodiments, structures 140 include oxygen (e.g., oxygen in an oxide of silicon).

[0028] Transistor structures 101A / 101B, 102 can have different dimensions or characteristics, for example, as required by a specific application or layout. For instance, to match higher or lower current requirements or depending on space constraints, FET structures 101A / 101B can have more or fewer (or wider or narrower) nanostrips 120. Figure 1A In an exemplary embodiment, each of the GAA FET structures 101A / 101B includes three nanoribbons 120. In some embodiments, structures 101A / 101B include more than three nanoribbons 120. In some embodiments, structures 101A / 101B include fewer than three nanoribbons 120.

[0029] FinFET structure 102 includes two fins 130. In some embodiments, structure 102 includes more than two fins 130. In some embodiments, structure 102 includes fewer than two fins 130. For example, to provide more or less current or depending on space constraints, FinFET structure 102 may have more or fewer (or taller or shorter) fins 130. The upper surface 137 of the fin 130 is at a first height H1 above a second height H2 of the upper surface 127 of the nanoribbon 120 stack. In some embodiments, for example, to provide more current, the surface 137 of the fin 130 is at a greater height H1 above the height H2 of the uppermost surface 127 of the nanoribbon 120. In some embodiments, the height H1 of the fin 130 is 1.5 times the height H2 of the nanoribbon 120. For example, the fin 130 may have a greater height H1 than the typical height of the fin 130 in a FinFET, because it allows the fin 130 to grow laterally from the material stack without requiring a high aspect ratio fin etching manufacturing process.

[0030] Transistor structures 101A / 101B, 102 can have different spacing or orientations, for example, to meet certain space constraints or minimize the occupied layout area. In applications with constrained layouts, the spacing of channel regions 121, 132 can be reduced. The stack 122 of nanoribbon 120 is separated from the fin 130 by a distance D. In some embodiments, the distance D is greater than the width W of the fin 130 and less than twice the width W. This spacing can provide sufficient distance between channel regions 121, 132 (e.g., for sufficiently low capacitance between channel regions 121, 132) without occupying an excessive area. In some embodiments, the distance D is greater than twice the width W, which can reduce the capacitance between channel regions 121, 132 and thus improve performance. In some embodiments, the distance D is less than the width W, which can reduce the area occupied by structures 101A / 101B, 102.

[0031] One or more gate dielectric layers 124 may be located between channel regions 121, 132 and gate electrodes 125, 135. The gate dielectric layer 124 provides electrical insulation between the channel regions 121, 132 and electrodes 125, 135. Layer 124 may have more than one layer. Layer 124 may have any suitable one or more materials. One or more layers of dielectric layer 124 may include silicon oxide, silicon dioxide (e.g., SiO2), silicon oxynitride, etc. Advantageously, the gate dielectric layer 124 includes a high dielectric constant (“high K”) dielectric, which can improve the transconductance of electrodes 125, 135 to channel regions 121, 132 and thereby improve the electrostatic control of electrodes 125, 135 to channel regions 121, 132. High-k dielectric materials can include one or more of various elements, such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc, in oxides of these elements and combinations thereof. Any other suitable materials can be deployed.

[0032] Transistor structures 101A / 101B include a gate electrode 125. A nanoribbon 120 extends through electrode 125. Transistor structure 102 includes a gate electrode 135 located above a first fin and a second fin 130. Gate electrodes 125 and 135 are adjacent and electrically coupled. Gate electrodes 125 and 135 on gate dielectric layer 124 may include at least one of p-type or n-type WFM, depending on whether transistor structures 101A / 101B and 102 are PMOS or NMOS transistors. In many embodiments, gate electrodes 125 and / or 135 are a stack of two or more metal layers. For example, a conformal layer or liner layer 126 or 136 is on one or more dielectric layers 124 and around a bulk or fill metal, thereby located between layer 124 and the bulk or fill metal. Figure 1AIn an exemplary embodiment, gate electrodes 125 and 135 include different filler metals. Gate electrodes 125 and 135 can be coupled to an interconnect network 195 on FET structures 101A / 101B and 102 via contact structures or vias (not shown).

[0033] Substrate 126 or 136 may be a seed or barrier metal and / or WFM adjacent to one or both channel regions 121, 132, for example, to set or influence the gate threshold voltage V. T In many embodiments, electrode 125 includes an n-type WFM layer 126. In many embodiments, electrode 125 includes a p-type WFM layer 136. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The p-type WFM layer enables the formation of a PMOS gate electrode having a work function between about 4.9 eV and about 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as aluminum carbide, hafnium carbide, zirconium carbide, titanium carbide, and tantalum carbide. The n-type WFM layer enables the formation of an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some embodiments, the bulk metal of electrodes 125, 135 is WFM.

[0034] View 106 shows gate electrodes 125, 135 on nanoribbons 120 and fins 130. A gate dielectric layer 124 is on spacer layer 119, and a gate metal liner 126 or 136 is on gate dielectric layer 124. Contact structures 115, 116 are located on and through an isolation dielectric 114 in a trench between electrodes 125. Spacer layer 119 is between electrodes 125, 135 and structures 115, 116. Isolation dielectric 114 is between electrodes 125, 135.

[0035] Plan view 106 shows the relative orientation of profile view 103 and observation plane A-A', as well as the relative orientation of profile views 104, 105 and their respective observation planes B-B' and C-C'.

[0036] Outline view 103 is again shown together with accompanying outline views 104 and 105, for example, to provide context for view 104, which is aligned with view 103 on the y-axis.

[0037] View 104 shows drain and / or source bodies 111, 112. Drain and source bodies 111 are located at the ends of nanoribbon 120, and drain and source bodies 112 are located at the ends of fin 130. In many embodiments, transistor structures 101A / 101B, 102 are physically symmetrical about channel regions 121, 132 (and gate electrodes 125, 135), respectively, and in many contexts, the identifiers of bodies 111, 112 (either as drain bodies 111, 112 or as source bodies 111, 112) may be interchangeably reversed. However, the bodies 111 and 112 can be classified as source or drain bodies 111 and 112 based on the electrical relationship between the transistor structures 101A / 101B, 102 and the bodies 111 and 112 and other components in a given circuit (e.g., and the direction of the current flowing through the structures 101A / 101B, 102 and the bodies 111 and 112).

[0038] The bodies 111 and 112 are electrically and physically coupled to the opposite ends of the channel regions 121 and 132, respectively. The source and drain bodies 111 and 112 are impurity-doped bodies, for example, regions of semiconductor material doped with one or more electrically active impurities and exhibiting increased charge carrier availability and associated conductivity. Bodies 111 and 112 may be doped with impurities of opposite types (e.g., n-type or p-type). The drain and source bodies 111 and 112 may comprise the predominant semiconductor material and one or more n-doped agents (e.g., donor impurities such as phosphorus, arsenic, or antimony) or p-type impurities (e.g., acceptor impurities such as boron or aluminum). Other dopant materials may be used. In many embodiments, source and drain bodies 111 comprise donor impurities, and source and drain bodies 112 comprise acceptor impurities.

[0039] The drain and source bodies 111, 112 can be formed by any suitable means. The bodies 111, 112 can be epitaxially grown semiconductor regions of, for example, group IV semiconductor materials (e.g., Si, Ge, SiGe, GeSn alloys). Other semiconductor materials can be used. The bodies 111, 112 can be substantially crystalline. The source and drain bodies 111, 112 can be polycrystalline or substantially monocrystalline, for example, having long-range ordered states at least at adjacent ends of the channel regions 121, 132, and merging or joining together to form a single body with few grain boundaries. The bodies 111 and 112 may be surrounded by an isolation dielectric 114 (e.g., in both y directions), which may fill the space between the gate electrodes 125 and / or 135 (e.g., in adjacent FET structures 101A / 101B, 102, which have channel regions 121, 132 aligned in the y direction and extending in the x direction).

[0040] Drain and source bodies 111, 112 are coupled to an interconnect network 195 over FET structures 101A / 101B, 102 via contact structures 115, 116. Contact structures 115, 116 may be formed of metal or other conductive materials, including an interface layer (e.g., a silicide layer) of metal alloyed with the semiconductor material of bodies 111 or 112. The interconnect network 195 includes layers having interconnects or wires for providing electrical wiring, typically formed of metal or other conductive materials. Adjacent interconnect layers may be formed of different materials and using different methods. Adjacent metallization layers and interconnect layers are interconnected via vias, which may be characterized as part of a metallization layer or between metallization layers. In the illustrated example, network 195 may be a front-side interconnect network 195 including metallization layers M0, V0, M1, M2 / V1, M3 / V2, M4 / V3, and M4-M12. However, network 195 may include any number of metallization layers, such as eight or more. Similarly, the back-side network 195 may include BM0, BM1, BM2, and BM3. However, network 195 may include any number of metallization layers, such as two to five metallization layers.

[0041] Substrate 199 may comprise any suitable material or a combination of materials. In some examples, substrate 199 may comprise single-crystal silicon (including silicon-on-insulator (SOI)), polycrystalline silicon, germanium, silicon-germanium, III-V alloy materials (e.g., gallium arsenide), silicon carbide (e.g., SiC), sapphire (e.g., Al2O3), or any combination thereof. Substrate 199 may specifically refer to a substrate material (e.g., a thick semiconductor material substrate or a thick semiconductor material layer) on which other materials (such as metals and dielectrics) are deposited. In some contexts, substrate 199 may refer to a substrate material layer and any deposited layers above the substrate, etc. In many embodiments, substrate 199 comprises semiconductor material beneath bodies 111, 112 and dielectric structure 140. In some such embodiments, trenches 194 are diced between channel regions 121 (e.g., nanoribbons 120), and trenches 194 are diced into silicon substrate 199. Substrate 199 may also comprise other semiconductor materials, metals, dielectrics, dopants, and other materials common in semiconductor substrates.

[0042] View 105 shows the xz plane of the channel region 132 extending longitudinally through the (vertical nanoribbon or) fin 130. Drain and / or source bodies 112 are located between adjacent FET structures 102, each having a channel region 132 extending in the x-direction and aligned in the y-direction. The vertical nanoribbon or fin 130 rests on an isolation structure 140 above a substrate 199. A gate electrode 135 rests above the channel region 132 of the fin 130, and a gate dielectric layer 124 rests between the electrode 135 and the fin 130. A layer 136 of the electrode 135 rests on layer 124. The drain and / or source bodies 112 and contact structure 116 are separated from the gate electrode 135 by a dielectric layer 129 on the fin and by a spacer layer 119. Layers 119 and 129 provide electrical isolation between adjacent structures and advantageously comprise a low-dielectric-constant (“low-K”) dielectric material. Layers 119 and 129 may also provide etching selectivity, for example, during manufacturing. In many embodiments, one or both of layers 119 and 129 comprise oxygen and silicon. In some such embodiments, one or both of layers 119 and 129 comprise nitrogen.

[0043] Figure 1B View 103 illustrates an IC device 100 having a gate isolation element 139 between separate gate electrodes 125, 135. Device 100 includes first, second, and third transistor structures 101A, 101B, 102 located on a substrate 199. Device 100 includes stacks 122 of lateral nanoribbons 120 in structure 101A and 101B, each stack 122 above a corresponding sub-fin 123 and between a pair of first source and drain bodies 111. FET structures 101A / 101B include a gate electrode 125. Device 100 includes vertical nanoribbons or fins 130 between a pair of source and drain bodies 112 in structure 102, and between transistor structures 101A, 101B. FET structure 102 includes a gate electrode 135. Fins 130 are located on a dielectric structure 140 in a trench 194 above the substrate 199. Groove 194 is located between fins 123.

[0044] Isolator 139 separates transistor structures 101A / 101B, 102. Isolator 139 provides electrical isolation between adjacent structures 101A / 101B, 102 and between gate electrodes 125, 135, and advantageously comprises a low-k dielectric material. In many embodiments, one or both layers 119, 129 comprise oxygen and silicon.

[0045] Figure 1CView 103 shows an IC device 100 including a shared gate electrode 125 over channel regions 121, 132. Transistor structures 101A / 101B, 102 include a gate electrode 125. The gate electrode 125 includes WFM layers 126, 136 of complementary conductivity type. Figure 1C In an exemplary embodiment, the gate electrode 125 includes the same fill metal located above the n-type WFM layer 126 and the p-type WFM layer 136.

[0046] Figure 2 This is a flowchart of a method 200 for forming both a FinFET channel and a nanoribbon GAAFET channel in the same IC device, according to some embodiments. Method 200 includes operations 210-280. Figure 2 Some of the operations shown are optional. Additional operations may be included. Figure 2 The example order is shown, but operations can be performed in other orders, and some operations can be omitted. Some operations can also be performed multiple times before other operations. Some operations can be included within other operations, making... Figure 2 The number of operations shown is not a limitation on method 200.

[0047] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G and Figure 3H Cross-sectional profiles and plan views of a workpiece or device 100 having a FinFET structure 102 adjacent to a GAAFET structure 101A / 101B at various manufacturing stages are shown according to some embodiments. Figures 3A to 3H This demonstrates the practical application. Figure 2 Possible examples of intermediate structures during embodiments of method 200.

[0048] return Figure 2 Method 200 begins with operation 210, in which a barrier material is deposited. The barrier material may be deposited on or over the sidewalls of the material stack to prevent subsequent crystal growth on the sidewalls. In many embodiments, the material stack includes a channel material layer and a sacrificial material layer. The channel material layer and the sacrificial material layer may be alternating (e.g., staggered).

[0049] A barrier material can be deposited on or over a sidewall to prevent growth while exposing an opposing sidewall (e.g., on the opposite side of a material stack) that can serve as a growth template for epitaxial growth of a crystal lattice. The barrier material can be any suitable material and can be deposited in any suitable manner. The barrier material can be a material that inhibits the growth (e.g., deposition) of channel and sacrificial materials, which are then selectively deposited on the exposed sidewalls. In many embodiments, the barrier material comprises carbon, nitrogen, or oxides. In many embodiments, the barrier material is deposited (conformally or by blanket deposition) and patterned (e.g., removed) by photolithography operations (e.g., masking areas to be blocked, depositing the barrier material in unmasked areas, and removing the masking material). In many embodiments, the barrier material is deposited on a first sidewall of a plurality of material stacks, exposing a second sidewall opposite to the first sidewall. In some such embodiments, adjacent pairs of material stacks have exposed inner sidewalls facing the other stack in the pair (e.g., the barrier material on the opposing outer sidewalls).

[0050] In some embodiments, alternating layers of channel material and sacrificial material have approximately equal heights (e.g., layer thicknesses). In other embodiments, one or the other layer of channel material or sacrificial material has a significantly greater height or thickness. For example, the sacrificial material layer may have a greater height or thickness to provide more space between the nanoribbon (channel material) layers (e.g., to be replaced by a metal gate when removed). In some embodiments, alternating channel and sacrificial layers typically have approximately equal heights or thicknesses, but with a thicker or thinner upper and / or lower layer. For example, the top or bottom sacrificial layer may be thicker (or thinner) to provide a greater fin height (or metal gate height).

[0051] Material stacks can be received on or in a substrate, such as an IC die or wafer, for example, with Figure 1AThe substrate 199 described is very similar. In some embodiments, a material stack is formed on the received substrate. The material stack can be formed, for example, by sequentially epitaxially depositing a channel material and a sacrificial material on the substrate using atomic layer deposition (ALD) or other chemical vapor deposition (CVD). Both the channel material and the sacrificial material can be epitaxially deposited into a lattice structure that is continuous (e.g., aligned and matched) with the lattice structure of the received substrate. In many embodiments, the received substrate is a silicon wafer, and one or both of the (e.g., grown) channel material and the sacrificial material comprise silicon, and one or both of the (e.g., grown) channel material and the sacrificial material comprise germanium. In many embodiments, the received substrate is a (100) silicon wafer, the (e.g., grown) channel material is silicon, and the (e.g., grown) sacrificial material is silicon-germanium. In some such embodiments, the channel material layer and the sacrificial material layer have upper and lower (100) surfaces, and the material stack has (e.g., the channel material layer and the sacrificial material layer have) sidewall (110) surfaces. In some such embodiments, the lattice structure is continuous from the crystalline substrate and through the material stack of the first and second layers. In some embodiments, the material stack of the layers is etched to form sidewalls (e.g., separated by the width of the final nanoribbons or nanosheets). In some such embodiments, etching continues into the substrate (on which the material stack is located) and forms trenches in the substrate (e.g., trenches located between two material stacks and the sidewalls of the two material stacks facing each other over the trench). Forming trenches may involve forming substrate sub-fins below the material stacks as located on either side of the trench (e.g., as trench sidewalls). Etching may be performed using a hard mask (e.g., photolithographically patterned) on top of the material stacks.

[0052] Figure 3A A material stack 322 in a workpiece or apparatus 100 is shown according to some embodiments, for example, after performing deposition operation 210, wherein a barrier material 355 is located on a sidewall 325 opposite to an exposed sidewall 326. The barrier material 355 is located on the outer sidewall 325, and the exposed inner sidewalls 326 face each other over a dielectric structure 140. The material stack 322 is located on a sub-fin 123 of a substrate 199. The material stack 322 includes alternating channel material layers 320 and sacrificial material layers 323. A hard mask 352 is located over the stack 322. The isolation structure 140 includes a dielectric material in a trench 194. The trench 194 is between two material stacks 322, and the sidewalls 326 of the stacks 322 face each other over the trench 194.

[0053] In view 303, which is located on the yz section observation plane A-A', the orientation of the xz section observation plane C-C' is shown, for example for reference purposes. View 305 is located on the observation plane C-C' and extends longitudinally through the fins (or vertical nanoribbons) that have not yet formed.

[0054] In view 306, which is an xy-plane diagram, the orientations of the yz-section observation planes A-A' and B-B' (as shown in views 303 and 304, respectively) and the xz-section observation plane C-C' (as shown in view 305) are illustrated, for example, for illustrative purposes. Barrier material 355 is located outside the stack 322, and the inner sidewalls 326 are exposed and face each other over the dielectric structure 140. In view 303, observation plane A-A' is shown laterally across the stack 322 and will pass through the gate electrode to be formed on the nanoribbons and fins. In view 304, observation plane B-B' is shown laterally across the stack 322 and will be located in the trench between the gate electrodes not yet formed on the nanoribbons and fins. (For example, for reference purposes, the unformed fins and gate electrodes are shown using a shaded dashed outline on the structure 140 above the substrate 199). It should be noted that the structures shown (e.g., material stack 322 and barrier material 355) may extend beyond the shown edges, for example, in the x-direction.

[0055] return Figure 2 Method 200 continues at operation 220, wherein a sacrificial material layer is grown on the exposed sidewalls of the material stack. The sacrificial layer can be grown in any suitable manner and with any suitable sacrificial material (e.g., the same sacrificial material as in the layer stack). In many embodiments, a new sacrificial material layer is grown on the stack sidewalls, for example, by epitaxial deposition (such as ALD) in the same manner as the sacrificial material layer in the layer stack.

[0056] Sacrificial material growth (e.g., laterally from the sidewalls of the stack) can establish a distance or spacing between the subsequently formed vertical channel layer (e.g., fins or vertical nanoribbons) and the material stack (and the final nanoribbon channel in the stack). At operation 220, a channel material layer can be grown on the sidewalls of the sacrificial material layer grown therein, and the thickness of the new sacrificial material layer can set or provide the space between the stack of material layers or nanoribbons and the vertical channel material layer (e.g., for one or more gate dielectrics and one or more gate metals). In some embodiments, the new sacrificial material layer is grown to a width or lateral thickness greater than the subsequently formed vertical channel layer (e.g., as in...). Figure 1AThe thickness is greater than the width (W) mentioned above. In some such embodiments, the new sacrificial material layer is grown to a thickness smaller than twice the width or lateral thickness of the subsequently formed vertical channel layer. This range (between one and two times the fin thickness or width) can provide sufficient space for subsequent gate formation (including removal of the sacrificial material and deposition of the gate dielectric and metal) without occupying or consuming excessive lateral (e.g., layout) area. In other embodiments, the new sacrificial material layer is grown to a thickness smaller than the width or lateral thickness of the subsequently formed vertical channel layer, which allows for a more compact device layout.

[0057] The exposed sidewalls of the material stack are shared sidewalls of the channel material layer and the sacrificial material layer, and the lattice structure of the substrate and the channel material layer and sacrificial material layer of the material stack can continue at the newly grown layer on the sidewall (here, in operation 220). In many embodiments, the sacrificial material layer is grown on the stack sidewall by epitaxially depositing the sacrificial material on the stack sidewall (and the channel material layer and sacrificial material layer in the stack). In some such embodiments, the lattice structure of the crystalline substrate remains continuous from the substrate, through the material stack through the channel material layer and the sacrificial material layer, and to the sacrificial material layer grown on the stack sidewall. In some such embodiments, for example, the sacrificial material layer grown on the stack sidewall has a sidewall (110) surface to match and be parallel and continuous with the material stack sidewall. In many embodiments, the sacrificial material layer grown on the stack sidewall has the same sacrificial material as the sacrificial material in the sacrificial layer of the material stack. In some such embodiments, a silicon-germanium sacrificial material layer is grown on the exposed sidewalls of a material stack of silicon channel layers and silicon-germanium sacrificial layers over silicon sub-fins and a substrate.

[0058] By growing laterally from the sidewalls of the stack, a new sacrificial material layer can be grown on (and protruded from) an isolation structure adjacent to the sub-fins below the material stack. The isolation structure can be on the substrate (and between a pair of substrate sub-fins) and can be a substrate below the newly formed sacrificial material layer.

[0059] Growing a sacrificial material layer on the exposed sidewalls of a material stack can be performed simultaneously with growing other sacrificial material layers on other exposed sidewalls of other material stacks. In some embodiments, adjacent pairs of material stacks have exposed inner sidewalls facing the other stack in the pair (e.g., blocking material on opposing outer sidewalls). In some such embodiments, for example, a sacrificial material layer is grown on the exposed sidewall of a first material stack, and another sacrificial material layer is grown on the exposed sidewall of a second material stack (e.g., simultaneously), wherein the newly grown sacrificial material layer is between the first and second material stacks.

[0060] For example, after growing one or more channel material layers (e.g., at operation 230), additional sacrificial material layers may subsequently be grown. In some embodiments, after pairs of channel material layers have been deposited on newly grown pairs of sacrificial material layers on the exposed inner sidewalls of pairs of adjacent material stacks, another sacrificial material layer is grown on and between the newly deposited pairs of channel material layers (e.g., the innermost pair growing inward from the adjacent material stack). This sacrificial material layer may complete the lateral stack growth and, for example, cover at least the sidewalls of the channel material layers, which may provide the necessary structural strength during subsequent processing.

[0061] return Figure 2 Method 200 continues by growing a channel material layer on the sacrificial material layer on the sidewall of the stack at operation 230. The channel layer can be grown in any suitable manner and with any suitable channel material (e.g., the same channel material as the channel material in the stack). In many embodiments, a new channel material layer is grown on the sidewall of the sacrificial material layer, for example, by epitaxial deposition (such as ultra-high vacuum or low-pressure CVD (UHVCVD or LPCVD)) in the same manner as the channel material layer in the stack.

[0062] Channel material growth (e.g., lateral growth from the sidewalls of a sacrificial material layer) can define the width or thickness of the channel fins (e.g., vertical nanoribbons), which can ensure sufficient mechanical strength of the fins. In some embodiments, the new channel material layer is grown to a width or lateral thickness (e.g., as in...) Figure 1A The width W) is greater than the height or vertical thickness of the channel material layer in the material stack. In some embodiments, the new channel material layer grows to a width or lateral thickness (e.g., as in...) Figure 1A The width (W) described therein is less than or equal to the width or lateral thickness of the previously formed sidewall sacrificial material layer. In some such embodiments, the new channel material layer grows to a thickness greater than half the width or lateral thickness of the sidewall sacrificial material layer.

[0063] A newly grown channel layer (here, at operation 230) on a sacrificial material layer grown on the sidewalls of the stack can continue the lattice structure of the substrate, the material stack channel material layer and the sacrificial material layer, and the sacrificial material layer on the sidewalls. In many embodiments, the channel material layer is grown on the sidewall sacrificial material layer by epitaxially depositing channel material on the sidewall sacrificial material layer. In some such embodiments, the lattice structure of the crystal substrate remains continuous from the substrate, through the material stack through the channel material layer and the sacrificial material layer, through the sacrificial material layer grown on the sidewalls of the stack, and to the channel material layer grown on the sidewall sacrificial material layer. In some such embodiments, for example, the channel material layer grown on the sidewall sacrificial material layer has a sidewall (110) surface to match and be parallel and continuous with the sidewalls of the material stack. In many embodiments, the channel material layer grown on the sidewall sacrificial material layer has the same channel material as the channel material in the channel layer of the material stack. In some such embodiments, a silicon channel material layer is grown on the sidewall sacrificial material layer of silicon germanium on the sidewall of a material stack of silicon channel layer and silicon germanium sacrificial layer above silicon sub-fins and substrate.

[0064] A new channel material layer can be grown or protruded above (and on) an isolation structure adjacent to the sub-fins below the material stack by laterally growing from the sidewalls of the stack and the sacrificial material layer on the sidewalls of the stack. The isolation structure can be above the substrate (and between a pair of substrate sub-fins) and can be a substrate below the newly formed channel material layer.

[0065] Growing a channel material layer on a sidewall sacrificial material layer can be performed simultaneously with growing other channel material layers on other sidewall sacrificial material layers on other material stacks. In some embodiments, adjacent pairs of material stacks have sidewall sacrificial material layers facing the other stack in the pair (e.g., blocking material on opposing outer sidewalls). In some such embodiments, for example, a channel material layer is grown on the sidewall sacrificial material layer of a first material stack, and another channel material layer is grown on the sidewall sacrificial material layer of a second material stack (e.g., simultaneously), wherein the newly grown channel material layer is between the first and second material stacks and the sidewall sacrificial material layers on the material stacks.

[0066] For example, additional sacrificial material layers and channel material layers can then be grown to create more fins. In some embodiments, after paired channel material layers have been deposited on paired sacrificial material layers grown on paired sidewalls of adjacent material stacks, another sacrificial material layer is grown on and between newly deposited paired channel material layers (e.g., the innermost paired layer growing inward from the adjacent material stack).

[0067] Figure 3B(For example, in view 303) A vertical sacrificial material layer 333 and a channel material layer 334 are shown between material stacks 322 in a workpiece or apparatus 100 after growth operations 220, 230, according to some embodiments. The vertical sacrificial material layer 333 and the channel material layer 334 are on an isolation structure 140. For example, the vertical sacrificial material layer 333 is continuous with the sacrificial layer 323, for example, having the same sacrificial material and the same uninterrupted lattice structure, as if grown on the sidewall 326, which is not obvious where the sacrificial materials of layers 323, 333 merge. The vertical channel material layer 334 is on the sidewall of layer 333, between the stacks 322. A vertical sacrificial material layer 333B is on and between the vertical channel material layers 334.

[0068] View 306 shows a vertical sacrificial material layer 333 and a channel material layer 334 between material stacks 322, covering the isolation structure 140 between the stacks 322. The vertical sacrificial material layer 333 is adjacent to the stack 322 (e.g., on or continuous with the stack 322). The vertical channel material layer 334 is on the vertical sacrificial material layer 333. The dashed outline of the gate electrode to be formed is located above the substrate 199, for example, for reference purposes.

[0069] return Figure 2 Continuing with method 200, at operation 240, the material stack, sidewall sacrificial layer, and channel layer are masked. In many embodiments, the material stack, sidewall sacrificial layer, and channel layer are masked after the barrier material deposited at operation 210 is removed. In many embodiments, the material stack, sidewall sacrificial layer, and channel layer are masked together. In some such embodiments, the material stack, sidewall sacrificial layer, and channel layer are masked by depositing a passivation layer over the material stack, sidewall sacrificial layer, and channel layer, and by depositing a dummy gate over the passivation layer. In some embodiments, the passivation layer is thermally grown. In some embodiments, the masking layer is deposited by ALD (e.g., oxide, such as silicon oxide). In some such embodiments, the masking layer is deposited by ALD over the thermally grown passivation layer.

[0070] The deposited dummy gate defines the channel by masking this portion of the channel material layer. Subsequent etching operations can remove the unmasked portion of the channel material. The dummy gate can be any suitable material, e.g., one that has satisfactory etch selectivity relative to other exposed structures and materials. In many embodiments, the dummy gate comprises polysilicon. In many embodiments, a hard mask is located over the dummy gate, e.g., for patterning the dummy gate, etc.

[0071] Figure 3CThe diagram shows (e.g., in view 303) vertical sacrificial material layers 333 and channel material layers 334, along with a material stack 322, which are together covered beneath a masking layer 329 in a workpiece or device 100, for example, during or after a masking operation 240, according to some embodiments. Layer 329 is on top of the stack 322 and the vertical layers 333, 334, and on the sidewalls 325 of the stack 322.

[0072] View 306 shows a masking layer 329 over the stack 322 and layers 333, 334. Dashed and shaded outlines of the gate electrodes that have not yet been formed are located over the substrate 199, for example, for reference purposes.

[0073] Figure 3D A dummy gate 358 is shown on a masking layer 329 over a stack 322 and layers 333, 334 in a workpiece or device 100 after a masking operation 240 is performed, according to some embodiments. A hard mask 359 is located on the dummy gate 358.

[0074] In view 303, the cross-sectional plane A-A' is a gate notch that passes through the dummy gate 358 on the masking layer 329, which is located above the stack 322 and vertical layers 333, 334, and on both sides of the stack 322 and vertical layers 333, 334. The dummy gate 358 is located on the isolation structure 140 on the substrate 199. The hard mask 359 is located on the top surface of the dummy gate 358. Layers 320, 323, 333, 334 extend through the dummy gate 358 in the x-direction. In view 305, the cross-sectional plane C-C' longitudinally passes through the vertical channel layer 334.

[0075] In view 304, the cross-sectional plane B-B' is the trench cut between the dummy gates 358. The masking layer 329 is exposed on top of the stack 322 and the vertical layers 333, 334, as well as on the sidewall 325 of the stack 322. Layers 320, 323, 333, and 334 extend in the x-direction, together covering the masking layer 329. The cross-sectional plane C-C' in view 305 longitudinally passes through the vertical trench layer 334.

[0076] In view 305, the cross-sectional plane C-C' is a fin cut that passes through the vertical channel layer 334 beneath the dummy gate 358 and through the dummy gate 358. A masking layer 329 is exposed between the dummy gates 358 on top of the vertical layer 334. Layer 334 extends in the x-direction and is covered by the masking layer 329. The orientations of the gate cut plane A-A' and the trench cut plane B-B' are shown.

[0077] View 306, which is an xy-plane view, shows the orientation of the yz-section observation planes A-A' and B-B' (gate cutout view 303 and trench cutout view 304, respectively) and the orientation of the xz-section observation plane C-C' (fin cutout view 305). A masking layer 329 lies on the substrate 199 and is exposed between strips of a hard mask 359 (which lies on top of the dummy gate 358).

[0078] return Figure 2 Method 200 continues by exposing the ends of the channel material layer at operation 250. The ends of the channel material layer in the material stack, and the ends of the vertical (e.g., sidewall) channel material layer, can be exposed by etching unmasked portions of the material stack and unmasked portions of the vertical material layer (etching both the lateral and vertical material layers, and both the sacrificial material layer and the channel material layer). The unmasked portions can be those portions not masked by the dummy gate. Those portions not masked by the dummy gate can be left unmasked by removing other masking layers (such as passivation layers located above the stack and vertical layers but exposed between the dummy gates) through etching between the dummy gates.

[0079] Any suitable etching can be used to expose the ends of the channel layer. In many embodiments, anisotropic dry etching cuts through the stack and vertical layers, thereby forming and exposing the layer ends on both sides of the dummy gate (e.g., on the sidewalls). In many embodiments, a spacer dielectric is conformally deposited over the dummy gate, and the spacer serves as a mask layer on the dummy gate sidewalls, thereby guiding the etching between the dummy gate and the spacer mask layer on the dummy gate sidewalls. The etching can penetrate entirely through the stack and vertical layers, down to the substrate (e.g., sub-fins) and the isolation structure between the sub-fins.

[0080] Figure 3E The diagram illustrates stacked layers 320, 323 and vertical layers 333, 334 etched through between dummy gates 358 in a workpiece or device 100 after exposure operation 250, according to some embodiments. The lateral channel layer 320 and vertical channel layer 334 are now segmented into nanoribbons and fins of more familiar channel lengths.

[0081] In view 303, layers 320, 323, 333, and 334 are still below masking layer 329 and are covered by dummy gate 358.

[0082] In view 304, there is no stack 322 and vertical layers 333, 334 (and layer 329) between the dummy gate 358. The substrate 199 and the isolation structure 140 (both etched slightly downwards) are exposed.

[0083] In view 305, spacer layer 119 is on the sidewalls of dummy gate 358 and hard mask 359. Cutout or opening 366 is between spacer layers 119 and extends through vertical layer 334 (and stack 322) and masking layer 329. Cutout or opening 366 extends downward and slightly into isolation structure 140.

[0084] In view 306, spacer layer 119 is on the sidewall of hard mask 359 (and dummy gate 358 below hard mask 359). Cutouts or openings 366 are located between spacer layers 119 and extend downward into isolation structure 140 and substrate 199.

[0085] return Figure 2 At operation 260, method 200 continues, wherein source and drain bodies are grown on the ends of the channel material layer. The source and drain bodies can be any suitable material and can be grown in any suitable manner. In many embodiments, the source and drain bodies are grown by epitaxially depositing a semiconductor material as a crystal body on the ends of the channel material layer. In many such embodiments, the source and drain bodies are grown by epitaxially depositing a very small amount of acceptor or donor impurities (e.g., as p-type or n-type dopant) with the semiconductor material. In many embodiments, the source and drain bodies are grown on the ends of the channel material after the sacrificial material is recessed backward from the ends. At operation 250, the laterally and vertically extending ends of the sacrificial material layer and the channel material layer can be exposed by etching. The recess etching can selectively remove the sacrificial material exposed at the layer ends. In some embodiments, a dielectric material is deposited at least adjacent to the channel material at the layer ends (e.g., between channel material layers in a material stack, replacing the sacrificial material).

[0086] Separate source and drain bodies can be grown at the ends of the lateral channel material layers and at the ends of the vertical sidewall channel material layers in the stack. For example, the first source and drain bodies grown at the ends of the lateral channel material layers (e.g., nanoribbons) in the stack can be as follows: Figure 1A As described in the source and drain bodies 111, and the second source and drain bodies grown on the ends of the vertical channel material layer (e.g., fins) can be as described in... Figure 1A The source and drain bodies 112 are as described above. The first source and drain bodies can be grown at the ends of each lateral channel material layer (e.g., nanoribbon) and can be merged into a single source or drain body for each material stack. The second source and drain bodies can be grown at the ends of each vertical channel material layer (e.g., fin) and can be merged into a single source or drain body for a set of fins.

[0087] For example, based on the conductivity type of the transistor structure, separate materials can be used to form the first source and drain bodies and the second source and drain bodies. In many embodiments, growing the first source and drain bodies includes epitaxially depositing a first semiconductor material and an acceptor impurity on the ends of a lateral channel material layer (e.g., nanoribbon), and growing the second source and drain bodies includes epitaxially depositing a second semiconductor material and a donor impurity on the ends of a vertical channel material layer (e.g., fin). In some embodiments, the first semiconductor material and the second semiconductor material are the same semiconductor material (e.g., a group IV semiconductor material, as per the description of the transistor structure). Figure 1A (as described above). In some embodiments, different semiconductor materials are used for the first semiconductor material and the second semiconductor material (e.g., silicon is used for the n-type source and drain bodies, and germanium or silicon-germanium is used for the p-type source and drain bodies).

[0088] Figure 3F Source and drain bodies 111, 112 are shown at the ends of channel material layers 320, 334 in a workpiece or device 100 after growth operation 260, according to some embodiments.

[0089] In view 303, layers 320, 323, 333, and 334 are still below masking layer 329 and are covered by dummy gate 358.

[0090] In the trench cutout view 304, source and drain bodies 111, 112 are located above the substrate 199 and on the isolation structure 140. Each stack body 322 has a single source or drain body 111, and a set of fins has a single source or drain body 112.

[0091] In view 305, the source and drain bodies 112 are in an opening 366 between layers 119, 329 and the vertical channel layer 334 (e.g., a fin). The source and drain bodies 112 are on the ends of layer 334 and on the isolation structure 140.

[0092] In view 306, spacer layer 119 is on the sidewall of hard mask 359. Source and drain bodies 112 are located above isolation structure 140 and substrate 199 in opening 366 between spacer layers 119.

[0093] return Figure 2Continuing with method 200, a lateral channel material layer and a vertical channel material layer are exposed at operation 270. The channel material layers can be exposed by removing the lateral and vertical sacrificial material layers. The sacrificial material layers can be removed by any suitable means, for example, by selective isotropic dry etching after removal of the dummy gate (and hard mask, in some embodiments). In many embodiments, the silicon-germanium sacrificial layer (e.g., lateral and vertical) is removed by selective etching relative to the silicon channel layer (e.g., nanoribbons and fins). In many embodiments, the exposed channel material layers in the stack (e.g., nanoribbons) have (100) top and bottom surfaces, and the exposed vertical channel material layers (e.g., fins) have (110) sidewall surfaces.

[0094] Figure 3G Exposed nanoribbons 120 and fins 130 are shown in a workpiece or device 100, for example, after an exposure operation 270 is performed, according to some embodiments.

[0095] In view 303, the nanoribbons 120 in the stack 122 (above the sub-fins 123) and the fins 130 on the isolation structure 140 are exposed.

[0096] In the trench cut view 304, the source and drain bodies 111, 112 are located above the substrate 199 and the isolation structure 140. The dielectric 114 is located above the source and drain bodies 111, 112 and on both sides of the source and drain bodies 111, 112, thereby filling the trench between the spacer layers.

[0097] In view 305, fin 130 is exposed over isolation structure 140. Source and drain bodies 112 are on the ends of fin 130 and on isolation structure 140. Layers 119 and 129 are on fin 130 adjacent to bodies 112. Dielectric 114 is located over source and drain bodies 112, thereby filling the space between spacer layers 119.

[0098] In view 306, nanoribbons 120 and fins 130 are exposed over the isolation structure 140. Spacer layers 119 are on the nanoribbons 120 and fins 130 adjacent to the bodies 111 and 112. Dielectric 114 is on the source and drain bodies 111 and 112 between the spacer layers 119.

[0099] return Figure 2 Method 200 continues by depositing gate material over the channel material layer at operation 280. The gate material can be any suitable material and can be deposited in any suitable manner. The gate material may include one or more suitable dielectric materials, for example, with... Figure 1AThe dielectric materials of the one or more gate dielectric layers 124 described are very similar. The gate material may include one or more suitable metals, for example, those similar to those in... Figure 1A The metals of the described gate electrodes 125 and 135 (including layers 126 and 136) are very similar. The gate metal can be deposited on a gate dielectric, which can be conformally deposited on a channel material layer. In many embodiments, a high-k dielectric layer is conformally deposited on the channel material layer. In some such embodiments, the high-k dielectric layer is conformally deposited on a thermally grown passivation layer on top of the channel material layer.

[0100] Seed and / or barrier metal, such as WFM, can be conformally deposited over the gate dielectric layer. In many embodiments, depositing gate material over a lateral channel material layer (e.g., nanoribbon) includes depositing an n-type WFM over the lateral channel material layer; and depositing gate material over a vertical channel material layer (e.g., fin) includes depositing a p-type WFM over the vertical channel material layer.

[0101] Figure 3H The diagram illustrates FET structures 101A / 101B, 102, which, according to some embodiments, have channel regions 121, 132 with nanoribbons 120 and fins 130, respectively, in an IC device 100 after performing deposition operation 280. The device 100 is substantially as follows: Figure 1A As described in the embodiments. It is worth noting that the FET structures 101A / 101B, 102 include a shared gate electrode 125 on the nanoribbon 120 and fin 130, which includes a common bulk or fill metal of the electrode 125 on the respective metal layers 126, 136.

[0102] In view 303, nanoribbons 120 and fins 130 in stack 122 extend through electrode 125. Fin 130 is located on isolation structure 140. FET structures 101A / 101B include an n-WFM layer 126 on gate dielectric layer 124. FET structure 102 includes a p-WFM layer 136 on gate dielectric layer 124.

[0103] In the trench cut view 304, contact structures 115, 116 are located on and above the source and drain bodies 111, 112, and extend through the insulating dielectric 114. The dielectric 114 is located on and on both sides of the source and drain bodies 111, 112, thereby filling the trench between the spacer layers.

[0104] In view 305, the gate electrode 125 is located above the fin 130 and is separated from the fin 130 by the gate dielectric layer 124. The metal layer 126 is on layer 124. The gate dielectric layer 124 is conformally located on the spacer layer 119.

[0105] In view 306, the stripe of the gate electrode 125 is above the nanoribbon 120 and the fin 130. Contact structures 115 and 116 are located above and through the insulating dielectric 114 in the trench between the electrodes 125. A spacer layer 119 is between the electrodes 125 and the structures 115 and 116. The insulating dielectric 114 is between the electrodes 125.

[0106] IC device 100 may include a substrate or other host component 399, or may be coupled to a substrate or other host component 399. Host component 399 may be a package substrate, an interposer, an IC die, etc. For example, substrate 199 may be an IC die including transistor structures 101A / 101B, substrate 199 may be coupled (e.g., soldered or otherwise bonded) to host component 399, and transistor structures 101A / 101B may be coupled to a power source (not shown) through host component 399.

[0107] The host component 399 is a planar platform and may include dielectric and metallization structures. The host component 399 mechanically supports and electrically couples one or more IC devices 100. At least one side of the host component 399 includes a substrate interconnect interface for bonding to one or more IC devices 100. The IC devices 100 may be directly bonded to the host component 399, for example, via optional solder bumps (e.g., hybrid bonding) or otherwise. The opposite side of the host component 399 may include similar interfaces, such as copper pads for connecting device 100 sockets to a host component (such as a printed circuit board (PCB)) and / or solder bumps for bonding device 100 to a host component (such as a printed circuit board (PCB)). The host component 399 can be any host component having a substrate interconnect interface, such as a packaged host component 399 or an interposer. The host component 399 itself may be a die. In many embodiments, the host component 399 includes one or more organic dielectrics, such as resins or other polymers, between metallization layers.

[0108] Figure 4 A diagram is shown of an example data server machine 406 employing an IC device according to some embodiments, wherein the IC device has nanoribbons and fins as channels in adjacent transistors. Server machine 406 can be any commercial server, for example, including any number of high-performance computing platforms housed in a rack and networked together for electronic data processing. In an exemplary embodiment, server machine 406 includes one or more devices 450 having nanoribbons and fins as channels in adjacent transistors.

[0109] As also shown in the figures, server machine 406 includes a battery and / or power supply 415 to provide power to device 450 and, in some embodiments, provides power delivery functions such as power regulation. Device 450 may be deployed as part of package-level integrated system 410. Integrated system 410 is further shown in unfolded figure 420. In an exemplary embodiment, device 450 (labeled “memory / processor”) includes at least one processor chip (e.g., a microprocessor, multi-core microprocessor, or graphics processor, etc.) and / or at least one memory chip (e.g., random access memory (RAM)) having the characteristics discussed herein. In an embodiment, device 450 is a microprocessor including static RAM (SRAM) cache memory. As shown, device 450 may be an IC device having nanoribbons and fins as channels in adjacent transistors, as discussed herein. Device 450, together with one or more of the following: power management IC (PMIC) 430, RF (radio) IC (RFIC) 425 including a broadband RF (radio) transmitter and / or receiver (TX / RX) (e.g., including a digital baseband, and the analog front-end module further including a power amplifier on the transmit path and a low-noise amplifier on the receive path), and controller 435, may be further coupled (e.g., communicatively coupled to) a board, interposer, or other substrate or host component 399. In some embodiments, RFIC 425, PMIC 430, controller 435, and device 450 have nanostrips and fins as channels in adjacent transistors.

[0110] Figure 5 This is a block diagram of an example computing device 500 according to some embodiments. For example, one or more components of computing device 500 may include any of the devices or structures discussed herein. Multiple components in Figure 5 The components are illustrated as being included in computing device 500, but any one or more of these components may be omitted or copied to suit an application. In some embodiments, some or all of the components included in computing device 500 may be attached to one or more printed circuit boards (e.g., a motherboard). In some embodiments, various components of these components may be fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, computing device 500 may not include... Figure 5The computing device 500 may include one or more of the components shown, but may include interface circuitry for coupling to said one or more components. For example, the computing device 500 may not include display device 503, but may include display device interface circuitry (e.g., connector and driver circuitry) to which display device 503 may be coupled. In another set of examples, the computing device 500 may not include audio output device 504, other output device 505, GPS device 509, audio input device 510, or other input device 511, but may include audio output device interface circuitry, other output device interface circuitry, GPS device interface circuitry, audio input device interface circuitry, and other input device interface circuitry to which audio output device 504, other output device 505, GPS device 509, audio input device 510, or other input device 511 may be coupled.

[0111] Computing device 500 may include processing device 501 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" refers to a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. Processing device 501 may include memory 521, communication device 522, cooling device 523, battery / power conditioning device 524, logic 525, interconnect 526 (i.e., optionally including redistribution layer (RDL) or metal-insulator-metal (MIM) devices), thermal regulation device 527, and hardware security device 528.

[0112] Processing device 501 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing device.

[0113] Computing device 500 may include memory 502, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drive. In some embodiments, memory 502 includes memory that shares a die with processing device 501. The memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0114] The computing device 500 may include a thermal regulator / cooling device 506. The thermal regulator / cooling device 506 can maintain the processing device 501 (and / or other components of the computing device 500) at a predetermined low temperature during operation.

[0115] In some embodiments, computing device 500 may include communication chip 507 (e.g., one or more communication chips). For example, communication chip 507 may be configured to manage wireless communication to facilitate the transmission of data to and from computing device 500. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data via a non-solid medium using modulated electromagnetic radiation. This term does not imply that the associated devices do not contain any wiring, although in some embodiments they may not contain wiring.

[0116] The 507 communication chip can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), Long Term Evolution (LTE) projects, and any amendments, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are often referred to as WiMAX networks. WiMAX is an acronym for Global Microwave Access Interoperability, a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. The 507 communication chip can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. Communication chip 507 may operate according to Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication chip 507 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, as well as any other wireless protocol designated 3G, 4G, 5G, and above. In other embodiments, communication chip 507 may operate according to other wireless protocols. Computing device 500 may include antenna 513 to facilitate wireless communication and / or receiving other wireless communications (such as AM or FM radio transmissions).

[0117] In some embodiments, communication chip 507 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, communication chip 507 may include multiple communication chips. For example, a first communication chip 507 may be dedicated to short-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication chip 507 may be dedicated to long-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 507 may be dedicated to wireless communications, and the second communication chip 507 may be dedicated to wired communications.

[0118] The computing device 500 may include a battery / power circuit 508. The battery / power circuit 508 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the computing device 500 to an energy source (e.g., AC line power) separate from the computing device 500.

[0119] The computing device 500 may include a display device 503 (or a corresponding interface circuit, as described above). For example, the display device 503 may include any visual indicator, such as a head-up display, computer monitor, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0120] The computing device 500 may include an audio output device 504 (or a corresponding interface circuit, as described above). For example, the audio output device 504 may include any device that generates audible indicators, such as a speaker, headphones, or earphones.

[0121] The computing device 500 may include an audio input device 510 (or a corresponding interface circuit, as described above). The audio input device 510 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0122] The computing device 500 may include a GPS device 509 (or a corresponding interface circuit, as described above). The GPS device 509 may communicate with a satellite-based system and may receive the location of the computing device 500, as is known in the art.

[0123] The computing device 500 may include other output devices 505 (or corresponding interface circuitry, as described above). Examples of other output devices 505 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0124] The computing device 500 may include other input devices 511 (or corresponding interface circuitry, as described above). Examples of other input devices 511 may include accelerometers, gyroscopes, compasses, image capture devices, keyboards, cursor control devices (such as mice), styluses, touchpads, barcode readers, quick-response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0125] Computing device 500 may include a security interface device 512. Security interface device 512 may include any device that provides security measures for computing device 500, such as intrusion detection, biometric authentication, secure encoding or decoding, access list management, malware detection, or spyware detection.

[0126] The computing device 500 or a subset of its components may have any suitable form factor, such as a handheld or mobile computing device (e.g., a cellular phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device.

[0127] The subject matter of this instruction manual is not limited to Figures 1A-5 The specific application shown is illustrated. This subject matter can be applied to other deposition applications as well as any suitable manufacturing applications, as those skilled in the art will understand.

[0128] The following examples relate to further embodiments, and the details in the examples may be used anywhere in one or more embodiments.

[0129] In one or more first embodiments, an apparatus includes: a first channel region including a stack of nanoribbons on a substrate between a first source and drain body of a first pair in a first transistor structure; and a second channel region including one or more fins between a second source and drain body of a second pair in a second transistor structure, the one or more fins being substantially vertical and substantially orthogonal to the nanoribbons, the one or more fins being on a dielectric structure on the substrate.

[0130] In one or more second embodiments further according to the first embodiment, the upper surface of the first nanoribbon in the nanoribbon is a (100) surface, and the sidewall of the first fin in one or more fins is a (110) surface.

[0131] In one or more third embodiments further according to the first or second embodiment, the dielectric structure is a first dielectric structure, the nanoribbon stack is on the sub-fin, the substrate includes the sub-fin, and the sub-fin is between the first dielectric structure and the second dielectric structure on the substrate.

[0132] In one or more fourth embodiments further according to the first to third embodiments, the sub-fin is a first sub-fin, the nanoribbon stack is a first stack of nanoribbons on the first sub-fin, and the first dielectric structure is between the first stack of nanoribbons on the first sub-fin and the second stack of nanoribbons on the second sub-fin.

[0133] In one or more fifth embodiments further according to the first to fourth embodiments, the first fin and the second fin of one or more fins are between the second source and drain bodies of the second pair, and the second transistor structure includes a gate electrode on the first fin and the second fin.

[0134] In one or more sixth embodiments further according to the first to fifth embodiments, the first source and drain bodies of the first pair include donor impurities, and the second source and drain bodies of the second pair include acceptor impurities.

[0135] In one or more seventh embodiments according to the first to sixth embodiments, the first transistor structure includes a first gate electrode through which a nanoribbon extends, the first gate electrode comprising an n-type work function metal (WFM), and the second transistor structure includes a second gate electrode on one or more fins, the second gate electrode comprising a p-type WFM.

[0136] In one or more eighth embodiments further according to the first to seventh embodiments, the first upper surface of the one or more fins is at a first height above the second height of the second upper surface of the nanoribbon stack.

[0137] In one or more ninth embodiments according to the first to eighth embodiments, the distance between the stack of nanoribbons and the one or more fins is greater than the width of the first fin among the one or more fins and less than twice the width of the first fin among the one or more fins.

[0138] In one or more tenth embodiments, an apparatus includes: a first transistor structure, a second transistor structure, and a third transistor structure on a substrate; a first stack of lateral nanoribbons in the first transistor structure and a second stack of lateral nanoribbons in the second transistor structure, the first stack of lateral nanoribbons being on a first sub-fin and between a first source and drain body of a first pair, the second stack of lateral nanoribbons being on a second sub-fin and between a second pair of first source and drain bodies, the substrate including the first sub-fin and the second sub-fin; and a vertical nanoribbon between a second source and drain body of a third pair in the third transistor structure between the first transistor structure and the second transistor structure, the vertical nanoribbon being on a dielectric structure in a trench on the substrate, the trench being between the first sub-fin and the second sub-fin.

[0139] In one or more eleventh embodiments further according to the tenth embodiment, the upper surface of the first transverse nanoribbon in the transverse nanoribbon is a (100) surface, and the sidewall of the vertical nanoribbon is a (110) surface.

[0140] In one or more twelfth embodiments according to the tenth or eleventh embodiment, the first source and drain bodies comprise n-type dopants, and the second source and drain bodies comprise p-type dopants.

[0141] In one or more thirteenth embodiments according to the tenth to twelfth embodiments, an n-type work function metal (WFM) is on and between the transverse nanoribbons in the first and second stacks of transverse nanoribbons, and a p-type WFM is on the vertical nanoribbons.

[0142] In one or more fourteenth embodiments according to the tenth to thirteenth embodiments, the device further includes a host component, the substrate being coupled to the host component, and the first, second, and third transistor structures being coupled to a power source through the host component.

[0143] In one or more fifteenth embodiments, a method includes: depositing a barrier material over a first sidewall of a material stack, the first sidewall being opposite an exposed second sidewall of the material stack, the material stack including alternating layers of channel material and sacrificial material; growing a third layer of sacrificial material over the second sidewall and the first and second layers; growing a fourth layer of channel material over the third layer of sacrificial material; exposing the first and fourth layers of channel material by removing the second and third layers of sacrificial material; and depositing a gate material over the first and fourth layers of channel material.

[0144] In one or more of the sixteenth embodiments according to the fifteenth embodiment, a fourth layer of channel material is grown on the third layer of the sacrificial material to have a sidewall (110) surface, and the first layer of the first layer of the channel material of the material stack includes an upper (100) surface.

[0145] In one or more of the seventeenth embodiments according to the fifteenth or sixteenth embodiments, growing the third layer includes epitaxially depositing a sacrificial material on the second sidewall of the material stack and on the first and second layers, and growing the fourth layer includes epitaxially depositing a channel material on the third layer of sacrificial material, the material stack of the first and second layers being above a crystal substrate, and the lattice structure being continuous from the crystal substrate through the material stack of the first and second layers to the third and fourth layers.

[0146] In one or more of the eighteenth embodiments according to the fifteenth to seventeenth embodiments, the third and fourth layers are grown on an isolation structure adjacent to the sub-fin below the material stack, and a crystal substrate is below the isolation structure, the crystal substrate including the sub-fin.

[0147] In one or more nineteenth embodiments according to the fifteenth to eighteenth embodiments, the method further includes growing a first source and drain body on a first end of a first layer and growing a second source and drain body on a second end of a fourth layer, wherein growing the first source and drain body on the first end of the first layer includes epitaxially depositing a first semiconductor material and an acceptor impurity on the first end of the first layer, and growing the second source and drain body on the second end of the fourth layer includes epitaxially depositing a second semiconductor material and a donor impurity on the second end of the second layer.

[0148] In one or more twentieth embodiments further according to the fifteenth to nineteenth embodiments, the material stack is a first material stack, a third layer of sacrificial material is grown on the second sidewall of the first material stack and on the first and second layers, a fifth layer of sacrificial material is grown on the third sidewall of the second material stack, the third, fourth and fifth layers are between the first and second material stacks, the fourth layer is between the third and fifth layers, a fourth layer of channel material is grown on the third layer of sacrificial material, a sixth layer of channel material is grown on the fifth layer of sacrificial material on the third sidewall of the second material stack, the fourth and sixth layers are between the third and fifth layers, and the method further includes growing a seventh layer of sacrificial material between the fourth and sixth layers.

[0149] This disclosure can be practiced through modifications and alterations, and the scope of the appended claims is not limited to the embodiments described herein. For example, the above embodiments may include specific combinations of features. However, the above embodiments are not limiting in this respect, and in various implementations, the above embodiments may include only a subset of such features, different orders of such features, different combinations of such features, and / or additional features different from those expressly listed. Therefore, the scope of the patent right should be determined with reference to the appended claims and the full scope of their equivalents.

Claims

1. An apparatus comprising: A first channel region, the first channel region including a stack of nanoribbons on a substrate, the stack of nanoribbons between a first source and drain body of a first pair in a first transistor structure; as well as The second channel region includes one or more fins between the second source and drain bodies of the second pair in the second transistor structure, the one or more fins being substantially vertical and substantially orthogonal to the nanoribbon erected on the dielectric structure above the substrate.

2. The apparatus according to claim 1, wherein: The upper surface of the first nanoribbon in the nanoribbon is a (100) surface; and The sidewall of the first fin of the one or more fins is the (110) surface.

3. The apparatus according to claim 1, wherein: The dielectric structure is a first dielectric structure; The nanoribbons are stacked on top of the sub-fin, and the substrate includes the sub-fin; and The sub-fin is located between the first dielectric structure and the second dielectric structure on the substrate.

4. The apparatus according to claim 3, wherein, The sub-fin is a first sub-fin, the nanoribbon stack is a first stack of nanoribbons on the first sub-fin, and the first dielectric structure is located between the first stack of nanoribbons on the first sub-fin and the second stack of nanoribbons on the second sub-fin.

5. The apparatus according to claim 4, wherein, The first and second fins of the one or more fins are located between the second source and drain bodies of the second pair, and the second transistor structure includes a gate electrode on the first and second fins.

6. The apparatus according to any one of claims 1 to 5, wherein, The first source and drain bodies of the first pair include donor impurities, and the second source and drain bodies of the second pair include acceptor impurities.

7. The apparatus according to any one of claims 1 to 5, wherein: The first transistor structure includes a first gate electrode; The nanoribbon extends through the first gate electrode; The first gate electrode comprises an n-type work function metal (WFM); The second transistor structure includes a second gate electrode on the one or more fins; and The second gate electrode includes a p-type WFM.

8. The apparatus according to any one of claims 1 to 5, wherein, The first upper surface of the one or more fins is located at a first height above the second upper surface of the nanoribbon stack.

9. The apparatus according to any one of claims 1 to 5, wherein, The distance between the stack of nanoribbons and the one or more fins is greater than the width of the first fin among the one or more fins, and less than twice the width of the first fin among the one or more fins.

10. A system comprising: A first channel region, the first channel region including a stack of nanoribbons on a substrate, the stack of nanoribbons between a first source and drain body of a first pair in a first transistor structure; The second channel region includes one or more fins, which are located between the second source and drain bodies of the second pair in the second transistor structure. The one or more fins are substantially vertical and substantially orthogonal to the nanoribbon and are located on the dielectric structure above the substrate. A host component, the host component being coupled to the substrate; as well as A power supply, which is coupled to the first transistor structure and the second transistor structure via the host component.

11. The system according to claim 10, wherein: The upper surface of the first nanoribbon in the nanoribbon is a (100) surface; and The sidewall of the first fin of the one or more fins is the (110) surface.

12. The system according to claim 10, wherein: The dielectric structure is a first dielectric structure; The nanoribbons are stacked on top of the sub-fin, and the substrate includes the sub-fin; and The sub-fin is located between the first dielectric structure and the second dielectric structure on the substrate.

13. The system according to claim 12, wherein, The sub-fin is a first sub-fin, the nanoribbon stack is a first stack of nanoribbons on the first sub-fin, and the first dielectric structure is located between the first stack of nanoribbons on the first sub-fin and the second stack of nanoribbons on the second sub-fin.

14. The system according to claim 13, wherein, The first and second fins of the one or more fins are located between the second source and drain bodies of the second pair, and the second transistor structure includes a gate electrode on the first and second fins.

15. The system according to any one of claims 10 to 14, wherein, The first source and drain bodies of the first pair include donor impurities, and the second source and drain bodies of the second pair include acceptor impurities.

16. The system according to any one of claims 10 to 14, wherein: The first transistor structure includes a first gate electrode; The nanoribbon extends through the first gate electrode; The first gate electrode comprises an n-type work function metal (WFM); The second transistor structure includes a second gate electrode on the one or more fins; and The second gate electrode includes a p-type WFM.

17. The system according to any one of claims 10 to 14, wherein, The first upper surface of the one or more fins is located at a first height above the second upper surface of the nanoribbon stack.

18. The system according to any one of claims 10 to 14, wherein, The distance between the stack of nanoribbons and the one or more fins is greater than the width of the first fin among the one or more fins, and less than twice the width of the first fin among the one or more fins.

19. A method comprising: A barrier material is deposited on a first sidewall of a material stack, the first sidewall being opposite to an exposed second sidewall of the material stack, the material stack comprising a first layer of alternating channel material and a second layer of sacrificial material; A third layer of the sacrificial material is grown on the second sidewall and on the first and second layers; A fourth layer of the channel material is grown on the third layer of the sacrificial material; The first and fourth layers of the channel material are exposed by removing the second and third layers of the sacrificial material; as well as A gate material is deposited on the first and fourth layers of the channel material.

20. The method according to claim 19, wherein, The fourth layer of the channel material is grown on the third layer of the sacrificial material to grow the fourth layer of the channel material to have a sidewall (110) surface, and the first layer of the first layer of the channel material of the material stack includes an upper (100) surface.

21. The method according to claim 19, wherein: Growing the third layer involves epitaxially depositing the sacrificial material on the second sidewall of the material stack and on the first and second layers of the material stack. Growing the fourth layer involves epitaxially depositing the channel material on the third layer of the sacrificial material; The material stack of the first and second layers is on a crystalline substrate; and The lattice structure is continuous from the crystal substrate, through the material stack of the first and second layers, and to the third and fourth layers.

22. The method according to claim 19, wherein: The third and fourth layers are grown on an isolation structure adjacent to the sub-fin below the material stack; and A crystal substrate is located beneath the isolation structure, and the crystal substrate includes the sub-fin.

23. The method according to any one of claims 19 to 22, further comprising growing a first source and drain body on a first end of the first layer, and growing a second source and drain body on a second end of the fourth layer, wherein: Growing the first source and drain bodies on the first end of the first layer includes epitaxially depositing a first semiconductor material and an acceptor impurity on the first end of the first layer; and Growing the second source and drain bodies on the second end of the fourth layer includes epitaxially depositing a second semiconductor material and donor impurities on the second end of the second layer.

24. The method according to any one of claims 19 to 22, wherein: The material stack is a first material stack; The third layer of the sacrificial material is grown on the second sidewall of the first material stack and on the first and second layers of the first material stack. The fifth layer of the sacrificial material is grown on the third sidewall of the second material stack. The third, fourth and fifth layers are between the first and second material stacks. The fourth layer is between the third and fifth layers. A fourth layer of channel material is grown on the third layer of the sacrificial material; a sixth layer of channel material is grown on the fifth layer of the sacrificial material on the third sidewall of the second material stack, with the fourth and sixth layers between the third and fifth layers; and The method further includes growing a seventh layer of the sacrificial material between the fourth and sixth layers.

Images