LED chip assembly and preparation method thereof

Abstract

The invention discloses an LED chip assembly and a preparation method thereof, and the method comprises the steps: providing an epitaxial wafer which comprises a substrate and an epitaxial layer, and forming a reflection bonding metal layer on the epitaxial layer; bonding the reflective bonding metal layer with the driving substrate, and removing the substrate; etching the epitaxial layer to form a plurality of epitaxial step structures; etching the reflective bonding metal layer to form a plurality of bonding step structures in one-to-one correspondence with the epitaxial step structures; depositing a reflection passivation layer on the epitaxial layer, wherein the reflection passivation layer extends from the top surface of the epitaxial step structure to the side surface of the epitaxial step structure; etching the reflection passivation layer corresponding to the top surface of the epitaxial step structure so as to completely expose the top surface of the epitaxial step structure; and depositing a common N electrode layer on the epitaxial step structure and the reflective passivation layer, wherein the common N electrode layer extends from the top surface of the epitaxial step structure to the side surface of the reflective passivation layer. According to the LED chip assembly prepared through the method, the brightness of the light-emitting chip is greatly improved, the light divergence angle is small, and light rays are concentrated.

Description

Technical Field

[0001] This application relates to the display field, and more particularly to an LED chip assembly and its fabrication method. Background Technology

[0002] Vertical LED chips refer to LEDs with two electrodes located on opposite sides of the epitaxial wafer. A patterned electrode and the entire p-type confinement layer serve as the second electrode, ensuring that almost all current flows vertically through the LED epitaxial layer, with very little lateral current. Vertical LED chips offer significant advantages over horizontal LED chips: higher anti-static capability, micron-level fabrication capability, and the use of high thermal conductivity substrates (such as Si, Ge, and SiC) instead of sapphire substrates, greatly improving heat dissipation efficiency. The two electrodes of a vertical LED chip are located on opposite sides of the LED epitaxial layer, and the n-electrode ensures that almost all current flows vertically through the LED epitaxial layer, with minimal lateral current, thus avoiding localized high temperatures. A typical simplified fabrication process for vertical LED chips includes: after MESA patterning and etching, sequentially performing bonding metal etching, SiO2 passivation layer deposition, passivation layer etching, and co-N ITO film deposition, ultimately obtaining the vertical LED chip wafer. The bonding metals are primarily ITO and composite metal films such as Au, Pt, and Sn. Thin films of metallic materials such as Au, Pt, and Sn exhibit a certain degree of light absorption, resulting in light intensity loss when light emitted from vertically structured LED chips passes through these films. SiO2 passivation films are transparent inorganic films. During the passivation film etching process, a micro-hole is opened on the top of the chip. Current flows from the common NiTiO2 through this micro-hole to the epitaxial layer for light emission. This narrow current transmission channel leads to current concentration and low current transmission efficiency. When a vertically structured LED chip emits light, the light diffuses through the top surface of the chip, resembling spherical emission. This divergence and poor concentration result in low luminous efficiency, brightness loss, and light divergence in the final chip. Summary of the Invention

[0003] In view of the shortcomings of the above-mentioned related technologies, the purpose of this application is to provide an LED chip component and its preparation method, which greatly improves the brightness of the light-emitting chip, has a small light divergence angle, and concentrates the light.

[0004] This application provides a method for fabricating an LED chip assembly, the steps of which include: An epitaxial wafer is provided, the epitaxial wafer including a substrate and an epitaxial layer disposed on the substrate, wherein a reflective bonding metal layer is formed on the side of the epitaxial layer away from the substrate; The reflective bonding metal layer is bonded to the driving substrate, and the substrate is removed; The epitaxial layer is etched to form multiple epitaxial step structures; The reflective bonding metal layer is etched to form multiple bonding step structures that correspond one-to-one with the epitaxial step structure; A reflective passivation layer is deposited on the epitaxial layer, the reflective passivation layer extending from the top surface of the epitaxial stepped structure to the side surface of the epitaxial stepped structure; The reflective passivation layer corresponding to the top surface of the epitaxial stepped structure is etched away so that the top surface of the epitaxial stepped structure is fully exposed. A common N-electrode layer is deposited on the epitaxial stepped structure and the reflective passivation layer, the common N-electrode layer extending from the top surface of the epitaxial stepped structure to the side surface of the reflective passivation layer.

[0005] Optionally, the orthographic projection of the epitaxial step structure is located on the bonding step structure, and the reflective passivation layer also extends from the side of the epitaxial step to the top and side surfaces of the bonding step structure.

[0006] Optionally, the reflective bonding metal layer is a multilayer structure, which includes Cr, Au, Sn, Au, Pt, sub-multilayer structures and ITO arranged from bottom to top. Each layer of the sub-multilayer structure contains Ag and Ti arranged from bottom to top, and the number of layers of the sub-multilayer structure is 3-5.

[0007] Optionally, the thickness of Ag can be in the range of 10nm-50nm, and the thickness of Ti can be in the range of 5-10nm.

[0008] Optionally, the reflective passivation layer is a distributed Bragg mirror or a full-angle mirror.

[0009] Optionally, the common N electrode layer is an ITO transparent conductive film.

[0010] Optionally, the LED chip assembly is a Mini LED chip assembly or a Micro LED chip assembly.

[0011] This application also provides an LED chip assembly, which is fabricated using the LED chip assembly fabrication method described above. The assembly includes a driving substrate, a reflective bonding metal layer, an epitaxial layer, a reflective passivation layer, and a common N-electrode layer. The reflective bonding metal layer is disposed on the driving substrate, and the epitaxial layer is disposed on the reflective bonding metal layer and bonded to the reflective bonding metal layer. The epitaxial layer is configured as an epitaxial step structure, and the reflective passivation layer extends from the top surface of the epitaxial step structure to the side surface of the epitaxial step structure.

[0012] Optionally, the orthographic projection of the epitaxial step structure is located on the bonding step structure, and the reflective passivation layer also extends from the side of the epitaxial step to the top and side surfaces of the bonding step structure.

[0013] Optionally, the reflective bonding metal layer is a multilayer structure, which includes Cr, Au, Sn, Au, Pt, sub-multilayer structures and ITO arranged from bottom to top. Each layer of the sub-multilayer structure contains Ag and Ti arranged from bottom to top, and the number of layers of the sub-multilayer structure is 3-5.

[0014] The LED chip assembly and manufacturing method of this application produce a light-emitting chip that emits light only from the top, sides and bottom of the chip with no light loss. The top has a large current transmission surface and high current transmission efficiency, which can greatly improve the brightness of the light-emitting chip. The light emission direction is close to perpendicular to the surface of the light-emitting chip, with a small light divergence angle and concentrated light. Attached Figure Description

[0015] Figure 1 A flowchart illustrating a method for manufacturing an LED chip assembly is provided for embodiments of this application. Figure 2 A schematic diagram illustrating the structure of the LED chip assembly fabrication method provided in this application embodiment; Figure 3 This is a schematic diagram of the structure of an LED chip assembly provided in an embodiment of this application.

[0016] Explanation of reference numerals in the attached figures: 1-Driving substrate; 2-Reflective bonding metal layer; 3-Epipolar layer; 4-Reflective passivation layer; 5-Common N-electrode layer. Detailed Implementation

[0017] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0019] In the description of this application, the terms "first," "second," etc., are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0020] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. The illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0021] The specific embodiments of this application will be further described below with reference to the accompanying drawings.

[0022] See Figure 1 and Figure 2 As shown, this application discloses a method for fabricating an LED chip assembly, the steps of which include: An epitaxial wafer is provided, the epitaxial wafer including a substrate and an epitaxial layer disposed on the substrate, wherein a reflective bonding metal layer is formed on the side of the epitaxial layer away from the substrate; The reflective bonding metal layer is bonded to the driving substrate, and the substrate is removed; The epitaxial layer 3 is etched to form multiple epitaxial step structures; The reflective bonding metal layer 2 is etched to form a plurality of bonding step structures that correspond one-to-one with the epitaxial step structure; A reflective passivation layer 4 is deposited on the epitaxial layer 3, the reflective passivation layer 4 extending from the top surface of the epitaxial stepped structure to the side surface of the epitaxial stepped structure; The reflective passivation layer 4 corresponding to the top surface of the epitaxial step structure is etched away so that the top surface of the epitaxial step structure is completely exposed. A common N-electrode layer 5 is deposited on the epitaxial stepped structure and the reflective passivation layer 4, the common N-electrode layer 5 extending from the top surface of the epitaxial stepped structure to the side surface of the reflective passivation layer 4.

[0023] Photoresist is coated on the surface of the reflective passivation layer 4. The reflective passivation layer 4 corresponding to the top surface of the epitaxial step structure is etched away according to the mask so that the top surface of the epitaxial step structure is completely exposed and the side reflective structure is almost undamaged. In this process, the etching procedure can be optimized and the etching rate ratio of photoresist and high reflective passivation film can be adjusted to be close to 1:1. The etching endpoint can be determined by detecting the characteristic signal of Ga, a characteristic element of epitaxial material, through the endpoint detection system. After etching using the above scheme, the integrity of the core structure can be guaranteed, and the mesa of the epitaxial layer 3 is completely exposed.

[0024] The LED chip assembly produced by this method emits light only from the top of the light-emitting chip. By setting a reflective bonding metal layer 2 and a reflective passivation layer 4, there is no light loss on the sides and bottom. The top current transmission surface is large and the current transmission efficiency is high, which can greatly improve the brightness of the light-emitting chip. The light emission direction is close to perpendicular to the surface of the light-emitting chip, the light divergence angle is small, and the light is concentrated.

[0025] In this embodiment, the orthographic projection of the epitaxial step structure is located on the bonding step structure, and the reflective passivation layer 4 extends from the side of the epitaxial step to the top and side surfaces of the bonding step structure.

[0026] In this embodiment, the reflective bonding metal layer 2 is a multilayer structure, comprising Cr, Au, Sn, Au, Pt, sub-multilayer structures, and ITO arranged from bottom to top. Each layer of the sub-multilayer structure contains Ag and Ti arranged from bottom to top, and the number of layers in the sub-multilayer structure is 3-5. This application significantly reduces the absorption of light by the light-emitting chip by the bonding metal by changing the type and structure of the bonding metal and introducing high-reflectivity metals such as Ag and Ti without reducing the conductivity of the metal. This multilayer structure can improve the reflectivity of light, and the design of the multilayer structure can reduce the stress difference caused by changes in the type and thickness of the film layers. At the same time, Ti near the top layer can also block the diffusion of Ag ions to the epitaxial layer 3. This improvement can improve the light reflection of the light-emitting chip, reduce the loss of light emitted by the light-emitting chip during the reflection process of the bottom bonding metal, and will not lose conductivity due to the introduction of new metals. The bonding process will not be seriously affected by the introduction of new metal materials.

[0027] In this embodiment, the thickness of Ag ranges from 10nm to 50nm, and the thickness of Ti ranges from 5nm to 10nm.

[0028] In this embodiment, the reflective passivation layer 4 is a distributed Bragg reflector (DBR) film or a full-angle reflector (ODR). Both DBRs and ORRs are high-reflectivity passivation film materials. After deposition, they can form a reflective structure on the sidewall of a vertically structured light-emitting chip. The light emitted from the light-emitting chip, after being excited by the quantum well, will be repeatedly reflected on the sidewall of the epitaxial layer 3, without any light loss. The main structure of a DBR is a cyclically stacked SiO2 and TiO2 material, while the main structure of an ORR is a reflective film combined with a metal thin film.

[0029] The passivation layer etching process incorporates full-surface filling and etching. An EPD endpoint detection system accurately controls the etching endpoint, ensuring the top of epitaxial layer 3 is completely exposed. However, the sidewalls of epitaxial layer 3 are still protected by the high-reflectivity passivation layer 4. This firstly increases the contact area between the top epitaxial layer 3 and ITO, thereby improving current transmission efficiency. Simultaneously, this etching scheme ensures that the light-emitting chip emits light only from the top, guaranteeing that the excitation light is emitted perpendicularly and correcting the light divergence angle. In this scheme, the high-reflectivity passivation film material reduces light emission loss from the sides of epitaxial layer 3. The bottom of epitaxial layer 3, being a high-reflectivity metal surface, also blocks light from emanating from the bottom, resulting in multiple reflections before the light finally reaches the target emission surface. Furthermore, the development of full-surface etching technology for the high-reflectivity passivation layer 4 increases the current transmission area, preventing current concentration and the resulting thermal emission that reduces quantum efficiency.

[0030] In this embodiment, the common N electrode layer 5 is an ITO transparent conductive film. By configuring the common N electrode layer 5 as an ITO transparent conductive film, a light-emitting chip with high brightness and convergent divergence angle is obtained. In other embodiments, the material of the common N electrode layer 5 can also be one or more of Cr, Ti, Pt, Au, Al, Cu, Ge, and Ni, and is not limited thereto.

[0031] In this embodiment, the LED chip assembly is a Mini LED chip assembly or a Micro LED chip assembly. In some embodiments, the LED chip assembly may also be a nano LED or an LED chip assembly of other sizes; this is not limited here, and the specific choice can be made according to the actual situation.

[0032] See Figure 3 As shown, this application also discloses an LED chip assembly, which is fabricated using the above-described LED chip assembly fabrication method. It includes a driving substrate 1, a reflective bonding metal layer 2, an epitaxial layer 3, a reflective passivation layer 4, and a common N-electrode layer 5. The reflective bonding metal layer 2 is disposed on the driving substrate 1, and the epitaxial layer 3 is disposed on and bonded to the reflective bonding metal layer 2. The epitaxial layer 3 is configured as an epitaxial step structure, and the reflective passivation layer 4 extends from the top surface of the epitaxial step structure to the side surface of the epitaxial step structure.

[0033] In this embodiment, the orthographic projection of the epitaxial step structure is located on the bonding step structure, and the reflective passivation layer 4 extends from the side of the epitaxial step to the top and side surfaces of the bonding step structure.

[0034] In this embodiment, the reflective bonding metal layer 2 is a multilayer structure, which includes Cr, Au, Sn, Au, Pt, sub-multilayer structures and ITO arranged from bottom to top. Each layer of the sub-multilayer structure contains Ag and Ti arranged from bottom to top, and the number of layers of the sub-multilayer structure is 3-5.

[0035] In this embodiment, the driving substrate 1 can be a silicon-based CMOS backplane or a TFT field-effect transistor display substrate.

[0036] In this embodiment, the substrate can be a growth substrate or a temporary substrate. For example, the epitaxial wafer can be a GaN-based blue-green light epitaxial wafer, with a sapphire growth substrate, a U-type GaN sacrificial layer, and a functional layer consisting of a sequentially stacked N-type GaN layer, an active layer, and a P-type GaN layer. As another example, the epitaxial wafer can be an aluminum indium phosphide (AIP)-based red light epitaxial wafer, with a sapphire temporary substrate, a BCB adhesive, GaN, or silicon carbide sacrificial layer, and a sequentially stacked P-type AlInP (or AlGaInP) layer, an active layer, and an N-type AlInP (or AlGaInP) layer. It is understood that regardless of whether the functional layer corresponds to blue-green or red light, the substrate can be a temporary substrate, and this application does not limit this.

[0037] In this embodiment, the epitaxial layer 3 includes a first semiconductor layer, an active layer, and a second semiconductor layer. The first semiconductor layer is connected to the common N-electrode layer 5, and the second semiconductor layer is connected to the reflective bonding metal layer 2. The first semiconductor layer can be an N-doped semiconductor layer or a P-doped semiconductor layer, and the second semiconductor layer can be a P-doped semiconductor layer or an N-doped semiconductor layer. The active layer can be a multiple quantum well (MQW) structure. Specifically, the aforementioned semiconductor layer can be a III-V group compound semiconductor material such as GaN, AlGaN, InGaN, AlInP, GaInP, or AlGaInP; the quantum well or quantum layer can be InGaN, AlGaN, InN, InAlN, or AlInGaN; and the quantum barrier alternately stacked with the quantum well layer can be GaN, AlN, AlGaN, AlInGaN, or InAlN; the multiple quantum well structure can include one, two, three, four, five, six, six, seven, or eight quantum wells (or at least one quantum hole); the wavelength emitted by the aforementioned active layer can be a wavelength in the blue light band, a wavelength in the green light band, or a wavelength in the red light band. This application does not specifically limit the specific wavelengths in the embodiments.

[0038] In this embodiment, the driving substrate 1 can be a circuit board, an array substrate, a glass driving substrate, a flexible driving substrate, a semiconductor driving substrate, or other types of driving substrates. No specific limitation is made in this embodiment. Specifically, the driving substrate 1 can be a CMOS substrate or a TFT array substrate. The material of the driving substrate 1 can be glass, transparent plastic, acrylic, quartz, sapphire, semiconductor materials, etc., which can be selected according to the actual situation. No specific limitation is made in this embodiment.

[0039] The LED chip assembly and manufacturing method of this application produce a light-emitting chip that emits light only from the top, sides and bottom of the chip with no light loss. The top has a large current transmission surface and high current transmission efficiency, which can greatly improve the brightness of the light-emitting chip. The light emission direction is close to perpendicular to the surface of the light-emitting chip, with a small light divergence angle and concentrated light.

[0040] It should be understood that the application of this application is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for preparing an LED chip assembly, characterized in that the steps include... include: An epitaxial wafer is provided, the epitaxial wafer including a substrate and an epitaxial layer disposed on the substrate, wherein a reflective bonding metal layer is formed on the side of the epitaxial layer away from the substrate; The reflective bonding metal layer is bonded to the driving substrate, and the substrate is removed; The epitaxial layer is etched to form multiple epitaxial step structures; The reflective bonding metal layer is etched to form multiple bonding step structures that correspond one-to-one with the epitaxial step structure; A reflective passivation layer is deposited on the epitaxial layer, the reflective passivation layer extending from the top surface of the epitaxial stepped structure to the side surface of the epitaxial stepped structure; The reflective passivation layer corresponding to the top surface of the epitaxial step structure is etched away so that the top surface of the epitaxial step structure is fully exposed. A common N-electrode layer is deposited on the epitaxial stepped structure and the reflective passivation layer, the common N-electrode layer extending from the top surface of the epitaxial stepped structure to the side surface of the reflective passivation layer.

2. The method for preparing an LED chip assembly as described in claim 1, characterized in that, The orthographic projection of the epitaxial step structure is located on the bonding step structure, and the reflective passivation layer extends from the side of the epitaxial step to the top and side surfaces of the bonding step structure.

3. The method for preparing an LED chip assembly as described in claim 1 or 2, characterized in that, The reflective bonding metal layer is a multilayer structure, which includes Cr, Au, Sn, Au, Pt, sub-multilayer structures and ITO arranged from bottom to top. Each layer of the sub-multilayer structure contains Ag and Ti arranged from bottom to top, and the number of layers of the sub-multilayer structure is 3-5.

4. The method for preparing an LED chip assembly as described in claim 3, characterized in that, The thickness of Ag ranges from 10 nm to 50 nm, while the thickness of Ti ranges from 5 to 10 nm.

5. The method for preparing an LED chip assembly as described in claim 1, 2, or 4, characterized in that, The reflective passivation layer is a distributed Bragg mirror or a full-angle mirror.

6. The method for preparing an LED chip assembly as described in claim 1, 2, or 4, characterized in that, The common N electrode layer is an ITO transparent conductive film.

7. The method for preparing an LED chip assembly as described in claim 1, 2, or 4, characterized in that, The LED chip assembly is a Mini LED chip assembly or a Micro LED chip assembly.

8. An LED chip assembly, manufactured using the method for preparing an LED chip assembly as described in any one of claims 1 to 7, characterized in that, The device includes a driving substrate, a reflective bonding metal layer, an epitaxial layer, a reflective passivation layer, and a common N-electrode layer. The reflective bonding metal layer is disposed on the driving substrate, and the epitaxial layer is disposed on and bonded to the reflective bonding metal layer. The epitaxial layer is configured as an epitaxial step structure, and the reflective passivation layer extends from the top surface of the epitaxial step structure to the side surface of the epitaxial step structure.

9. The LED chip assembly as described in claim 8, characterized in that, The orthographic projection of the epitaxial step structure is located on the bonding step structure, and the reflective passivation layer extends from the side of the epitaxial step to the top and side surfaces of the bonding step structure.

10. The LED chip assembly as described in claim 8, characterized in that, The reflective bonding metal layer is a multilayer structure, which includes Cr, Au, Sn, Au, Pt, sub-multilayer structures and ITO arranged from bottom to top. Each layer of the sub-multilayer structure contains Ag and Ti arranged from bottom to top, and the number of layers of the sub-multilayer structure is 3-5.

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